grf_cvreg.h revision 1.1.2.1
1 /* $NetBSD: grf_cvreg.h,v 1.1.2.1 1995/10/21 15:15:44 chopps Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Michael Teske 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Ezra Story, by Kari 18 * Mettinen and by Bernd Ernesti. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef _GRF_CVREG_H 35 #define _GRF_CVREG_H 36 37 /* 38 * This is derived from ciruss driver source 39 */ 40 41 /* Extension to grfvideo_mode to support text modes. 42 * This can be passed to both text & gfx functions 43 * without worry. If gv.depth == 4, then the extended 44 * fields for a text mode are present. 45 */ 46 47 struct grfcvtext_mode { 48 struct grfvideo_mode gv; 49 unsigned short fx; /* font x dimension */ 50 unsigned short fy; /* font y dimension */ 51 unsigned short cols; /* screen dimensions */ 52 unsigned short rows; 53 void *fdata; /* font data */ 54 unsigned short fdstart; 55 unsigned short fdend; 56 }; 57 58 59 /* read VGA register */ 60 #define vgar(ba, reg) (*(((volatile unsigned char *)ba)+reg)) 61 62 /* write VGA register */ 63 #define vgaw(ba, reg, val) \ 64 *(((volatile unsigned char *)ba)+reg) = ((val) & 0xff) 65 66 /* 67 * defines for the used register addresses (mw) 68 * 69 * NOTE: there are some registers that have different addresses when 70 * in mono or color mode. We only support color mode, and thus 71 * some addresses won't work in mono-mode! 72 * 73 * General and VGA-registers taken from retina driver. Fixed a few 74 * bugs in it. (SR and GR read address is Port + 1, NOT Port) 75 * 76 */ 77 78 /* General Registers: */ 79 #define GREG_MISC_OUTPUT_R 0x03CC 80 #define GREG_MISC_OUTPUT_W 0x03C2 81 #define GREG_FEATURE_CONTROL_R 0x03CA 82 #define GREG_FEATURE_CONTROL_W 0x03DA 83 #define GREG_INPUT_STATUS0_R 0x03C2 84 #define GREG_INPUT_STATUS1_R 0x03DA 85 86 /* Setup Registers: */ 87 #define SREG_OPTION_SELECT 0x0102 88 #define SREG_VIDEO_SUBS_ENABLE 0x46E8 89 90 /* Attribute Controller: */ 91 #define ACT_ADDRESS 0x03C0 92 #define ACT_ADDRESS_R 0x03C1 93 #define ACT_ADDRESS_W 0x03C0 94 #define ACT_ADDRESS_RESET 0x03DA 95 #define ACT_ID_PALETTE0 0x00 96 #define ACT_ID_PALETTE1 0x01 97 #define ACT_ID_PALETTE2 0x02 98 #define ACT_ID_PALETTE3 0x03 99 #define ACT_ID_PALETTE4 0x04 100 #define ACT_ID_PALETTE5 0x05 101 #define ACT_ID_PALETTE6 0x06 102 #define ACT_ID_PALETTE7 0x07 103 #define ACT_ID_PALETTE8 0x08 104 #define ACT_ID_PALETTE9 0x09 105 #define ACT_ID_PALETTE10 0x0A 106 #define ACT_ID_PALETTE11 0x0B 107 #define ACT_ID_PALETTE12 0x0C 108 #define ACT_ID_PALETTE13 0x0D 109 #define ACT_ID_PALETTE14 0x0E 110 #define ACT_ID_PALETTE15 0x0F 111 #define ACT_ID_ATTR_MODE_CNTL 0x10 112 #define ACT_ID_OVERSCAN_COLOR 0x11 113 #define ACT_ID_COLOR_PLANE_ENA 0x12 114 #define ACT_ID_HOR_PEL_PANNING 0x13 115 #define ACT_ID_COLOR_SELECT 0x14 116 117 /* Graphics Controller: */ 118 #define GCT_ADDRESS 0x03CE 119 #define GCT_ADDRESS_R 0x03CF 120 #define GCT_ADDRESS_W 0x03CF 121 #define GCT_ID_SET_RESET 0x00 122 #define GCT_ID_ENABLE_SET_RESET 0x01 123 #define GCT_ID_COLOR_COMPARE 0x02 124 #define GCT_ID_DATA_ROTATE 0x03 125 #define GCT_ID_READ_MAP_SELECT 0x04 126 #define GCT_ID_GRAPHICS_MODE 0x05 127 #define GCT_ID_MISC 0x06 128 #define GCT_ID_COLOR_XCARE 0x07 129 #define GCT_ID_BITMASK 0x08 130 131 /* Sequencer: */ 132 #define SEQ_ADDRESS 0x03C4 133 #define SEQ_ADDRESS_R 0x03C5 134 #define SEQ_ADDRESS_W 0x03C5 135 #define SEQ_ID_RESET 0x00 136 #define SEQ_ID_CLOCKING_MODE 0x01 137 #define SEQ_ID_MAP_MASK 0x02 138 #define SEQ_ID_CHAR_MAP_SELECT 0x03 139 #define SEQ_ID_MEMORY_MODE 0x04 140 #define SEQ_ID_UNKNOWN1 0x05 141 #define SEQ_ID_UNKNOWN2 0x06 142 #define SEQ_ID_UNKNOWN3 0x07 143 /* S3 extensions */ 144 #define SEQ_ID_UNLOCK_EXT 0x08 145 #define SEQ_ID_EXT_SEQ_REG9 0x09 146 #define SEQ_ID_BUS_REQ_CNTL 0x0A 147 #define SEQ_ID_EXT_MISC_SEQ 0x0B 148 #define SEQ_ID_UNKNOWN4 0x0C 149 #define SEQ_ID_EXT_SEQ 0x0D 150 #define SEQ_ID_UNKNOWN5 0x0E 151 #define SEQ_ID_UNKNOWN6 0x0F 152 #define SEQ_ID_MCLK_LO 0x10 153 #define SEQ_ID_MCLK_HI 0x11 154 #define SEQ_ID_DCLK_LO 0x12 155 #define SEQ_ID_DCLK_HI 0x13 156 #define SEQ_ID_CLKSYN_CNTL_1 0x14 157 #define SEQ_ID_CLKSYN_CNTL_2 0x15 158 #define SEQ_ID_CLKSYN_TEST_HI 0x16 /* reserved for S3 testing of the */ 159 #define SEQ_ID_CLKSYN_TEST_LO 0x17 /* internal clock synthesizer */ 160 #define SEQ_ID_RAMDAC_CNTL 0x18 161 162 /* CRT Controller: */ 163 #define CRT_ADDRESS 0x03D4 164 #define CRT_ADDRESS_R 0x03D5 165 #define CRT_ADDRESS_W 0x03D5 166 #define CRT_ID_HOR_TOTAL 0x00 167 #define CRT_ID_HOR_DISP_ENA_END 0x01 168 #define CRT_ID_START_HOR_BLANK 0x02 169 #define CRT_ID_END_HOR_BLANK 0x03 170 #define CRT_ID_START_HOR_RETR 0x04 171 #define CRT_ID_END_HOR_RETR 0x05 172 #define CRT_ID_VER_TOTAL 0x06 173 #define CRT_ID_OVERFLOW 0x07 174 #define CRT_ID_PRESET_ROW_SCAN 0x08 175 #define CRT_ID_MAX_SCAN_LINE 0x09 176 #define CRT_ID_CURSOR_START 0x0A 177 #define CRT_ID_CURSOR_END 0x0B 178 #define CRT_ID_START_ADDR_HIGH 0x0C 179 #define CRT_ID_START_ADDR_LOW 0x0D 180 #define CRT_ID_CURSOR_LOC_HIGH 0x0E 181 #define CRT_ID_CURSOR_LOC_LOW 0x0F 182 #define CRT_ID_START_VER_RETR 0x10 183 #define CRT_ID_END_VER_RETR 0x11 184 #define CRT_ID_VER_DISP_ENA_END 0x12 185 #define CRT_ID_SCREEN_OFFSET 0x13 186 #define CRT_ID_UNDERLINE_LOC 0x14 187 #define CRT_ID_START_VER_BLANK 0x15 188 #define CRT_ID_END_VER_BLANK 0x16 189 #define CRT_ID_MODE_CONTROL 0x17 190 #define CRT_ID_LINE_COMPARE 0x18 191 #define CRT_ID_GD_LATCH_RBACK 0x22 192 #define CRT_ID_ACT_TOGGLE_RBACK 0x24 193 #define CRT_ID_ACT_INDEX_RBACK 0x26 194 /* S3 extensions: S3 VGA Registers */ 195 #define CRT_ID_DEVICE_HIGH 0x2D 196 #define CRT_ID_DEVICE_LOW 0x2E 197 #define CRT_ID_REVISION 0x2F 198 #define CRT_ID_CHIP_ID_REV 0x30 199 #define CRT_ID_MEMORY_CONF 0x31 200 #define CRT_ID_BACKWAD_COMP_1 0x32 201 #define CRT_ID_BACKWAD_COMP_2 0x33 202 #define CRT_ID_BACKWAD_COMP_3 0x34 203 #define CRT_ID_REGISTER_LOCK 0x35 204 #define CRT_ID_CONFIG_1 0x36 205 #define CRT_ID_CONFIG_2 0x37 206 #define CRT_ID_REGISTER_LOCK_1 0x38 207 #define CRT_ID_REGISTER_LOCK_2 0x39 208 #define CRT_ID_MISC_1 0x3A 209 #define CRT_ID_DISPLAY_FIFO 0x3B 210 #define CRT_ID_LACE_RETR_START 0x3C 211 /* S3 extensions: System Control Registers */ 212 #define CRT_ID_SYSTEM_CONFIG 0x40 213 #define CRT_ID_BIOS_FLAG 0x41 214 #define CRT_ID_LACE_CONTROL 0x42 215 #define CRT_ID_EXT_MODE 0x43 216 #define CRT_ID_HWGC_MODE 0x45 /* HWGC = Hardware Graphics Cursor */ 217 #define CRT_ID_HWGC_ORIGIN_X_HI 0x46 218 #define CRT_ID_HWGC_ORIGIN_X_LO 0x47 219 #define CRT_ID_HWGC_ORIGIN_Y_HI 0x48 220 #define CRT_ID_HWGC_ORIGIN_Y_LO 0x49 221 #define CRT_ID_HWGC_FG_STACK 0x4A 222 #define CRT_ID_HWGC_BG_STACK 0x4B 223 #define CRT_ID_HWGC_START_AD_HI 0x4C 224 #define CRT_ID_HWGC_START_AD_LO 0x4D 225 #define CRT_ID_HWGC_DSTART_X 0x4E 226 #define CRT_ID_HWGC_DSTART_Y 0x4F 227 /* S3 extensions: System Extension Registers */ 228 #define CRT_ID_EXT_SYS_CNTL_1 0x50 229 #define CRT_ID_EXT_SYS_CNTL_2 0x51 230 #define CRT_ID_EXT_BIOS_FLAG_1 0x52 231 #define CRT_ID_EXT_MEM_CNTL_1 0x53 232 #define CRT_ID_EXT_MEM_CNTL_2 0x54 233 #define CRT_ID_EXT_DAC_CNTL 0x55 234 #define CRT_ID_EX_SYNC_1 0x56 235 #define CRT_ID_EX_SYNC_2 0x57 236 #define CRT_ID_LAW_CNTL 0x58 /* LAW = Linear Address Window */ 237 #define CRT_ID_LAW_POS_HI 0x59 238 #define CRT_ID_LAW_POS_LO 0x5A 239 #define CRT_ID_GOUT_PORT 0x5C 240 #define CRT_ID_EXT_HOR_OVF 0x5D 241 #define CRT_ID_EXT_VER_OVF 0x5E 242 #define CRT_ID_EXT_MEM_CNTL_3 0x60 243 #define CRT_ID_EX_SYNC_3 0x63 244 #define CRT_ID_EXT_MISC_CNTL 0x65 245 #define CRT_ID_EXT_MISC_CNTL_1 0x66 246 #define CRT_ID_EXT_MISC_CNTL_2 0x67 247 #define CRT_ID_CONFIG_3 0x68 248 #define CRT_ID_EXT_SYS_CNTL_3 0x69 249 #define CRT_ID_EXT_SYS_CNTL_4 0x6A 250 #define CRT_ID_EXT_BIOS_FLAG_3 0x6B 251 #define CRT_ID_EXT_BIOS_FLAG_4 0x6C 252 253 /* Enhanced Commands Registers: */ 254 #define ECR_SUBSYSTEM_STAT 0x42E8 255 #define ECR_SUBSYSTEM_CNTL 0x42E8 256 #define ECR_ADV_FUNC_CNTL 0x4AE8 257 #define ECR_CURRENT_Y_POS 0x82E8 258 #define ECR_CURRENT_Y_POS2 0x82EA /* Trio64 only */ 259 #define ECR_CURRENT_X_POS 0x86E8 260 #define ECR_CURRENT_X_POS2 0x86EA /* Trio64 only */ 261 #define ECR_DEST_Y__AX_STEP 0x8AE8 262 #define ECR_DEST_Y2__AX_STEP2 0x8AEA /* Trio64 only */ 263 #define ECR_DEST_X__DIA_STEP 0x8EE8 264 #define ECR_DEST_X2__DIA_STEP2 0x8EEA /* Trio64 only */ 265 #define ECR_ERR_TERM 0x92E8 266 #define ECR_ERR_TERM2 0x92EA /* Trio64 only */ 267 #define ECR_MAJ_AXIS_PIX_CNT 0x96E8 268 #define ECR_MAJ_AXIS_PIX_CNT2 0x96EA /* Trio64 only */ 269 #define ECR_GP_STAT 0x9AE8 /* GP = Graphics Processor */ 270 #define ECR_DRAW_CMD 0x9AE8 271 #define ECR_DRAW_CMD2 0x9AEA /* Trio64 only */ 272 #define ECR_SHORT_STROKE 0x9EE8 273 #define ECR_BKGD_COLOR 0xA2E8 /* BKGD = Background */ 274 #define ECR_FRGD_COLOR 0xA6E8 /* FRGD = Foreground */ 275 #define ECR_BITPLANE_WRITE_MASK 0xAAE8 276 #define ECR_BITPLANE_READ_MASK 0xAEE8 277 #define ECR_COLOR_COMPARE 0xB2E8 278 #define ECR_BKGD_MIX 0xB6E8 279 #define ECR_FRGD_MIX 0xBAE8 280 #define ECR_READ_REG_DATA 0xBEE8 281 #define ECR_ID_MIN_AXIS_PIX_CNT 0x00 282 #define ECR_ID_SCISSORS_TOP 0x01 283 #define ECR_ID_SCISSORS_LEFT 0x02 284 #define ECR_ID_SCISSORS_BUTTOM 0x03 285 #define ECR_ID_SCISSORS_RIGHT 0x04 286 #define ECR_ID_PIX_CNTL 0x0A 287 #define ECR_ID_MULT_CNTL_MISC_2 0x0D 288 #define ECR_ID_MULT_CNTL_MISC 0x0E 289 #define ECR_ID_READ_SEL 0x0F 290 #define ECR_PIX_TRANS 0xE2E8 291 #define ECR_PIX_TRANS_EXT 0xE2EA 292 #define ECR_PATTERN_Y 0xEAE8 /* Trio64 only */ 293 #define ECR_PATTERN_X 0xEAEA /* Trio64 only */ 294 295 296 /* Pass-through */ 297 #define PASS_ADDRESS 0x40001 298 #define PASS_ADDRESS_W 0x40001 299 300 /* Video DAC */ 301 #define VDAC_ADDRESS 0x03c8 302 #define VDAC_ADDRESS_W 0x03c8 303 #define VDAC_ADDRESS_R 0x03c7 304 #define VDAC_STATE 0x03c7 305 #define VDAC_DATA 0x03c9 306 #define VDAC_MASK 0x03c6 307 308 309 #define WGfx(ba, idx, val) \ 310 do { vgaw(ba, GCT_ADDRESS, idx); vgaw(ba, GCT_ADDRESS_W , val); } while (0) 311 312 #define WSeq(ba, idx, val) \ 313 do { vgaw(ba, SEQ_ADDRESS, idx); vgaw(ba, SEQ_ADDRESS_W , val); } while (0) 314 315 #define WCrt(ba, idx, val) \ 316 do { vgaw(ba, CRT_ADDRESS, idx); vgaw(ba, CRT_ADDRESS_W , val); } while (0) 317 318 #define WAttr(ba, idx, val) \ 319 do { \ 320 unsigned char tmp;\ 321 tmp = vgar(ba, ACT_ADDRESS_RESET);\ 322 vgaw(ba, ACT_ADDRESS_W, idx);\ 323 vgaw(ba, ACT_ADDRESS_W, val);\ 324 } while (0) 325 326 327 #define SetTextPlane(ba, m) \ 328 do { \ 329 WGfx(ba, GCT_ID_READ_MAP_SELECT, m & 3 );\ 330 WSeq(ba, SEQ_ID_MAP_MASK, (1 << (m & 3)));\ 331 } while (0) 332 333 /* Special wakeup/passthrough registers on graphics boards 334 * 335 * The methods have diverged a bit for each board, so 336 * WPass(P) has been converted into a set of specific 337 * inline functions. 338 */ 339 340 static inline unsigned char 341 RAttr(ba, idx) 342 volatile void *ba; 343 short idx; 344 { 345 346 vgaw(ba, ACT_ADDRESS_W, idx); 347 delay(0); 348 return vgar(ba, ACT_ADDRESS_R); 349 } 350 351 static inline unsigned char 352 RSeq(ba, idx) 353 volatile void *ba; 354 short idx; 355 { 356 vgaw(ba, SEQ_ADDRESS, idx); 357 return vgar(ba, SEQ_ADDRESS_R); 358 } 359 360 static inline unsigned char 361 RCrt(ba, idx) 362 volatile void *ba; 363 short idx; 364 { 365 vgaw(ba, CRT_ADDRESS, idx); 366 return vgar(ba, CRT_ADDRESS_R); 367 } 368 369 static inline unsigned char 370 RGfx(ba, idx) 371 volatile void *ba; 372 short idx; 373 { 374 vgaw(ba, GCT_ADDRESS, idx); 375 return vgar(ba, GCT_ADDRESS_R); 376 } 377 378 379 static inline void 380 cv_write_port(bits, BoardAddr) 381 unsigned short bits; 382 volatile unsigned char *BoardAddr; 383 { 384 volatile char *addr; 385 static unsigned char CVPortBits=0; /* mirror port bits here */ 386 387 addr = BoardAddr + 0x40001; 388 if (bits & 0x8000) 389 CVPortBits |= bits&0xFF; /* Set bits */ 390 else { 391 bits = bits & 0xFF; 392 bits = (~bits) & 0xFF ; 393 CVPortBits &= bits; /* Clear bits */ 394 } 395 396 *addr = CVPortBits; 397 } 398 399 #define set_port_bits(b, ba) cv_write_port((unsigned short )b | 0x8000,ba) 400 #define clear_port_bits(b, ba) cv_write_port((unsigned short )b & 0xff,ba) 401 402 403 /* 404 * Monitor Switch 405 * 0 = CyberVision Signal 406 * 1 = Amiga Signal, 407 * ba = boardaddr 408 */ 409 410 static inline void 411 cvscreen(toggle, ba) 412 char toggle; 413 volatile unsigned char *ba; 414 { 415 416 if (toggle) 417 cv_write_port (0x10, ba); 418 else 419 cv_write_port (0x8010, ba); 420 } 421 422 /* 0 = on, 1= off */ 423 /* ba= registerbase */ 424 static inline void 425 gfx_on_off(toggle, ba) 426 char toggle; 427 volatile unsigned char *ba; 428 { 429 unsigned char r; 430 431 toggle &= 0x1; 432 toggle = toggle << 5; 433 434 r = RSeq(ba, 0x1); 435 r &= 0xDF; /* Bit 5 auf 0!!! */ 436 WSeq(ba, 1, r | toggle); 437 } 438 439 int cv_mode __P((register struct grf_softc *gp, int cmd, void *arg, int a2, int a3)); 440 int cv_load_mon __P((struct grf_softc *gp, struct grfcvtext_mode *gv)); 441 int grfcv_cnprobe __P((void)); 442 #if 0 443 void grfcv_iteinit __P((struct grf_softc *gp)); 444 #endif 445 446 static unsigned char clocks[]={ 447 0x13, 0x61, 0x6b, 0x6d, 0x51, 0x69, 0x54, 0x69, 448 0x4f, 0x68, 0x6b, 0x6b, 0x18, 0x61, 0x7b, 0x6c, 449 0x51, 0x67, 0x24, 0x62, 0x56, 0x67, 0x77, 0x6a, 450 0x1d, 0x61, 0x53, 0x66, 0x6b, 0x68, 0x79, 0x69, 451 0x7c, 0x69, 0x7f, 0x69, 0x22, 0x61, 0x54, 0x65, 452 0x56, 0x65, 0x58, 0x65, 0x67, 0x66, 0x41, 0x63, 453 0x27, 0x61, 0x13, 0x41, 0x37, 0x62, 0x6b, 0x4d, 454 0x23, 0x43, 0x51, 0x49, 0x79, 0x66, 0x54, 0x49, 455 0x7d, 0x66, 0x34, 0x56, 0x4f, 0x63, 0x1f, 0x42, 456 0x6b, 0x4b, 0x7e, 0x4d, 0x18, 0x41, 0x2a, 0x43, 457 0x7b, 0x4c, 0x74, 0x4b, 0x51, 0x47, 0x65, 0x49, 458 0x24, 0x42, 0x68, 0x49, 0x56, 0x47, 0x75, 0x4a, 459 0x77, 0x4a, 0x31, 0x43, 0x1d, 0x41, 0x71, 0x49, 460 0x53, 0x46, 0x29, 0x42, 0x6b, 0x48, 0x1f, 0x41, 461 0x79, 0x49, 0x6f, 0x48, 0x7c, 0x49, 0x38, 0x43, 462 0x7f, 0x49, 0x5d, 0x46, 0x22, 0x41, 0x53, 0x45, 463 0x54, 0x45, 0x55, 0x45, 0x56, 0x45, 0x57, 0x45, 464 0x58, 0x45, 0x25, 0x41, 0x67, 0x46, 0x5b, 0x45, 465 0x41, 0x43, 0x78, 0x47, 0x27, 0x41, 0x51, 0x44, 466 0x13, 0x21, 0x7d, 0x47, 0x37, 0x42, 0x71, 0x46, 467 0x6b, 0x2d, 0x14, 0x21, 0x23, 0x23, 0x7d, 0x2f, 468 0x51, 0x29, 0x61, 0x2b, 0x79, 0x46, 0x1d, 0x22, 469 0x54, 0x29, 0x45, 0x27, 0x7d, 0x46, 0x7f, 0x46, 470 0x4f, 0x43, 0x2f, 0x41, 0x1f, 0x22, 0x6a, 0x2b, 471 0x6b, 0x2b, 0x5b, 0x29, 0x7e, 0x2d, 0x65, 0x44, 472 0x18, 0x21, 0x5e, 0x29, 0x2a, 0x23, 0x45, 0x26, 473 0x7b, 0x2c, 0x19, 0x21, 0x74, 0x2b, 0x75, 0x2b, 474 0x51, 0x27, 0x3f, 0x25, 0x65, 0x29, 0x40, 0x25, 475 0x24, 0x22, 0x41, 0x25, 0x68, 0x29, 0x42, 0x25, 476 0x56, 0x27, 0x7e, 0x2b, 0x75, 0x2a, 0x1c, 0x21, 477 0x77, 0x2a, 0x4f, 0x26, 0x31, 0x23, 0x6f, 0x29, 478 0x1d, 0x21, 0x32, 0x23, 0x71, 0x29, 0x72, 0x29, 479 0x53, 0x26, 0x69, 0x28, 0x29, 0x22, 0x75, 0x29, 480 0x6b, 0x28, 0x1f, 0x21, 0x1f, 0x21, 0x6d, 0x28, 481 0x79, 0x29, 0x2b, 0x22, 0x6f, 0x28, 0x59, 0x26, 482 0x7c, 0x29, 0x7d, 0x29, 0x38, 0x23, 0x21, 0x21, 483 0x7f, 0x29, 0x39, 0x23, 0x5d, 0x26, 0x75, 0x28, 484 0x22, 0x21, 0x77, 0x28, 0x53, 0x25, 0x6c, 0x27, 485 0x54, 0x25, 0x61, 0x26, 0x55, 0x25, 0x30, 0x22, 486 0x56, 0x25, 0x63, 0x26, 0x57, 0x25, 0x71, 0x27, 487 0x58, 0x25, 0x7f, 0x28, 0x25, 0x21, 0x74, 0x27, 488 0x67, 0x26, 0x40, 0x23, 0x5b, 0x25, 0x26, 0x21, 489 0x41, 0x23, 0x34, 0x22, 0x78, 0x27, 0x6b, 0x26, 490 0x27, 0x21, 0x35, 0x22, 0x51, 0x24, 0x7b, 0x27, 491 0x13, 0x1, 0x13, 0x1, 0x7d, 0x27, 0x4c, 0x9, 492 0x37, 0x22, 0x5b, 0xb, 0x71, 0x26, 0x5c, 0xb, 493 0x6b, 0xd, 0x47, 0x23, 0x14, 0x1, 0x4f, 0x9, 494 0x23, 0x3, 0x75, 0x26, 0x7d, 0xf, 0x1c, 0x2, 495 0x51, 0x9, 0x59, 0x24, 0x61, 0xb, 0x69, 0x25, 496 0x79, 0x26, 0x34, 0x5, 0x1d, 0x2, 0x6b, 0x25, 497 0x54, 0x9, 0x35, 0x5, 0x45, 0x7, 0x6d, 0x25, 498 0x7d, 0x26, 0x16, 0x1, 0x7f, 0x26, 0x77, 0xd, 499 0x4f, 0x23, 0x78, 0xd, 0x2f, 0x21, 0x27, 0x3, 500 0x1f, 0x2, 0x59, 0x9, 0x6a, 0xb, 0x73, 0x25, 501 0x6b, 0xb, 0x63, 0x24, 0x5b, 0x9, 0x20, 0x2, 502 0x7e, 0xd, 0x4b, 0x7, 0x65, 0x24, 0x43, 0x22, 503 0x18, 0x1, 0x6f, 0xb, 0x5e, 0x9, 0x70, 0xb, 504 0x2a, 0x3, 0x33, 0x4, 0x45, 0x6, 0x60, 0x9, 505 0x7b, 0xc, 0x19, 0x1, 0x19, 0x1, 0x7d, 0xc, 506 0x74, 0xb, 0x50, 0x7, 0x75, 0xb, 0x63, 0x9, 507 0x51, 0x7, 0x23, 0x2, 0x3f, 0x5, 0x1a, 0x1, 508 0x65, 0x9, 0x2d, 0x3, 0x40, 0x5, 0x0, 0x0, 509 }; 510 511 #endif /* _GRF_RHREG_H */ 512 513
Indexes created Tue Oct 07 11:09:55 GMT 2025