grf_cvreg.h revision 1.15
1 /* $NetBSD: grf_cvreg.h,v 1.15 2010/02/05 12:13:36 phx Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Michael Teske 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Ezra Story, by Kari 18 * Mettinen and by Bernd Ernesti. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef _GRF_CVREG_H 35 #define _GRF_CVREG_H 36 37 /* 38 * This is derived from ciruss driver source 39 */ 40 41 /* Extension to grfvideo_mode to support text modes. 42 * This can be passed to both text & gfx functions 43 * without worry. If gv.depth == 4, then the extended 44 * fields for a text mode are present. 45 */ 46 47 struct grfcvtext_mode { 48 struct grfvideo_mode gv; 49 unsigned short fx; /* font x dimension */ 50 unsigned short fy; /* font y dimension */ 51 unsigned short cols; /* screen dimensions */ 52 unsigned short rows; 53 void *fdata; /* font data */ 54 unsigned short fdstart; 55 unsigned short fdend; 56 }; 57 58 /* maximum console size */ 59 #define MAXROWS 200 60 #define MAXCOLS 200 61 62 63 /* read VGA register */ 64 #define vgar(ba, reg) \ 65 (*(((volatile char *)ba)+reg)) 66 67 /* write VGA register */ 68 #define vgaw(ba, reg, val) \ 69 *(((volatile char *)ba)+reg) = ((val) & 0xff); \ 70 amiga_membarrier() 71 72 /* read 32 Bit VGA register */ 73 #define vgar32(ba, reg) \ 74 ( *((volatile unsigned long *) (((volatile char *)ba)+reg)) ) 75 76 /* write 32 Bit VGA register */ 77 #define vgaw32(ba, reg, val) \ 78 *((unsigned long *) (((volatile char *)ba)+reg)) = val; \ 79 amiga_membarrier() 80 81 /* read 16 Bit VGA register */ 82 #define vgar16(ba, reg) \ 83 ( *((volatile unsigned short *) (((volatile char *)ba)+reg)) ) 84 85 /* write 16 Bit VGA register */ 86 #define vgaw16(ba, reg, val) \ 87 *((volatile unsigned short *) (((volatile char *)ba)+reg)) = val; \ 88 amiga_membarrier() 89 90 #ifdef _KERNEL 91 int grfcv_cnprobe(void); 92 void grfcv_iteinit(struct grf_softc *); 93 static inline void GfxBusyWait(volatile void *); 94 static inline void GfxFifoWait(volatile void *); 95 static inline unsigned char RAttr(volatile void *, short); 96 static inline unsigned char RSeq(volatile void *, short); 97 static inline unsigned char RCrt(volatile void *, short); 98 static inline unsigned char RGfx(volatile void *, short); 99 #endif 100 101 102 /* 103 * defines for the used register addresses (mw) 104 * 105 * NOTE: there are some registers that have different addresses when 106 * in mono or color mode. We only support color mode, and thus 107 * some addresses won't work in mono-mode! 108 * 109 * General and VGA-registers taken from retina driver. Fixed a few 110 * bugs in it. (SR and GR read address is Port + 1, NOT Port) 111 * 112 */ 113 114 /* General Registers: */ 115 #define GREG_MISC_OUTPUT_R 0x03CC 116 #define GREG_MISC_OUTPUT_W 0x03C2 117 #define GREG_FEATURE_CONTROL_R 0x03CA 118 #define GREG_FEATURE_CONTROL_W 0x03DA 119 #define GREG_INPUT_STATUS0_R 0x03C2 120 #define GREG_INPUT_STATUS1_R 0x03DA 121 122 /* Setup Registers: */ 123 #define SREG_OPTION_SELECT 0x0102 124 #define SREG_VIDEO_SUBS_ENABLE 0x46E8 125 126 /* Attribute Controller: */ 127 #define ACT_ADDRESS 0x03C0 128 #define ACT_ADDRESS_R 0x03C1 129 #define ACT_ADDRESS_W 0x03C0 130 #define ACT_ADDRESS_RESET 0x03DA 131 #define ACT_ID_PALETTE0 0x00 132 #define ACT_ID_PALETTE1 0x01 133 #define ACT_ID_PALETTE2 0x02 134 #define ACT_ID_PALETTE3 0x03 135 #define ACT_ID_PALETTE4 0x04 136 #define ACT_ID_PALETTE5 0x05 137 #define ACT_ID_PALETTE6 0x06 138 #define ACT_ID_PALETTE7 0x07 139 #define ACT_ID_PALETTE8 0x08 140 #define ACT_ID_PALETTE9 0x09 141 #define ACT_ID_PALETTE10 0x0A 142 #define ACT_ID_PALETTE11 0x0B 143 #define ACT_ID_PALETTE12 0x0C 144 #define ACT_ID_PALETTE13 0x0D 145 #define ACT_ID_PALETTE14 0x0E 146 #define ACT_ID_PALETTE15 0x0F 147 #define ACT_ID_ATTR_MODE_CNTL 0x10 148 #define ACT_ID_OVERSCAN_COLOR 0x11 149 #define ACT_ID_COLOR_PLANE_ENA 0x12 150 #define ACT_ID_HOR_PEL_PANNING 0x13 151 #define ACT_ID_COLOR_SELECT 0x14 152 153 /* Graphics Controller: */ 154 #define GCT_ADDRESS 0x03CE 155 #define GCT_ADDRESS_R 0x03CF 156 #define GCT_ADDRESS_W 0x03CF 157 #define GCT_ID_SET_RESET 0x00 158 #define GCT_ID_ENABLE_SET_RESET 0x01 159 #define GCT_ID_COLOR_COMPARE 0x02 160 #define GCT_ID_DATA_ROTATE 0x03 161 #define GCT_ID_READ_MAP_SELECT 0x04 162 #define GCT_ID_GRAPHICS_MODE 0x05 163 #define GCT_ID_MISC 0x06 164 #define GCT_ID_COLOR_XCARE 0x07 165 #define GCT_ID_BITMASK 0x08 166 167 /* Sequencer: */ 168 #define SEQ_ADDRESS 0x03C4 169 #define SEQ_ADDRESS_R 0x03C5 170 #define SEQ_ADDRESS_W 0x03C5 171 #define SEQ_ID_RESET 0x00 172 #define SEQ_ID_CLOCKING_MODE 0x01 173 #define SEQ_ID_MAP_MASK 0x02 174 #define SEQ_ID_CHAR_MAP_SELECT 0x03 175 #define SEQ_ID_MEMORY_MODE 0x04 176 #define SEQ_ID_UNKNOWN1 0x05 177 #define SEQ_ID_UNKNOWN2 0x06 178 #define SEQ_ID_UNKNOWN3 0x07 179 /* S3 extensions */ 180 #define SEQ_ID_UNLOCK_EXT 0x08 181 #define SEQ_ID_EXT_SEQ_REG9 0x09 182 #define SEQ_ID_BUS_REQ_CNTL 0x0A 183 #define SEQ_ID_EXT_MISC_SEQ 0x0B 184 #define SEQ_ID_UNKNOWN4 0x0C 185 #define SEQ_ID_EXT_SEQ 0x0D 186 #define SEQ_ID_UNKNOWN5 0x0E 187 #define SEQ_ID_UNKNOWN6 0x0F 188 #define SEQ_ID_MCLK_LO 0x10 189 #define SEQ_ID_MCLK_HI 0x11 190 #define SEQ_ID_DCLK_LO 0x12 191 #define SEQ_ID_DCLK_HI 0x13 192 #define SEQ_ID_CLKSYN_CNTL_1 0x14 193 #define SEQ_ID_CLKSYN_CNTL_2 0x15 194 #define SEQ_ID_CLKSYN_TEST_HI 0x16 /* reserved for S3 testing of the */ 195 #define SEQ_ID_CLKSYN_TEST_LO 0x17 /* internal clock synthesizer */ 196 #define SEQ_ID_RAMDAC_CNTL 0x18 197 #define SEQ_ID_MORE_MAGIC 0x1A 198 199 /* CRT Controller: */ 200 #define CRT_ADDRESS 0x03D4 201 #define CRT_ADDRESS_R 0x03D5 202 #define CRT_ADDRESS_W 0x03D5 203 #define CRT_ID_HOR_TOTAL 0x00 204 #define CRT_ID_HOR_DISP_ENA_END 0x01 205 #define CRT_ID_START_HOR_BLANK 0x02 206 #define CRT_ID_END_HOR_BLANK 0x03 207 #define CRT_ID_START_HOR_RETR 0x04 208 #define CRT_ID_END_HOR_RETR 0x05 209 #define CRT_ID_VER_TOTAL 0x06 210 #define CRT_ID_OVERFLOW 0x07 211 #define CRT_ID_PRESET_ROW_SCAN 0x08 212 #define CRT_ID_MAX_SCAN_LINE 0x09 213 #define CRT_ID_CURSOR_START 0x0A 214 #define CRT_ID_CURSOR_END 0x0B 215 #define CRT_ID_START_ADDR_HIGH 0x0C 216 #define CRT_ID_START_ADDR_LOW 0x0D 217 #define CRT_ID_CURSOR_LOC_HIGH 0x0E 218 #define CRT_ID_CURSOR_LOC_LOW 0x0F 219 #define CRT_ID_START_VER_RETR 0x10 220 #define CRT_ID_END_VER_RETR 0x11 221 #define CRT_ID_VER_DISP_ENA_END 0x12 222 #define CRT_ID_SCREEN_OFFSET 0x13 223 #define CRT_ID_UNDERLINE_LOC 0x14 224 #define CRT_ID_START_VER_BLANK 0x15 225 #define CRT_ID_END_VER_BLANK 0x16 226 #define CRT_ID_MODE_CONTROL 0x17 227 #define CRT_ID_LINE_COMPARE 0x18 228 #define CRT_ID_GD_LATCH_RBACK 0x22 229 #define CRT_ID_ACT_TOGGLE_RBACK 0x24 230 #define CRT_ID_ACT_INDEX_RBACK 0x26 231 /* S3 extensions: S3 VGA Registers */ 232 #define CRT_ID_DEVICE_HIGH 0x2D 233 #define CRT_ID_DEVICE_LOW 0x2E 234 #define CRT_ID_REVISION 0x2F 235 #define CRT_ID_CHIP_ID_REV 0x30 236 #define CRT_ID_MEMORY_CONF 0x31 237 #define CRT_ID_BACKWAD_COMP_1 0x32 238 #define CRT_ID_BACKWAD_COMP_2 0x33 239 #define CRT_ID_BACKWAD_COMP_3 0x34 240 #define CRT_ID_REGISTER_LOCK 0x35 241 #define CRT_ID_CONFIG_1 0x36 242 #define CRT_ID_CONFIG_2 0x37 243 #define CRT_ID_REGISTER_LOCK_1 0x38 244 #define CRT_ID_REGISTER_LOCK_2 0x39 245 #define CRT_ID_MISC_1 0x3A 246 #define CRT_ID_DISPLAY_FIFO 0x3B 247 #define CRT_ID_LACE_RETR_START 0x3C 248 /* S3 extensions: System Control Registers */ 249 #define CRT_ID_SYSTEM_CONFIG 0x40 250 #define CRT_ID_BIOS_FLAG 0x41 251 #define CRT_ID_LACE_CONTROL 0x42 252 #define CRT_ID_EXT_MODE 0x43 253 #define CRT_ID_HWGC_MODE 0x45 /* HWGC = Hardware Graphics Cursor */ 254 #define CRT_ID_HWGC_ORIGIN_X_HI 0x46 255 #define CRT_ID_HWGC_ORIGIN_X_LO 0x47 256 #define CRT_ID_HWGC_ORIGIN_Y_HI 0x48 257 #define CRT_ID_HWGC_ORIGIN_Y_LO 0x49 258 #define CRT_ID_HWGC_FG_STACK 0x4A 259 #define CRT_ID_HWGC_BG_STACK 0x4B 260 #define CRT_ID_HWGC_START_AD_HI 0x4C 261 #define CRT_ID_HWGC_START_AD_LO 0x4D 262 #define CRT_ID_HWGC_DSTART_X 0x4E 263 #define CRT_ID_HWGC_DSTART_Y 0x4F 264 /* S3 extensions: System Extension Registers */ 265 #define CRT_ID_EXT_SYS_CNTL_1 0x50 266 #define CRT_ID_EXT_SYS_CNTL_2 0x51 267 #define CRT_ID_EXT_BIOS_FLAG_1 0x52 268 #define CRT_ID_EXT_MEM_CNTL_1 0x53 269 #define CRT_ID_EXT_MEM_CNTL_2 0x54 270 #define CRT_ID_EXT_DAC_CNTL 0x55 271 #define CRT_ID_EX_SYNC_1 0x56 272 #define CRT_ID_EX_SYNC_2 0x57 273 #define CRT_ID_LAW_CNTL 0x58 /* LAW = Linear Address Window */ 274 #define CRT_ID_LAW_POS_HI 0x59 275 #define CRT_ID_LAW_POS_LO 0x5A 276 #define CRT_ID_GOUT_PORT 0x5C 277 #define CRT_ID_EXT_HOR_OVF 0x5D 278 #define CRT_ID_EXT_VER_OVF 0x5E 279 #define CRT_ID_EXT_MEM_CNTL_3 0x60 280 #define CRT_ID_EX_SYNC_3 0x63 281 #define CRT_ID_EXT_MISC_CNTL 0x65 282 #define CRT_ID_EXT_MISC_CNTL_1 0x66 283 #define CRT_ID_EXT_MISC_CNTL_2 0x67 284 #define CRT_ID_CONFIG_3 0x68 285 #define CRT_ID_EXT_SYS_CNTL_3 0x69 286 #define CRT_ID_EXT_SYS_CNTL_4 0x6A 287 #define CRT_ID_EXT_BIOS_FLAG_3 0x6B 288 #define CRT_ID_EXT_BIOS_FLAG_4 0x6C 289 290 /* Enhanced Commands Registers: */ 291 #define ECR_SUBSYSTEM_STAT 0x42E8 292 #define ECR_SUBSYSTEM_CNTL 0x42E8 293 #define ECR_ADV_FUNC_CNTL 0x4AE8 294 #define ECR_CURRENT_Y_POS 0x82E8 295 #define ECR_CURRENT_Y_POS2 0x82EA /* Trio64 only */ 296 #define ECR_CURRENT_X_POS 0x86E8 297 #define ECR_CURRENT_X_POS2 0x86EA /* Trio64 only */ 298 #define ECR_DEST_Y__AX_STEP 0x8AE8 299 #define ECR_DEST_Y2__AX_STEP2 0x8AEA /* Trio64 only */ 300 #define ECR_DEST_X__DIA_STEP 0x8EE8 301 #define ECR_DEST_X2__DIA_STEP2 0x8EEA /* Trio64 only */ 302 #define ECR_ERR_TERM 0x92E8 303 #define ECR_ERR_TERM2 0x92EA /* Trio64 only */ 304 #define ECR_MAJ_AXIS_PIX_CNT 0x96E8 305 #define ECR_MAJ_AXIS_PIX_CNT2 0x96EA /* Trio64 only */ 306 #define ECR_GP_STAT 0x9AE8 /* GP = Graphics Processor */ 307 #define ECR_DRAW_CMD 0x9AE8 308 #define ECR_DRAW_CMD2 0x9AEA /* Trio64 only */ 309 #define ECR_SHORT_STROKE 0x9EE8 310 #define ECR_BKGD_COLOR 0xA2E8 /* BKGD = Background */ 311 #define ECR_FRGD_COLOR 0xA6E8 /* FRGD = Foreground */ 312 #define ECR_BITPLANE_WRITE_MASK 0xAAE8 313 #define ECR_BITPLANE_READ_MASK 0xAEE8 314 #define ECR_COLOR_COMPARE 0xB2E8 315 #define ECR_BKGD_MIX 0xB6E8 316 #define ECR_FRGD_MIX 0xBAE8 317 #define ECR_READ_REG_DATA 0xBEE8 318 #define ECR_ID_MIN_AXIS_PIX_CNT 0x00 319 #define ECR_ID_SCISSORS_TOP 0x01 320 #define ECR_ID_SCISSORS_LEFT 0x02 321 #define ECR_ID_SCISSORS_BUTTOM 0x03 322 #define ECR_ID_SCISSORS_RIGHT 0x04 323 #define ECR_ID_PIX_CNTL 0x0A 324 #define ECR_ID_MULT_CNTL_MISC_2 0x0D 325 #define ECR_ID_MULT_CNTL_MISC 0x0E 326 #define ECR_ID_READ_SEL 0x0F 327 #define ECR_PIX_TRANS 0xE2E8 328 #define ECR_PIX_TRANS_EXT 0xE2EA 329 #define ECR_PATTERN_Y 0xEAE8 /* Trio64 only */ 330 #define ECR_PATTERN_X 0xEAEA /* Trio64 only */ 331 332 333 /* Pass-through */ 334 #define PASS_ADDRESS 0x40001 335 #define PASS_ADDRESS_W 0x40001 336 337 /* Video DAC */ 338 #define VDAC_ADDRESS 0x03c8 339 #define VDAC_ADDRESS_W 0x03c8 340 #define VDAC_ADDRESS_R 0x03c7 341 #define VDAC_STATE 0x03c7 342 #define VDAC_DATA 0x03c9 343 #define VDAC_MASK 0x03c6 344 345 346 #define WGfx(ba, idx, val) \ 347 do { vgaw(ba, GCT_ADDRESS, idx); vgaw(ba, GCT_ADDRESS_W , val); } while (0) 348 349 #define WSeq(ba, idx, val) \ 350 do { vgaw(ba, SEQ_ADDRESS, idx); vgaw(ba, SEQ_ADDRESS_W , val); } while (0) 351 352 #define WCrt(ba, idx, val) \ 353 do { vgaw(ba, CRT_ADDRESS, idx); vgaw(ba, CRT_ADDRESS_W , val); } while (0) 354 355 #define WAttr(ba, idx, val) \ 356 do { \ 357 unsigned char tmp;\ 358 tmp = vgar(ba, ACT_ADDRESS_RESET);\ 359 vgaw(ba, ACT_ADDRESS_W, idx);\ 360 vgaw(ba, ACT_ADDRESS_W, val);\ 361 } while (0) 362 363 364 #define SetTextPlane(ba, m) \ 365 do { \ 366 WGfx(ba, GCT_ID_READ_MAP_SELECT, m & 3 );\ 367 WSeq(ba, SEQ_ID_MAP_MASK, (1 << (m & 3)));\ 368 } while (0) 369 370 371 /* Gfx engine busy wait */ 372 373 static inline void 374 GfxBusyWait (ba) 375 volatile void *ba; 376 { 377 int test; 378 379 do { 380 test = vgar16 (ba, ECR_GP_STAT); 381 amiga_cpu_sync(); 382 } while (test & (1 << 9)); 383 } 384 385 386 static inline void 387 GfxFifoWait(ba) 388 volatile void *ba; 389 { 390 int test; 391 392 do { 393 test = vgar16 (ba, ECR_GP_STAT); 394 } while (test & 0x0f); 395 } 396 397 398 /* Special wakeup/passthrough registers on graphics boards 399 * 400 * The methods have diverged a bit for each board, so 401 * WPass(P) has been converted into a set of specific 402 * inline functions. 403 */ 404 405 static inline unsigned char 406 RAttr(ba, idx) 407 volatile void *ba; 408 short idx; 409 { 410 411 vgaw(ba, ACT_ADDRESS_W, idx); 412 delay(0); 413 return vgar(ba, ACT_ADDRESS_R); 414 } 415 416 static inline unsigned char 417 RSeq(ba, idx) 418 volatile void *ba; 419 short idx; 420 { 421 vgaw(ba, SEQ_ADDRESS, idx); 422 return vgar(ba, SEQ_ADDRESS_R); 423 } 424 425 static inline unsigned char 426 RCrt(ba, idx) 427 volatile void *ba; 428 short idx; 429 { 430 vgaw(ba, CRT_ADDRESS, idx); 431 return vgar(ba, CRT_ADDRESS_R); 432 } 433 434 static inline unsigned char 435 RGfx(ba, idx) 436 volatile void *ba; 437 short idx; 438 { 439 vgaw(ba, GCT_ADDRESS, idx); 440 return vgar(ba, GCT_ADDRESS_R); 441 } 442 443 #endif /* _GRF_RHREG_H */ 444
Indexes created Sat Sep 27 14:09:57 GMT 2025