grf_cvreg.h revision 1.4
1 /* $NetBSD: grf_cvreg.h,v 1.4 1996/03/02 14:02:58 veego Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Michael Teske 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Ezra Story, by Kari 18 * Mettinen and by Bernd Ernesti. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef _GRF_CVREG_H 35 #define _GRF_CVREG_H 36 37 /* 38 * This is derived from ciruss driver source 39 */ 40 41 /* Extension to grfvideo_mode to support text modes. 42 * This can be passed to both text & gfx functions 43 * without worry. If gv.depth == 4, then the extended 44 * fields for a text mode are present. 45 */ 46 47 struct grfcvtext_mode { 48 struct grfvideo_mode gv; 49 unsigned short fx; /* font x dimension */ 50 unsigned short fy; /* font y dimension */ 51 unsigned short cols; /* screen dimensions */ 52 unsigned short rows; 53 void *fdata; /* font data */ 54 unsigned short fdstart; 55 unsigned short fdend; 56 }; 57 58 59 /* read VGA register */ 60 #define vgar(ba, reg) (*(((volatile caddr_t)ba)+reg)) 61 62 /* write VGA register */ 63 #define vgaw(ba, reg, val) \ 64 *(((volatile caddr_t)ba)+reg) = ((val) & 0xff) 65 66 67 /* read 32 Bit VGA register */ 68 #define vgar32(ba, reg) ( *((unsigned long *) (((volatile caddr_t)ba)+reg)) ) 69 70 /* write 32 Bit VGA register */ 71 #define vgaw32(ba, reg, val) \ 72 *((unsigned long *) (((volatile caddr_t)ba)+reg)) = val 73 74 /* read 16 Bit VGA register */ 75 #define vgar16(ba, reg) ( *((unsigned short *) (((volatile caddr_t)ba)+reg)) ) 76 77 /* write 16 Bit VGA register */ 78 #define vgaw16(ba, reg, val) \ 79 *((unsigned short *) (((volatile caddr_t)ba)+reg)) = val 80 81 int grfcv_cnprobe __P((void)); 82 void grfcv_iteinit __P((struct grf_softc *)); 83 static inline void GfxBusyWait __P((volatile caddr_t)); 84 static inline void GfxFifoWait __P((volatile caddr_t)); 85 static inline unsigned char RAttr __P((volatile caddr_t, short)); 86 static inline unsigned char RSeq __P((volatile caddr_t, short)); 87 static inline unsigned char RCrt __P((volatile caddr_t, short)); 88 static inline unsigned char RGfx __P((volatile caddr_t, short)); 89 90 91 /* 92 * defines for the used register addresses (mw) 93 * 94 * NOTE: there are some registers that have different addresses when 95 * in mono or color mode. We only support color mode, and thus 96 * some addresses won't work in mono-mode! 97 * 98 * General and VGA-registers taken from retina driver. Fixed a few 99 * bugs in it. (SR and GR read address is Port + 1, NOT Port) 100 * 101 */ 102 103 /* General Registers: */ 104 #define GREG_MISC_OUTPUT_R 0x03CC 105 #define GREG_MISC_OUTPUT_W 0x03C2 106 #define GREG_FEATURE_CONTROL_R 0x03CA 107 #define GREG_FEATURE_CONTROL_W 0x03DA 108 #define GREG_INPUT_STATUS0_R 0x03C2 109 #define GREG_INPUT_STATUS1_R 0x03DA 110 111 /* Setup Registers: */ 112 #define SREG_OPTION_SELECT 0x0102 113 #define SREG_VIDEO_SUBS_ENABLE 0x46E8 114 115 /* Attribute Controller: */ 116 #define ACT_ADDRESS 0x03C0 117 #define ACT_ADDRESS_R 0x03C1 118 #define ACT_ADDRESS_W 0x03C0 119 #define ACT_ADDRESS_RESET 0x03DA 120 #define ACT_ID_PALETTE0 0x00 121 #define ACT_ID_PALETTE1 0x01 122 #define ACT_ID_PALETTE2 0x02 123 #define ACT_ID_PALETTE3 0x03 124 #define ACT_ID_PALETTE4 0x04 125 #define ACT_ID_PALETTE5 0x05 126 #define ACT_ID_PALETTE6 0x06 127 #define ACT_ID_PALETTE7 0x07 128 #define ACT_ID_PALETTE8 0x08 129 #define ACT_ID_PALETTE9 0x09 130 #define ACT_ID_PALETTE10 0x0A 131 #define ACT_ID_PALETTE11 0x0B 132 #define ACT_ID_PALETTE12 0x0C 133 #define ACT_ID_PALETTE13 0x0D 134 #define ACT_ID_PALETTE14 0x0E 135 #define ACT_ID_PALETTE15 0x0F 136 #define ACT_ID_ATTR_MODE_CNTL 0x10 137 #define ACT_ID_OVERSCAN_COLOR 0x11 138 #define ACT_ID_COLOR_PLANE_ENA 0x12 139 #define ACT_ID_HOR_PEL_PANNING 0x13 140 #define ACT_ID_COLOR_SELECT 0x14 141 142 /* Graphics Controller: */ 143 #define GCT_ADDRESS 0x03CE 144 #define GCT_ADDRESS_R 0x03CF 145 #define GCT_ADDRESS_W 0x03CF 146 #define GCT_ID_SET_RESET 0x00 147 #define GCT_ID_ENABLE_SET_RESET 0x01 148 #define GCT_ID_COLOR_COMPARE 0x02 149 #define GCT_ID_DATA_ROTATE 0x03 150 #define GCT_ID_READ_MAP_SELECT 0x04 151 #define GCT_ID_GRAPHICS_MODE 0x05 152 #define GCT_ID_MISC 0x06 153 #define GCT_ID_COLOR_XCARE 0x07 154 #define GCT_ID_BITMASK 0x08 155 156 /* Sequencer: */ 157 #define SEQ_ADDRESS 0x03C4 158 #define SEQ_ADDRESS_R 0x03C5 159 #define SEQ_ADDRESS_W 0x03C5 160 #define SEQ_ID_RESET 0x00 161 #define SEQ_ID_CLOCKING_MODE 0x01 162 #define SEQ_ID_MAP_MASK 0x02 163 #define SEQ_ID_CHAR_MAP_SELECT 0x03 164 #define SEQ_ID_MEMORY_MODE 0x04 165 #define SEQ_ID_UNKNOWN1 0x05 166 #define SEQ_ID_UNKNOWN2 0x06 167 #define SEQ_ID_UNKNOWN3 0x07 168 /* S3 extensions */ 169 #define SEQ_ID_UNLOCK_EXT 0x08 170 #define SEQ_ID_EXT_SEQ_REG9 0x09 171 #define SEQ_ID_BUS_REQ_CNTL 0x0A 172 #define SEQ_ID_EXT_MISC_SEQ 0x0B 173 #define SEQ_ID_UNKNOWN4 0x0C 174 #define SEQ_ID_EXT_SEQ 0x0D 175 #define SEQ_ID_UNKNOWN5 0x0E 176 #define SEQ_ID_UNKNOWN6 0x0F 177 #define SEQ_ID_MCLK_LO 0x10 178 #define SEQ_ID_MCLK_HI 0x11 179 #define SEQ_ID_DCLK_LO 0x12 180 #define SEQ_ID_DCLK_HI 0x13 181 #define SEQ_ID_CLKSYN_CNTL_1 0x14 182 #define SEQ_ID_CLKSYN_CNTL_2 0x15 183 #define SEQ_ID_CLKSYN_TEST_HI 0x16 /* reserved for S3 testing of the */ 184 #define SEQ_ID_CLKSYN_TEST_LO 0x17 /* internal clock synthesizer */ 185 #define SEQ_ID_RAMDAC_CNTL 0x18 186 #define SEQ_ID_MORE_MAGIC 0x1A 187 188 /* CRT Controller: */ 189 #define CRT_ADDRESS 0x03D4 190 #define CRT_ADDRESS_R 0x03D5 191 #define CRT_ADDRESS_W 0x03D5 192 #define CRT_ID_HOR_TOTAL 0x00 193 #define CRT_ID_HOR_DISP_ENA_END 0x01 194 #define CRT_ID_START_HOR_BLANK 0x02 195 #define CRT_ID_END_HOR_BLANK 0x03 196 #define CRT_ID_START_HOR_RETR 0x04 197 #define CRT_ID_END_HOR_RETR 0x05 198 #define CRT_ID_VER_TOTAL 0x06 199 #define CRT_ID_OVERFLOW 0x07 200 #define CRT_ID_PRESET_ROW_SCAN 0x08 201 #define CRT_ID_MAX_SCAN_LINE 0x09 202 #define CRT_ID_CURSOR_START 0x0A 203 #define CRT_ID_CURSOR_END 0x0B 204 #define CRT_ID_START_ADDR_HIGH 0x0C 205 #define CRT_ID_START_ADDR_LOW 0x0D 206 #define CRT_ID_CURSOR_LOC_HIGH 0x0E 207 #define CRT_ID_CURSOR_LOC_LOW 0x0F 208 #define CRT_ID_START_VER_RETR 0x10 209 #define CRT_ID_END_VER_RETR 0x11 210 #define CRT_ID_VER_DISP_ENA_END 0x12 211 #define CRT_ID_SCREEN_OFFSET 0x13 212 #define CRT_ID_UNDERLINE_LOC 0x14 213 #define CRT_ID_START_VER_BLANK 0x15 214 #define CRT_ID_END_VER_BLANK 0x16 215 #define CRT_ID_MODE_CONTROL 0x17 216 #define CRT_ID_LINE_COMPARE 0x18 217 #define CRT_ID_GD_LATCH_RBACK 0x22 218 #define CRT_ID_ACT_TOGGLE_RBACK 0x24 219 #define CRT_ID_ACT_INDEX_RBACK 0x26 220 /* S3 extensions: S3 VGA Registers */ 221 #define CRT_ID_DEVICE_HIGH 0x2D 222 #define CRT_ID_DEVICE_LOW 0x2E 223 #define CRT_ID_REVISION 0x2F 224 #define CRT_ID_CHIP_ID_REV 0x30 225 #define CRT_ID_MEMORY_CONF 0x31 226 #define CRT_ID_BACKWAD_COMP_1 0x32 227 #define CRT_ID_BACKWAD_COMP_2 0x33 228 #define CRT_ID_BACKWAD_COMP_3 0x34 229 #define CRT_ID_REGISTER_LOCK 0x35 230 #define CRT_ID_CONFIG_1 0x36 231 #define CRT_ID_CONFIG_2 0x37 232 #define CRT_ID_REGISTER_LOCK_1 0x38 233 #define CRT_ID_REGISTER_LOCK_2 0x39 234 #define CRT_ID_MISC_1 0x3A 235 #define CRT_ID_DISPLAY_FIFO 0x3B 236 #define CRT_ID_LACE_RETR_START 0x3C 237 /* S3 extensions: System Control Registers */ 238 #define CRT_ID_SYSTEM_CONFIG 0x40 239 #define CRT_ID_BIOS_FLAG 0x41 240 #define CRT_ID_LACE_CONTROL 0x42 241 #define CRT_ID_EXT_MODE 0x43 242 #define CRT_ID_HWGC_MODE 0x45 /* HWGC = Hardware Graphics Cursor */ 243 #define CRT_ID_HWGC_ORIGIN_X_HI 0x46 244 #define CRT_ID_HWGC_ORIGIN_X_LO 0x47 245 #define CRT_ID_HWGC_ORIGIN_Y_HI 0x48 246 #define CRT_ID_HWGC_ORIGIN_Y_LO 0x49 247 #define CRT_ID_HWGC_FG_STACK 0x4A 248 #define CRT_ID_HWGC_BG_STACK 0x4B 249 #define CRT_ID_HWGC_START_AD_HI 0x4C 250 #define CRT_ID_HWGC_START_AD_LO 0x4D 251 #define CRT_ID_HWGC_DSTART_X 0x4E 252 #define CRT_ID_HWGC_DSTART_Y 0x4F 253 /* S3 extensions: System Extension Registers */ 254 #define CRT_ID_EXT_SYS_CNTL_1 0x50 255 #define CRT_ID_EXT_SYS_CNTL_2 0x51 256 #define CRT_ID_EXT_BIOS_FLAG_1 0x52 257 #define CRT_ID_EXT_MEM_CNTL_1 0x53 258 #define CRT_ID_EXT_MEM_CNTL_2 0x54 259 #define CRT_ID_EXT_DAC_CNTL 0x55 260 #define CRT_ID_EX_SYNC_1 0x56 261 #define CRT_ID_EX_SYNC_2 0x57 262 #define CRT_ID_LAW_CNTL 0x58 /* LAW = Linear Address Window */ 263 #define CRT_ID_LAW_POS_HI 0x59 264 #define CRT_ID_LAW_POS_LO 0x5A 265 #define CRT_ID_GOUT_PORT 0x5C 266 #define CRT_ID_EXT_HOR_OVF 0x5D 267 #define CRT_ID_EXT_VER_OVF 0x5E 268 #define CRT_ID_EXT_MEM_CNTL_3 0x60 269 #define CRT_ID_EX_SYNC_3 0x63 270 #define CRT_ID_EXT_MISC_CNTL 0x65 271 #define CRT_ID_EXT_MISC_CNTL_1 0x66 272 #define CRT_ID_EXT_MISC_CNTL_2 0x67 273 #define CRT_ID_CONFIG_3 0x68 274 #define CRT_ID_EXT_SYS_CNTL_3 0x69 275 #define CRT_ID_EXT_SYS_CNTL_4 0x6A 276 #define CRT_ID_EXT_BIOS_FLAG_3 0x6B 277 #define CRT_ID_EXT_BIOS_FLAG_4 0x6C 278 279 /* Enhanced Commands Registers: */ 280 #define ECR_SUBSYSTEM_STAT 0x42E8 281 #define ECR_SUBSYSTEM_CNTL 0x42E8 282 #define ECR_ADV_FUNC_CNTL 0x4AE8 283 #define ECR_CURRENT_Y_POS 0x82E8 284 #define ECR_CURRENT_Y_POS2 0x82EA /* Trio64 only */ 285 #define ECR_CURRENT_X_POS 0x86E8 286 #define ECR_CURRENT_X_POS2 0x86EA /* Trio64 only */ 287 #define ECR_DEST_Y__AX_STEP 0x8AE8 288 #define ECR_DEST_Y2__AX_STEP2 0x8AEA /* Trio64 only */ 289 #define ECR_DEST_X__DIA_STEP 0x8EE8 290 #define ECR_DEST_X2__DIA_STEP2 0x8EEA /* Trio64 only */ 291 #define ECR_ERR_TERM 0x92E8 292 #define ECR_ERR_TERM2 0x92EA /* Trio64 only */ 293 #define ECR_MAJ_AXIS_PIX_CNT 0x96E8 294 #define ECR_MAJ_AXIS_PIX_CNT2 0x96EA /* Trio64 only */ 295 #define ECR_GP_STAT 0x9AE8 /* GP = Graphics Processor */ 296 #define ECR_DRAW_CMD 0x9AE8 297 #define ECR_DRAW_CMD2 0x9AEA /* Trio64 only */ 298 #define ECR_SHORT_STROKE 0x9EE8 299 #define ECR_BKGD_COLOR 0xA2E8 /* BKGD = Background */ 300 #define ECR_FRGD_COLOR 0xA6E8 /* FRGD = Foreground */ 301 #define ECR_BITPLANE_WRITE_MASK 0xAAE8 302 #define ECR_BITPLANE_READ_MASK 0xAEE8 303 #define ECR_COLOR_COMPARE 0xB2E8 304 #define ECR_BKGD_MIX 0xB6E8 305 #define ECR_FRGD_MIX 0xBAE8 306 #define ECR_READ_REG_DATA 0xBEE8 307 #define ECR_ID_MIN_AXIS_PIX_CNT 0x00 308 #define ECR_ID_SCISSORS_TOP 0x01 309 #define ECR_ID_SCISSORS_LEFT 0x02 310 #define ECR_ID_SCISSORS_BUTTOM 0x03 311 #define ECR_ID_SCISSORS_RIGHT 0x04 312 #define ECR_ID_PIX_CNTL 0x0A 313 #define ECR_ID_MULT_CNTL_MISC_2 0x0D 314 #define ECR_ID_MULT_CNTL_MISC 0x0E 315 #define ECR_ID_READ_SEL 0x0F 316 #define ECR_PIX_TRANS 0xE2E8 317 #define ECR_PIX_TRANS_EXT 0xE2EA 318 #define ECR_PATTERN_Y 0xEAE8 /* Trio64 only */ 319 #define ECR_PATTERN_X 0xEAEA /* Trio64 only */ 320 321 322 /* Pass-through */ 323 #define PASS_ADDRESS 0x40001 324 #define PASS_ADDRESS_W 0x40001 325 326 /* Video DAC */ 327 #define VDAC_ADDRESS 0x03c8 328 #define VDAC_ADDRESS_W 0x03c8 329 #define VDAC_ADDRESS_R 0x03c7 330 #define VDAC_STATE 0x03c7 331 #define VDAC_DATA 0x03c9 332 #define VDAC_MASK 0x03c6 333 334 335 #define WGfx(ba, idx, val) \ 336 do { vgaw(ba, GCT_ADDRESS, idx); vgaw(ba, GCT_ADDRESS_W , val); } while (0) 337 338 #define WSeq(ba, idx, val) \ 339 do { vgaw(ba, SEQ_ADDRESS, idx); vgaw(ba, SEQ_ADDRESS_W , val); } while (0) 340 341 #define WCrt(ba, idx, val) \ 342 do { vgaw(ba, CRT_ADDRESS, idx); vgaw(ba, CRT_ADDRESS_W , val); } while (0) 343 344 #define WAttr(ba, idx, val) \ 345 do { \ 346 unsigned char tmp;\ 347 tmp = vgar(ba, ACT_ADDRESS_RESET);\ 348 vgaw(ba, ACT_ADDRESS_W, idx);\ 349 vgaw(ba, ACT_ADDRESS_W, val);\ 350 } while (0) 351 352 353 #define SetTextPlane(ba, m) \ 354 do { \ 355 WGfx(ba, GCT_ID_READ_MAP_SELECT, m & 3 );\ 356 WSeq(ba, SEQ_ID_MAP_MASK, (1 << (m & 3)));\ 357 } while (0) 358 359 360 /* Gfx engine busy wait */ 361 362 static inline void 363 GfxBusyWait (ba) 364 volatile caddr_t ba; 365 { 366 int test; 367 368 do { 369 test = vgar16 (ba, ECR_GP_STAT); 370 asm volatile ("nop"); 371 } while (test & (1 << 9)); 372 } 373 374 375 static inline void 376 GfxFifoWait(ba) 377 volatile caddr_t ba; 378 { 379 int test; 380 381 do { 382 test = vgar16 (ba, ECR_GP_STAT); 383 } while (test & 0x0f); 384 } 385 386 387 /* Special wakeup/passthrough registers on graphics boards 388 * 389 * The methods have diverged a bit for each board, so 390 * WPass(P) has been converted into a set of specific 391 * inline functions. 392 */ 393 394 static inline unsigned char 395 RAttr(ba, idx) 396 volatile caddr_t ba; 397 short idx; 398 { 399 400 vgaw(ba, ACT_ADDRESS_W, idx); 401 delay(0); 402 return vgar(ba, ACT_ADDRESS_R); 403 } 404 405 static inline unsigned char 406 RSeq(ba, idx) 407 volatile caddr_t ba; 408 short idx; 409 { 410 vgaw(ba, SEQ_ADDRESS, idx); 411 return vgar(ba, SEQ_ADDRESS_R); 412 } 413 414 static inline unsigned char 415 RCrt(ba, idx) 416 volatile caddr_t ba; 417 short idx; 418 { 419 vgaw(ba, CRT_ADDRESS, idx); 420 return vgar(ba, CRT_ADDRESS_R); 421 } 422 423 static inline unsigned char 424 RGfx(ba, idx) 425 volatile caddr_t ba; 426 short idx; 427 { 428 vgaw(ba, GCT_ADDRESS, idx); 429 return vgar(ba, GCT_ADDRESS_R); 430 } 431 432 #endif /* _GRF_RHREG_H */ 433 434
Indexes created Thu Sep 25 08:09:54 GMT 2025