grf_etreg.h revision 1.1.4.2
1 /* $NetBSD: grf_etreg.h,v 1.1.4.2 1996/06/11 05:42:07 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Tobias Abt 5 * Copyright (c) 1995 Ezra Story 6 * Copyright (c) 1995 Kari Mettinen 7 * Copyright (c) 1994 Markus Wild 8 * Copyright (c) 1994 Lutz Vieweg 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by Lutz Vieweg. 22 * 4. The name of the author may not be used to endorse or promote products 23 * derived from this software without specific prior written permission 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 27 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 29 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 34 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #ifndef _GRF_ETREG_H 38 #define _GRF_ETREG_H 39 40 /* 41 * Written & Copyright by Kari Mettinen, Ezra Story. 42 * 43 * This is derived from Cirrus driver source 44 */ 45 46 /* Extension to grfvideo_mode to support text modes. 47 * This can be passed to both text & gfx functions 48 * without worry. If gv.depth == 4, then the extended 49 * fields for a text mode are present. 50 */ 51 struct grfettext_mode { 52 struct grfvideo_mode gv; 53 unsigned short fx; /* font x dimension */ 54 unsigned short fy; /* font y dimension */ 55 unsigned short cols; /* screen dimensions */ 56 unsigned short rows; 57 void *fdata; /* font data */ 58 unsigned short fdstart; 59 unsigned short fdend; 60 }; 61 62 63 /* Tseng boards types, stored in ettype in grf_et.c. 64 * used to decide how to handle Pass-through, etc. 65 */ 66 67 #define OMNIBUS 2181 68 #define DOMINO 2167 69 #define MERLIN 2117 70 71 /* VGA controller types */ 72 #define ET4000 0 73 #define ETW32 1 74 75 /* DAC types */ 76 #define SIERRA11483 0 /* Sierra 11483 HiColor DAC */ 77 #define SIERRA15025 1 /* Sierra 15025 TrueColor DAC */ 78 #define MUSICDAC 2 /* MUSIC TrueColor DAC */ 79 #define MERLINDAC 3 /* Merlin's BrookTree TrueColor DAC */ 80 81 /* read VGA register */ 82 #define vgar(ba, reg) (*(((volatile unsigned char *)ba)+reg)) 83 84 /* write VGA register */ 85 #define vgaw(ba, reg, val) \ 86 *(((volatile unsigned char *)ba)+reg) = ((unsigned char)val) 87 88 /* 89 * defines for the used register addresses (mw) 90 * 91 * NOTE: there are some registers that have different addresses when 92 * in mono or color mode. We only support color mode, and thus 93 * some addresses won't work in mono-mode! 94 * 95 * General and VGA-registers taken from retina driver. Fixed a few 96 * bugs in it. (SR and GR read address is Port + 1, NOT Port) 97 * 98 */ 99 100 /* General Registers: */ 101 #define GREG_STATUS0_R 0x03C2 102 #define GREG_STATUS1_R 0x03DA 103 #define GREG_MISC_OUTPUT_R 0x03CC 104 #define GREG_MISC_OUTPUT_W 0x03C2 105 #define GREG_FEATURE_CONTROL_R 0x03CA 106 #define GREG_FEATURE_CONTROL_W 0x03DA 107 #define GREG_POS 0x0102 108 #define GREG_HERCULESCOMPAT 0x03BF 109 #define GREG_VIDEOSYSENABLE 0x03C3 110 #define GREG_DISPMODECONTROL 0x03D8 111 #define GREG_COLORSELECT 0x03D9 112 #define GREG_ATNTMODECONTROL 0x03DE 113 #define GREG_SEGMENTSELECT 0x03CD 114 115 /* ETW32 special */ 116 #define W32mappedRegs 0xfff00 117 118 /* MMU */ 119 #define MMU_APERTURE0 0x80000 120 #define MMU_APERTURE1 0xa0000 121 #define MMU_APERTURE2 0xc0000 122 123 /* Accellerator */ 124 125 /* Attribute Controller: */ 126 #define ACT_ADDRESS 0x03C0 127 #define ACT_ADDRESS_R 0x03C1 128 #define ACT_ADDRESS_W 0x03C0 129 #define ACT_ADDRESS_RESET 0x03DA 130 #define ACT_ID_PALETTE0 0x00 131 #define ACT_ID_PALETTE1 0x01 132 #define ACT_ID_PALETTE2 0x02 133 #define ACT_ID_PALETTE3 0x03 134 #define ACT_ID_PALETTE4 0x04 135 #define ACT_ID_PALETTE5 0x05 136 #define ACT_ID_PALETTE6 0x06 137 #define ACT_ID_PALETTE7 0x07 138 #define ACT_ID_PALETTE8 0x08 139 #define ACT_ID_PALETTE9 0x09 140 #define ACT_ID_PALETTE10 0x0A 141 #define ACT_ID_PALETTE11 0x0B 142 #define ACT_ID_PALETTE12 0x0C 143 #define ACT_ID_PALETTE13 0x0D 144 #define ACT_ID_PALETTE14 0x0E 145 #define ACT_ID_PALETTE15 0x0F 146 #define ACT_ID_ATTR_MODE_CNTL 0x10 147 #define ACT_ID_OVERSCAN_COLOR 0x11 148 #define ACT_ID_COLOR_PLANE_ENA 0x12 149 #define ACT_ID_HOR_PEL_PANNING 0x13 150 #define ACT_ID_COLOR_SELECT 0x14 151 #define ACT_ID_MISCELLANEOUS 0x16 152 153 /* Graphics Controller: */ 154 #define GCT_ADDRESS 0x03CE 155 #define GCT_ADDRESS_R 0x03CF 156 #define GCT_ADDRESS_W 0x03CF 157 #define GCT_ID_SET_RESET 0x00 158 #define GCT_ID_ENABLE_SET_RESET 0x01 159 #define GCT_ID_COLOR_COMPARE 0x02 160 #define GCT_ID_DATA_ROTATE 0x03 161 #define GCT_ID_READ_MAP_SELECT 0x04 162 #define GCT_ID_GRAPHICS_MODE 0x05 163 #define GCT_ID_MISC 0x06 164 #define GCT_ID_COLOR_XCARE 0x07 165 #define GCT_ID_BITMASK 0x08 166 167 /* Sequencer: */ 168 #define SEQ_ADDRESS 0x03C4 169 #define SEQ_ADDRESS_R 0x03C5 170 #define SEQ_ADDRESS_W 0x03C5 171 #define SEQ_ID_RESET 0x00 172 #define SEQ_ID_CLOCKING_MODE 0x01 173 #define SEQ_ID_MAP_MASK 0x02 174 #define SEQ_ID_CHAR_MAP_SELECT 0x03 175 #define SEQ_ID_MEMORY_MODE 0x04 176 #define SEQ_ID_STATE_CONTROL 0x06 177 #define SEQ_ID_AUXILIARY_MODE 0x07 178 179 /* don't know about them right now... 180 #define TEXT_PLANE_CHAR 0x01 181 #define TEXT_PLANE_ATTR 0x02 182 #define TEXT_PLANE_FONT 0x04 183 */ 184 185 /* CRT Controller: */ 186 #define CRT_ADDRESS 0x03D4 187 #define CRT_ADDRESS_R 0x03D5 188 #define CRT_ADDRESS_W 0x03D5 189 #define CRT_ID_HOR_TOTAL 0x00 190 #define CRT_ID_HOR_DISP_ENA_END 0x01 191 #define CRT_ID_START_HOR_BLANK 0x02 192 #define CRT_ID_END_HOR_BLANK 0x03 193 #define CRT_ID_START_HOR_RETR 0x04 194 #define CRT_ID_END_HOR_RETR 0x05 195 #define CRT_ID_VER_TOTAL 0x06 196 #define CRT_ID_OVERFLOW 0x07 197 #define CRT_ID_PRESET_ROW_SCAN 0x08 198 #define CRT_ID_MAX_ROW_ADDRESS 0x09 199 #define CRT_ID_CURSOR_START 0x0A 200 #define CRT_ID_CURSOR_END 0x0B 201 #define CRT_ID_START_ADDR_HIGH 0x0C 202 #define CRT_ID_START_ADDR_LOW 0x0D 203 #define CRT_ID_CURSOR_LOC_HIGH 0x0E 204 #define CRT_ID_CURSOR_LOC_LOW 0x0F 205 #define CRT_ID_START_VER_RETR 0x10 206 #define CRT_ID_END_VER_RETR 0x11 207 #define CRT_ID_VER_DISP_ENA_END 0x12 208 #define CRT_ID_OFFSET 0x13 209 #define CRT_ID_UNDERLINE_LOC 0x14 210 #define CRT_ID_START_VER_BLANK 0x15 211 #define CRT_ID_END_VER_BLANK 0x16 212 #define CRT_ID_MODE_CONTROL 0x17 213 #define CRT_ID_LINE_COMPARE 0x18 214 215 #define CRT_ID_SEGMENT_COMP 0x30 216 #define CRT_ID_GENERAL_PURPOSE 0x31 217 #define CRT_ID_RASCAS_CONFIG 0x32 218 #define CTR_ID_EXT_START 0x33 219 #define CRT_ID_6845_COMPAT 0x34 220 #define CRT_ID_OVERFLOW_HIGH 0x35 221 #define CRT_ID_VIDEO_CONFIG1 0x36 222 #define CRT_ID_VIDEO_CONFIG2 0x37 223 #define CRT_ID_HOR_OVERFLOW 0x3f 224 225 /* IMAGE port */ 226 #define IMA_ADDRESS 0x217a 227 #define IMA_ADDRESS_R 0x217b 228 #define IMA_ADDRESS_W 0x217b 229 #define IMA_STARTADDRESSLOW 0xf0 230 #define IMA_STARTADDRESSMIDDLE 0xf1 231 #define IMA_STARTADDRESSHIGH 0xf2 232 #define IMA_TRANSFERLENGTHLOW 0xf3 233 #define IMA_TRANSFERLENGTHHIGH 0xf4 234 #define IMA_ROWOFFSETLOW 0xf5 235 #define IMA_ROWOFFSETHIGH 0xf6 236 #define IMA_PORTCONTROL 0xf7 237 238 /* Pass-through */ 239 #define PASS_ADDRESS 0x8000 240 #define PASS_ADDRESS_W 0x8000 241 #define PASS_ADDRESS_DOM 0xa000 242 #define PASS_ADDRESS_DOMW 0xb000 243 244 /* Video DAC */ 245 #define VDAC_ADDRESS 0x03c8 246 #define VDAC_ADDRESS_W 0x03c8 247 #define VDAC_ADDRESS_R 0x03c7 248 #define VDAC_STATE 0x03c7 249 #define VDAC_DATA 0x03c9 250 #define VDAC_MASK 0x03c6 251 #define HDR 0x03c6 /* Hidden DAC register, 4 reads to access */ 252 253 #define VDAC_COMMAND 0x03c6 254 #define VDAC_XINDEX 0x03c7 255 #define VDAC_XDATA 0x03c8 256 257 #define MERLIN_VDAC_INDEX 0x01 258 #define MERLIN_VDAC_COLORS 0x05 259 #define MERLIN_VDAC_SPRITE 0x09 260 #define MERLIN_VDAC_DATA 0x19 261 #define MERLIN_SWITCH_REG 0x0401 262 263 #define WGfx(ba, idx, val) \ 264 do { vgaw(ba, GCT_ADDRESS, idx); vgaw(ba, GCT_ADDRESS_W , val); } while (0) 265 266 #define WSeq(ba, idx, val) \ 267 do { vgaw(ba, SEQ_ADDRESS, idx); vgaw(ba, SEQ_ADDRESS_W , val); } while (0) 268 269 #define WCrt(ba, idx, val) \ 270 do { vgaw(ba, CRT_ADDRESS, idx); vgaw(ba, CRT_ADDRESS_W , val); } while (0) 271 272 #define WIma(ba, idx, val) \ 273 do { vgaw(ba, IMA_ADDRESS, idx); vgaw(ba, IMA_ADDRESS_W , val); } while (0) 274 275 #define WAttr(ba, idx, val) \ 276 do { \ 277 if(vgar(ba, GREG_STATUS1_R));\ 278 vgaw(ba, ACT_ADDRESS_W, idx);\ 279 vgaw(ba, ACT_ADDRESS_W, val);\ 280 } while (0) 281 282 #define SetTextPlane(ba, m) \ 283 do { \ 284 WGfx(ba, GCT_ID_READ_MAP_SELECT, m & 3 );\ 285 WSeq(ba, SEQ_ID_MAP_MASK, (1 << (m & 3)));\ 286 } while (0) 287 288 #define setMerlinDACmode(ba, mode) \ 289 do { \ 290 vgaw(ba, VDAC_MASK, mode | (vgar(ba, VDAC_MASK) & 0x0f));\ 291 } while (0) 292 293 /* Special wakeup/passthrough registers on graphics boards 294 * 295 * The methods have diverged a bit for each board, so 296 * WPass(P) has been converted into a set of specific 297 * inline functions. 298 */ 299 static inline void RegWakeup(volatile void *ba) { 300 extern int ettype; 301 302 switch (ettype) { 303 case OMNIBUS: 304 vgaw(ba, PASS_ADDRESS_W, 0x00); 305 break; 306 case DOMINO: 307 vgaw(ba, PASS_ADDRESS_DOM, 0x00); 308 break; 309 case MERLIN: 310 break; 311 } 312 delay(200000); 313 } 314 315 316 static inline void RegOnpass(volatile void *ba) { 317 extern int ettype; 318 extern unsigned char pass_toggle; 319 extern unsigned char Merlin_switch; 320 321 switch (ettype) { 322 case OMNIBUS: 323 vgaw(ba, PASS_ADDRESS_W, 0x00); 324 break; 325 case DOMINO: 326 vgaw(ba, PASS_ADDRESS_DOMW, 0x00); 327 break; 328 case MERLIN: 329 Merlin_switch &= 0xfe; 330 vgaw(ba, MERLIN_SWITCH_REG, Merlin_switch); 331 break; 332 } 333 pass_toggle = 1; 334 delay(200000); 335 } 336 337 338 static inline void RegOffpass(volatile void *ba) { 339 extern int ettype; 340 extern unsigned char pass_toggle; 341 extern unsigned char Merlin_switch; 342 343 switch (ettype) { 344 case OMNIBUS: 345 vgaw(ba, PASS_ADDRESS_W, 0x01); 346 break; 347 case DOMINO: 348 vgaw(ba, PASS_ADDRESS_DOM, 0x00); 349 break; 350 case MERLIN: 351 Merlin_switch |= 0x01; 352 vgaw(ba, MERLIN_SWITCH_REG, Merlin_switch); 353 break; 354 } 355 pass_toggle = 0; 356 delay(200000); 357 } 358 359 static inline unsigned char RAttr(volatile void * ba, short idx) { 360 if(vgar(ba, GREG_STATUS1_R)); 361 vgaw(ba, ACT_ADDRESS_W, idx); 362 return vgar (ba, ACT_ADDRESS_R); 363 } 364 365 static inline unsigned char RSeq(volatile void * ba, short idx) { 366 vgaw (ba, SEQ_ADDRESS, idx); 367 return vgar (ba, SEQ_ADDRESS_R); 368 } 369 370 static inline unsigned char RCrt(volatile void * ba, short idx) { 371 vgaw (ba, CRT_ADDRESS, idx); 372 return vgar (ba, CRT_ADDRESS_R); 373 } 374 375 static inline unsigned char RGfx(volatile void * ba, short idx) { 376 vgaw(ba, GCT_ADDRESS, idx); 377 return vgar (ba, GCT_ADDRESS_R); 378 } 379 380 int et_mode __P((register struct grf_softc *gp, u_long cmd, void *arg, u_long a2, int a3)); 381 int et_load_mon __P((struct grf_softc *gp, struct grfettext_mode *gv)); 382 int grfet_cnprobe __P((void)); 383 void grfet_iteinit __P((struct grf_softc *gp)); 384 385 #endif /* _GRF_ETREG_H */ 386
Indexes created Tue Oct 14 15:09:51 GMT 2025