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grf_rtreg.h revision 1.1
      1  1.1  mw #ifndef _GRF_RTREG_H
      2  1.1  mw #define _GRF_RTREG_H
      3  1.1  mw 
      4  1.1  mw /* NOTE: this driver for the MacroSystem Retina board was only possible,
      5  1.1  mw          because MacroSystem provided information about the pecularities
      6  1.1  mw          of the board. THANKS! Competition in Europe among gfx board
      7  1.1  mw          manufacturers is rather tough, so Lutz Vieweg, who wrote the
      8  1.1  mw          initial driver, has made an agreement with MS not to document
      9  1.1  mw          the driver source (see also his Copyright disclaimer at the
     10  1.1  mw          beginning of grf_rt.cc and ite_rt.cc).
     11  1.1  mw          -> ALL comments and register defines after
     12  1.1  mw 	 -> "/* -------------- START OF CODE -------------- * /"
     13  1.1  mw 	 -> have been added by myself (mw) from studying the publically
     14  1.1  mw 	 -> available "NCR 77C22E+" Data Manual
     15  1.1  mw 
     16  1.1  mw 	 Lutz' original driver source (without any of my comments) is
     17  1.1  mw 	 available on request. */
     18  1.1  mw 
     19  1.1  mw 
     20  1.1  mw #if 0
     21  1.1  mw /* these are in dev/devices.h */
     22  1.1  mw 
     23  1.1  mw /* definitions to find the autoconfig-board under
     24  1.1  mw    AmigaDOS */
     25  1.1  mw 
     26  1.1  mw #define RETINA_MANUFACTURER     0x4754
     27  1.1  mw #define RETINA_PRODUCT          6
     28  1.1  mw #define RETINA_SERIALNUMBER     1
     29  1.1  mw #endif
     30  1.1  mw 
     31  1.1  mw 
     32  1.1  mw /*
     33  1.1  mw    For more information on the structure entries take a look at
     34  1.1  mw    grf_rt.cc and ite_rt.cc.
     35  1.1  mw */
     36  1.1  mw 
     37  1.1  mw struct MonDef {
     38  1.1  mw 
     39  1.1  mw 	/* first the general monitor characteristics */
     40  1.1  mw 
     41  1.1  mw 	unsigned long  FQ;
     42  1.1  mw 	unsigned char  FLG;
     43  1.1  mw 
     44  1.1  mw 	unsigned short MW;  /* screen width in pixels */
     45  1.1  mw 	unsigned short MH;  /* screen height in pixels */
     46  1.1  mw 
     47  1.1  mw 	unsigned short HBS;
     48  1.1  mw 	unsigned short HSS;
     49  1.1  mw 	unsigned short HSE;
     50  1.1  mw 	unsigned short HBE;
     51  1.1  mw 	unsigned short HT;
     52  1.1  mw 	unsigned short VBS;
     53  1.1  mw 	unsigned short VSS;
     54  1.1  mw 	unsigned short VSE;
     55  1.1  mw 	unsigned short VBE;
     56  1.1  mw 	unsigned short VT;
     57  1.1  mw 
     58  1.1  mw 	unsigned short DEP;  /* Color-depth, 4 for text-mode */
     59  1.1  mw 	                     /* values != 4 currently not supported */
     60  1.1  mw 
     61  1.1  mw 	unsigned char * PAL; /* points to n*3 byte RGB-palette data */
     62  1.1  mw 	                     /* n=16 for the text-mode */
     63  1.1  mw 
     64  1.1  mw 	/* all following entries are text-specific in
     65  1.1  mw 	   any way. Make sure your monitor
     66  1.1  mw 	   parameters are calculated for the
     67  1.1  mw 	   appropriate font width and height!
     68  1.1  mw 	*/
     69  1.1  mw 
     70  1.1  mw 	unsigned short  TX;     /* screen-width  in characters */
     71  1.1  mw 	                        /* currently, TX has to be a   */
     72  1.1  mw 	                        /* multiple of 16!             */
     73  1.1  mw 	unsigned short  TY;     /* screen-height in characters */
     74  1.1  mw 	unsigned short  XY;     /* TX*TY (speeds up some calcs.) */
     75  1.1  mw 
     76  1.1  mw 	unsigned short  FX;     /* font-width (valid values: 4,7-16) */
     77  1.1  mw 	unsigned short  FY;     /* font-height (valid range: 1-32) */
     78  1.1  mw 	unsigned char * FData;  /* pointer to the font-data */
     79  1.1  mw 
     80  1.1  mw 	/* The font data is simply an array of bytes defining
     81  1.1  mw 	   the chars in ascending order, line by line. If your
     82  1.1  mw 	   font is wider than 8 pixel, FData has to be an
     83  1.1  mw 	   array of words. */
     84  1.1  mw 
     85  1.1  mw 	unsigned short  FLo;    /* lowest character defined */
     86  1.1  mw 	unsigned short  FHi;    /* highest char. defined */
     87  1.1  mw 
     88  1.1  mw };
     89  1.1  mw 
     90  1.1  mw 
     91  1.1  mw #if 0
     92  1.1  mw /* Some ready-made MonDef structures are available in grf_rt.cc */
     93  1.1  mw 
     94  1.1  mw extern struct MonDef MON_640_512_60;
     95  1.1  mw extern struct MonDef MON_768_600_60;
     96  1.1  mw extern struct MonDef MON_768_600_80;
     97  1.1  mw 
     98  1.1  mw /* text-screen resolutions wider than 1024 are currently damaged.
     99  1.1  mw    The VRAM access seems to become unstable at higher resolutions.
    100  1.1  mw    This may hopefully be subject of change.
    101  1.1  mw */
    102  1.1  mw 
    103  1.1  mw extern struct MonDef MON_1024_768_80;
    104  1.1  mw extern struct MonDef MON_1024_1024_59;
    105  1.1  mw 
    106  1.1  mw /* WARNING: THE FOLLOWING MONITOR MODES EXCEED THE 90-MHz LIMIT THE PROCESSOR
    107  1.1  mw             HAS BEEN SPECIFIED FOR. USE AT YOUR OWN RISK (AND THINK ABOUT
    108  1.1  mw             MOUNTING SOME COOLING DEVICE AT THE PROCESSOR AND RAMDAC)!     */
    109  1.1  mw extern struct MonDef MON_1280_1024_60;
    110  1.1  mw extern struct MonDef MON_1280_1024_69;
    111  1.1  mw 
    112  1.1  mw /* Default monitor (change if this is too much for your monitor :-)) */
    113  1.1  mw #define DEFAULT_MONDEF	MON_768_600_80
    114  1.1  mw 
    115  1.1  mw #else
    116  1.1  mw 
    117  1.1  mw /* nothing exported for now... */
    118  1.1  mw 
    119  1.1  mw #endif
    120  1.1  mw 
    121  1.1  mw /* a standard 16-color palette is available in grf_rt.cc
    122  1.1  mw    and used by the standard monitor-definitions above */
    123  1.1  mw extern unsigned char NCRStdPalette[];
    124  1.1  mw 
    125  1.1  mw /* The prototypes for C
    126  1.1  mw    with a little explanation
    127  1.1  mw 
    128  1.1  mw 	unsigned char * InitNCR(volatile void * BoardAdress, struct MonDef * md = &MON_640_512_60);
    129  1.1  mw 
    130  1.1  mw    This routine initialises the Retina hardware, opens a
    131  1.1  mw    text-mode screen, and sets the cursor to position 0.
    132  1.1  mw    The routine returns 0 if it was unable to open the screen,
    133  1.1  mw    or an unsigned char * to the display/attribute memory
    134  1.1  mw    when it succeeded. The organisation of the display memory
    135  1.1  mw    is a little strange (Intel-typically...) :
    136  1.1  mw 
    137  1.1  mw    Byte  00    01    02    03    04     05    06   etc.
    138  1.1  mw        Char0  Attr0  --    --   Char1 Attr1   --   etc.
    139  1.1  mw 
    140  1.1  mw    You may set a character and its associated attribute byte
    141  1.1  mw    with a single word-access, or you may perform to byte writes
    142  1.1  mw    for the char and attribute. Each 2. word has no meaning,
    143  1.1  mw    and writes to theese locations are ignored.
    144  1.1  mw 
    145  1.1  mw    The attribute byte for each character has the following
    146  1.1  mw    structure:
    147  1.1  mw 
    148  1.1  mw    Bit  7     6     5     4     3     2     1     0
    149  1.1  mw       BLINK BACK2 BACK1 BACK0 FORE3 FORE2 FORE1 FORE0
    150  1.1  mw 
    151  1.1  mw    Were FORE is the foreground-color index (0-15) and
    152  1.1  mw    BACK is the background color index (0-7). BLINK
    153  1.1  mw    enables blinking for the associated character.
    154  1.1  mw    The higher 8 colors in the standard palette are
    155  1.1  mw    lighter than the lower 8, so you may see FORE3 as
    156  1.1  mw    an intensity bit. If FORE == 1 or FORE == 9 and
    157  1.1  mw    BACK == 0 the character is underlined. Since I don't
    158  1.1  mw    think this looks good, it will probably change in a
    159  1.1  mw    future release.
    160  1.1  mw 
    161  1.1  mw    There's no routine "SetChar" or "SetAttr" provided,
    162  1.1  mw    because I think it's so trivial... a function call
    163  1.1  mw    would be pure overhead. As an example, a routine
    164  1.1  mw    to set the char code and attribute at position x,y:
    165  1.1  mw    (assumed the value returned by InitNCR was stored
    166  1.1  mw     into "DispMem", the actual MonDef struct * is hold
    167  1.1  mw     in "MDef")
    168  1.1  mw 
    169  1.1  mw    void SetChar(unsigned char chr, unsigned char attr,
    170  1.1  mw                 unsigned short x, unsigned short y) {
    171  1.1  mw 
    172  1.1  mw       unsigned struct MonDef * md = MDef;
    173  1.1  mw       unsigned char * c = DispMem + x*4 + y*md->TX*4;
    174  1.1  mw 
    175  1.1  mw       *c++ = chr;
    176  1.1  mw       *c++ = attr;
    177  1.1  mw    }
    178  1.1  mw 
    179  1.1  mw    Currently, InitNCR() disables the Retina VBLANK IRQ,
    180  1.1  mw    but beware: When running the Retina WB-Emu under
    181  1.1  mw    AmigaDOS, the VBLANK IRQ is ENABLED.
    182  1.1  mw 
    183  1.1  mw 
    184  1.1  mw 
    185  1.1  mw 	void SetCursorPos(unsigned short pos);
    186  1.1  mw 
    187  1.1  mw    This routine sets the hardware-cursor position
    188  1.1  mw    to the screen location pos. pos can be calculated
    189  1.1  mw    as (x + y * md->TY).
    190  1.1  mw 
    191  1.1  mw 
    192  1.1  mw 	void ScreenUp(void);
    193  1.1  mw 
    194  1.1  mw    A somewhat optimized routine that scrolls the whole
    195  1.1  mw    screen up one row. A good idea to compile this piece
    196  1.1  mw    of code with optimization enabled.
    197  1.1  mw 
    198  1.1  mw 
    199  1.1  mw 	void ScreenDown(void);
    200  1.1  mw 
    201  1.1  mw    A somewhat optimized routine that scrolls the whole
    202  1.1  mw    screen down one row. A good idea to compile this piece
    203  1.1  mw    of code with optimization enabled.
    204  1.1  mw */
    205  1.1  mw 
    206  1.1  mw /* -------------- START OF CODE -------------- */
    207  1.1  mw 
    208  1.1  mw /* read VGA register */
    209  1.1  mw #define vgar(ba, reg) (*(((volatile unsigned char *)ba)+reg))
    210  1.1  mw 
    211  1.1  mw /* write VGA register */
    212  1.1  mw #define vgaw(ba, reg, val) \
    213  1.1  mw 	*(((volatile unsigned char *)ba)+reg) = val
    214  1.1  mw 
    215  1.1  mw /* defines for the used register addresses (mw)
    216  1.1  mw 
    217  1.1  mw    NOTE: there are some registers that have different addresses when
    218  1.1  mw          in mono or color mode. We only support color mode, and thus
    219  1.1  mw          some addresses won't work in mono-mode! */
    220  1.1  mw 
    221  1.1  mw /* General Registers: */
    222  1.1  mw #define GREG_STATUS0_R		0x43C2
    223  1.1  mw #define GREG_STATUS1_R		0x43DA
    224  1.1  mw #define GREG_MISC_OUTPUT_R	0x43CC
    225  1.1  mw #define GREG_MISC_OUTPUT_W	0x43C2
    226  1.1  mw #define GREG_FEATURE_CONTROL_R	0x43CA
    227  1.1  mw #define GREG_FEATURE_CONTROL_W	0x43DA
    228  1.1  mw #define GREG_POS		0x4102
    229  1.1  mw 
    230  1.1  mw /* Attribute Controller: */
    231  1.1  mw #define ACT_ADDRESS		0x43C0
    232  1.1  mw #define ACT_ADDRESS_R		0x03C0
    233  1.1  mw #define ACT_ADDRESS_W		0x43C0
    234  1.1  mw #define ACT_ID_PALETTE0		0x00
    235  1.1  mw #define ACT_ID_PALETTE1		0x01
    236  1.1  mw #define ACT_ID_PALETTE2		0x02
    237  1.1  mw #define ACT_ID_PALETTE3		0x03
    238  1.1  mw #define ACT_ID_PALETTE4		0x04
    239  1.1  mw #define ACT_ID_PALETTE5		0x05
    240  1.1  mw #define ACT_ID_PALETTE6		0x06
    241  1.1  mw #define ACT_ID_PALETTE7		0x07
    242  1.1  mw #define ACT_ID_PALETTE8		0x08
    243  1.1  mw #define ACT_ID_PALETTE9		0x09
    244  1.1  mw #define ACT_ID_PALETTE10	0x0A
    245  1.1  mw #define ACT_ID_PALETTE11	0x0B
    246  1.1  mw #define ACT_ID_PALETTE12	0x0C
    247  1.1  mw #define ACT_ID_PALETTE13	0x0D
    248  1.1  mw #define ACT_ID_PALETTE14	0x0E
    249  1.1  mw #define ACT_ID_PALETTE15	0x0F
    250  1.1  mw #define ACT_ID_ATTR_MODE_CNTL	0x10
    251  1.1  mw #define ACT_ID_OVERSCAN_COLOR	0x11
    252  1.1  mw #define ACT_ID_COLOR_PLANE_ENA	0x12
    253  1.1  mw #define ACT_ID_HOR_PEL_PANNING	0x13
    254  1.1  mw #define ACT_ID_COLOR_SELECT	0x14
    255  1.1  mw 
    256  1.1  mw /* Graphics Controller: */
    257  1.1  mw #define GCT_ADDRESS		0x43CE
    258  1.1  mw #define GCT_ADDRESS_R		0x03CE
    259  1.1  mw #define GCT_ADDRESS_W		0x03CE
    260  1.1  mw #define GCT_ID_SET_RESET	0x00
    261  1.1  mw #define GCT_ID_ENABLE_SET_RESET	0x01
    262  1.1  mw #define GCT_ID_COLOR_COMPARE	0x02
    263  1.1  mw #define GCT_ID_DATA_ROTATE	0x03
    264  1.1  mw #define GCT_ID_READ_MAP_SELECT	0x04
    265  1.1  mw #define GCT_ID_GRAPHICS_MODE	0x05
    266  1.1  mw #define GCT_ID_MISC		0x06
    267  1.1  mw #define GCT_ID_COLOR_XCARE	0x07
    268  1.1  mw #define GCT_ID_BITMASK		0x08
    269  1.1  mw 
    270  1.1  mw /* Sequencer: */
    271  1.1  mw #define SEQ_ADDRESS		0x43C4
    272  1.1  mw #define SEQ_ADDRESS_R		0x03C4
    273  1.1  mw #define SEQ_ADDRESS_W		0x03C4
    274  1.1  mw #define SEQ_ID_RESET		0x00
    275  1.1  mw #define SEQ_ID_CLOCKING_MODE	0x01
    276  1.1  mw #define SEQ_ID_MAP_MASK		0x02
    277  1.1  mw #define SEQ_ID_CHAR_MAP_SELECT	0x03
    278  1.1  mw #define SEQ_ID_MEMORY_MODE	0x04
    279  1.1  mw #define SEQ_ID_EXTENDED_ENABLE	0x05	/* down from here, all seq registers are NCR extensions */
    280  1.1  mw #define SEQ_ID_CHIP_ID		0x08
    281  1.1  mw #define SEQ_ID_CURSOR_COLOR1	0x0A
    282  1.1  mw #define SEQ_ID_CURSOR_COLOR0	0x0B
    283  1.1  mw #define SEQ_ID_CURSOR_CONTROL	0x0C
    284  1.1  mw #define SEQ_ID_CURSOR_X_LOC_HI	0x0D
    285  1.1  mw #define SEQ_ID_CURSOR_X_LOC_LO	0x0E
    286  1.1  mw #define SEQ_ID_CURSOR_Y_LOC_HI	0x0F
    287  1.1  mw #define SEQ_ID_CURSOR_Y_LOC_LO	0x10
    288  1.1  mw #define SEQ_ID_CURSOR_X_INDEX	0x11
    289  1.1  mw #define SEQ_ID_CURSOR_Y_INDEX	0x12
    290  1.1  mw #define SEQ_ID_CURSOR_STORE_LO	0x14
    291  1.1  mw #define SEQ_ID_CURSOR_STORE_HI	0x15
    292  1.1  mw #define SEQ_ID_CURSOR_STORE_MID	0x16
    293  1.1  mw #define SEQ_ID_CURSOR_PIXELMASK	0x17
    294  1.1  mw #define SEQ_ID_PRIM_HOST_OFF_HI	0x18
    295  1.1  mw #define SEQ_ID_PRIM_HOST_OFF_LO	0x19
    296  1.1  mw #define SEQ_ID_SEC_HOST_OFF_HI	0x1C
    297  1.1  mw #define SEQ_ID_SEC_HOST_OFF_LO	0x1D
    298  1.1  mw #define SEQ_ID_EXTENDED_MEM_ENA	0x1E
    299  1.1  mw #define SEQ_ID_EXT_CLOCK_MODE	0x1F
    300  1.1  mw #define SEQ_ID_EXT_VIDEO_ADDR	0x20
    301  1.1  mw #define SEQ_ID_EXT_PIXEL_CNTL	0x21
    302  1.1  mw #define SEQ_ID_BUS_WIDTH_FEEDB	0x22
    303  1.1  mw #define SEQ_ID_PERF_SELECT	0x23
    304  1.1  mw #define SEQ_ID_COLOR_EXP_WFG	0x24
    305  1.1  mw #define SEQ_ID_COLOR_EXP_WBG	0x25
    306  1.1  mw #define SEQ_ID_EXT_RW_CONTROL	0x26
    307  1.1  mw #define SEQ_ID_MISC_FEATURE_SEL	0x27
    308  1.1  mw #define SEQ_ID_COLOR_KEY_CNTL	0x28
    309  1.1  mw #define SEQ_ID_COLOR_KEY_MATCH	0x29
    310  1.1  mw #define SEQ_ID_CRC_CONTROL	0x2D
    311  1.1  mw #define SEQ_ID_CRC_DATA_LOW	0x2E
    312  1.1  mw #define SEQ_ID_CRC_DATA_HIGH	0x2F
    313  1.1  mw 
    314  1.1  mw /* CRT Controller: */
    315  1.1  mw #define CRT_ADDRESS		0x43D4
    316  1.1  mw #define CRT_ADDRESS_R		0x03D4
    317  1.1  mw #define CRT_ADDRESS_W		0x03D4
    318  1.1  mw #define CRT_ID_HOR_TOTAL	0x00
    319  1.1  mw #define CRT_ID_HOR_DISP_ENA_END	0x01
    320  1.1  mw #define CRT_ID_START_HOR_BLANK	0x02
    321  1.1  mw #define CRT_ID_END_HOR_BLANK	0x03
    322  1.1  mw #define CRT_ID_START_HOR_RETR	0x04
    323  1.1  mw #define CRT_ID_END_HOR_RETR	0x05
    324  1.1  mw #define CRT_ID_VER_TOTAL	0x06
    325  1.1  mw #define CRT_ID_OVERFLOW		0x07
    326  1.1  mw #define CRT_ID_PRESET_ROW_SCAN	0x08
    327  1.1  mw #define CRT_ID_MAX_SCAN_LINE	0x09
    328  1.1  mw #define CRT_ID_CURSOR_START	0x0A
    329  1.1  mw #define CRT_ID_CURSOR_END	0x0B
    330  1.1  mw #define CRT_ID_START_ADDR_HIGH	0x0C
    331  1.1  mw #define CRT_ID_START_ADDR_LOW	0x0D
    332  1.1  mw #define CRT_ID_CURSOR_LOC_HIGH	0x0E
    333  1.1  mw #define CRT_ID_CURSOR_LOC_LOW	0x0F
    334  1.1  mw #define CRT_ID_START_VER_RETR	0x10
    335  1.1  mw #define CRT_ID_END_VER_RETR	0x11
    336  1.1  mw #define CRT_ID_VER_DISP_ENA_END	0x12
    337  1.1  mw #define CRT_ID_OFFSET		0x13
    338  1.1  mw #define CRT_ID_UNDERLINE_LOC	0x14
    339  1.1  mw #define CRT_ID_START_VER_BLANK	0x15
    340  1.1  mw #define CRT_ID_END_VER_BLANK	0x16
    341  1.1  mw #define CRT_ID_MODE_CONTROL	0x17
    342  1.1  mw #define CRT_ID_LINE_COMPARE	0x18
    343  1.1  mw #define CRT_ID_EXT_HOR_TIMING1	0x30	/* down from here, all crt registers are NCR extensions */
    344  1.1  mw #define CRT_ID_EXT_START_ADDR	0x31
    345  1.1  mw #define CRT_ID_EXT_HOR_TIMING2	0x32
    346  1.1  mw #define CRT_ID_EXT_VER_TIMING	0x33
    347  1.1  mw 
    348  1.1  mw /* Video DAC (these are *pure* guesses from the usage of these registers,
    349  1.1  mw    I don't have a data sheet for this chip:-/) */
    350  1.1  mw #define VDAC_REG_D		0x800d	/* well.. */
    351  1.1  mw #define VDAC_REG_SELECT		0x8001	/* perhaps.. */
    352  1.1  mw #define VDAC_REG_DATA		0x8003	/* dito.. */
    353  1.1  mw 
    354  1.1  mw #define WGfx(ba, idx, val) \
    355  1.1  mw 	vgaw(ba, GCT_ADDRESS, idx);\
    356  1.1  mw 	vgaw(ba, GCT_ADDRESS_W , val)\
    357  1.1  mw 
    358  1.1  mw #define WSeq(ba, idx, val)\
    359  1.1  mw 	vgaw(ba, SEQ_ADDRESS, idx);\
    360  1.1  mw 	vgaw(ba, SEQ_ADDRESS_W , val)
    361  1.1  mw 
    362  1.1  mw #define WCrt(ba, idx, val)\
    363  1.1  mw 	vgaw(ba, CRT_ADDRESS, idx);\
    364  1.1  mw 	vgaw(ba, CRT_ADDRESS_W , val)
    365  1.1  mw 
    366  1.1  mw #define WAttr(ba, idx, val)\
    367  1.1  mw 	vgaw(ba, ACT_ADDRESS, idx);\
    368  1.1  mw 	vgaw(ba, ACT_ADDRESS_W, val)
    369  1.1  mw 
    370  1.1  mw #define Map(m)\
    371  1.1  mw 	WGfx(ba, GCT_ID_READ_MAP_SELECT, m & 3 );\
    372  1.1  mw 	WSeq(ba, SEQ_ID_MAP_MASK, (1 << (m & 3)))\
    373  1.1  mw 
    374  1.1  mw static inline unsigned char RAttr(volatile void * ba, short idx) {
    375  1.1  mw 	vgaw (ba, ACT_ADDRESS, idx);
    376  1.1  mw 	return vgar (ba, ACT_ADDRESS_R);
    377  1.1  mw }
    378  1.1  mw 
    379  1.1  mw static inline unsigned char RSeq(volatile void * ba, short idx) {
    380  1.1  mw 	vgaw (ba, SEQ_ADDRESS, idx);
    381  1.1  mw 	return vgar (ba, SEQ_ADDRESS_R);
    382  1.1  mw }
    383  1.1  mw 
    384  1.1  mw static inline unsigned char RCrt(volatile void * ba, short idx) {
    385  1.1  mw 	vgaw (ba, CRT_ADDRESS, idx);
    386  1.1  mw 	return vgar (ba, CRT_ADDRESS_R);
    387  1.1  mw }
    388  1.1  mw 
    389  1.1  mw static inline unsigned char RGfx(volatile void * ba, short idx) {
    390  1.1  mw 	vgaw(ba, GCT_ADDRESS, idx);
    391  1.1  mw 	return vgar (ba, GCT_ADDRESS_R);
    392  1.1  mw }
    393  1.1  mw 
    394  1.1  mw /* yes I know they don't belong here... */
    395  1.1  mw struct ite_softc;
    396  1.1  mw extern void retina_init (struct ite_softc *ip);
    397  1.1  mw extern void retina_cursor (struct ite_softc *ip, int flag);
    398  1.1  mw extern void retina_deinit (struct ite_softc *ip);
    399  1.1  mw extern void retina_putc (struct ite_softc *ip, int c, int dy, int dx, int mode);
    400  1.1  mw extern void retina_clear (struct ite_softc *ip, int sy, int sx, int h, int w);
    401  1.1  mw extern void retina_scroll (struct ite_softc *ip, int sy, int sx, int count, int dir);
    402  1.1  mw 
    403  1.1  mw #endif /* _GRF_RTREG_H */
    404