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grf_rtreg.h revision 1.7
      1  1.7   veego /*	$NetBSD: grf_rtreg.h,v 1.7 1996/04/21 21:11:23 veego Exp $	*/
      2  1.3  chopps 
      3  1.6  chopps /*
      4  1.6  chopps  * Copyright (c) 1993 Markus Wild
      5  1.6  chopps  * Copyright (c) 1993 Lutz Vieweg
      6  1.6  chopps  * All rights reserved.
      7  1.6  chopps  *
      8  1.6  chopps  * Redistribution and use in source and binary forms, with or without
      9  1.6  chopps  * modification, are permitted provided that the following conditions
     10  1.6  chopps  * are met:
     11  1.6  chopps  * 1. Redistributions of source code must retain the above copyright
     12  1.6  chopps  *    notice, this list of conditions and the following disclaimer.
     13  1.6  chopps  * 2. Redistributions in binary form must reproduce the above copyright
     14  1.6  chopps  *    notice, this list of conditions and the following disclaimer in the
     15  1.6  chopps  *    documentation and/or other materials provided with the distribution.
     16  1.6  chopps  * 3. All advertising materials mentioning features or use of this software
     17  1.6  chopps  *    must display the following acknowledgement:
     18  1.6  chopps  *      This product includes software developed by Lutz Vieweg.
     19  1.6  chopps  * 4. The name of the author may not be used to endorse or promote products
     20  1.6  chopps  *    derived from this software without specific prior written permission
     21  1.6  chopps  *
     22  1.6  chopps  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     23  1.6  chopps  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     24  1.6  chopps  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     25  1.6  chopps  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     26  1.6  chopps  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     27  1.6  chopps  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     28  1.6  chopps  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     29  1.6  chopps  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     30  1.6  chopps  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     31  1.6  chopps  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     32  1.6  chopps  */
     33  1.1      mw #ifndef _GRF_RTREG_H
     34  1.1      mw #define _GRF_RTREG_H
     35  1.1      mw 
     36  1.6  chopps /*
     37  1.6  chopps  * This driver for the MacroSystem Retina board was only possible,
     38  1.6  chopps  * because MacroSystem provided information about the pecularities
     39  1.6  chopps  * of the board. THANKS! Competition in Europe among gfx board
     40  1.6  chopps  * manufacturers is rather tough, so Lutz Vieweg, who wrote the
     41  1.6  chopps  * initial driver, has made an agreement with MS not to document
     42  1.6  chopps  * the driver source (see also his comment below).
     43  1.6  chopps  * -> ALL comments and register defines after
     44  1.7   veego  * -> " -------------- START OF CODE -------------- "
     45  1.6  chopps  * -> have been added by myself (mw) from studying the publically
     46  1.6  chopps  * -> available "NCR 77C22E+" Data Manual
     47  1.6  chopps  */
     48  1.6  chopps /*
     49  1.6  chopps  * This code offers low-level routines to access the Retina graphics-board
     50  1.6  chopps  * manufactured by MS MacroSystem GmbH from within NetBSD for the Amiga.
     51  1.6  chopps  *
     52  1.6  chopps  * Thanks to MacroSystem for providing me with the neccessary information
     53  1.6  chopps  * to create theese routines. The sparse documentation of this code
     54  1.6  chopps  * results from the agreements between MS and me.
     55  1.6  chopps  */
     56  1.1      mw 
     57  1.1      mw #if 0
     58  1.1      mw /* these are in dev/devices.h */
     59  1.1      mw 
     60  1.1      mw /* definitions to find the autoconfig-board under
     61  1.1      mw    AmigaDOS */
     62  1.1      mw 
     63  1.1      mw #define RETINA_MANUFACTURER     0x4754
     64  1.1      mw #define RETINA_PRODUCT          6
     65  1.1      mw #define RETINA_SERIALNUMBER     1
     66  1.1      mw #endif
     67  1.1      mw 
     68  1.1      mw 
     69  1.1      mw /*
     70  1.1      mw    For more information on the structure entries take a look at
     71  1.1      mw    grf_rt.cc and ite_rt.cc.
     72  1.1      mw */
     73  1.1      mw 
     74  1.1      mw struct MonDef {
     75  1.1      mw 
     76  1.1      mw 	/* first the general monitor characteristics */
     77  1.1      mw 
     78  1.1      mw 	unsigned long  FQ;
     79  1.1      mw 	unsigned char  FLG;
     80  1.1      mw 
     81  1.1      mw 	unsigned short MW;  /* screen width in pixels */
     82  1.2      mw                             /* has to be at least a multiple of 8, */
     83  1.2      mw                             /* has to be a multiple of 64 in 256-color mode */
     84  1.2      mw                             /* if you want to use some great tricks */
     85  1.2      mw                             /* to speed up the vertical scrolling */
     86  1.1      mw 	unsigned short MH;  /* screen height in pixels */
     87  1.1      mw 
     88  1.1      mw 	unsigned short HBS;
     89  1.1      mw 	unsigned short HSS;
     90  1.1      mw 	unsigned short HSE;
     91  1.1      mw 	unsigned short HBE;
     92  1.1      mw 	unsigned short HT;
     93  1.1      mw 	unsigned short VBS;
     94  1.1      mw 	unsigned short VSS;
     95  1.1      mw 	unsigned short VSE;
     96  1.1      mw 	unsigned short VBE;
     97  1.1      mw 	unsigned short VT;
     98  1.1      mw 
     99  1.1      mw 	unsigned short DEP;  /* Color-depth, 4 for text-mode */
    100  1.2      mw                              /* 8 enables 256-color graphics-mode, */
    101  1.2      mw                              /* 16 and 24bit gfx not supported yet */
    102  1.1      mw 
    103  1.2      mw 	unsigned char * PAL; /* points to 16*3 byte RGB-palette data */
    104  1.2      mw                              /* use LoadPalette() to set colors 0..255 */
    105  1.2      mw                              /* in 256-color-gfx mode */
    106  1.1      mw 
    107  1.2      mw 	/* all following entries are font-specific in
    108  1.2      mw 	   text mode. Make sure your monitor
    109  1.1      mw 	   parameters are calculated for the
    110  1.1      mw 	   appropriate font width and height!
    111  1.1      mw 	*/
    112  1.1      mw 
    113  1.2      mw        unsigned short  TX;     /* Text-mode (DEP=4):          */
    114  1.2      mw                                /* screen-width  in characters */
    115  1.2      mw                                /* currently, TX has to be a   */
    116  1.2      mw                                /* multiple of 16!             */
    117  1.2      mw 
    118  1.2      mw                                /* Gfx-mode (DEP > 4)          */
    119  1.2      mw                                /* "logical" screen-width,     */
    120  1.2      mw                                /* use values > MW to allow    */
    121  1.2      mw                                /* hardware-panning            */
    122  1.2      mw                                /* has to be a multiple of 8   */
    123  1.2      mw 
    124  1.2      mw        unsigned short  TY;     /* Text-mode:                  */
    125  1.2      mw                                /* screen-height in characters */
    126  1.2      mw 
    127  1.2      mw                                /* Gfx-mode: "logical" screen  */
    128  1.2      mw                                /* height for panning          */
    129  1.2      mw 
    130  1.2      mw        /* the following values are currently unused for gfx-mode */
    131  1.2      mw 
    132  1.1      mw 	unsigned short  XY;     /* TX*TY (speeds up some calcs.) */
    133  1.1      mw 
    134  1.1      mw 	unsigned short  FX;     /* font-width (valid values: 4,7-16) */
    135  1.1      mw 	unsigned short  FY;     /* font-height (valid range: 1-32) */
    136  1.1      mw 	unsigned char * FData;  /* pointer to the font-data */
    137  1.1      mw 
    138  1.1      mw 	/* The font data is simply an array of bytes defining
    139  1.1      mw 	   the chars in ascending order, line by line. If your
    140  1.1      mw 	   font is wider than 8 pixel, FData has to be an
    141  1.1      mw 	   array of words. */
    142  1.1      mw 
    143  1.1      mw 	unsigned short  FLo;    /* lowest character defined */
    144  1.1      mw 	unsigned short  FHi;    /* highest char. defined */
    145  1.1      mw 
    146  1.1      mw };
    147  1.1      mw 
    148  1.1      mw 
    149  1.1      mw #if 0
    150  1.1      mw /* Some ready-made MonDef structures are available in grf_rt.cc */
    151  1.1      mw 
    152  1.1      mw extern struct MonDef MON_640_512_60;
    153  1.1      mw extern struct MonDef MON_768_600_60;
    154  1.1      mw extern struct MonDef MON_768_600_80;
    155  1.1      mw 
    156  1.1      mw /* text-screen resolutions wider than 1024 are currently damaged.
    157  1.1      mw    The VRAM access seems to become unstable at higher resolutions.
    158  1.1      mw    This may hopefully be subject of change.
    159  1.1      mw */
    160  1.1      mw 
    161  1.1      mw extern struct MonDef MON_1024_768_80;
    162  1.1      mw extern struct MonDef MON_1024_1024_59;
    163  1.1      mw 
    164  1.1      mw /* WARNING: THE FOLLOWING MONITOR MODES EXCEED THE 90-MHz LIMIT THE PROCESSOR
    165  1.1      mw             HAS BEEN SPECIFIED FOR. USE AT YOUR OWN RISK (AND THINK ABOUT
    166  1.1      mw             MOUNTING SOME COOLING DEVICE AT THE PROCESSOR AND RAMDAC)!     */
    167  1.1      mw extern struct MonDef MON_1280_1024_60;
    168  1.1      mw extern struct MonDef MON_1280_1024_69;
    169  1.1      mw 
    170  1.1      mw /* Default monitor (change if this is too much for your monitor :-)) */
    171  1.1      mw #define DEFAULT_MONDEF	MON_768_600_80
    172  1.1      mw 
    173  1.1      mw #else
    174  1.1      mw 
    175  1.1      mw /* nothing exported for now... */
    176  1.1      mw 
    177  1.1      mw #endif
    178  1.1      mw 
    179  1.1      mw /* a standard 16-color palette is available in grf_rt.cc
    180  1.1      mw    and used by the standard monitor-definitions above */
    181  1.1      mw extern unsigned char NCRStdPalette[];
    182  1.1      mw 
    183  1.2      mw /* The prototypes for C
    184  1.1      mw    with a little explanation
    185  1.1      mw 
    186  1.1      mw 	unsigned char * InitNCR(volatile void * BoardAdress, struct MonDef * md = &MON_640_512_60);
    187  1.1      mw 
    188  1.1      mw    This routine initialises the Retina hardware, opens a
    189  1.2      mw    text- or gfx-mode screen, depending on the the value of MonDef.DEP,
    190  1.2      mw    and sets the cursor to position 0.
    191  1.2      mw    It takes as arguments a pointer to the hardware-base
    192  1.2      mw    address as it is denoted in the DevConf structure
    193  1.2      mw    of the AmigaDOS, and a pointer to a struct MonDef
    194  1.2      mw    which describes the screen-mode parameters.
    195  1.2      mw 
    196  1.1      mw    The routine returns 0 if it was unable to open the screen,
    197  1.1      mw    or an unsigned char * to the display/attribute memory
    198  1.1      mw    when it succeeded. The organisation of the display memory
    199  1.2      mw    is a little strange in text-mode (Intel-typically...) :
    200  1.1      mw 
    201  1.1      mw    Byte  00    01    02    03    04     05    06   etc.
    202  1.1      mw        Char0  Attr0  --    --   Char1 Attr1   --   etc.
    203  1.1      mw 
    204  1.1      mw    You may set a character and its associated attribute byte
    205  1.1      mw    with a single word-access, or you may perform to byte writes
    206  1.1      mw    for the char and attribute. Each 2. word has no meaning,
    207  1.1      mw    and writes to theese locations are ignored.
    208  1.1      mw 
    209  1.1      mw    The attribute byte for each character has the following
    210  1.1      mw    structure:
    211  1.1      mw 
    212  1.1      mw    Bit  7     6     5     4     3     2     1     0
    213  1.1      mw       BLINK BACK2 BACK1 BACK0 FORE3 FORE2 FORE1 FORE0
    214  1.1      mw 
    215  1.1      mw    Were FORE is the foreground-color index (0-15) and
    216  1.1      mw    BACK is the background color index (0-7). BLINK
    217  1.1      mw    enables blinking for the associated character.
    218  1.1      mw    The higher 8 colors in the standard palette are
    219  1.1      mw    lighter than the lower 8, so you may see FORE3 as
    220  1.1      mw    an intensity bit. If FORE == 1 or FORE == 9 and
    221  1.1      mw    BACK == 0 the character is underlined. Since I don't
    222  1.1      mw    think this looks good, it will probably change in a
    223  1.1      mw    future release.
    224  1.1      mw 
    225  1.1      mw    There's no routine "SetChar" or "SetAttr" provided,
    226  1.1      mw    because I think it's so trivial... a function call
    227  1.1      mw    would be pure overhead. As an example, a routine
    228  1.1      mw    to set the char code and attribute at position x,y:
    229  1.1      mw    (assumed the value returned by InitNCR was stored
    230  1.1      mw     into "DispMem", the actual MonDef struct * is hold
    231  1.1      mw     in "MDef")
    232  1.1      mw 
    233  1.1      mw    void SetChar(unsigned char chr, unsigned char attr,
    234  1.1      mw                 unsigned short x, unsigned short y) {
    235  1.1      mw 
    236  1.1      mw       unsigned struct MonDef * md = MDef;
    237  1.1      mw       unsigned char * c = DispMem + x*4 + y*md->TX*4;
    238  1.1      mw 
    239  1.1      mw       *c++ = chr;
    240  1.2      mw       *c   = attr;
    241  1.2      mw 
    242  1.1      mw    }
    243  1.1      mw 
    244  1.2      mw    In Gfx-mode, the memory organisation is rather simple,
    245  1.2      mw    1 byte per pixel in 256-color mode, one pixel after
    246  1.2      mw    each other, line by line.
    247  1.2      mw 
    248  1.1      mw    Currently, InitNCR() disables the Retina VBLANK IRQ,
    249  1.1      mw    but beware: When running the Retina WB-Emu under
    250  1.1      mw    AmigaDOS, the VBLANK IRQ is ENABLED.
    251  1.1      mw 
    252  1.1      mw 	void SetCursorPos(unsigned short pos);
    253  1.1      mw 
    254  1.1      mw    This routine sets the hardware-cursor position
    255  1.1      mw    to the screen location pos. pos can be calculated
    256  1.1      mw    as (x + y * md->TY).
    257  1.2      mw    Text-mode only!
    258  1.1      mw 
    259  1.1      mw 	void ScreenUp(void);
    260  1.1      mw 
    261  1.1      mw    A somewhat optimized routine that scrolls the whole
    262  1.1      mw    screen up one row. A good idea to compile this piece
    263  1.1      mw    of code with optimization enabled.
    264  1.2      mw    Text-mode only!
    265  1.1      mw 
    266  1.1      mw 	void ScreenDown(void);
    267  1.1      mw 
    268  1.1      mw    A somewhat optimized routine that scrolls the whole
    269  1.1      mw    screen down one row. A good idea to compile this piece
    270  1.1      mw    of code with optimization enabled.
    271  1.2      mw    Text-mode only!
    272  1.2      mw 
    273  1.2      mw 	unsigned char * SetSegmentPtr(unsigned long adress);
    274  1.2      mw 
    275  1.2      mw    Sets the beginning of the 64k-memory segment to the
    276  1.2      mw    adress specified by the unsigned long. If adress MOD 64
    277  1.2      mw    is != 0, the return value will point to the segments
    278  1.2      mw    start in the Amiga adress space + (adress MOD 64).
    279  1.2      mw    Don't use more than (65536-64) bytes in the segment
    280  1.2      mw    you set if you aren't sure that (adress MOD 64) == 0.
    281  1.2      mw    See retina.doc from MS for further information.
    282  1.2      mw 
    283  1.2      mw 	void ClearScreen(unsigned char color);
    284  1.2      mw 
    285  1.2      mw    Fills the whole screen with "color" - 256-color mode only!
    286  1.2      mw 
    287  1.2      mw 	void LoadPalette(unsigned char * pal, unsigned char firstcol,
    288  1.2      mw 	                 unsigned char colors);
    289  1.2      mw 
    290  1.2      mw    Loads the palette-registers. "pal" points to an array of unsigned char
    291  1.2      mw    triplets, for the red, green and blue component. "firstcol" determines the
    292  1.2      mw    number of the first palette-register to load (256 available). "colors"
    293  1.2      mw    is the number of colors you want to put in the palette registers.
    294  1.2      mw 
    295  1.2      mw 	void SetPalette(unsigned char colornum, unsigned char red,
    296  1.2      mw 	                unsigned char green, unsigned char blue);
    297  1.2      mw 
    298  1.2      mw    Allows you to set a single color in the palette, "colornum" is the number
    299  1.2      mw    of the palette entry (256 available), "red", "green" and "blue" are the
    300  1.2      mw    three components.
    301  1.2      mw 
    302  1.2      mw 	void SetPanning(unsigned short xoff, unsigned short yoff);
    303  1.2      mw 
    304  1.2      mw    Moves the logical coordinate (xoff, yoff) to the upper left corner
    305  1.2      mw    of your screen. Of course, you shouldn't specify excess values that would
    306  1.2      mw    show garbage in the lower right area of your screen... SetPanning()
    307  1.2      mw    does NOT check for boundaries.
    308  1.1      mw */
    309  1.1      mw 
    310  1.1      mw /* -------------- START OF CODE -------------- */
    311  1.1      mw 
    312  1.1      mw /* read VGA register */
    313  1.1      mw #define vgar(ba, reg) (*(((volatile unsigned char *)ba)+reg))
    314  1.1      mw 
    315  1.1      mw /* write VGA register */
    316  1.1      mw #define vgaw(ba, reg, val) \
    317  1.1      mw 	*(((volatile unsigned char *)ba)+reg) = val
    318  1.1      mw 
    319  1.1      mw /* defines for the used register addresses (mw)
    320  1.1      mw 
    321  1.1      mw    NOTE: there are some registers that have different addresses when
    322  1.1      mw          in mono or color mode. We only support color mode, and thus
    323  1.1      mw          some addresses won't work in mono-mode! */
    324  1.1      mw 
    325  1.1      mw /* General Registers: */
    326  1.1      mw #define GREG_STATUS0_R		0x43C2
    327  1.1      mw #define GREG_STATUS1_R		0x43DA
    328  1.1      mw #define GREG_MISC_OUTPUT_R	0x43CC
    329  1.1      mw #define GREG_MISC_OUTPUT_W	0x43C2
    330  1.1      mw #define GREG_FEATURE_CONTROL_R	0x43CA
    331  1.1      mw #define GREG_FEATURE_CONTROL_W	0x43DA
    332  1.1      mw #define GREG_POS		0x4102
    333  1.1      mw 
    334  1.1      mw /* Attribute Controller: */
    335  1.1      mw #define ACT_ADDRESS		0x43C0
    336  1.1      mw #define ACT_ADDRESS_R		0x03C0
    337  1.1      mw #define ACT_ADDRESS_W		0x43C0
    338  1.1      mw #define ACT_ID_PALETTE0		0x00
    339  1.1      mw #define ACT_ID_PALETTE1		0x01
    340  1.1      mw #define ACT_ID_PALETTE2		0x02
    341  1.1      mw #define ACT_ID_PALETTE3		0x03
    342  1.1      mw #define ACT_ID_PALETTE4		0x04
    343  1.1      mw #define ACT_ID_PALETTE5		0x05
    344  1.1      mw #define ACT_ID_PALETTE6		0x06
    345  1.1      mw #define ACT_ID_PALETTE7		0x07
    346  1.1      mw #define ACT_ID_PALETTE8		0x08
    347  1.1      mw #define ACT_ID_PALETTE9		0x09
    348  1.1      mw #define ACT_ID_PALETTE10	0x0A
    349  1.1      mw #define ACT_ID_PALETTE11	0x0B
    350  1.1      mw #define ACT_ID_PALETTE12	0x0C
    351  1.1      mw #define ACT_ID_PALETTE13	0x0D
    352  1.1      mw #define ACT_ID_PALETTE14	0x0E
    353  1.1      mw #define ACT_ID_PALETTE15	0x0F
    354  1.1      mw #define ACT_ID_ATTR_MODE_CNTL	0x10
    355  1.1      mw #define ACT_ID_OVERSCAN_COLOR	0x11
    356  1.1      mw #define ACT_ID_COLOR_PLANE_ENA	0x12
    357  1.1      mw #define ACT_ID_HOR_PEL_PANNING	0x13
    358  1.1      mw #define ACT_ID_COLOR_SELECT	0x14
    359  1.1      mw 
    360  1.1      mw /* Graphics Controller: */
    361  1.1      mw #define GCT_ADDRESS		0x43CE
    362  1.1      mw #define GCT_ADDRESS_R		0x03CE
    363  1.1      mw #define GCT_ADDRESS_W		0x03CE
    364  1.1      mw #define GCT_ID_SET_RESET	0x00
    365  1.1      mw #define GCT_ID_ENABLE_SET_RESET	0x01
    366  1.1      mw #define GCT_ID_COLOR_COMPARE	0x02
    367  1.1      mw #define GCT_ID_DATA_ROTATE	0x03
    368  1.1      mw #define GCT_ID_READ_MAP_SELECT	0x04
    369  1.1      mw #define GCT_ID_GRAPHICS_MODE	0x05
    370  1.1      mw #define GCT_ID_MISC		0x06
    371  1.1      mw #define GCT_ID_COLOR_XCARE	0x07
    372  1.1      mw #define GCT_ID_BITMASK		0x08
    373  1.1      mw 
    374  1.1      mw /* Sequencer: */
    375  1.1      mw #define SEQ_ADDRESS		0x43C4
    376  1.1      mw #define SEQ_ADDRESS_R		0x03C4
    377  1.1      mw #define SEQ_ADDRESS_W		0x03C4
    378  1.1      mw #define SEQ_ID_RESET		0x00
    379  1.1      mw #define SEQ_ID_CLOCKING_MODE	0x01
    380  1.1      mw #define SEQ_ID_MAP_MASK		0x02
    381  1.1      mw #define SEQ_ID_CHAR_MAP_SELECT	0x03
    382  1.1      mw #define SEQ_ID_MEMORY_MODE	0x04
    383  1.1      mw #define SEQ_ID_EXTENDED_ENABLE	0x05	/* down from here, all seq registers are NCR extensions */
    384  1.2      mw #define SEQ_ID_UNKNOWN1         0x06	/* it does exist so it's probably usefull */
    385  1.2      mw #define SEQ_ID_UNKNOWN2         0x07	/* it does exist so it's probably usefull */
    386  1.1      mw #define SEQ_ID_CHIP_ID		0x08
    387  1.2      mw #define SEQ_ID_UNKNOWN3         0x09	/* it does exist so it's probably usefull */
    388  1.1      mw #define SEQ_ID_CURSOR_COLOR1	0x0A
    389  1.1      mw #define SEQ_ID_CURSOR_COLOR0	0x0B
    390  1.1      mw #define SEQ_ID_CURSOR_CONTROL	0x0C
    391  1.1      mw #define SEQ_ID_CURSOR_X_LOC_HI	0x0D
    392  1.1      mw #define SEQ_ID_CURSOR_X_LOC_LO	0x0E
    393  1.1      mw #define SEQ_ID_CURSOR_Y_LOC_HI	0x0F
    394  1.1      mw #define SEQ_ID_CURSOR_Y_LOC_LO	0x10
    395  1.1      mw #define SEQ_ID_CURSOR_X_INDEX	0x11
    396  1.1      mw #define SEQ_ID_CURSOR_Y_INDEX	0x12
    397  1.2      mw #define SEQ_ID_CURSOR_STORE_HI	0x13	/* printed manual is wrong about these.. */
    398  1.1      mw #define SEQ_ID_CURSOR_STORE_LO	0x14
    399  1.2      mw #define SEQ_ID_CURSOR_ST_OFF_HI	0x15
    400  1.2      mw #define SEQ_ID_CURSOR_ST_OFF_LO	0x16
    401  1.1      mw #define SEQ_ID_CURSOR_PIXELMASK	0x17
    402  1.1      mw #define SEQ_ID_PRIM_HOST_OFF_HI	0x18
    403  1.1      mw #define SEQ_ID_PRIM_HOST_OFF_LO	0x19
    404  1.2      mw #define SEQ_ID_DISP_OFF_HI	0x1A
    405  1.2      mw #define SEQ_ID_DISP_OFF_LO	0x1B
    406  1.1      mw #define SEQ_ID_SEC_HOST_OFF_HI	0x1C
    407  1.1      mw #define SEQ_ID_SEC_HOST_OFF_LO	0x1D
    408  1.1      mw #define SEQ_ID_EXTENDED_MEM_ENA	0x1E
    409  1.1      mw #define SEQ_ID_EXT_CLOCK_MODE	0x1F
    410  1.1      mw #define SEQ_ID_EXT_VIDEO_ADDR	0x20
    411  1.1      mw #define SEQ_ID_EXT_PIXEL_CNTL	0x21
    412  1.1      mw #define SEQ_ID_BUS_WIDTH_FEEDB	0x22
    413  1.1      mw #define SEQ_ID_PERF_SELECT	0x23
    414  1.1      mw #define SEQ_ID_COLOR_EXP_WFG	0x24
    415  1.1      mw #define SEQ_ID_COLOR_EXP_WBG	0x25
    416  1.1      mw #define SEQ_ID_EXT_RW_CONTROL	0x26
    417  1.1      mw #define SEQ_ID_MISC_FEATURE_SEL	0x27
    418  1.1      mw #define SEQ_ID_COLOR_KEY_CNTL	0x28
    419  1.1      mw #define SEQ_ID_COLOR_KEY_MATCH	0x29
    420  1.2      mw #define SEQ_ID_UNKNOWN4         0x2A
    421  1.2      mw #define SEQ_ID_UNKNOWN5         0x2B
    422  1.2      mw #define SEQ_ID_UNKNOWN6         0x2C
    423  1.1      mw #define SEQ_ID_CRC_CONTROL	0x2D
    424  1.1      mw #define SEQ_ID_CRC_DATA_LOW	0x2E
    425  1.1      mw #define SEQ_ID_CRC_DATA_HIGH	0x2F
    426  1.1      mw 
    427  1.1      mw /* CRT Controller: */
    428  1.1      mw #define CRT_ADDRESS		0x43D4
    429  1.1      mw #define CRT_ADDRESS_R		0x03D4
    430  1.1      mw #define CRT_ADDRESS_W		0x03D4
    431  1.1      mw #define CRT_ID_HOR_TOTAL	0x00
    432  1.1      mw #define CRT_ID_HOR_DISP_ENA_END	0x01
    433  1.1      mw #define CRT_ID_START_HOR_BLANK	0x02
    434  1.1      mw #define CRT_ID_END_HOR_BLANK	0x03
    435  1.1      mw #define CRT_ID_START_HOR_RETR	0x04
    436  1.1      mw #define CRT_ID_END_HOR_RETR	0x05
    437  1.1      mw #define CRT_ID_VER_TOTAL	0x06
    438  1.1      mw #define CRT_ID_OVERFLOW		0x07
    439  1.1      mw #define CRT_ID_PRESET_ROW_SCAN	0x08
    440  1.1      mw #define CRT_ID_MAX_SCAN_LINE	0x09
    441  1.1      mw #define CRT_ID_CURSOR_START	0x0A
    442  1.1      mw #define CRT_ID_CURSOR_END	0x0B
    443  1.1      mw #define CRT_ID_START_ADDR_HIGH	0x0C
    444  1.1      mw #define CRT_ID_START_ADDR_LOW	0x0D
    445  1.1      mw #define CRT_ID_CURSOR_LOC_HIGH	0x0E
    446  1.1      mw #define CRT_ID_CURSOR_LOC_LOW	0x0F
    447  1.1      mw #define CRT_ID_START_VER_RETR	0x10
    448  1.1      mw #define CRT_ID_END_VER_RETR	0x11
    449  1.1      mw #define CRT_ID_VER_DISP_ENA_END	0x12
    450  1.1      mw #define CRT_ID_OFFSET		0x13
    451  1.1      mw #define CRT_ID_UNDERLINE_LOC	0x14
    452  1.1      mw #define CRT_ID_START_VER_BLANK	0x15
    453  1.1      mw #define CRT_ID_END_VER_BLANK	0x16
    454  1.1      mw #define CRT_ID_MODE_CONTROL	0x17
    455  1.1      mw #define CRT_ID_LINE_COMPARE	0x18
    456  1.2      mw #define CRT_ID_UNKNOWN1         0x19	/* are these register really void ? */
    457  1.2      mw #define CRT_ID_UNKNOWN2         0x1A
    458  1.2      mw #define CRT_ID_UNKNOWN3         0x1B
    459  1.2      mw #define CRT_ID_UNKNOWN4         0x1C
    460  1.2      mw #define CRT_ID_UNKNOWN5         0x1D
    461  1.2      mw #define CRT_ID_UNKNOWN6         0x1E
    462  1.2      mw #define CRT_ID_UNKNOWN7         0x1F
    463  1.2      mw #define CRT_ID_UNKNOWN8         0x20
    464  1.2      mw #define CRT_ID_UNKNOWN9         0x21
    465  1.2      mw #define CRT_ID_UNKNOWN10      	0x22
    466  1.2      mw #define CRT_ID_UNKNOWN11      	0x23
    467  1.2      mw #define CRT_ID_UNKNOWN12      	0x24
    468  1.2      mw #define CRT_ID_UNKNOWN13      	0x25
    469  1.2      mw #define CRT_ID_UNKNOWN14      	0x26
    470  1.2      mw #define CRT_ID_UNKNOWN15      	0x27
    471  1.2      mw #define CRT_ID_UNKNOWN16      	0x28
    472  1.2      mw #define CRT_ID_UNKNOWN17      	0x29
    473  1.2      mw #define CRT_ID_UNKNOWN18      	0x2A
    474  1.2      mw #define CRT_ID_UNKNOWN19      	0x2B
    475  1.2      mw #define CRT_ID_UNKNOWN20      	0x2C
    476  1.2      mw #define CRT_ID_UNKNOWN21      	0x2D
    477  1.2      mw #define CRT_ID_UNKNOWN22      	0x2E
    478  1.2      mw #define CRT_ID_UNKNOWN23      	0x2F
    479  1.1      mw #define CRT_ID_EXT_HOR_TIMING1	0x30	/* down from here, all crt registers are NCR extensions */
    480  1.1      mw #define CRT_ID_EXT_START_ADDR	0x31
    481  1.1      mw #define CRT_ID_EXT_HOR_TIMING2	0x32
    482  1.1      mw #define CRT_ID_EXT_VER_TIMING	0x33
    483  1.1      mw 
    484  1.1      mw /* Video DAC (these are *pure* guesses from the usage of these registers,
    485  1.1      mw    I don't have a data sheet for this chip:-/) */
    486  1.1      mw #define VDAC_REG_D		0x800d	/* well.. */
    487  1.1      mw #define VDAC_REG_SELECT		0x8001	/* perhaps.. */
    488  1.1      mw #define VDAC_REG_DATA		0x8003	/* dito.. */
    489  1.1      mw 
    490  1.1      mw #define WGfx(ba, idx, val) \
    491  1.2      mw 	do { vgaw(ba, GCT_ADDRESS, idx); vgaw(ba, GCT_ADDRESS_W , val); } while (0)
    492  1.2      mw 
    493  1.2      mw #define WSeq(ba, idx, val) \
    494  1.2      mw 	do { vgaw(ba, SEQ_ADDRESS, idx); vgaw(ba, SEQ_ADDRESS_W , val); } while (0)
    495  1.2      mw 
    496  1.2      mw #define WCrt(ba, idx, val) \
    497  1.2      mw 	do { vgaw(ba, CRT_ADDRESS, idx); vgaw(ba, CRT_ADDRESS_W , val); } while (0)
    498  1.2      mw 
    499  1.2      mw #define WAttr(ba, idx, val) \
    500  1.2      mw 	do { vgaw(ba, ACT_ADDRESS, idx); vgaw(ba, ACT_ADDRESS_W, val); } while (0)
    501  1.1      mw 
    502  1.2      mw #define Map(m) \
    503  1.2      mw 	do { WGfx(ba, GCT_ID_READ_MAP_SELECT, m & 3 ); WSeq(ba, SEQ_ID_MAP_MASK, (1 << (m & 3))); } while (0)
    504  1.1      mw 
    505  1.1      mw static inline unsigned char RAttr(volatile void * ba, short idx) {
    506  1.1      mw 	vgaw (ba, ACT_ADDRESS, idx);
    507  1.1      mw 	return vgar (ba, ACT_ADDRESS_R);
    508  1.1      mw }
    509  1.1      mw 
    510  1.1      mw static inline unsigned char RSeq(volatile void * ba, short idx) {
    511  1.1      mw 	vgaw (ba, SEQ_ADDRESS, idx);
    512  1.1      mw 	return vgar (ba, SEQ_ADDRESS_R);
    513  1.1      mw }
    514  1.1      mw 
    515  1.1      mw static inline unsigned char RCrt(volatile void * ba, short idx) {
    516  1.1      mw 	vgaw (ba, CRT_ADDRESS, idx);
    517  1.1      mw 	return vgar (ba, CRT_ADDRESS_R);
    518  1.1      mw }
    519  1.1      mw 
    520  1.1      mw static inline unsigned char RGfx(volatile void * ba, short idx) {
    521  1.1      mw 	vgaw(ba, GCT_ADDRESS, idx);
    522  1.1      mw 	return vgar (ba, GCT_ADDRESS_R);
    523  1.1      mw }
    524  1.1      mw 
    525  1.4  chopps int grfrt_cnprobe __P((void));
    526  1.4  chopps void grfrt_iteinit __P((struct grf_softc *));
    527  1.1      mw #endif /* _GRF_RTREG_H */
    528