gtsc.c revision 1.13
1 /* $NetBSD: gtsc.c,v 1.13 1995/09/04 13:04:43 chopps Exp $ */ 2 3 /* 4 * Copyright (c) 1994 Christian E. Hopps 5 * Copyright (c) 1982, 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * @(#)dma.c 37 */ 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/device.h> 42 #include <scsi/scsi_all.h> 43 #include <scsi/scsiconf.h> 44 #include <amiga/amiga/custom.h> 45 #include <amiga/amiga/cc.h> 46 #include <amiga/amiga/device.h> 47 #include <amiga/amiga/isr.h> 48 #include <amiga/dev/dmavar.h> 49 #include <amiga/dev/sbicreg.h> 50 #include <amiga/dev/sbicvar.h> 51 #include <amiga/dev/gtscreg.h> 52 #include <amiga/dev/zbusvar.h> 53 #include <amiga/dev/gvpbusvar.h> 54 55 void gtscattach __P((struct device *, struct device *, void *)); 56 int gtscmatch __P((struct device *, struct cfdata *, void *)); 57 int gtscprint __P((void *auxp, char *)); 58 59 void gtsc_enintr __P((struct sbic_softc *)); 60 void gtsc_dmastop __P((struct sbic_softc *)); 61 int gtsc_dmanext __P((struct sbic_softc *)); 62 int gtsc_dmaintr __P((struct sbic_softc *)); 63 int gtsc_dmago __P((struct sbic_softc *, char *, int, int)); 64 65 struct scsi_adapter gtsc_scsiswitch = { 66 sbic_scsicmd, 67 sbic_minphys, 68 0, /* no lun support */ 69 0, /* no lun support */ 70 }; 71 72 struct scsi_device gtsc_scsidev = { 73 NULL, /* use default error handler */ 74 NULL, /* have a queue served by this ??? */ 75 NULL, /* have no async handler ??? */ 76 NULL, /* Use default done routine */ 77 }; 78 79 int gtsc_maxdma = 0; /* Maximum size per DMA transfer */ 80 int gtsc_dmamask = 0; 81 int gtsc_dmabounce = 0; 82 int gtsc_clock_override = 0; 83 84 #ifdef DEBUG 85 int gtsc_debug = 0; 86 #endif 87 88 struct cfdriver gtsccd = { 89 NULL, "gtsc", (cfmatch_t)gtscmatch, gtscattach, 90 DV_DULL, sizeof(struct sbic_softc), NULL, 0 }; 91 92 int 93 gtscmatch(pdp, cdp, auxp) 94 struct device *pdp; 95 struct cfdata *cdp; 96 void *auxp; 97 { 98 struct gvpbus_args *gap; 99 100 gap = auxp; 101 if (gap->flags & GVP_SCSI) 102 return(1); 103 return(0); 104 } 105 106 /* 107 * attach all devices on our board. 108 */ 109 void 110 gtscattach(pdp, dp, auxp) 111 struct device *pdp, *dp; 112 void *auxp; 113 { 114 volatile struct sdmac *rp; 115 struct gvpbus_args *gap; 116 struct sbic_softc *sc; 117 118 gap = auxp; 119 sc = (struct sbic_softc *)dp; 120 sc->sc_cregs = rp = gap->zargs.va; 121 122 /* 123 * disable ints and reset bank register 124 */ 125 rp->CNTR = 0; 126 if ((gap->flags & GVP_NOBANK) == 0) 127 rp->bank = 0; 128 129 sc->sc_dmago = gtsc_dmago; 130 sc->sc_enintr = gtsc_enintr; 131 sc->sc_dmanext = gtsc_dmanext; 132 sc->sc_dmastop = gtsc_dmastop; 133 sc->sc_dmacmd = 0; 134 135 sc->sc_flags |= SBICF_BADDMA; 136 if (gtsc_dmamask) 137 sc->sc_dmamask = gtsc_dmamask; 138 else if (gap->flags & GVP_24BITDMA) 139 sc->sc_dmamask = ~0x00ffffff; 140 else if (gap->flags & GVP_25BITDMA) 141 sc->sc_dmamask = ~0x01ffffff; 142 else 143 sc->sc_dmamask = ~0x07ffffff; 144 printf(": dmamask 0x%x", ~sc->sc_dmamask); 145 146 if ((gap->flags & GVP_NOBANK) == 0) 147 sc->gtsc_bankmask = (~sc->sc_dmamask >> 18) & 0x01c0; 148 149 #if 0 150 /* 151 * if the user requests a bounce buffer or 152 * the users kva space is not ztwo and dma needs it 153 * try and allocate a bounce buffer. If we allocate 154 * one and it is in ztwo space leave maxdma to user 155 * setting or default to MAXPHYS else the address must 156 * be on the chip bus so decrease it to either the users 157 * setting or 1024 bytes. 158 * 159 * XXX this needs to change if we move to multiple memory segments. 160 */ 161 if (gtsc_dmabounce || kvtop(sc) & sc->sc_dmamask) { 162 sc->sc_dmabuffer = (char *) alloc_z2mem(MAXPHYS * 8); /* XXX */ 163 if (isztwomem(sc->sc_dmabuffer)) 164 printf(" bounce pa 0x%x", kvtop(sc->sc_dmabuffer)); 165 else if (gtsc_maxdma == 0) { 166 gtsc_maxdma = 1024; 167 printf(" bounce pa 0x%x", 168 PREP_DMA_MEM(sc->sc_dmabuffer)); 169 } 170 } 171 #endif 172 if (gtsc_maxdma == 0) 173 gtsc_maxdma = MAXPHYS; 174 175 printf(" flags %x", gap->flags); 176 printf(" maxdma %d\n", gtsc_maxdma); 177 178 sc->sc_sbicp = (sbic_regmap_p) ((int)rp + 0x61); 179 sc->sc_clkfreq = gtsc_clock_override ? gtsc_clock_override : 180 ((gap->flags & GVP_14MHZ) ? 143 : 72); 181 printf("sc_clkfreg: %d.%dMhz\n", sc->sc_clkfreq / 10, sc->sc_clkfreq % 10); 182 183 sc->sc_link.adapter_softc = sc; 184 sc->sc_link.adapter_target = 7; 185 sc->sc_link.adapter = >sc_scsiswitch; 186 sc->sc_link.device = >sc_scsidev; 187 sc->sc_link.openings = 2; 188 189 sbicinit(sc); 190 191 sc->sc_isr.isr_intr = gtsc_dmaintr; 192 sc->sc_isr.isr_arg = sc; 193 sc->sc_isr.isr_ipl = 2; 194 add_isr(&sc->sc_isr); 195 196 /* 197 * attach all scsi units on us 198 */ 199 config_found(dp, &sc->sc_link, gtscprint); 200 } 201 202 /* 203 * print diag if pnp is NULL else just extra 204 */ 205 int 206 gtscprint(auxp, pnp) 207 void *auxp; 208 char *pnp; 209 { 210 if (pnp == NULL) 211 return(UNCONF); 212 return(QUIET); 213 } 214 215 void 216 gtsc_enintr(dev) 217 struct sbic_softc *dev; 218 { 219 volatile struct sdmac *sdp; 220 221 sdp = dev->sc_cregs; 222 223 dev->sc_flags |= SBICF_INTR; 224 sdp->CNTR = GVP_CNTR_INTEN; 225 } 226 227 int 228 gtsc_dmago(dev, addr, count, flags) 229 struct sbic_softc *dev; 230 char *addr; 231 int count, flags; 232 { 233 volatile struct sdmac *sdp; 234 235 sdp = dev->sc_cregs; 236 /* 237 * Set up the command word based on flags 238 */ 239 dev->sc_dmacmd = GVP_CNTR_INTEN; 240 if ((flags & DMAGO_READ) == 0) 241 dev->sc_dmacmd |= GVP_CNTR_DDIR; 242 243 #ifdef DEBUG 244 if (gtsc_debug & DDB_IO) 245 printf("gtsc_dmago: cmd %x\n", dev->sc_dmacmd); 246 #endif 247 dev->sc_flags |= SBICF_INTR; 248 sdp->CNTR = dev->sc_dmacmd; 249 if((u_int)dev->sc_cur->dc_addr & dev->sc_dmamask) { 250 #if 1 251 printf("gtsc_dmago: pa %08x->%08x dmacmd %x", 252 dev->sc_cur->dc_addr, 253 (u_int)dev->sc_cur->dc_addr & ~dev->sc_dmamask, 254 dev->sc_dmacmd); 255 #endif 256 sdp->ACR = 0x00f80000; /***********************************/ 257 } else 258 sdp->ACR = (u_int) dev->sc_cur->dc_addr; 259 if (dev->gtsc_bankmask) 260 sdp->bank = 261 dev->gtsc_bankmask & (((u_int)dev->sc_cur->dc_addr) >> 18); 262 sdp->ST_DMA = 1; 263 264 /* 265 * restrict transfer count to maximum 266 */ 267 if (dev->sc_tcnt > gtsc_maxdma) 268 dev->sc_tcnt = gtsc_maxdma; 269 #if 1 270 if((u_int)dev->sc_cur->dc_addr & dev->sc_dmamask) 271 printf(" tcnt %d\n", dev->sc_tcnt); 272 #endif 273 return(dev->sc_tcnt); 274 } 275 276 void 277 gtsc_dmastop(dev) 278 struct sbic_softc *dev; 279 { 280 volatile struct sdmac *sdp; 281 int s; 282 283 sdp = dev->sc_cregs; 284 285 #ifdef DEBUG 286 if (gtsc_debug & DDB_FOLLOW) 287 printf("gtsc_dmastop()\n"); 288 #endif 289 if (dev->sc_dmacmd) { 290 /* 291 * clear possible interrupt and stop dma 292 */ 293 s = splbio(); 294 sdp->CNTR &= ~GVP_CNTR_INT_P; 295 sdp->SP_DMA = 1; 296 dev->sc_dmacmd = 0; 297 splx(s); 298 } 299 } 300 301 int 302 gtsc_dmaintr(dev) 303 struct sbic_softc *dev; 304 { 305 volatile struct sdmac *sdp; 306 int stat; 307 308 sdp = dev->sc_cregs; 309 stat = sdp->CNTR; 310 if ((stat & GVP_CNTR_INT_P) == 0) 311 return (0); 312 #ifdef DEBUG 313 if (gtsc_debug & DDB_FOLLOW) 314 printf("%s: dmaintr 0x%x\n", dev->sc_dev.dv_xname, stat); 315 #endif 316 if (dev->sc_flags & SBICF_INTR) 317 if (sbicintr(dev)) 318 return (1); 319 return(0); 320 } 321 322 323 int 324 gtsc_dmanext(dev) 325 struct sbic_softc *dev; 326 { 327 volatile struct sdmac *sdp; 328 int i, stat; 329 330 sdp = dev->sc_cregs; 331 332 if (dev->sc_cur > dev->sc_last) { 333 /* shouldn't happen !! */ 334 printf("gtsc_dmanext at end !!!\n"); 335 gtsc_dmastop(dev); 336 return(0); 337 } 338 /* 339 * clear possible interrupt and stop dma 340 */ 341 sdp->CNTR &= ~GVP_CNTR_INT_P; 342 sdp->SP_DMA = 1; 343 344 sdp->CNTR = dev->sc_dmacmd; 345 sdp->ACR = (u_int) dev->sc_cur->dc_addr; 346 if (dev->gtsc_bankmask) 347 sdp->bank = 348 dev->gtsc_bankmask & ((u_int)dev->sc_cur->dc_addr >> 18); 349 sdp->ST_DMA = 1; 350 351 dev->sc_tcnt = dev->sc_cur->dc_count << 1; 352 if (dev->sc_tcnt > gtsc_maxdma) 353 dev->sc_tcnt = gtsc_maxdma; 354 #ifdef DEBUG 355 if (gtsc_debug & DDB_FOLLOW) 356 printf("gtsc_dmanext ret: %d\n", dev->sc_tcnt); 357 #endif 358 return(dev->sc_tcnt); 359 } 360 361 #ifdef DEBUG 362 void 363 gtsc_dump() 364 { 365 int i; 366 367 for (i = 0; i < gtsccd.cd_ndevs; ++i) 368 if (gtsccd.cd_devs[i]) 369 sbic_dump(gtsccd.cd_devs[i]); 370 } 371 #endif 372
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