gtsc.c revision 1.23
1 /* $NetBSD: gtsc.c,v 1.23 1998/01/12 10:39:42 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1994 Christian E. Hopps 5 * Copyright (c) 1982, 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * @(#)dma.c 37 */ 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/device.h> 42 #include <dev/scsipi/scsi_all.h> 43 #include <dev/scsipi/scsipi_all.h> 44 #include <dev/scsipi/scsiconf.h> 45 #include <amiga/amiga/custom.h> 46 #include <amiga/amiga/cc.h> 47 #include <amiga/amiga/device.h> 48 #include <amiga/amiga/isr.h> 49 #include <amiga/dev/dmavar.h> 50 #include <amiga/dev/sbicreg.h> 51 #include <amiga/dev/sbicvar.h> 52 #include <amiga/dev/gtscreg.h> 53 #include <amiga/dev/zbusvar.h> 54 #include <amiga/dev/gvpbusvar.h> 55 56 void gtscattach __P((struct device *, struct device *, void *)); 57 int gtscmatch __P((struct device *, struct cfdata *, void *)); 58 59 void gtsc_enintr __P((struct sbic_softc *)); 60 void gtsc_dmastop __P((struct sbic_softc *)); 61 int gtsc_dmanext __P((struct sbic_softc *)); 62 int gtsc_dmaintr __P((void *)); 63 int gtsc_dmago __P((struct sbic_softc *, char *, int, int)); 64 65 #ifdef DEBUG 66 void gtsc_dump __P((void)); 67 #endif 68 69 struct scsipi_adapter gtsc_scsiswitch = { 70 sbic_scsicmd, 71 sbic_minphys, 72 0, /* no lun support */ 73 0, /* no lun support */ 74 }; 75 76 struct scsipi_device gtsc_scsidev = { 77 NULL, /* use default error handler */ 78 NULL, /* have a queue served by this ??? */ 79 NULL, /* have no async handler ??? */ 80 NULL, /* Use default done routine */ 81 }; 82 83 int gtsc_maxdma = 0; /* Maximum size per DMA transfer */ 84 int gtsc_dmamask = 0; 85 int gtsc_dmabounce = 0; 86 int gtsc_clock_override = 0; 87 88 #ifdef DEBUG 89 int gtsc_debug = 0; 90 #endif 91 92 struct cfattach gtsc_ca = { 93 sizeof(struct sbic_softc), gtscmatch, gtscattach 94 }; 95 96 int 97 gtscmatch(pdp, cfp, auxp) 98 struct device *pdp; 99 struct cfdata *cfp; 100 void *auxp; 101 { 102 struct gvpbus_args *gap; 103 104 gap = auxp; 105 if (gap->flags & GVP_SCSI) 106 return(1); 107 return(0); 108 } 109 110 /* 111 * attach all devices on our board. 112 */ 113 void 114 gtscattach(pdp, dp, auxp) 115 struct device *pdp, *dp; 116 void *auxp; 117 { 118 volatile struct sdmac *rp; 119 struct gvpbus_args *gap; 120 struct sbic_softc *sc; 121 122 gap = auxp; 123 sc = (struct sbic_softc *)dp; 124 sc->sc_cregs = rp = gap->zargs.va; 125 126 /* 127 * disable ints and reset bank register 128 */ 129 rp->CNTR = 0; 130 if ((gap->flags & GVP_NOBANK) == 0) 131 rp->bank = 0; 132 133 sc->sc_dmago = gtsc_dmago; 134 sc->sc_enintr = gtsc_enintr; 135 sc->sc_dmanext = gtsc_dmanext; 136 sc->sc_dmastop = gtsc_dmastop; 137 sc->sc_dmacmd = 0; 138 139 sc->sc_flags |= SBICF_BADDMA; 140 if (gtsc_dmamask) 141 sc->sc_dmamask = gtsc_dmamask; 142 else if (gap->flags & GVP_24BITDMA) 143 sc->sc_dmamask = ~0x00ffffff; 144 else if (gap->flags & GVP_25BITDMA) 145 sc->sc_dmamask = ~0x01ffffff; 146 else 147 sc->sc_dmamask = ~0x07ffffff; 148 printf(": dmamask 0x%lx", ~sc->sc_dmamask); 149 150 if ((gap->flags & GVP_NOBANK) == 0) 151 sc->gtsc_bankmask = (~sc->sc_dmamask >> 18) & 0x01c0; 152 153 #if 0 154 /* 155 * if the user requests a bounce buffer or 156 * the users kva space is not ztwo and dma needs it 157 * try and allocate a bounce buffer. If we allocate 158 * one and it is in ztwo space leave maxdma to user 159 * setting or default to MAXPHYS else the address must 160 * be on the chip bus so decrease it to either the users 161 * setting or 1024 bytes. 162 * 163 * XXX this needs to change if we move to multiple memory segments. 164 */ 165 if (gtsc_dmabounce || kvtop(sc) & sc->sc_dmamask) { 166 sc->sc_dmabuffer = (char *) alloc_z2mem(MAXPHYS * 8); /* XXX */ 167 if (isztwomem(sc->sc_dmabuffer)) 168 printf(" bounce pa 0x%x", kvtop(sc->sc_dmabuffer)); 169 else if (gtsc_maxdma == 0) { 170 gtsc_maxdma = 1024; 171 printf(" bounce pa 0x%x", 172 PREP_DMA_MEM(sc->sc_dmabuffer)); 173 } 174 } 175 #endif 176 if (gtsc_maxdma == 0) 177 gtsc_maxdma = MAXPHYS; 178 179 printf(" flags %x", gap->flags); 180 printf(" maxdma %d\n", gtsc_maxdma); 181 182 sc->sc_sbicp = (sbic_regmap_p) ((int)rp + 0x61); 183 sc->sc_clkfreq = gtsc_clock_override ? gtsc_clock_override : 184 ((gap->flags & GVP_14MHZ) ? 143 : 72); 185 printf("sc_clkfreg: %ld.%ldMhz\n", sc->sc_clkfreq / 10, sc->sc_clkfreq % 10); 186 187 sc->sc_link.scsipi_scsi.channel = SCSI_CHANNEL_ONLY_ONE; 188 sc->sc_link.adapter_softc = sc; 189 sc->sc_link.scsipi_scsi.adapter_target = 7; 190 sc->sc_link.adapter = >sc_scsiswitch; 191 sc->sc_link.device = >sc_scsidev; 192 sc->sc_link.openings = 2; 193 sc->sc_link.scsipi_scsi.max_target = 7; 194 sc->sc_link.type = BUS_SCSI; 195 196 sbicinit(sc); 197 198 sc->sc_isr.isr_intr = gtsc_dmaintr; 199 sc->sc_isr.isr_arg = sc; 200 sc->sc_isr.isr_ipl = 2; 201 add_isr(&sc->sc_isr); 202 203 /* 204 * attach all scsi units on us 205 */ 206 config_found(dp, &sc->sc_link, scsiprint); 207 } 208 209 void 210 gtsc_enintr(dev) 211 struct sbic_softc *dev; 212 { 213 volatile struct sdmac *sdp; 214 215 sdp = dev->sc_cregs; 216 217 dev->sc_flags |= SBICF_INTR; 218 sdp->CNTR = GVP_CNTR_INTEN; 219 } 220 221 int 222 gtsc_dmago(dev, addr, count, flags) 223 struct sbic_softc *dev; 224 char *addr; 225 int count, flags; 226 { 227 volatile struct sdmac *sdp; 228 229 sdp = dev->sc_cregs; 230 /* 231 * Set up the command word based on flags 232 */ 233 dev->sc_dmacmd = GVP_CNTR_INTEN; 234 if ((flags & DMAGO_READ) == 0) 235 dev->sc_dmacmd |= GVP_CNTR_DDIR; 236 237 #ifdef DEBUG 238 if (gtsc_debug & DDB_IO) 239 printf("gtsc_dmago: cmd %x\n", dev->sc_dmacmd); 240 #endif 241 dev->sc_flags |= SBICF_INTR; 242 sdp->CNTR = dev->sc_dmacmd; 243 if((u_int)dev->sc_cur->dc_addr & dev->sc_dmamask) { 244 #if 1 245 printf("gtsc_dmago: pa %p->%lx dmacmd %x", 246 dev->sc_cur->dc_addr, 247 (u_int)dev->sc_cur->dc_addr & ~dev->sc_dmamask, 248 dev->sc_dmacmd); 249 #endif 250 sdp->ACR = 0x00f80000; /***********************************/ 251 } else 252 sdp->ACR = (u_int) dev->sc_cur->dc_addr; 253 if (dev->gtsc_bankmask) 254 sdp->bank = 255 dev->gtsc_bankmask & (((u_int)dev->sc_cur->dc_addr) >> 18); 256 sdp->ST_DMA = 1; 257 258 /* 259 * restrict transfer count to maximum 260 */ 261 if (dev->sc_tcnt > gtsc_maxdma) 262 dev->sc_tcnt = gtsc_maxdma; 263 #if 1 264 if((u_int)dev->sc_cur->dc_addr & dev->sc_dmamask) 265 printf(" tcnt %ld\n", dev->sc_tcnt); 266 #endif 267 return(dev->sc_tcnt); 268 } 269 270 void 271 gtsc_dmastop(dev) 272 struct sbic_softc *dev; 273 { 274 volatile struct sdmac *sdp; 275 int s; 276 277 sdp = dev->sc_cregs; 278 279 #ifdef DEBUG 280 if (gtsc_debug & DDB_FOLLOW) 281 printf("gtsc_dmastop()\n"); 282 #endif 283 if (dev->sc_dmacmd) { 284 /* 285 * clear possible interrupt and stop dma 286 */ 287 s = splbio(); 288 sdp->CNTR &= ~GVP_CNTR_INT_P; 289 sdp->SP_DMA = 1; 290 dev->sc_dmacmd = 0; 291 splx(s); 292 } 293 } 294 295 int 296 gtsc_dmaintr(arg) 297 void *arg; 298 { 299 struct sbic_softc *dev = arg; 300 volatile struct sdmac *sdp; 301 int stat; 302 303 sdp = dev->sc_cregs; 304 stat = sdp->CNTR; 305 if ((stat & GVP_CNTR_INT_P) == 0) 306 return (0); 307 #ifdef DEBUG 308 if (gtsc_debug & DDB_FOLLOW) 309 printf("%s: dmaintr 0x%x\n", dev->sc_dev.dv_xname, stat); 310 #endif 311 if (dev->sc_flags & SBICF_INTR) 312 if (sbicintr(dev)) 313 return (1); 314 return(0); 315 } 316 317 318 int 319 gtsc_dmanext(dev) 320 struct sbic_softc *dev; 321 { 322 volatile struct sdmac *sdp; 323 324 sdp = dev->sc_cregs; 325 326 if (dev->sc_cur > dev->sc_last) { 327 /* shouldn't happen !! */ 328 printf("gtsc_dmanext at end !!!\n"); 329 gtsc_dmastop(dev); 330 return(0); 331 } 332 /* 333 * clear possible interrupt and stop dma 334 */ 335 sdp->CNTR &= ~GVP_CNTR_INT_P; 336 sdp->SP_DMA = 1; 337 338 sdp->CNTR = dev->sc_dmacmd; 339 sdp->ACR = (u_int) dev->sc_cur->dc_addr; 340 if (dev->gtsc_bankmask) 341 sdp->bank = 342 dev->gtsc_bankmask & ((u_int)dev->sc_cur->dc_addr >> 18); 343 sdp->ST_DMA = 1; 344 345 dev->sc_tcnt = dev->sc_cur->dc_count << 1; 346 if (dev->sc_tcnt > gtsc_maxdma) 347 dev->sc_tcnt = gtsc_maxdma; 348 #ifdef DEBUG 349 if (gtsc_debug & DDB_FOLLOW) 350 printf("gtsc_dmanext ret: %ld\n", dev->sc_tcnt); 351 #endif 352 return(dev->sc_tcnt); 353 } 354 355 #ifdef DEBUG 356 void 357 gtsc_dump() 358 { 359 extern struct cfdriver gtsc_cd; 360 int i; 361 362 for (i = 0; i < gtsc_cd.cd_ndevs; ++i) 363 if (gtsc_cd.cd_devs[i]) 364 sbic_dump(gtsc_cd.cd_devs[i]); 365 } 366 #endif 367
Indexes created Mon Sep 29 18:09:42 GMT 2025