if_ed_zbus.c revision 1.2.4.2
1 1.2.4.2 tls /* $NetBSD: if_ed_zbus.c,v 1.2.4.2 2012/11/20 03:00:58 tls Exp $ */ 2 1.2.4.2 tls 3 1.2.4.2 tls /*- 4 1.2.4.2 tls * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 1.2.4.2 tls * All rights reserved. 6 1.2.4.2 tls * 7 1.2.4.2 tls * This code is derived from software contributed to The NetBSD Foundation 8 1.2.4.2 tls * by Frank Wille. 9 1.2.4.2 tls * 10 1.2.4.2 tls * Redistribution and use in source and binary forms, with or without 11 1.2.4.2 tls * modification, are permitted provided that the following conditions 12 1.2.4.2 tls * are met: 13 1.2.4.2 tls * 1. Redistributions of source code must retain the above copyright 14 1.2.4.2 tls * notice, this list of conditions and the following disclaimer. 15 1.2.4.2 tls * 2. Redistributions in binary form must reproduce the above copyright 16 1.2.4.2 tls * notice, this list of conditions and the following disclaimer in the 17 1.2.4.2 tls * documentation and/or other materials provided with the distribution. 18 1.2.4.2 tls * 19 1.2.4.2 tls * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 1.2.4.2 tls * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 1.2.4.2 tls * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 1.2.4.2 tls * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 1.2.4.2 tls * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 1.2.4.2 tls * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 1.2.4.2 tls * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 1.2.4.2 tls * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 1.2.4.2 tls * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 1.2.4.2 tls * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 1.2.4.2 tls * POSSIBILITY OF SUCH DAMAGE. 30 1.2.4.2 tls */ 31 1.2.4.2 tls 32 1.2.4.2 tls /* 33 1.2.4.2 tls * Device driver for the Hydra Systems and ASDG ethernet cards. 34 1.2.4.2 tls * Based on the National Semiconductor DS8390/WD83C690. 35 1.2.4.2 tls */ 36 1.2.4.2 tls 37 1.2.4.2 tls #include <sys/cdefs.h> 38 1.2.4.2 tls __KERNEL_RCSID(0, "$NetBSD: if_ed_zbus.c,v 1.2.4.2 2012/11/20 03:00:58 tls Exp $"); 39 1.2.4.2 tls 40 1.2.4.2 tls #include <sys/param.h> 41 1.2.4.2 tls #include <sys/device.h> 42 1.2.4.2 tls #include <sys/bus.h> 43 1.2.4.2 tls 44 1.2.4.2 tls #include <net/if.h> 45 1.2.4.2 tls #include <net/if_media.h> 46 1.2.4.2 tls #include <net/if_ether.h> 47 1.2.4.2 tls 48 1.2.4.2 tls #include <dev/ic/dp8390reg.h> 49 1.2.4.2 tls #include <dev/ic/dp8390var.h> 50 1.2.4.2 tls 51 1.2.4.2 tls #include <amiga/amiga/device.h> 52 1.2.4.2 tls #include <amiga/amiga/isr.h> 53 1.2.4.2 tls #include <amiga/dev/zbusvar.h> 54 1.2.4.2 tls 55 1.2.4.2 tls #define ETHER_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 56 1.2.4.2 tls 57 1.2.4.2 tls /* Hydra Systems AmigaNet */ 58 1.2.4.2 tls #define HYDRA_MANID 2121 59 1.2.4.2 tls #define HYDRA_PRODID 1 60 1.2.4.2 tls #define HYDRA_REGADDR 0xffe1 61 1.2.4.2 tls #define HYDRA_MEMADDR 0 62 1.2.4.2 tls #define HYDRA_PROMADDR 0xffc0 63 1.2.4.2 tls 64 1.2.4.2 tls /* ASDG LANRover */ 65 1.2.4.2 tls #define ASDG_MANID 1023 66 1.2.4.2 tls #define ASDG_PRODID 254 67 1.2.4.2 tls #define ASDG_REGADDR 0x1 68 1.2.4.2 tls #define ASDG_MEMADDR 0x8000 69 1.2.4.2 tls #define ASDG_PROMADDR 0x100 70 1.2.4.2 tls 71 1.2.4.2 tls /* Buffer size is always 16k */ 72 1.2.4.2 tls #define ED_ZBUS_MEMSIZE 0x4000 73 1.2.4.2 tls 74 1.2.4.2 tls int ed_zbus_match(device_t, cfdata_t , void *); 75 1.2.4.2 tls void ed_zbus_attach(device_t, device_t, void *); 76 1.2.4.2 tls int ed_zbus_test_mem(struct dp8390_softc *); 77 1.2.4.2 tls void ed_zbus_read_hdr(struct dp8390_softc *, int, struct dp8390_ring *); 78 1.2.4.2 tls int ed_zbus_ring_copy(struct dp8390_softc *, int, void *, u_short); 79 1.2.4.2 tls int ed_zbus_write_mbuf(struct dp8390_softc *, struct mbuf *, int); 80 1.2.4.2 tls 81 1.2.4.2 tls struct ed_zbus_softc { 82 1.2.4.2 tls struct dp8390_softc sc_dp8390; 83 1.2.4.2 tls struct bus_space_tag sc_bst; 84 1.2.4.2 tls struct isr sc_isr; 85 1.2.4.2 tls }; 86 1.2.4.2 tls 87 1.2.4.2 tls CFATTACH_DECL_NEW(ed_zbus, sizeof(struct ed_zbus_softc), 88 1.2.4.2 tls ed_zbus_match, ed_zbus_attach, NULL, NULL); 89 1.2.4.2 tls 90 1.2.4.2 tls 91 1.2.4.2 tls int 92 1.2.4.2 tls ed_zbus_match(device_t parent, cfdata_t cf, void *aux) 93 1.2.4.2 tls { 94 1.2.4.2 tls struct zbus_args *zap = aux; 95 1.2.4.2 tls 96 1.2.4.2 tls if (zap->manid == HYDRA_MANID && zap->prodid == HYDRA_PRODID) 97 1.2.4.2 tls return 1; 98 1.2.4.2 tls else if (zap->manid == ASDG_MANID && zap->prodid == ASDG_PRODID) 99 1.2.4.2 tls return 1; 100 1.2.4.2 tls return 0; 101 1.2.4.2 tls } 102 1.2.4.2 tls 103 1.2.4.2 tls void 104 1.2.4.2 tls ed_zbus_attach(device_t parent, device_t self, void *aux) 105 1.2.4.2 tls { 106 1.2.4.2 tls struct ed_zbus_softc *zsc = device_private(self); 107 1.2.4.2 tls struct dp8390_softc *sc = &zsc->sc_dp8390; 108 1.2.4.2 tls struct zbus_args *zap = aux; 109 1.2.4.2 tls bus_space_handle_t promh; 110 1.2.4.2 tls bus_addr_t memaddr, promaddr, regaddr; 111 1.2.4.2 tls int i; 112 1.2.4.2 tls 113 1.2.4.2 tls zsc->sc_bst.base = (bus_addr_t)zap->va; 114 1.2.4.2 tls zsc->sc_bst.absm = &amiga_bus_stride_1; 115 1.2.4.2 tls 116 1.2.4.2 tls if (zap->manid == HYDRA_MANID) { 117 1.2.4.2 tls regaddr = HYDRA_REGADDR; 118 1.2.4.2 tls memaddr = HYDRA_MEMADDR; 119 1.2.4.2 tls promaddr = HYDRA_PROMADDR; 120 1.2.4.2 tls } else { 121 1.2.4.2 tls regaddr = ASDG_REGADDR; 122 1.2.4.2 tls memaddr = ASDG_MEMADDR; 123 1.2.4.2 tls promaddr = ASDG_PROMADDR; 124 1.2.4.2 tls } 125 1.2.4.2 tls 126 1.2.4.2 tls sc->sc_dev = self; 127 1.2.4.2 tls sc->sc_regt = &zsc->sc_bst; 128 1.2.4.2 tls sc->sc_buft = &zsc->sc_bst; 129 1.2.4.2 tls 130 1.2.4.2 tls if (bus_space_map(sc->sc_regt, regaddr, 0x20, 0, &sc->sc_regh)) { 131 1.2.4.2 tls aprint_error_dev(self, "can't map i/o space\n"); 132 1.2.4.2 tls return; 133 1.2.4.2 tls } 134 1.2.4.2 tls 135 1.2.4.2 tls if (bus_space_map(sc->sc_buft, memaddr, ED_ZBUS_MEMSIZE, 0, 136 1.2.4.2 tls &sc->sc_bufh)) { 137 1.2.4.2 tls aprint_error_dev(self, "can't map buffer space\n"); 138 1.2.4.2 tls return; 139 1.2.4.2 tls } 140 1.2.4.2 tls 141 1.2.4.2 tls /* SRAM buffer size is always 16K */ 142 1.2.4.2 tls sc->mem_start = 0; 143 1.2.4.2 tls sc->mem_size = ED_ZBUS_MEMSIZE; 144 1.2.4.2 tls 145 1.2.4.2 tls /* 146 1.2.4.2 tls * Read the ethernet address from the PROM. 147 1.2.4.2 tls * Interrupts must be inactive when reading the PROM, as the 148 1.2.4.2 tls * interrupt line is shared with one of its address lines. 149 1.2.4.2 tls */ 150 1.2.4.2 tls 151 1.2.4.2 tls NIC_PUT(sc->sc_regt, sc->sc_regh, ED_P0_IMR, 0x00); 152 1.2.4.2 tls NIC_PUT(sc->sc_regt, sc->sc_regh, ED_P0_ISR, 0xff); 153 1.2.4.2 tls 154 1.2.4.2 tls if (bus_space_map(&zsc->sc_bst, promaddr, ETHER_ADDR_LEN * 2, 0, 155 1.2.4.2 tls &promh) == 0) { 156 1.2.4.2 tls for (i = 0; i < ETHER_ADDR_LEN; i++) 157 1.2.4.2 tls sc->sc_enaddr[i] = 158 1.2.4.2 tls bus_space_read_1(&zsc->sc_bst, promh, i * 2); 159 1.2.4.2 tls 160 1.2.4.2 tls bus_space_unmap(&zsc->sc_bst, promh, ETHER_ADDR_LEN * 2); 161 1.2.4.2 tls } 162 1.2.4.2 tls 163 1.2.4.2 tls /* Initialize sc_reg_map[]. Registers have stride 2 on the bus. */ 164 1.2.4.2 tls for (i = 0; i < 16; i++) 165 1.2.4.2 tls sc->sc_reg_map[i] = i << 1; 166 1.2.4.2 tls 167 1.2.4.2 tls /* 168 1.2.4.2 tls * Set 2 word FIFO threshold, no auto-init Remote DMA, 169 1.2.4.2 tls * byte order 68k, word-wide DMA xfers. 170 1.2.4.2 tls */ 171 1.2.4.2 tls sc->dcr_reg = ED_DCR_FT0 | ED_DCR_WTS | ED_DCR_LS | ED_DCR_BOS; 172 1.2.4.2 tls 173 1.2.4.2 tls /* Remote DMA abort .*/ 174 1.2.4.2 tls sc->cr_proto = ED_CR_RD2; 175 1.2.4.2 tls 176 1.2.4.2 tls /* 177 1.2.4.2 tls * Override all functions which deal with the buffer, because 178 1.2.4.2 tls * this implementation only allows 16-bit buffer accesses. 179 1.2.4.2 tls */ 180 1.2.4.2 tls sc->test_mem = ed_zbus_test_mem; 181 1.2.4.2 tls sc->read_hdr = ed_zbus_read_hdr; 182 1.2.4.2 tls sc->ring_copy = ed_zbus_ring_copy; 183 1.2.4.2 tls sc->write_mbuf = ed_zbus_write_mbuf; 184 1.2.4.2 tls 185 1.2.4.2 tls sc->sc_flags = device_cfdata(self)->cf_flags; 186 1.2.4.2 tls sc->is790 = 0; 187 1.2.4.2 tls sc->sc_media_init = dp8390_media_init; 188 1.2.4.2 tls sc->sc_enabled = 1; 189 1.2.4.2 tls 190 1.2.4.2 tls /* Do generic DS8390/WD83C690 config. */ 191 1.2.4.2 tls if (dp8390_config(sc)) { 192 1.2.4.2 tls bus_space_unmap(sc->sc_buft, sc->sc_bufh, ED_ZBUS_MEMSIZE); 193 1.2.4.2 tls bus_space_unmap(sc->sc_regt, sc->sc_regh, 0x10); 194 1.2.4.2 tls return; 195 1.2.4.2 tls } 196 1.2.4.2 tls 197 1.2.4.2 tls /* establish level 2 interrupt handler */ 198 1.2.4.2 tls zsc->sc_isr.isr_intr = dp8390_intr; 199 1.2.4.2 tls zsc->sc_isr.isr_arg = sc; 200 1.2.4.2 tls zsc->sc_isr.isr_ipl = 2; 201 1.2.4.2 tls add_isr(&zsc->sc_isr); 202 1.2.4.2 tls } 203 1.2.4.2 tls 204 1.2.4.2 tls int 205 1.2.4.2 tls ed_zbus_test_mem(struct dp8390_softc *sc) 206 1.2.4.2 tls { 207 1.2.4.2 tls bus_space_tag_t buft = sc->sc_buft; 208 1.2.4.2 tls bus_space_handle_t bufh = sc->sc_bufh; 209 1.2.4.2 tls int i; 210 1.2.4.2 tls 211 1.2.4.2 tls bus_space_set_region_2(buft, bufh, sc->mem_start, 0, 212 1.2.4.2 tls sc->mem_size >> 1); 213 1.2.4.2 tls 214 1.2.4.2 tls for (i = 0; i < sc->mem_size; i += 2) { 215 1.2.4.2 tls if (bus_space_read_2(sc->sc_buft, sc->sc_bufh, i)) { 216 1.2.4.2 tls printf(": failed to clear NIC buffer at offset %x - " 217 1.2.4.2 tls "check configuration\n", (sc->mem_start + i)); 218 1.2.4.2 tls return 1; 219 1.2.4.2 tls } 220 1.2.4.2 tls } 221 1.2.4.2 tls return 0; 222 1.2.4.2 tls } 223 1.2.4.2 tls 224 1.2.4.2 tls void 225 1.2.4.2 tls ed_zbus_read_hdr(struct dp8390_softc *sc, int src, struct dp8390_ring *hdrp) 226 1.2.4.2 tls { 227 1.2.4.2 tls bus_space_tag_t buft = sc->sc_buft; 228 1.2.4.2 tls bus_space_handle_t bufh = sc->sc_bufh; 229 1.2.4.2 tls uint16_t wrd[2]; 230 1.2.4.2 tls 231 1.2.4.2 tls /* 232 1.2.4.2 tls * Read the 4-byte header as two 16-bit words in little-endian 233 1.2.4.2 tls * format. Convert into big-endian and put them into hdrp. 234 1.2.4.2 tls */ 235 1.2.4.2 tls bus_space_read_region_stream_2(buft, bufh, src, wrd, 2); 236 1.2.4.2 tls hdrp->rsr = wrd[0] & 0xff; 237 1.2.4.2 tls hdrp->next_packet = wrd[0] >> 8; 238 1.2.4.2 tls hdrp->count = bswap16(wrd[1]); 239 1.2.4.2 tls } 240 1.2.4.2 tls 241 1.2.4.2 tls /* 242 1.2.4.2 tls * Copy `amount' bytes from a packet in the ring buffer to a linear 243 1.2.4.2 tls * destination buffer, given a source offset and destination address. 244 1.2.4.2 tls * Takes into account ring-wrap. 245 1.2.4.2 tls */ 246 1.2.4.2 tls int 247 1.2.4.2 tls ed_zbus_ring_copy(struct dp8390_softc *sc, int src, void *dst, u_short amount) 248 1.2.4.2 tls { 249 1.2.4.2 tls bus_space_tag_t buft = sc->sc_buft; 250 1.2.4.2 tls bus_space_handle_t bufh = sc->sc_bufh; 251 1.2.4.2 tls u_short tmp_amount; 252 1.2.4.2 tls u_char readbyte[2]; 253 1.2.4.2 tls 254 1.2.4.2 tls /* Does copy wrap to lower addr in ring buffer? */ 255 1.2.4.2 tls if (src + amount > sc->mem_end) { 256 1.2.4.2 tls tmp_amount = sc->mem_end - src; 257 1.2.4.2 tls 258 1.2.4.2 tls /* copy amount up to end of NIC memory */ 259 1.2.4.2 tls bus_space_read_region_stream_2(buft, bufh, src, dst, 260 1.2.4.2 tls tmp_amount >> 1); 261 1.2.4.2 tls 262 1.2.4.2 tls amount -= tmp_amount; 263 1.2.4.2 tls src = sc->mem_ring; 264 1.2.4.2 tls dst = (u_char *)dst + tmp_amount; 265 1.2.4.2 tls } 266 1.2.4.2 tls 267 1.2.4.2 tls bus_space_read_region_stream_2(buft, bufh, src, dst, amount >> 1); 268 1.2.4.2 tls 269 1.2.4.2 tls /* handle odd length packet */ 270 1.2.4.2 tls if (amount & 1) { 271 1.2.4.2 tls bus_space_read_region_stream_2(buft, bufh, src + amount - 1, 272 1.2.4.2 tls (u_int16_t *)readbyte, 1); 273 1.2.4.2 tls *((u_char *)dst + amount - 1) = readbyte[0]; 274 1.2.4.2 tls amount++; 275 1.2.4.2 tls } 276 1.2.4.2 tls 277 1.2.4.2 tls return src + amount; 278 1.2.4.2 tls } 279 1.2.4.2 tls 280 1.2.4.2 tls /* 281 1.2.4.2 tls * Copy packet from mbuf to the board memory. Currently uses an extra 282 1.2.4.2 tls * buffer/extra memory copy, unless the whole packet fits in one mbuf. 283 1.2.4.2 tls * As in the test_mem function, we use word-wide writes. 284 1.2.4.2 tls */ 285 1.2.4.2 tls int 286 1.2.4.2 tls ed_zbus_write_mbuf(struct dp8390_softc *sc, struct mbuf *m, int buf) 287 1.2.4.2 tls { 288 1.2.4.2 tls u_char *data, savebyte[2]; 289 1.2.4.2 tls int len, wantbyte; 290 1.2.4.2 tls u_short totlen = 0; 291 1.2.4.2 tls 292 1.2.4.2 tls wantbyte = 0; 293 1.2.4.2 tls 294 1.2.4.2 tls for (; m ; m = m->m_next) { 295 1.2.4.2 tls data = mtod(m, u_char *); 296 1.2.4.2 tls len = m->m_len; 297 1.2.4.2 tls totlen += len; 298 1.2.4.2 tls if (len > 0) { 299 1.2.4.2 tls /* Finish the last word. */ 300 1.2.4.2 tls if (wantbyte) { 301 1.2.4.2 tls savebyte[1] = *data; 302 1.2.4.2 tls bus_space_write_region_stream_2(sc->sc_buft, 303 1.2.4.2 tls sc->sc_bufh, buf, 304 1.2.4.2 tls (u_int16_t *)savebyte, 1); 305 1.2.4.2 tls buf += 2; 306 1.2.4.2 tls data++; 307 1.2.4.2 tls len--; 308 1.2.4.2 tls wantbyte = 0; 309 1.2.4.2 tls } 310 1.2.4.2 tls /* Output contiguous words. */ 311 1.2.4.2 tls if (len > 1) { 312 1.2.4.2 tls bus_space_write_region_stream_2(sc->sc_buft, 313 1.2.4.2 tls sc->sc_bufh, buf, 314 1.2.4.2 tls (u_int16_t *)data, len >> 1); 315 1.2.4.2 tls buf += len & ~1; 316 1.2.4.2 tls data += len & ~1; 317 1.2.4.2 tls len &= 1; 318 1.2.4.2 tls } 319 1.2.4.2 tls /* Save last byte, if necessary. */ 320 1.2.4.2 tls if (len == 1) { 321 1.2.4.2 tls savebyte[0] = *data; 322 1.2.4.2 tls wantbyte = 1; 323 1.2.4.2 tls } 324 1.2.4.2 tls } 325 1.2.4.2 tls } 326 1.2.4.2 tls 327 1.2.4.2 tls len = ETHER_PAD_LEN - totlen; 328 1.2.4.2 tls if (wantbyte) { 329 1.2.4.2 tls savebyte[1] = 0; 330 1.2.4.2 tls bus_space_write_region_stream_2(sc->sc_buft, sc->sc_bufh, 331 1.2.4.2 tls buf, (u_int16_t *)savebyte, 1); 332 1.2.4.2 tls buf += 2; 333 1.2.4.2 tls totlen++; 334 1.2.4.2 tls len--; 335 1.2.4.2 tls } 336 1.2.4.2 tls /* if sent data is shorter than EHTER_PAD_LEN, put 0 to padding */ 337 1.2.4.2 tls if (len > 0) { 338 1.2.4.2 tls bus_space_set_region_2(sc->sc_buft, sc->sc_bufh, buf, 0, 339 1.2.4.2 tls len >> 1); 340 1.2.4.2 tls totlen = ETHER_PAD_LEN; 341 1.2.4.2 tls } 342 1.2.4.2 tls return totlen; 343 1.2.4.2 tls } 344
Indexes created Thu Oct 02 14:10:14 GMT 2025