if_esreg.h revision 1.6
1 /* $NetBSD: if_esreg.h,v 1.6 2003/01/28 22:35:05 wiz Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Michael L. Hitch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Michael L. Hitch. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * SMC 91C90 register definitions 35 */ 36 37 union smcregs { 38 struct { 39 volatile u_short tcr; /* Transmit Control Register */ 40 volatile u_short ephsr; /* EPH Status Register */ 41 volatile u_short rcr; /* Receive Control Register */ 42 volatile u_short ecr; /* Counter Register */ 43 volatile u_short mir; /* Memory Information Register */ 44 volatile u_short mcr; /* Memory Configuration Register */ 45 volatile u_short resv; 46 volatile u_short bsr; /* Bank Select Register */ 47 } b0; 48 struct { 49 volatile u_short cr; /* Configuration Register */ 50 volatile u_short bar; /* Base Address Register */ 51 volatile u_short iar[3]; /* Individual Address Registers */ 52 volatile u_short gpr; /* General Purpose Register */ 53 volatile u_short ctr; /* Control Register */ 54 volatile u_short bsr; /* Bank Select Register */ 55 } b1; 56 struct { 57 volatile u_short mmucr; /* MMU Command Register */ 58 volatile u_char pnr; /* Packet Number Register */ 59 volatile u_char arr; /* Allocation Result Register */ 60 volatile u_short fifo; /* FIFO Ports Register */ 61 volatile u_short ptr; /* Pointer Register */ 62 volatile u_short data; /* Data Register */ 63 volatile u_short datax; /* Data Register (2nd mapping) */ 64 volatile u_char ist; /* Interrupt Status Register */ 65 volatile u_char msk; /* Interrupt Mask Register */ 66 volatile u_short bsr; /* Bank Select Register */ 67 } b2; 68 struct { 69 volatile u_short mt[4]; /* Multicast Table */ 70 volatile u_short resv[3]; 71 volatile u_short bsr; /* Bank Select Register */ 72 } b3; 73 /* 74 * Bank 2 registers defined as u_short fields 75 */ 76 struct { 77 volatile u_short mmucr; /* MMU Command Register */ 78 volatile u_short pnrarr;/* Packet Number/Allocation Result */ 79 volatile u_short fifo; /* FIFO Ports Register */ 80 volatile u_short ptr; /* Pointer Register */ 81 volatile u_short data; /* Data Register */ 82 volatile u_short datax; /* Data Register (2nd mapping) */ 83 volatile u_short istmsk;/* Interrupt Status/Mask Register */ 84 volatile u_short bsr; /* Bank Select Register */ 85 } w2; 86 }; 87 88 /* Transmit Control Register */ 89 #define TCR_PAD_EN 0x8000 /* Pad short frames */ 90 #define TCR_TXENA 0x0100 /* Transmit enabled */ 91 #define TCR_MON_CSN 0x0004 /* Monitor carrier */ 92 93 /* EPH Status Register */ 94 #define EPHSR_16COL 0x1000 /* 16 collisions reached */ 95 #define EPHSR_MULCOL 0x0400 /* Multiple collsions */ 96 #define EPHSR_TX_SUC 0x0100 /* Last transmit successful */ 97 #define EPHSR_LOST_CAR 0x0004 /* Lost carrier */ 98 99 /* Receive Control Register */ 100 #define RCR_ALLMUL 0x0400 /* Accept all Multicast frames */ 101 #define RCR_PRMS 0x0200 /* Promiscuous mode */ 102 #define RCR_EPH_RST 0x0080 /* Software activated Reset */ 103 #define RCR_FILT_CAR 0x0040 /* Filter carrier */ 104 #define RCR_STRIP_CRC 0x0002 /* Strip CRC */ 105 #define RCR_RXEN 0x0001 /* Receiver enabled */ 106 107 /* Counter Register */ 108 #define ECR_MCC 0xf000 /* Multiple collision count */ 109 #define ECR_SCC 0x0f00 /* Single collision count */ 110 #define ECR_EDTX 0x00f0 /* Excess deferred TX count */ 111 #define ECR_DTX 0x000f /* Deferred TX count */ 112 113 /* Configuration Register */ 114 #define CR_RAM32K 0x2000 /* 32Kx16 RAM */ 115 #define CR_NO_WAIT_ST 0x0010 /* No wait state */ 116 #define CR_SET_SQLCH 0x0002 /* Squelch level 240mv */ 117 118 /* Control Register */ 119 #define CTR_TE_ENA 0x2000 /* Transmit Error enable */ 120 #define CTR_AUTO_RLSE 0x0008 /* Auto Release */ 121 122 /* MMU Command Register */ 123 #define MMUCR_NOOP 0x0000 /* No operation */ 124 #define MMUCR_ALLOC 0x2000 /* Allocate memory for TX */ 125 #define MMUCR_RESET 0x4000 /* Reset to intitial state */ 126 #define MMUCR_REM_RX 0x6000 /* Remove frame from top of RX FIFO */ 127 #define MMUCR_REMRLS_RX 0x8000 /* Remove & release from top of RX FIFO */ 128 #define MMUCR_RLSPKT 0xa000 /* Release specific packet */ 129 #define MMUCR_ENQ_TX 0xc000 /* Enqueue packet into TX FIFO */ 130 #define MMUCR_RESET_TX 0xe000 /* Reset TX FIFOs */ 131 #define MMUCR_BUSY 0x0100 /* MMU busy */ 132 133 /* Allocation Result Register */ 134 #define ARR_FAILED 0x80 /* Allocation failed */ 135 #define ARR_APN 0x1f /* Allocated packet number */ 136 137 /* FIFO Ports Register */ 138 #define FIFO_TEMPTY 0x8000 /* TX queue empty */ 139 #define FIFO_TXPNR 0x1f00 /* TX done packet number */ 140 #define FIFO_REMPTY 0x0080 /* RX FIFO empty */ 141 #define FIFO_RXPNR 0x001f /* RX FIFO packet number */ 142 143 /* Pointer Register */ 144 #define PTR_RCV 0x0080 /* Use Receive area */ 145 #define PTR_AUTOINCR 0x0040 /* Auto increment pointer on access */ 146 #define PTR_READ 0x0020 /* Read access */ 147 148 /* Interrupt Status Register */ 149 #define IST_EPHINT 0x20 /* EPH Interrupt */ 150 #define IST_RX_OVRN 0x10 /* RX Overrun */ 151 #define IST_ALLOC 0x08 /* MMU Allocation completed */ 152 #define IST_TX_EMPTY 0x04 /* TX FIFO empty */ 153 #define IST_TX 0x02 /* TX complete */ 154 #define IST_RX 0x01 /* RX complete */ 155 156 /* Interrupt Acknowlege Register */ 157 #define ACK_RX_OVRN IST_RX_OVRN 158 #define ACK_TX_EMPTY IST_TX_EMPTY 159 #define ACK_TX IST_TX 160 161 /* Interrupt Mask Register */ 162 #define MSK_EPHINT 0x20 /* EPH Interrupt */ 163 #define MSK_RX_OVRN 0x10 /* RX Overrun */ 164 #define MSK_ALLOC 0x08 /* MMU Allocation completed */ 165 #define MSK_TX_EMPTY 0x04 /* TX FIFO empty */ 166 #define MSK_TX 0x02 /* TX complete */ 167 #define MSK_RX 0x01 /* RX complete */ 168 169 /* Bank Select Register */ 170 #define BSR_MASK 0x0300 171 #define BSR_BANK0 0x0000 /* Select bank 0 */ 172 #define BSR_BANK1 0x0100 /* Select bank 1 */ 173 #define BSR_BANK2 0x0200 /* Select bank 2 */ 174 #define BSR_BANK3 0x0300 /* Select bank 3 */ 175 176 /* Packet Receive Frame Status Word */ 177 #define RFSW_ALGNERR 0x8000 /* Alignment Error */ 178 #define RFSW_BRDCST 0x4000 /* Broadcast frame */ 179 #define RFSW_BADCRC 0x2000 /* Bad CRC */ 180 #define RFSW_ODDFRM 0x1000 /* Odd number of bytes in frame */ 181 #define RFSW_TOOLNG 0x0800 /* Frame was too long */ 182 #define RFSW_TOOSHORT 0x0400 /* Frame was too short */ 183 #define RFSW_HASH 0x007e /* Multicast hash value */ 184 #define RFSW_MULTCAST 0x0001 /* Multicast frame */ 185 186 /* Control byte */ 187 #define CTLB_ODD 0x20 /* Odd number of bytes in frame */ 188 #define CTLB_CRC 0x10 /* Append CRC to transmitted frame */ 189
Indexes created Tue Oct 14 15:09:51 GMT 2025