ite_rt.c revision 1.10
1 1.5 chopps /* 2 1.10 chopps * $Id: ite_rt.c,v 1.10 1994/06/15 19:06:21 chopps Exp $ 3 1.5 chopps */ 4 1.5 chopps 5 1.10 chopps #include "grfrt.h" 6 1.10 chopps #if NGRFRT > 0 7 1.10 chopps 8 1.6 chopps #include <sys/param.h> 9 1.6 chopps #include <sys/conf.h> 10 1.6 chopps #include <sys/proc.h> 11 1.9 chopps #include <sys/device.h> 12 1.6 chopps #include <sys/ioctl.h> 13 1.6 chopps #include <sys/tty.h> 14 1.6 chopps #include <sys/systm.h> 15 1.7 chopps #include <dev/cons.h> 16 1.9 chopps #include <machine/cpu.h> 17 1.9 chopps #include <amiga/amiga/device.h> 18 1.6 chopps #include <amiga/dev/itevar.h> 19 1.6 chopps #include <amiga/dev/grfioctl.h> 20 1.6 chopps #include <amiga/dev/grfvar.h> 21 1.6 chopps #include <amiga/dev/grf_rtreg.h> 22 1.7 chopps 23 1.8 chopps int retina_console = 1; 24 1.7 chopps 25 1.9 chopps void retina_cursor __P((struct ite_softc *,int)); 26 1.9 chopps void retina_scroll __P((struct ite_softc *,int,int,int,int)); 27 1.9 chopps void retina_deinit __P((struct ite_softc *)); 28 1.9 chopps void retina_clear __P((struct ite_softc *,int,int,int,int)); 29 1.9 chopps void retina_putc __P((struct ite_softc *,int,int,int,int)); 30 1.9 chopps void retina_init __P((struct ite_softc *)); 31 1.9 chopps 32 1.7 chopps /* 33 1.9 chopps * this function is called from grf_rt to init the grf_softc->g_conpri 34 1.9 chopps * field each time a retina is attached. 35 1.7 chopps */ 36 1.7 chopps int 37 1.9 chopps grfrt_cnprobe() 38 1.7 chopps { 39 1.9 chopps static int done; 40 1.9 chopps int rv; 41 1.9 chopps 42 1.9 chopps if (retina_console && done == 0) 43 1.9 chopps rv = CN_INTERNAL; 44 1.9 chopps else 45 1.9 chopps rv = CN_NORMAL; 46 1.9 chopps done = 1; 47 1.9 chopps return(rv); 48 1.7 chopps } 49 1.1 mw 50 1.9 chopps /* 51 1.9 chopps * init the required fields in the grf_softc struct for a 52 1.9 chopps * grf to function as an ite. 53 1.9 chopps */ 54 1.9 chopps void 55 1.9 chopps grfrt_iteinit(gp) 56 1.9 chopps struct grf_softc *gp; 57 1.1 mw { 58 1.9 chopps gp->g_iteinit = retina_init; 59 1.9 chopps gp->g_itedeinit = retina_deinit; 60 1.9 chopps gp->g_iteclear = retina_clear; 61 1.9 chopps gp->g_iteputc = retina_putc; 62 1.9 chopps gp->g_itescroll = retina_scroll; 63 1.9 chopps gp->g_itecursor = retina_cursor; 64 1.9 chopps } 65 1.1 mw 66 1.9 chopps void 67 1.9 chopps retina_init(ip) 68 1.9 chopps struct ite_softc *ip; 69 1.9 chopps { 70 1.9 chopps struct MonDef *md; 71 1.1 mw 72 1.9 chopps ip->priv = ip->grf->g_data; 73 1.9 chopps md = (struct MonDef *) ip->priv; 74 1.1 mw 75 1.9 chopps ip->cols = md->TX; 76 1.9 chopps ip->rows = md->TY; 77 1.1 mw } 78 1.1 mw 79 1.1 mw 80 1.1 mw void retina_cursor(struct ite_softc *ip, int flag) 81 1.1 mw { 82 1.1 mw volatile u_char *ba = ip->grf->g_regkva; 83 1.1 mw 84 1.1 mw if (flag == ERASE_CURSOR) 85 1.1 mw { 86 1.1 mw /* disable cursor */ 87 1.1 mw WCrt (ba, CRT_ID_CURSOR_START, RCrt (ba, CRT_ID_CURSOR_START) | 0x20); 88 1.1 mw } 89 1.1 mw else 90 1.1 mw { 91 1.1 mw int pos = ip->curx + ip->cury * ip->cols; 92 1.1 mw 93 1.1 mw /* make sure to enable cursor */ 94 1.1 mw WCrt (ba, CRT_ID_CURSOR_START, RCrt (ba, CRT_ID_CURSOR_START) & ~0x20); 95 1.1 mw 96 1.1 mw /* and position it */ 97 1.1 mw WCrt (ba, CRT_ID_CURSOR_LOC_HIGH, (u_char) (pos >> 8)); 98 1.1 mw WCrt (ba, CRT_ID_CURSOR_LOC_LOW, (u_char) pos); 99 1.1 mw 100 1.1 mw ip->cursorx = ip->curx; 101 1.1 mw ip->cursory = ip->cury; 102 1.1 mw } 103 1.1 mw } 104 1.1 mw 105 1.1 mw 106 1.1 mw 107 1.1 mw static void screen_up (struct ite_softc *ip, int top, int bottom, int lines) 108 1.1 mw { 109 1.1 mw volatile u_char * ba = ip->grf->g_regkva; 110 1.1 mw volatile u_char * fb = ip->grf->g_fbkva; 111 1.1 mw const struct MonDef * md = (struct MonDef *) ip->priv; 112 1.3 mw #ifdef BANKEDDEVPAGER 113 1.3 mw int bank; 114 1.3 mw #endif 115 1.1 mw 116 1.1 mw /* do some bounds-checking here.. */ 117 1.1 mw if (top >= bottom) 118 1.1 mw return; 119 1.1 mw 120 1.1 mw if (top + lines >= bottom) 121 1.1 mw { 122 1.1 mw retina_clear (ip, top, 0, bottom - top, ip->cols); 123 1.1 mw return; 124 1.1 mw } 125 1.1 mw 126 1.1 mw 127 1.3 mw #ifdef BANKEDDEVPAGER 128 1.3 mw /* make sure to save/restore active bank (and if it's only 129 1.3 mw for tests of the feature in text-mode..) */ 130 1.3 mw bank = (RSeq (ba, SEQ_ID_PRIM_HOST_OFF_LO) 131 1.3 mw | (RSeq (ba, SEQ_ID_PRIM_HOST_OFF_HI) << 8)); 132 1.3 mw #endif 133 1.3 mw 134 1.1 mw /* the trick here is to use a feature of the NCR chip. It can 135 1.1 mw optimize data access in various read/write modes. One of 136 1.1 mw the modes is able to read/write from/to different zones. 137 1.1 mw 138 1.1 mw Thus, by setting the read-offset to lineN, and the write-offset 139 1.1 mw to line0, we just cause read/write cycles for all characters 140 1.1 mw up to the last line, and have the chip transfer the data. The 141 1.1 mw `addqb' are the cheapest way to cause read/write cycles (DONT 142 1.1 mw use `tas' on the Amiga!), their results are completely ignored 143 1.1 mw by the NCR chip, it just replicates what it just read. */ 144 1.1 mw 145 1.1 mw /* write to primary, read from secondary */ 146 1.1 mw WSeq (ba, SEQ_ID_EXTENDED_MEM_ENA, (RSeq(ba, SEQ_ID_EXTENDED_MEM_ENA) & 0x1f) | 0 ); 147 1.1 mw /* clear extended chain4 mode */ 148 1.1 mw WSeq (ba, SEQ_ID_EXT_VIDEO_ADDR, RSeq(ba, SEQ_ID_EXT_VIDEO_ADDR) & ~0x02); 149 1.1 mw 150 1.1 mw /* set write mode 1, "[...] data in the read latches is written 151 1.1 mw to memory during CPU memory write cycles. [...]" */ 152 1.1 mw WGfx (ba, GCT_ID_GRAPHICS_MODE, (RGfx(ba, GCT_ID_GRAPHICS_MODE) & 0xfc) | 1); 153 1.1 mw 154 1.1 mw { 155 1.1 mw /* write to line TOP */ 156 1.1 mw long toploc = top * (md->TX / 16); 157 1.1 mw WSeq (ba, SEQ_ID_PRIM_HOST_OFF_LO, ((unsigned char)toploc)); 158 1.1 mw WSeq (ba, SEQ_ID_PRIM_HOST_OFF_HI, ((unsigned char)(toploc >> 8))); 159 1.1 mw } 160 1.1 mw { 161 1.1 mw /* read from line TOP + LINES */ 162 1.1 mw long fromloc = (top+lines) * (md->TX / 16); 163 1.1 mw WSeq (ba, SEQ_ID_SEC_HOST_OFF_LO, ((unsigned char)fromloc)) ; 164 1.1 mw WSeq (ba, SEQ_ID_SEC_HOST_OFF_HI, ((unsigned char)(fromloc >> 8))) ; 165 1.1 mw } 166 1.1 mw { 167 1.1 mw unsigned char * p = (unsigned char *) fb; 168 1.1 mw /* transfer all characters but LINES lines, unroll by 16 */ 169 1.1 mw short x = (1 + bottom - (top + lines)) * (md->TX / 16) - 1; 170 1.1 mw do { 171 1.1 mw asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p)); 172 1.1 mw asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p)); 173 1.1 mw asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p)); 174 1.1 mw asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p)); 175 1.1 mw asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p)); 176 1.1 mw asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p)); 177 1.1 mw asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p)); 178 1.1 mw asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p)); 179 1.1 mw asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p)); 180 1.1 mw asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p)); 181 1.1 mw asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p)); 182 1.1 mw asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p)); 183 1.1 mw asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p)); 184 1.1 mw asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p)); 185 1.1 mw asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p)); 186 1.1 mw asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p)); 187 1.1 mw } while (x--); 188 1.1 mw } 189 1.1 mw 190 1.1 mw /* reset to default values */ 191 1.1 mw WSeq (ba, SEQ_ID_SEC_HOST_OFF_HI, 0); 192 1.1 mw WSeq (ba, SEQ_ID_SEC_HOST_OFF_LO, 0); 193 1.1 mw WSeq (ba, SEQ_ID_PRIM_HOST_OFF_HI, 0); 194 1.1 mw WSeq (ba, SEQ_ID_PRIM_HOST_OFF_LO, 0); 195 1.1 mw /* write mode 0 */ 196 1.1 mw WGfx (ba, GCT_ID_GRAPHICS_MODE, (RGfx(ba, GCT_ID_GRAPHICS_MODE) & 0xfc) | 0); 197 1.1 mw /* extended chain4 enable */ 198 1.1 mw WSeq (ba, SEQ_ID_EXT_VIDEO_ADDR , RSeq(ba, SEQ_ID_EXT_VIDEO_ADDR) | 0x02); 199 1.1 mw /* read/write to primary on A0, secondary on B0 */ 200 1.1 mw WSeq (ba, SEQ_ID_EXTENDED_MEM_ENA, (RSeq(ba, SEQ_ID_EXTENDED_MEM_ENA) & 0x1f) | 0x40 ); 201 1.1 mw 202 1.1 mw 203 1.1 mw /* fill the free lines with spaces */ 204 1.1 mw 205 1.1 mw { /* feed latches with value */ 206 1.1 mw unsigned short * f = (unsigned short *) fb; 207 1.1 mw 208 1.1 mw f += (1 + bottom - lines) * md->TX * 2; 209 1.1 mw *f = 0x2010; 210 1.1 mw { 211 1.1 mw volatile unsigned short dummy = *((volatile unsigned short *)f); 212 1.1 mw } 213 1.1 mw } 214 1.1 mw 215 1.1 mw /* clear extended chain4 mode */ 216 1.1 mw WSeq (ba, SEQ_ID_EXT_VIDEO_ADDR, RSeq(ba, SEQ_ID_EXT_VIDEO_ADDR) & ~0x02); 217 1.1 mw /* set write mode 1, "[...] data in the read latches is written 218 1.1 mw to memory during CPU memory write cycles. [...]" */ 219 1.1 mw WGfx (ba, GCT_ID_GRAPHICS_MODE, (RGfx(ba, GCT_ID_GRAPHICS_MODE) & 0xfc) | 1); 220 1.1 mw 221 1.1 mw { 222 1.1 mw unsigned long * p = (unsigned long *) fb; 223 1.1 mw short x = (lines * (md->TX/16)) - 1; 224 1.1 mw const unsigned long dummyval = 0; 225 1.1 mw 226 1.1 mw p += (1 + bottom - lines) * (md->TX/4); 227 1.1 mw 228 1.1 mw do { 229 1.1 mw *p++ = dummyval; 230 1.1 mw *p++ = dummyval; 231 1.1 mw *p++ = dummyval; 232 1.1 mw *p++ = dummyval; 233 1.1 mw } while (x--); 234 1.1 mw } 235 1.1 mw 236 1.1 mw /* write mode 0 */ 237 1.1 mw WGfx (ba, GCT_ID_GRAPHICS_MODE, (RGfx(ba, GCT_ID_GRAPHICS_MODE) & 0xfc) | 0); 238 1.1 mw /* extended chain4 enable */ 239 1.1 mw WSeq (ba, SEQ_ID_EXT_VIDEO_ADDR , RSeq(ba, SEQ_ID_EXT_VIDEO_ADDR) | 0x02); 240 1.3 mw 241 1.3 mw #ifdef BANKEDDEVPAGER 242 1.3 mw /* restore former bank */ 243 1.3 mw WSeq (ba, SEQ_ID_PRIM_HOST_OFF_LO, (unsigned char) bank); 244 1.3 mw bank >>= 8; 245 1.3 mw WSeq (ba, SEQ_ID_PRIM_HOST_OFF_HI, (unsigned char) bank); 246 1.3 mw #endif 247 1.1 mw }; 248 1.1 mw 249 1.1 mw static void screen_down (struct ite_softc *ip, int top, int bottom, int lines) 250 1.1 mw { 251 1.1 mw volatile u_char * ba = ip->grf->g_regkva; 252 1.1 mw volatile u_char * fb = ip->grf->g_fbkva; 253 1.1 mw const struct MonDef * md = (struct MonDef *) ip->priv; 254 1.3 mw #ifdef BANKEDDEVPAGER 255 1.3 mw int bank; 256 1.3 mw #endif 257 1.1 mw 258 1.1 mw /* do some bounds-checking here.. */ 259 1.1 mw if (top >= bottom) 260 1.1 mw return; 261 1.1 mw 262 1.1 mw if (top + lines >= bottom) 263 1.1 mw { 264 1.1 mw retina_clear (ip, top, 0, bottom - top, ip->cols); 265 1.1 mw return; 266 1.1 mw } 267 1.1 mw 268 1.3 mw #ifdef BANKEDDEVPAGER 269 1.3 mw /* make sure to save/restore active bank (and if it's only 270 1.3 mw for tests of the feature in text-mode..) */ 271 1.3 mw bank = (RSeq (ba, SEQ_ID_PRIM_HOST_OFF_LO) 272 1.3 mw | (RSeq (ba, SEQ_ID_PRIM_HOST_OFF_HI) << 8)); 273 1.3 mw #endif 274 1.1 mw /* see screen_up() for explanation of chip-tricks */ 275 1.1 mw 276 1.1 mw /* write to primary, read from secondary */ 277 1.1 mw WSeq (ba, SEQ_ID_EXTENDED_MEM_ENA, (RSeq(ba, SEQ_ID_EXTENDED_MEM_ENA) & 0x1f) | 0 ); 278 1.1 mw /* clear extended chain4 mode */ 279 1.1 mw WSeq (ba, SEQ_ID_EXT_VIDEO_ADDR, RSeq(ba, SEQ_ID_EXT_VIDEO_ADDR) & ~0x02); 280 1.1 mw 281 1.1 mw /* set write mode 1, "[...] data in the read latches is written 282 1.1 mw to memory during CPU memory write cycles. [...]" */ 283 1.1 mw WGfx (ba, GCT_ID_GRAPHICS_MODE, (RGfx(ba, GCT_ID_GRAPHICS_MODE) & 0xfc) | 1); 284 1.1 mw 285 1.1 mw { 286 1.1 mw /* write to line TOP + LINES */ 287 1.1 mw long toloc = (top + lines) * (md->TX / 16); 288 1.1 mw WSeq (ba, SEQ_ID_PRIM_HOST_OFF_LO, ((unsigned char)toloc)); 289 1.1 mw WSeq (ba, SEQ_ID_PRIM_HOST_OFF_HI, ((unsigned char)(toloc >> 8))); 290 1.1 mw } 291 1.1 mw { 292 1.1 mw /* read from line TOP */ 293 1.1 mw long fromloc = top * (md->TX / 16); 294 1.1 mw WSeq (ba, SEQ_ID_SEC_HOST_OFF_LO, ((unsigned char)fromloc)); 295 1.1 mw WSeq (ba, SEQ_ID_SEC_HOST_OFF_HI, ((unsigned char)(fromloc >> 8))) ; 296 1.1 mw } 297 1.1 mw 298 1.1 mw { 299 1.1 mw unsigned char * p = (unsigned char *) fb; 300 1.1 mw short x = (1 + bottom - (top + lines)) * (md->TX / 16) - 1; 301 1.1 mw p += (1 + bottom - (top + lines)) * md->TX; 302 1.1 mw do { 303 1.1 mw asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p)); 304 1.1 mw asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p)); 305 1.1 mw asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p)); 306 1.1 mw asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p)); 307 1.1 mw asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p)); 308 1.1 mw asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p)); 309 1.1 mw asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p)); 310 1.1 mw asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p)); 311 1.1 mw asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p)); 312 1.1 mw asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p)); 313 1.1 mw asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p)); 314 1.1 mw asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p)); 315 1.1 mw asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p)); 316 1.1 mw asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p)); 317 1.1 mw asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p)); 318 1.1 mw asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p)); 319 1.1 mw } while (x--); 320 1.1 mw } 321 1.1 mw 322 1.1 mw WSeq (ba, SEQ_ID_PRIM_HOST_OFF_HI, 0); 323 1.1 mw WSeq (ba, SEQ_ID_PRIM_HOST_OFF_LO, 0); 324 1.1 mw WSeq (ba, SEQ_ID_SEC_HOST_OFF_HI, 0); 325 1.1 mw WSeq (ba, SEQ_ID_SEC_HOST_OFF_LO, 0); 326 1.1 mw 327 1.1 mw /* write mode 0 */ 328 1.1 mw WGfx (ba, GCT_ID_GRAPHICS_MODE, (RGfx(ba, GCT_ID_GRAPHICS_MODE) & 0xfc) | 0); 329 1.1 mw /* extended chain4 enable */ 330 1.1 mw WSeq (ba, SEQ_ID_EXT_VIDEO_ADDR , RSeq(ba, SEQ_ID_EXT_VIDEO_ADDR) | 0x02); 331 1.1 mw /* read/write to primary on A0, secondary on B0 */ 332 1.1 mw WSeq (ba, SEQ_ID_EXTENDED_MEM_ENA, (RSeq(ba, SEQ_ID_EXTENDED_MEM_ENA) & 0x1f) | 0x40 ); 333 1.1 mw 334 1.1 mw /* fill the free lines with spaces */ 335 1.1 mw 336 1.1 mw { /* feed latches with value */ 337 1.1 mw unsigned short * f = (unsigned short *) fb; 338 1.1 mw 339 1.1 mw f += top * md->TX * 2; 340 1.1 mw *f = 0x2010; 341 1.1 mw { 342 1.1 mw volatile unsigned short dummy = *((volatile unsigned short *)f); 343 1.1 mw } 344 1.1 mw } 345 1.1 mw 346 1.1 mw /* clear extended chain4 mode */ 347 1.1 mw WSeq (ba, SEQ_ID_EXT_VIDEO_ADDR, RSeq(ba, SEQ_ID_EXT_VIDEO_ADDR) & ~0x02); 348 1.1 mw /* set write mode 1, "[...] data in the read latches is written 349 1.1 mw to memory during CPU memory write cycles. [...]" */ 350 1.1 mw WGfx (ba, GCT_ID_GRAPHICS_MODE, (RGfx(ba, GCT_ID_GRAPHICS_MODE) & 0xfc) | 1); 351 1.1 mw 352 1.1 mw { 353 1.1 mw unsigned long * p = (unsigned long *) fb; 354 1.1 mw short x = (lines * (md->TX/16)) - 1; 355 1.1 mw const unsigned long dummyval = 0; 356 1.1 mw 357 1.1 mw p += top * (md->TX/4); 358 1.1 mw 359 1.1 mw do { 360 1.1 mw *p++ = dummyval; 361 1.1 mw *p++ = dummyval; 362 1.1 mw *p++ = dummyval; 363 1.1 mw *p++ = dummyval; 364 1.1 mw } while (x--); 365 1.1 mw } 366 1.1 mw 367 1.1 mw /* write mode 0 */ 368 1.1 mw WGfx (ba, GCT_ID_GRAPHICS_MODE, (RGfx(ba, GCT_ID_GRAPHICS_MODE) & 0xfc) | 0); 369 1.1 mw /* extended chain4 enable */ 370 1.1 mw WSeq (ba, SEQ_ID_EXT_VIDEO_ADDR , RSeq(ba, SEQ_ID_EXT_VIDEO_ADDR) | 0x02); 371 1.1 mw 372 1.3 mw #ifdef BANKEDDEVPAGER 373 1.3 mw /* restore former bank */ 374 1.3 mw WSeq (ba, SEQ_ID_PRIM_HOST_OFF_LO, (unsigned char) bank); 375 1.3 mw bank >>= 8; 376 1.3 mw WSeq (ba, SEQ_ID_PRIM_HOST_OFF_HI, (unsigned char) bank); 377 1.3 mw #endif 378 1.1 mw }; 379 1.1 mw 380 1.1 mw void retina_deinit(struct ite_softc *ip) 381 1.1 mw { 382 1.1 mw ip->flags &= ~ITE_INITED; 383 1.1 mw } 384 1.1 mw 385 1.1 mw 386 1.1 mw void retina_putc(struct ite_softc *ip, int c, int dy, int dx, int mode) 387 1.1 mw { 388 1.1 mw volatile u_char * ba = ip->grf->g_regkva; 389 1.1 mw volatile u_char * fb = ip->grf->g_fbkva; 390 1.1 mw register u_char attr; 391 1.1 mw 392 1.1 mw attr = (mode & ATTR_INV) ? 0x21 : 0x10; 393 1.1 mw if (mode & ATTR_UL) attr = 0x01; /* ???????? */ 394 1.1 mw if (mode & ATTR_BOLD) attr |= 0x08; 395 1.1 mw if (mode & ATTR_BLINK) attr |= 0x80; 396 1.1 mw 397 1.1 mw fb += 4 * (dy * ip->cols + dx); 398 1.1 mw *fb++ = c; *fb = attr; 399 1.1 mw } 400 1.1 mw 401 1.1 mw void retina_clear(struct ite_softc *ip, int sy, int sx, int h, int w) 402 1.1 mw { 403 1.1 mw volatile u_char * ba = ip->grf->g_regkva; 404 1.1 mw u_short * fb = (u_short *) ip->grf->g_fbkva; 405 1.1 mw short x; 406 1.1 mw const u_short fillval = 0x2010; 407 1.1 mw /* could probably be optimized just like the scrolling functions !! */ 408 1.1 mw fb += 2 * (sy * ip->cols + sx); 409 1.1 mw while (h--) 410 1.1 mw { 411 1.1 mw for (x = 2 * (w - 1); x >= 0; x -= 2) 412 1.1 mw fb[x] = fillval; 413 1.1 mw fb += 2 * ip->cols; 414 1.1 mw } 415 1.1 mw } 416 1.1 mw 417 1.1 mw void retina_scroll(struct ite_softc *ip, int sy, int sx, int count, int dir) 418 1.1 mw { 419 1.1 mw volatile u_char * ba = ip->grf->g_regkva; 420 1.4 chopps u_long * fb = (u_long *) ip->grf->g_fbkva; 421 1.1 mw register int height, dy, i; 422 1.1 mw 423 1.1 mw retina_cursor(ip, ERASE_CURSOR); 424 1.1 mw 425 1.1 mw if (dir == SCROLL_UP) 426 1.1 mw { 427 1.1 mw screen_up (ip, sy - count, ip->bottom_margin, count); 428 1.1 mw /* bcopy (fb + sy * ip->cols, fb + (sy - count) * ip->cols, 4 * (ip->bottom_margin - sy + 1) * ip->cols); */ 429 1.1 mw /* retina_clear (ip, ip->bottom_margin + 1 - count, 0, count, ip->cols); */ 430 1.1 mw } 431 1.1 mw else if (dir == SCROLL_DOWN) 432 1.1 mw { 433 1.1 mw screen_down (ip, sy, ip->bottom_margin, count); 434 1.1 mw /* bcopy (fb + sy * ip->cols, fb + (sy + count) * ip->cols, 4 * (ip->bottom_margin - sy - count + 1) * ip->cols); */ 435 1.1 mw /* retina_clear (ip, sy, 0, count, ip->cols); */ 436 1.1 mw } 437 1.1 mw else if (dir == SCROLL_RIGHT) 438 1.1 mw { 439 1.1 mw bcopy (fb + sx + sy * ip->cols, fb + sx + sy * ip->cols + count, 4 * (ip->cols - (sx + count))); 440 1.1 mw retina_clear (ip, sy, sx, 1, count); 441 1.1 mw } 442 1.1 mw else 443 1.1 mw { 444 1.1 mw bcopy (fb + sx + sy * ip->cols, fb + sx - count + sy * ip->cols, 4 * (ip->cols - sx)); 445 1.1 mw retina_clear (ip, sy, ip->cols - count, 1, count); 446 1.1 mw } 447 1.1 mw } 448 1.10 chopps 449 1.10 chopps #endif /* NGRFRT */ 450
Indexes created Fri Sep 26 08:10:20 GMT 2025