ite_rt.c revision 1.6
1 1.5 chopps /* 2 1.6 chopps * $Id: ite_rt.c,v 1.6 1994/02/13 21:10:47 chopps Exp $ 3 1.5 chopps */ 4 1.5 chopps 5 1.1 mw #include "ite.h" 6 1.1 mw #if NITE > 0 7 1.1 mw 8 1.6 chopps #include <sys/param.h> 9 1.6 chopps #include <sys/conf.h> 10 1.6 chopps #include <sys/proc.h> 11 1.6 chopps #include <sys/ioctl.h> 12 1.6 chopps #include <sys/tty.h> 13 1.6 chopps #include <sys/systm.h> 14 1.1 mw 15 1.6 chopps #include <amiga/dev/itevar.h> 16 1.1 mw 17 1.6 chopps #include <machine/cpu.h> 18 1.1 mw 19 1.1 mw /* XXX */ 20 1.6 chopps #include <amiga/dev/grfioctl.h> 21 1.6 chopps #include <amiga/dev/grfvar.h> 22 1.6 chopps #include <amiga/dev/grf_rtreg.h> 23 1.1 mw 24 1.1 mw void retina_init(struct ite_softc *ip) 25 1.1 mw { 26 1.1 mw struct MonDef *md; 27 1.1 mw 28 1.1 mw if (ip->grf == 0) 29 1.1 mw ip->grf = &grf_softc[ip - ite_softc]; 30 1.1 mw 31 1.2 mw ip->priv = ip->grf->g_data; 32 1.1 mw md = (struct MonDef *) ip->priv; 33 1.1 mw 34 1.1 mw ip->cols = md->TX; 35 1.1 mw ip->rows = md->TY; 36 1.1 mw } 37 1.1 mw 38 1.1 mw 39 1.1 mw void retina_cursor(struct ite_softc *ip, int flag) 40 1.1 mw { 41 1.1 mw volatile u_char *ba = ip->grf->g_regkva; 42 1.1 mw 43 1.1 mw if (flag == ERASE_CURSOR) 44 1.1 mw { 45 1.1 mw /* disable cursor */ 46 1.1 mw WCrt (ba, CRT_ID_CURSOR_START, RCrt (ba, CRT_ID_CURSOR_START) | 0x20); 47 1.1 mw } 48 1.1 mw else 49 1.1 mw { 50 1.1 mw int pos = ip->curx + ip->cury * ip->cols; 51 1.1 mw 52 1.1 mw /* make sure to enable cursor */ 53 1.1 mw WCrt (ba, CRT_ID_CURSOR_START, RCrt (ba, CRT_ID_CURSOR_START) & ~0x20); 54 1.1 mw 55 1.1 mw /* and position it */ 56 1.1 mw WCrt (ba, CRT_ID_CURSOR_LOC_HIGH, (u_char) (pos >> 8)); 57 1.1 mw WCrt (ba, CRT_ID_CURSOR_LOC_LOW, (u_char) pos); 58 1.1 mw 59 1.1 mw ip->cursorx = ip->curx; 60 1.1 mw ip->cursory = ip->cury; 61 1.1 mw } 62 1.1 mw } 63 1.1 mw 64 1.1 mw 65 1.1 mw 66 1.1 mw static void screen_up (struct ite_softc *ip, int top, int bottom, int lines) 67 1.1 mw { 68 1.1 mw volatile u_char * ba = ip->grf->g_regkva; 69 1.1 mw volatile u_char * fb = ip->grf->g_fbkva; 70 1.1 mw const struct MonDef * md = (struct MonDef *) ip->priv; 71 1.3 mw #ifdef BANKEDDEVPAGER 72 1.3 mw int bank; 73 1.3 mw #endif 74 1.1 mw 75 1.1 mw /* do some bounds-checking here.. */ 76 1.1 mw if (top >= bottom) 77 1.1 mw return; 78 1.1 mw 79 1.1 mw if (top + lines >= bottom) 80 1.1 mw { 81 1.1 mw retina_clear (ip, top, 0, bottom - top, ip->cols); 82 1.1 mw return; 83 1.1 mw } 84 1.1 mw 85 1.1 mw 86 1.3 mw #ifdef BANKEDDEVPAGER 87 1.3 mw /* make sure to save/restore active bank (and if it's only 88 1.3 mw for tests of the feature in text-mode..) */ 89 1.3 mw bank = (RSeq (ba, SEQ_ID_PRIM_HOST_OFF_LO) 90 1.3 mw | (RSeq (ba, SEQ_ID_PRIM_HOST_OFF_HI) << 8)); 91 1.3 mw #endif 92 1.3 mw 93 1.1 mw /* the trick here is to use a feature of the NCR chip. It can 94 1.1 mw optimize data access in various read/write modes. One of 95 1.1 mw the modes is able to read/write from/to different zones. 96 1.1 mw 97 1.1 mw Thus, by setting the read-offset to lineN, and the write-offset 98 1.1 mw to line0, we just cause read/write cycles for all characters 99 1.1 mw up to the last line, and have the chip transfer the data. The 100 1.1 mw `addqb' are the cheapest way to cause read/write cycles (DONT 101 1.1 mw use `tas' on the Amiga!), their results are completely ignored 102 1.1 mw by the NCR chip, it just replicates what it just read. */ 103 1.1 mw 104 1.1 mw /* write to primary, read from secondary */ 105 1.1 mw WSeq (ba, SEQ_ID_EXTENDED_MEM_ENA, (RSeq(ba, SEQ_ID_EXTENDED_MEM_ENA) & 0x1f) | 0 ); 106 1.1 mw /* clear extended chain4 mode */ 107 1.1 mw WSeq (ba, SEQ_ID_EXT_VIDEO_ADDR, RSeq(ba, SEQ_ID_EXT_VIDEO_ADDR) & ~0x02); 108 1.1 mw 109 1.1 mw /* set write mode 1, "[...] data in the read latches is written 110 1.1 mw to memory during CPU memory write cycles. [...]" */ 111 1.1 mw WGfx (ba, GCT_ID_GRAPHICS_MODE, (RGfx(ba, GCT_ID_GRAPHICS_MODE) & 0xfc) | 1); 112 1.1 mw 113 1.1 mw { 114 1.1 mw /* write to line TOP */ 115 1.1 mw long toploc = top * (md->TX / 16); 116 1.1 mw WSeq (ba, SEQ_ID_PRIM_HOST_OFF_LO, ((unsigned char)toploc)); 117 1.1 mw WSeq (ba, SEQ_ID_PRIM_HOST_OFF_HI, ((unsigned char)(toploc >> 8))); 118 1.1 mw } 119 1.1 mw { 120 1.1 mw /* read from line TOP + LINES */ 121 1.1 mw long fromloc = (top+lines) * (md->TX / 16); 122 1.1 mw WSeq (ba, SEQ_ID_SEC_HOST_OFF_LO, ((unsigned char)fromloc)) ; 123 1.1 mw WSeq (ba, SEQ_ID_SEC_HOST_OFF_HI, ((unsigned char)(fromloc >> 8))) ; 124 1.1 mw } 125 1.1 mw { 126 1.1 mw unsigned char * p = (unsigned char *) fb; 127 1.1 mw /* transfer all characters but LINES lines, unroll by 16 */ 128 1.1 mw short x = (1 + bottom - (top + lines)) * (md->TX / 16) - 1; 129 1.1 mw do { 130 1.1 mw asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p)); 131 1.1 mw asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p)); 132 1.1 mw asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p)); 133 1.1 mw asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p)); 134 1.1 mw asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p)); 135 1.1 mw asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p)); 136 1.1 mw asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p)); 137 1.1 mw asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p)); 138 1.1 mw asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p)); 139 1.1 mw asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p)); 140 1.1 mw asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p)); 141 1.1 mw asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p)); 142 1.1 mw asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p)); 143 1.1 mw asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p)); 144 1.1 mw asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p)); 145 1.1 mw asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p)); 146 1.1 mw } while (x--); 147 1.1 mw } 148 1.1 mw 149 1.1 mw /* reset to default values */ 150 1.1 mw WSeq (ba, SEQ_ID_SEC_HOST_OFF_HI, 0); 151 1.1 mw WSeq (ba, SEQ_ID_SEC_HOST_OFF_LO, 0); 152 1.1 mw WSeq (ba, SEQ_ID_PRIM_HOST_OFF_HI, 0); 153 1.1 mw WSeq (ba, SEQ_ID_PRIM_HOST_OFF_LO, 0); 154 1.1 mw /* write mode 0 */ 155 1.1 mw WGfx (ba, GCT_ID_GRAPHICS_MODE, (RGfx(ba, GCT_ID_GRAPHICS_MODE) & 0xfc) | 0); 156 1.1 mw /* extended chain4 enable */ 157 1.1 mw WSeq (ba, SEQ_ID_EXT_VIDEO_ADDR , RSeq(ba, SEQ_ID_EXT_VIDEO_ADDR) | 0x02); 158 1.1 mw /* read/write to primary on A0, secondary on B0 */ 159 1.1 mw WSeq (ba, SEQ_ID_EXTENDED_MEM_ENA, (RSeq(ba, SEQ_ID_EXTENDED_MEM_ENA) & 0x1f) | 0x40 ); 160 1.1 mw 161 1.1 mw 162 1.1 mw /* fill the free lines with spaces */ 163 1.1 mw 164 1.1 mw { /* feed latches with value */ 165 1.1 mw unsigned short * f = (unsigned short *) fb; 166 1.1 mw 167 1.1 mw f += (1 + bottom - lines) * md->TX * 2; 168 1.1 mw *f = 0x2010; 169 1.1 mw { 170 1.1 mw volatile unsigned short dummy = *((volatile unsigned short *)f); 171 1.1 mw } 172 1.1 mw } 173 1.1 mw 174 1.1 mw /* clear extended chain4 mode */ 175 1.1 mw WSeq (ba, SEQ_ID_EXT_VIDEO_ADDR, RSeq(ba, SEQ_ID_EXT_VIDEO_ADDR) & ~0x02); 176 1.1 mw /* set write mode 1, "[...] data in the read latches is written 177 1.1 mw to memory during CPU memory write cycles. [...]" */ 178 1.1 mw WGfx (ba, GCT_ID_GRAPHICS_MODE, (RGfx(ba, GCT_ID_GRAPHICS_MODE) & 0xfc) | 1); 179 1.1 mw 180 1.1 mw { 181 1.1 mw unsigned long * p = (unsigned long *) fb; 182 1.1 mw short x = (lines * (md->TX/16)) - 1; 183 1.1 mw const unsigned long dummyval = 0; 184 1.1 mw 185 1.1 mw p += (1 + bottom - lines) * (md->TX/4); 186 1.1 mw 187 1.1 mw do { 188 1.1 mw *p++ = dummyval; 189 1.1 mw *p++ = dummyval; 190 1.1 mw *p++ = dummyval; 191 1.1 mw *p++ = dummyval; 192 1.1 mw } while (x--); 193 1.1 mw } 194 1.1 mw 195 1.1 mw /* write mode 0 */ 196 1.1 mw WGfx (ba, GCT_ID_GRAPHICS_MODE, (RGfx(ba, GCT_ID_GRAPHICS_MODE) & 0xfc) | 0); 197 1.1 mw /* extended chain4 enable */ 198 1.1 mw WSeq (ba, SEQ_ID_EXT_VIDEO_ADDR , RSeq(ba, SEQ_ID_EXT_VIDEO_ADDR) | 0x02); 199 1.3 mw 200 1.3 mw #ifdef BANKEDDEVPAGER 201 1.3 mw /* restore former bank */ 202 1.3 mw WSeq (ba, SEQ_ID_PRIM_HOST_OFF_LO, (unsigned char) bank); 203 1.3 mw bank >>= 8; 204 1.3 mw WSeq (ba, SEQ_ID_PRIM_HOST_OFF_HI, (unsigned char) bank); 205 1.3 mw #endif 206 1.1 mw }; 207 1.1 mw 208 1.1 mw static void screen_down (struct ite_softc *ip, int top, int bottom, int lines) 209 1.1 mw { 210 1.1 mw volatile u_char * ba = ip->grf->g_regkva; 211 1.1 mw volatile u_char * fb = ip->grf->g_fbkva; 212 1.1 mw const struct MonDef * md = (struct MonDef *) ip->priv; 213 1.3 mw #ifdef BANKEDDEVPAGER 214 1.3 mw int bank; 215 1.3 mw #endif 216 1.1 mw 217 1.1 mw /* do some bounds-checking here.. */ 218 1.1 mw if (top >= bottom) 219 1.1 mw return; 220 1.1 mw 221 1.1 mw if (top + lines >= bottom) 222 1.1 mw { 223 1.1 mw retina_clear (ip, top, 0, bottom - top, ip->cols); 224 1.1 mw return; 225 1.1 mw } 226 1.1 mw 227 1.3 mw #ifdef BANKEDDEVPAGER 228 1.3 mw /* make sure to save/restore active bank (and if it's only 229 1.3 mw for tests of the feature in text-mode..) */ 230 1.3 mw bank = (RSeq (ba, SEQ_ID_PRIM_HOST_OFF_LO) 231 1.3 mw | (RSeq (ba, SEQ_ID_PRIM_HOST_OFF_HI) << 8)); 232 1.3 mw #endif 233 1.1 mw /* see screen_up() for explanation of chip-tricks */ 234 1.1 mw 235 1.1 mw /* write to primary, read from secondary */ 236 1.1 mw WSeq (ba, SEQ_ID_EXTENDED_MEM_ENA, (RSeq(ba, SEQ_ID_EXTENDED_MEM_ENA) & 0x1f) | 0 ); 237 1.1 mw /* clear extended chain4 mode */ 238 1.1 mw WSeq (ba, SEQ_ID_EXT_VIDEO_ADDR, RSeq(ba, SEQ_ID_EXT_VIDEO_ADDR) & ~0x02); 239 1.1 mw 240 1.1 mw /* set write mode 1, "[...] data in the read latches is written 241 1.1 mw to memory during CPU memory write cycles. [...]" */ 242 1.1 mw WGfx (ba, GCT_ID_GRAPHICS_MODE, (RGfx(ba, GCT_ID_GRAPHICS_MODE) & 0xfc) | 1); 243 1.1 mw 244 1.1 mw { 245 1.1 mw /* write to line TOP + LINES */ 246 1.1 mw long toloc = (top + lines) * (md->TX / 16); 247 1.1 mw WSeq (ba, SEQ_ID_PRIM_HOST_OFF_LO, ((unsigned char)toloc)); 248 1.1 mw WSeq (ba, SEQ_ID_PRIM_HOST_OFF_HI, ((unsigned char)(toloc >> 8))); 249 1.1 mw } 250 1.1 mw { 251 1.1 mw /* read from line TOP */ 252 1.1 mw long fromloc = top * (md->TX / 16); 253 1.1 mw WSeq (ba, SEQ_ID_SEC_HOST_OFF_LO, ((unsigned char)fromloc)); 254 1.1 mw WSeq (ba, SEQ_ID_SEC_HOST_OFF_HI, ((unsigned char)(fromloc >> 8))) ; 255 1.1 mw } 256 1.1 mw 257 1.1 mw { 258 1.1 mw unsigned char * p = (unsigned char *) fb; 259 1.1 mw short x = (1 + bottom - (top + lines)) * (md->TX / 16) - 1; 260 1.1 mw p += (1 + bottom - (top + lines)) * md->TX; 261 1.1 mw do { 262 1.1 mw asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p)); 263 1.1 mw asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p)); 264 1.1 mw asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p)); 265 1.1 mw asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p)); 266 1.1 mw asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p)); 267 1.1 mw asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p)); 268 1.1 mw asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p)); 269 1.1 mw asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p)); 270 1.1 mw asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p)); 271 1.1 mw asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p)); 272 1.1 mw asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p)); 273 1.1 mw asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p)); 274 1.1 mw asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p)); 275 1.1 mw asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p)); 276 1.1 mw asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p)); 277 1.1 mw asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p)); 278 1.1 mw } while (x--); 279 1.1 mw } 280 1.1 mw 281 1.1 mw WSeq (ba, SEQ_ID_PRIM_HOST_OFF_HI, 0); 282 1.1 mw WSeq (ba, SEQ_ID_PRIM_HOST_OFF_LO, 0); 283 1.1 mw WSeq (ba, SEQ_ID_SEC_HOST_OFF_HI, 0); 284 1.1 mw WSeq (ba, SEQ_ID_SEC_HOST_OFF_LO, 0); 285 1.1 mw 286 1.1 mw /* write mode 0 */ 287 1.1 mw WGfx (ba, GCT_ID_GRAPHICS_MODE, (RGfx(ba, GCT_ID_GRAPHICS_MODE) & 0xfc) | 0); 288 1.1 mw /* extended chain4 enable */ 289 1.1 mw WSeq (ba, SEQ_ID_EXT_VIDEO_ADDR , RSeq(ba, SEQ_ID_EXT_VIDEO_ADDR) | 0x02); 290 1.1 mw /* read/write to primary on A0, secondary on B0 */ 291 1.1 mw WSeq (ba, SEQ_ID_EXTENDED_MEM_ENA, (RSeq(ba, SEQ_ID_EXTENDED_MEM_ENA) & 0x1f) | 0x40 ); 292 1.1 mw 293 1.1 mw /* fill the free lines with spaces */ 294 1.1 mw 295 1.1 mw { /* feed latches with value */ 296 1.1 mw unsigned short * f = (unsigned short *) fb; 297 1.1 mw 298 1.1 mw f += top * md->TX * 2; 299 1.1 mw *f = 0x2010; 300 1.1 mw { 301 1.1 mw volatile unsigned short dummy = *((volatile unsigned short *)f); 302 1.1 mw } 303 1.1 mw } 304 1.1 mw 305 1.1 mw /* clear extended chain4 mode */ 306 1.1 mw WSeq (ba, SEQ_ID_EXT_VIDEO_ADDR, RSeq(ba, SEQ_ID_EXT_VIDEO_ADDR) & ~0x02); 307 1.1 mw /* set write mode 1, "[...] data in the read latches is written 308 1.1 mw to memory during CPU memory write cycles. [...]" */ 309 1.1 mw WGfx (ba, GCT_ID_GRAPHICS_MODE, (RGfx(ba, GCT_ID_GRAPHICS_MODE) & 0xfc) | 1); 310 1.1 mw 311 1.1 mw { 312 1.1 mw unsigned long * p = (unsigned long *) fb; 313 1.1 mw short x = (lines * (md->TX/16)) - 1; 314 1.1 mw const unsigned long dummyval = 0; 315 1.1 mw 316 1.1 mw p += top * (md->TX/4); 317 1.1 mw 318 1.1 mw do { 319 1.1 mw *p++ = dummyval; 320 1.1 mw *p++ = dummyval; 321 1.1 mw *p++ = dummyval; 322 1.1 mw *p++ = dummyval; 323 1.1 mw } while (x--); 324 1.1 mw } 325 1.1 mw 326 1.1 mw /* write mode 0 */ 327 1.1 mw WGfx (ba, GCT_ID_GRAPHICS_MODE, (RGfx(ba, GCT_ID_GRAPHICS_MODE) & 0xfc) | 0); 328 1.1 mw /* extended chain4 enable */ 329 1.1 mw WSeq (ba, SEQ_ID_EXT_VIDEO_ADDR , RSeq(ba, SEQ_ID_EXT_VIDEO_ADDR) | 0x02); 330 1.1 mw 331 1.3 mw #ifdef BANKEDDEVPAGER 332 1.3 mw /* restore former bank */ 333 1.3 mw WSeq (ba, SEQ_ID_PRIM_HOST_OFF_LO, (unsigned char) bank); 334 1.3 mw bank >>= 8; 335 1.3 mw WSeq (ba, SEQ_ID_PRIM_HOST_OFF_HI, (unsigned char) bank); 336 1.3 mw #endif 337 1.1 mw }; 338 1.1 mw 339 1.1 mw void retina_deinit(struct ite_softc *ip) 340 1.1 mw { 341 1.1 mw ip->flags &= ~ITE_INITED; 342 1.1 mw } 343 1.1 mw 344 1.1 mw 345 1.1 mw void retina_putc(struct ite_softc *ip, int c, int dy, int dx, int mode) 346 1.1 mw { 347 1.1 mw volatile u_char * ba = ip->grf->g_regkva; 348 1.1 mw volatile u_char * fb = ip->grf->g_fbkva; 349 1.1 mw register u_char attr; 350 1.1 mw 351 1.1 mw attr = (mode & ATTR_INV) ? 0x21 : 0x10; 352 1.1 mw if (mode & ATTR_UL) attr = 0x01; /* ???????? */ 353 1.1 mw if (mode & ATTR_BOLD) attr |= 0x08; 354 1.1 mw if (mode & ATTR_BLINK) attr |= 0x80; 355 1.1 mw 356 1.1 mw fb += 4 * (dy * ip->cols + dx); 357 1.1 mw *fb++ = c; *fb = attr; 358 1.1 mw } 359 1.1 mw 360 1.1 mw void retina_clear(struct ite_softc *ip, int sy, int sx, int h, int w) 361 1.1 mw { 362 1.1 mw volatile u_char * ba = ip->grf->g_regkva; 363 1.1 mw u_short * fb = (u_short *) ip->grf->g_fbkva; 364 1.1 mw short x; 365 1.1 mw const u_short fillval = 0x2010; 366 1.1 mw /* could probably be optimized just like the scrolling functions !! */ 367 1.1 mw fb += 2 * (sy * ip->cols + sx); 368 1.1 mw while (h--) 369 1.1 mw { 370 1.1 mw for (x = 2 * (w - 1); x >= 0; x -= 2) 371 1.1 mw fb[x] = fillval; 372 1.1 mw fb += 2 * ip->cols; 373 1.1 mw } 374 1.1 mw } 375 1.1 mw 376 1.1 mw void retina_scroll(struct ite_softc *ip, int sy, int sx, int count, int dir) 377 1.1 mw { 378 1.1 mw volatile u_char * ba = ip->grf->g_regkva; 379 1.4 chopps u_long * fb = (u_long *) ip->grf->g_fbkva; 380 1.1 mw register int height, dy, i; 381 1.1 mw 382 1.1 mw retina_cursor(ip, ERASE_CURSOR); 383 1.1 mw 384 1.1 mw if (dir == SCROLL_UP) 385 1.1 mw { 386 1.1 mw screen_up (ip, sy - count, ip->bottom_margin, count); 387 1.1 mw /* bcopy (fb + sy * ip->cols, fb + (sy - count) * ip->cols, 4 * (ip->bottom_margin - sy + 1) * ip->cols); */ 388 1.1 mw /* retina_clear (ip, ip->bottom_margin + 1 - count, 0, count, ip->cols); */ 389 1.1 mw } 390 1.1 mw else if (dir == SCROLL_DOWN) 391 1.1 mw { 392 1.1 mw screen_down (ip, sy, ip->bottom_margin, count); 393 1.1 mw /* bcopy (fb + sy * ip->cols, fb + (sy + count) * ip->cols, 4 * (ip->bottom_margin - sy - count + 1) * ip->cols); */ 394 1.1 mw /* retina_clear (ip, sy, 0, count, ip->cols); */ 395 1.1 mw } 396 1.1 mw else if (dir == SCROLL_RIGHT) 397 1.1 mw { 398 1.1 mw bcopy (fb + sx + sy * ip->cols, fb + sx + sy * ip->cols + count, 4 * (ip->cols - (sx + count))); 399 1.1 mw retina_clear (ip, sy, sx, 1, count); 400 1.1 mw } 401 1.1 mw else 402 1.1 mw { 403 1.1 mw bcopy (fb + sx + sy * ip->cols, fb + sx - count + sy * ip->cols, 4 * (ip->cols - sx)); 404 1.1 mw retina_clear (ip, sy, ip->cols - count, 1, count); 405 1.1 mw } 406 1.1 mw } 407 1.1 mw 408 1.1 mw #endif 409 1.1 mw 410 1.1 mw 411 1.1 mw 412
Indexes created Fri Sep 26 08:10:20 GMT 2025