ite_rt.c revision 1.8
1 1.5 chopps /* 2 1.8 chopps * $Id: ite_rt.c,v 1.8 1994/04/05 18:19:27 chopps Exp $ 3 1.5 chopps */ 4 1.5 chopps 5 1.1 mw #include "ite.h" 6 1.1 mw #if NITE > 0 7 1.1 mw 8 1.6 chopps #include <sys/param.h> 9 1.6 chopps #include <sys/conf.h> 10 1.6 chopps #include <sys/proc.h> 11 1.6 chopps #include <sys/ioctl.h> 12 1.6 chopps #include <sys/tty.h> 13 1.6 chopps #include <sys/systm.h> 14 1.7 chopps #include <dev/cons.h> 15 1.1 mw 16 1.6 chopps #include <amiga/dev/itevar.h> 17 1.1 mw 18 1.6 chopps #include <machine/cpu.h> 19 1.1 mw 20 1.1 mw /* XXX */ 21 1.6 chopps #include <amiga/dev/grfioctl.h> 22 1.6 chopps #include <amiga/dev/grfvar.h> 23 1.6 chopps #include <amiga/dev/grf_rtreg.h> 24 1.7 chopps 25 1.8 chopps int retina_console = 1; 26 1.7 chopps 27 1.7 chopps /* 28 1.7 chopps * retina_cnprobe is called when the console is being initialized 29 1.7 chopps * i.e. very early. grfconfig() has been called, so this implies 30 1.7 chopps * that rt_init() was called. If we are functioning retina_inited 31 1.7 chopps * will be true. 32 1.7 chopps */ 33 1.7 chopps int 34 1.7 chopps retina_cnprobe(min) 35 1.7 chopps int min; 36 1.7 chopps { 37 1.7 chopps extern int retina_inited; /* in grf_rt.c */ 38 1.8 chopps if (retina_inited) { 39 1.8 chopps if (retina_console) 40 1.8 chopps return(CN_INTERNAL); 41 1.8 chopps else 42 1.8 chopps return(CN_NORMAL); 43 1.8 chopps } 44 1.8 chopps return(CN_DEAD); 45 1.7 chopps } 46 1.1 mw 47 1.1 mw void retina_init(struct ite_softc *ip) 48 1.1 mw { 49 1.1 mw struct MonDef *md; 50 1.1 mw 51 1.1 mw if (ip->grf == 0) 52 1.1 mw ip->grf = &grf_softc[ip - ite_softc]; 53 1.1 mw 54 1.2 mw ip->priv = ip->grf->g_data; 55 1.1 mw md = (struct MonDef *) ip->priv; 56 1.1 mw 57 1.1 mw ip->cols = md->TX; 58 1.1 mw ip->rows = md->TY; 59 1.1 mw } 60 1.1 mw 61 1.1 mw 62 1.1 mw void retina_cursor(struct ite_softc *ip, int flag) 63 1.1 mw { 64 1.1 mw volatile u_char *ba = ip->grf->g_regkva; 65 1.1 mw 66 1.1 mw if (flag == ERASE_CURSOR) 67 1.1 mw { 68 1.1 mw /* disable cursor */ 69 1.1 mw WCrt (ba, CRT_ID_CURSOR_START, RCrt (ba, CRT_ID_CURSOR_START) | 0x20); 70 1.1 mw } 71 1.1 mw else 72 1.1 mw { 73 1.1 mw int pos = ip->curx + ip->cury * ip->cols; 74 1.1 mw 75 1.1 mw /* make sure to enable cursor */ 76 1.1 mw WCrt (ba, CRT_ID_CURSOR_START, RCrt (ba, CRT_ID_CURSOR_START) & ~0x20); 77 1.1 mw 78 1.1 mw /* and position it */ 79 1.1 mw WCrt (ba, CRT_ID_CURSOR_LOC_HIGH, (u_char) (pos >> 8)); 80 1.1 mw WCrt (ba, CRT_ID_CURSOR_LOC_LOW, (u_char) pos); 81 1.1 mw 82 1.1 mw ip->cursorx = ip->curx; 83 1.1 mw ip->cursory = ip->cury; 84 1.1 mw } 85 1.1 mw } 86 1.1 mw 87 1.1 mw 88 1.1 mw 89 1.1 mw static void screen_up (struct ite_softc *ip, int top, int bottom, int lines) 90 1.1 mw { 91 1.1 mw volatile u_char * ba = ip->grf->g_regkva; 92 1.1 mw volatile u_char * fb = ip->grf->g_fbkva; 93 1.1 mw const struct MonDef * md = (struct MonDef *) ip->priv; 94 1.3 mw #ifdef BANKEDDEVPAGER 95 1.3 mw int bank; 96 1.3 mw #endif 97 1.1 mw 98 1.1 mw /* do some bounds-checking here.. */ 99 1.1 mw if (top >= bottom) 100 1.1 mw return; 101 1.1 mw 102 1.1 mw if (top + lines >= bottom) 103 1.1 mw { 104 1.1 mw retina_clear (ip, top, 0, bottom - top, ip->cols); 105 1.1 mw return; 106 1.1 mw } 107 1.1 mw 108 1.1 mw 109 1.3 mw #ifdef BANKEDDEVPAGER 110 1.3 mw /* make sure to save/restore active bank (and if it's only 111 1.3 mw for tests of the feature in text-mode..) */ 112 1.3 mw bank = (RSeq (ba, SEQ_ID_PRIM_HOST_OFF_LO) 113 1.3 mw | (RSeq (ba, SEQ_ID_PRIM_HOST_OFF_HI) << 8)); 114 1.3 mw #endif 115 1.3 mw 116 1.1 mw /* the trick here is to use a feature of the NCR chip. It can 117 1.1 mw optimize data access in various read/write modes. One of 118 1.1 mw the modes is able to read/write from/to different zones. 119 1.1 mw 120 1.1 mw Thus, by setting the read-offset to lineN, and the write-offset 121 1.1 mw to line0, we just cause read/write cycles for all characters 122 1.1 mw up to the last line, and have the chip transfer the data. The 123 1.1 mw `addqb' are the cheapest way to cause read/write cycles (DONT 124 1.1 mw use `tas' on the Amiga!), their results are completely ignored 125 1.1 mw by the NCR chip, it just replicates what it just read. */ 126 1.1 mw 127 1.1 mw /* write to primary, read from secondary */ 128 1.1 mw WSeq (ba, SEQ_ID_EXTENDED_MEM_ENA, (RSeq(ba, SEQ_ID_EXTENDED_MEM_ENA) & 0x1f) | 0 ); 129 1.1 mw /* clear extended chain4 mode */ 130 1.1 mw WSeq (ba, SEQ_ID_EXT_VIDEO_ADDR, RSeq(ba, SEQ_ID_EXT_VIDEO_ADDR) & ~0x02); 131 1.1 mw 132 1.1 mw /* set write mode 1, "[...] data in the read latches is written 133 1.1 mw to memory during CPU memory write cycles. [...]" */ 134 1.1 mw WGfx (ba, GCT_ID_GRAPHICS_MODE, (RGfx(ba, GCT_ID_GRAPHICS_MODE) & 0xfc) | 1); 135 1.1 mw 136 1.1 mw { 137 1.1 mw /* write to line TOP */ 138 1.1 mw long toploc = top * (md->TX / 16); 139 1.1 mw WSeq (ba, SEQ_ID_PRIM_HOST_OFF_LO, ((unsigned char)toploc)); 140 1.1 mw WSeq (ba, SEQ_ID_PRIM_HOST_OFF_HI, ((unsigned char)(toploc >> 8))); 141 1.1 mw } 142 1.1 mw { 143 1.1 mw /* read from line TOP + LINES */ 144 1.1 mw long fromloc = (top+lines) * (md->TX / 16); 145 1.1 mw WSeq (ba, SEQ_ID_SEC_HOST_OFF_LO, ((unsigned char)fromloc)) ; 146 1.1 mw WSeq (ba, SEQ_ID_SEC_HOST_OFF_HI, ((unsigned char)(fromloc >> 8))) ; 147 1.1 mw } 148 1.1 mw { 149 1.1 mw unsigned char * p = (unsigned char *) fb; 150 1.1 mw /* transfer all characters but LINES lines, unroll by 16 */ 151 1.1 mw short x = (1 + bottom - (top + lines)) * (md->TX / 16) - 1; 152 1.1 mw do { 153 1.1 mw asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p)); 154 1.1 mw asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p)); 155 1.1 mw asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p)); 156 1.1 mw asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p)); 157 1.1 mw asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p)); 158 1.1 mw asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p)); 159 1.1 mw asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p)); 160 1.1 mw asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p)); 161 1.1 mw asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p)); 162 1.1 mw asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p)); 163 1.1 mw asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p)); 164 1.1 mw asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p)); 165 1.1 mw asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p)); 166 1.1 mw asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p)); 167 1.1 mw asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p)); 168 1.1 mw asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p)); 169 1.1 mw } while (x--); 170 1.1 mw } 171 1.1 mw 172 1.1 mw /* reset to default values */ 173 1.1 mw WSeq (ba, SEQ_ID_SEC_HOST_OFF_HI, 0); 174 1.1 mw WSeq (ba, SEQ_ID_SEC_HOST_OFF_LO, 0); 175 1.1 mw WSeq (ba, SEQ_ID_PRIM_HOST_OFF_HI, 0); 176 1.1 mw WSeq (ba, SEQ_ID_PRIM_HOST_OFF_LO, 0); 177 1.1 mw /* write mode 0 */ 178 1.1 mw WGfx (ba, GCT_ID_GRAPHICS_MODE, (RGfx(ba, GCT_ID_GRAPHICS_MODE) & 0xfc) | 0); 179 1.1 mw /* extended chain4 enable */ 180 1.1 mw WSeq (ba, SEQ_ID_EXT_VIDEO_ADDR , RSeq(ba, SEQ_ID_EXT_VIDEO_ADDR) | 0x02); 181 1.1 mw /* read/write to primary on A0, secondary on B0 */ 182 1.1 mw WSeq (ba, SEQ_ID_EXTENDED_MEM_ENA, (RSeq(ba, SEQ_ID_EXTENDED_MEM_ENA) & 0x1f) | 0x40 ); 183 1.1 mw 184 1.1 mw 185 1.1 mw /* fill the free lines with spaces */ 186 1.1 mw 187 1.1 mw { /* feed latches with value */ 188 1.1 mw unsigned short * f = (unsigned short *) fb; 189 1.1 mw 190 1.1 mw f += (1 + bottom - lines) * md->TX * 2; 191 1.1 mw *f = 0x2010; 192 1.1 mw { 193 1.1 mw volatile unsigned short dummy = *((volatile unsigned short *)f); 194 1.1 mw } 195 1.1 mw } 196 1.1 mw 197 1.1 mw /* clear extended chain4 mode */ 198 1.1 mw WSeq (ba, SEQ_ID_EXT_VIDEO_ADDR, RSeq(ba, SEQ_ID_EXT_VIDEO_ADDR) & ~0x02); 199 1.1 mw /* set write mode 1, "[...] data in the read latches is written 200 1.1 mw to memory during CPU memory write cycles. [...]" */ 201 1.1 mw WGfx (ba, GCT_ID_GRAPHICS_MODE, (RGfx(ba, GCT_ID_GRAPHICS_MODE) & 0xfc) | 1); 202 1.1 mw 203 1.1 mw { 204 1.1 mw unsigned long * p = (unsigned long *) fb; 205 1.1 mw short x = (lines * (md->TX/16)) - 1; 206 1.1 mw const unsigned long dummyval = 0; 207 1.1 mw 208 1.1 mw p += (1 + bottom - lines) * (md->TX/4); 209 1.1 mw 210 1.1 mw do { 211 1.1 mw *p++ = dummyval; 212 1.1 mw *p++ = dummyval; 213 1.1 mw *p++ = dummyval; 214 1.1 mw *p++ = dummyval; 215 1.1 mw } while (x--); 216 1.1 mw } 217 1.1 mw 218 1.1 mw /* write mode 0 */ 219 1.1 mw WGfx (ba, GCT_ID_GRAPHICS_MODE, (RGfx(ba, GCT_ID_GRAPHICS_MODE) & 0xfc) | 0); 220 1.1 mw /* extended chain4 enable */ 221 1.1 mw WSeq (ba, SEQ_ID_EXT_VIDEO_ADDR , RSeq(ba, SEQ_ID_EXT_VIDEO_ADDR) | 0x02); 222 1.3 mw 223 1.3 mw #ifdef BANKEDDEVPAGER 224 1.3 mw /* restore former bank */ 225 1.3 mw WSeq (ba, SEQ_ID_PRIM_HOST_OFF_LO, (unsigned char) bank); 226 1.3 mw bank >>= 8; 227 1.3 mw WSeq (ba, SEQ_ID_PRIM_HOST_OFF_HI, (unsigned char) bank); 228 1.3 mw #endif 229 1.1 mw }; 230 1.1 mw 231 1.1 mw static void screen_down (struct ite_softc *ip, int top, int bottom, int lines) 232 1.1 mw { 233 1.1 mw volatile u_char * ba = ip->grf->g_regkva; 234 1.1 mw volatile u_char * fb = ip->grf->g_fbkva; 235 1.1 mw const struct MonDef * md = (struct MonDef *) ip->priv; 236 1.3 mw #ifdef BANKEDDEVPAGER 237 1.3 mw int bank; 238 1.3 mw #endif 239 1.1 mw 240 1.1 mw /* do some bounds-checking here.. */ 241 1.1 mw if (top >= bottom) 242 1.1 mw return; 243 1.1 mw 244 1.1 mw if (top + lines >= bottom) 245 1.1 mw { 246 1.1 mw retina_clear (ip, top, 0, bottom - top, ip->cols); 247 1.1 mw return; 248 1.1 mw } 249 1.1 mw 250 1.3 mw #ifdef BANKEDDEVPAGER 251 1.3 mw /* make sure to save/restore active bank (and if it's only 252 1.3 mw for tests of the feature in text-mode..) */ 253 1.3 mw bank = (RSeq (ba, SEQ_ID_PRIM_HOST_OFF_LO) 254 1.3 mw | (RSeq (ba, SEQ_ID_PRIM_HOST_OFF_HI) << 8)); 255 1.3 mw #endif 256 1.1 mw /* see screen_up() for explanation of chip-tricks */ 257 1.1 mw 258 1.1 mw /* write to primary, read from secondary */ 259 1.1 mw WSeq (ba, SEQ_ID_EXTENDED_MEM_ENA, (RSeq(ba, SEQ_ID_EXTENDED_MEM_ENA) & 0x1f) | 0 ); 260 1.1 mw /* clear extended chain4 mode */ 261 1.1 mw WSeq (ba, SEQ_ID_EXT_VIDEO_ADDR, RSeq(ba, SEQ_ID_EXT_VIDEO_ADDR) & ~0x02); 262 1.1 mw 263 1.1 mw /* set write mode 1, "[...] data in the read latches is written 264 1.1 mw to memory during CPU memory write cycles. [...]" */ 265 1.1 mw WGfx (ba, GCT_ID_GRAPHICS_MODE, (RGfx(ba, GCT_ID_GRAPHICS_MODE) & 0xfc) | 1); 266 1.1 mw 267 1.1 mw { 268 1.1 mw /* write to line TOP + LINES */ 269 1.1 mw long toloc = (top + lines) * (md->TX / 16); 270 1.1 mw WSeq (ba, SEQ_ID_PRIM_HOST_OFF_LO, ((unsigned char)toloc)); 271 1.1 mw WSeq (ba, SEQ_ID_PRIM_HOST_OFF_HI, ((unsigned char)(toloc >> 8))); 272 1.1 mw } 273 1.1 mw { 274 1.1 mw /* read from line TOP */ 275 1.1 mw long fromloc = top * (md->TX / 16); 276 1.1 mw WSeq (ba, SEQ_ID_SEC_HOST_OFF_LO, ((unsigned char)fromloc)); 277 1.1 mw WSeq (ba, SEQ_ID_SEC_HOST_OFF_HI, ((unsigned char)(fromloc >> 8))) ; 278 1.1 mw } 279 1.1 mw 280 1.1 mw { 281 1.1 mw unsigned char * p = (unsigned char *) fb; 282 1.1 mw short x = (1 + bottom - (top + lines)) * (md->TX / 16) - 1; 283 1.1 mw p += (1 + bottom - (top + lines)) * md->TX; 284 1.1 mw do { 285 1.1 mw asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p)); 286 1.1 mw asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p)); 287 1.1 mw asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p)); 288 1.1 mw asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p)); 289 1.1 mw asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p)); 290 1.1 mw asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p)); 291 1.1 mw asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p)); 292 1.1 mw asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p)); 293 1.1 mw asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p)); 294 1.1 mw asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p)); 295 1.1 mw asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p)); 296 1.1 mw asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p)); 297 1.1 mw asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p)); 298 1.1 mw asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p)); 299 1.1 mw asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p)); 300 1.1 mw asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p)); 301 1.1 mw } while (x--); 302 1.1 mw } 303 1.1 mw 304 1.1 mw WSeq (ba, SEQ_ID_PRIM_HOST_OFF_HI, 0); 305 1.1 mw WSeq (ba, SEQ_ID_PRIM_HOST_OFF_LO, 0); 306 1.1 mw WSeq (ba, SEQ_ID_SEC_HOST_OFF_HI, 0); 307 1.1 mw WSeq (ba, SEQ_ID_SEC_HOST_OFF_LO, 0); 308 1.1 mw 309 1.1 mw /* write mode 0 */ 310 1.1 mw WGfx (ba, GCT_ID_GRAPHICS_MODE, (RGfx(ba, GCT_ID_GRAPHICS_MODE) & 0xfc) | 0); 311 1.1 mw /* extended chain4 enable */ 312 1.1 mw WSeq (ba, SEQ_ID_EXT_VIDEO_ADDR , RSeq(ba, SEQ_ID_EXT_VIDEO_ADDR) | 0x02); 313 1.1 mw /* read/write to primary on A0, secondary on B0 */ 314 1.1 mw WSeq (ba, SEQ_ID_EXTENDED_MEM_ENA, (RSeq(ba, SEQ_ID_EXTENDED_MEM_ENA) & 0x1f) | 0x40 ); 315 1.1 mw 316 1.1 mw /* fill the free lines with spaces */ 317 1.1 mw 318 1.1 mw { /* feed latches with value */ 319 1.1 mw unsigned short * f = (unsigned short *) fb; 320 1.1 mw 321 1.1 mw f += top * md->TX * 2; 322 1.1 mw *f = 0x2010; 323 1.1 mw { 324 1.1 mw volatile unsigned short dummy = *((volatile unsigned short *)f); 325 1.1 mw } 326 1.1 mw } 327 1.1 mw 328 1.1 mw /* clear extended chain4 mode */ 329 1.1 mw WSeq (ba, SEQ_ID_EXT_VIDEO_ADDR, RSeq(ba, SEQ_ID_EXT_VIDEO_ADDR) & ~0x02); 330 1.1 mw /* set write mode 1, "[...] data in the read latches is written 331 1.1 mw to memory during CPU memory write cycles. [...]" */ 332 1.1 mw WGfx (ba, GCT_ID_GRAPHICS_MODE, (RGfx(ba, GCT_ID_GRAPHICS_MODE) & 0xfc) | 1); 333 1.1 mw 334 1.1 mw { 335 1.1 mw unsigned long * p = (unsigned long *) fb; 336 1.1 mw short x = (lines * (md->TX/16)) - 1; 337 1.1 mw const unsigned long dummyval = 0; 338 1.1 mw 339 1.1 mw p += top * (md->TX/4); 340 1.1 mw 341 1.1 mw do { 342 1.1 mw *p++ = dummyval; 343 1.1 mw *p++ = dummyval; 344 1.1 mw *p++ = dummyval; 345 1.1 mw *p++ = dummyval; 346 1.1 mw } while (x--); 347 1.1 mw } 348 1.1 mw 349 1.1 mw /* write mode 0 */ 350 1.1 mw WGfx (ba, GCT_ID_GRAPHICS_MODE, (RGfx(ba, GCT_ID_GRAPHICS_MODE) & 0xfc) | 0); 351 1.1 mw /* extended chain4 enable */ 352 1.1 mw WSeq (ba, SEQ_ID_EXT_VIDEO_ADDR , RSeq(ba, SEQ_ID_EXT_VIDEO_ADDR) | 0x02); 353 1.1 mw 354 1.3 mw #ifdef BANKEDDEVPAGER 355 1.3 mw /* restore former bank */ 356 1.3 mw WSeq (ba, SEQ_ID_PRIM_HOST_OFF_LO, (unsigned char) bank); 357 1.3 mw bank >>= 8; 358 1.3 mw WSeq (ba, SEQ_ID_PRIM_HOST_OFF_HI, (unsigned char) bank); 359 1.3 mw #endif 360 1.1 mw }; 361 1.1 mw 362 1.1 mw void retina_deinit(struct ite_softc *ip) 363 1.1 mw { 364 1.1 mw ip->flags &= ~ITE_INITED; 365 1.1 mw } 366 1.1 mw 367 1.1 mw 368 1.1 mw void retina_putc(struct ite_softc *ip, int c, int dy, int dx, int mode) 369 1.1 mw { 370 1.1 mw volatile u_char * ba = ip->grf->g_regkva; 371 1.1 mw volatile u_char * fb = ip->grf->g_fbkva; 372 1.1 mw register u_char attr; 373 1.1 mw 374 1.1 mw attr = (mode & ATTR_INV) ? 0x21 : 0x10; 375 1.1 mw if (mode & ATTR_UL) attr = 0x01; /* ???????? */ 376 1.1 mw if (mode & ATTR_BOLD) attr |= 0x08; 377 1.1 mw if (mode & ATTR_BLINK) attr |= 0x80; 378 1.1 mw 379 1.1 mw fb += 4 * (dy * ip->cols + dx); 380 1.1 mw *fb++ = c; *fb = attr; 381 1.1 mw } 382 1.1 mw 383 1.1 mw void retina_clear(struct ite_softc *ip, int sy, int sx, int h, int w) 384 1.1 mw { 385 1.1 mw volatile u_char * ba = ip->grf->g_regkva; 386 1.1 mw u_short * fb = (u_short *) ip->grf->g_fbkva; 387 1.1 mw short x; 388 1.1 mw const u_short fillval = 0x2010; 389 1.1 mw /* could probably be optimized just like the scrolling functions !! */ 390 1.1 mw fb += 2 * (sy * ip->cols + sx); 391 1.1 mw while (h--) 392 1.1 mw { 393 1.1 mw for (x = 2 * (w - 1); x >= 0; x -= 2) 394 1.1 mw fb[x] = fillval; 395 1.1 mw fb += 2 * ip->cols; 396 1.1 mw } 397 1.1 mw } 398 1.1 mw 399 1.1 mw void retina_scroll(struct ite_softc *ip, int sy, int sx, int count, int dir) 400 1.1 mw { 401 1.1 mw volatile u_char * ba = ip->grf->g_regkva; 402 1.4 chopps u_long * fb = (u_long *) ip->grf->g_fbkva; 403 1.1 mw register int height, dy, i; 404 1.1 mw 405 1.1 mw retina_cursor(ip, ERASE_CURSOR); 406 1.1 mw 407 1.1 mw if (dir == SCROLL_UP) 408 1.1 mw { 409 1.1 mw screen_up (ip, sy - count, ip->bottom_margin, count); 410 1.1 mw /* bcopy (fb + sy * ip->cols, fb + (sy - count) * ip->cols, 4 * (ip->bottom_margin - sy + 1) * ip->cols); */ 411 1.1 mw /* retina_clear (ip, ip->bottom_margin + 1 - count, 0, count, ip->cols); */ 412 1.1 mw } 413 1.1 mw else if (dir == SCROLL_DOWN) 414 1.1 mw { 415 1.1 mw screen_down (ip, sy, ip->bottom_margin, count); 416 1.1 mw /* bcopy (fb + sy * ip->cols, fb + (sy + count) * ip->cols, 4 * (ip->bottom_margin - sy - count + 1) * ip->cols); */ 417 1.1 mw /* retina_clear (ip, sy, 0, count, ip->cols); */ 418 1.1 mw } 419 1.1 mw else if (dir == SCROLL_RIGHT) 420 1.1 mw { 421 1.1 mw bcopy (fb + sx + sy * ip->cols, fb + sx + sy * ip->cols + count, 4 * (ip->cols - (sx + count))); 422 1.1 mw retina_clear (ip, sy, sx, 1, count); 423 1.1 mw } 424 1.1 mw else 425 1.1 mw { 426 1.1 mw bcopy (fb + sx + sy * ip->cols, fb + sx - count + sy * ip->cols, 4 * (ip->cols - sx)); 427 1.1 mw retina_clear (ip, sy, ip->cols - count, 1, count); 428 1.1 mw } 429 1.1 mw } 430 1.1 mw 431 1.1 mw #endif 432 1.1 mw 433 1.1 mw 434 1.1 mw 435
Indexes created Fri Sep 26 08:10:20 GMT 2025