ivsc.c revision 1.28.8.2 1 1.28.8.2 nathanw /* $NetBSD: ivsc.c,v 1.28.8.2 2002/02/28 04:06:50 nathanw Exp $ */
2 1.28.8.2 nathanw
3 1.28.8.2 nathanw /*
4 1.28.8.2 nathanw * Copyright (c) 1994 Michael L. Hitch
5 1.28.8.2 nathanw * Copyright (c) 1982, 1990 The Regents of the University of California.
6 1.28.8.2 nathanw * All rights reserved.
7 1.28.8.2 nathanw *
8 1.28.8.2 nathanw * Redistribution and use in source and binary forms, with or without
9 1.28.8.2 nathanw * modification, are permitted provided that the following conditions
10 1.28.8.2 nathanw * are met:
11 1.28.8.2 nathanw * 1. Redistributions of source code must retain the above copyright
12 1.28.8.2 nathanw * notice, this list of conditions and the following disclaimer.
13 1.28.8.2 nathanw * 2. Redistributions in binary form must reproduce the above copyright
14 1.28.8.2 nathanw * notice, this list of conditions and the following disclaimer in the
15 1.28.8.2 nathanw * documentation and/or other materials provided with the distribution.
16 1.28.8.2 nathanw * 3. All advertising materials mentioning features or use of this software
17 1.28.8.2 nathanw * must display the following acknowledgement:
18 1.28.8.2 nathanw * This product includes software developed by the University of
19 1.28.8.2 nathanw * California, Berkeley and its contributors.
20 1.28.8.2 nathanw * 4. Neither the name of the University nor the names of its contributors
21 1.28.8.2 nathanw * may be used to endorse or promote products derived from this software
22 1.28.8.2 nathanw * without specific prior written permission.
23 1.28.8.2 nathanw *
24 1.28.8.2 nathanw * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 1.28.8.2 nathanw * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 1.28.8.2 nathanw * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 1.28.8.2 nathanw * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 1.28.8.2 nathanw * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 1.28.8.2 nathanw * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 1.28.8.2 nathanw * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 1.28.8.2 nathanw * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 1.28.8.2 nathanw * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 1.28.8.2 nathanw * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 1.28.8.2 nathanw * SUCH DAMAGE.
35 1.28.8.2 nathanw *
36 1.28.8.2 nathanw * @(#)ivsdma.c
37 1.28.8.2 nathanw */
38 1.28.8.2 nathanw
39 1.28.8.2 nathanw #include <sys/cdefs.h>
40 1.28.8.2 nathanw __KERNEL_RCSID(0, "$NetBSD: ivsc.c,v 1.28.8.2 2002/02/28 04:06:50 nathanw Exp $");
41 1.28.8.2 nathanw
42 1.28.8.2 nathanw #include <sys/param.h>
43 1.28.8.2 nathanw #include <sys/systm.h>
44 1.28.8.2 nathanw #include <sys/kernel.h>
45 1.28.8.2 nathanw #include <sys/device.h>
46 1.28.8.2 nathanw #include <dev/scsipi/scsi_all.h>
47 1.28.8.2 nathanw #include <dev/scsipi/scsipi_all.h>
48 1.28.8.2 nathanw #include <dev/scsipi/scsiconf.h>
49 1.28.8.2 nathanw #include <amiga/amiga/custom.h>
50 1.28.8.2 nathanw #include <amiga/amiga/device.h>
51 1.28.8.2 nathanw #include <amiga/amiga/isr.h>
52 1.28.8.2 nathanw #include <amiga/dev/scireg.h>
53 1.28.8.2 nathanw #include <amiga/dev/scivar.h>
54 1.28.8.2 nathanw #include <amiga/dev/zbusvar.h>
55 1.28.8.2 nathanw
56 1.28.8.2 nathanw void ivscattach(struct device *, struct device *, void *);
57 1.28.8.2 nathanw int ivscmatch(struct device *, struct cfdata *, void *);
58 1.28.8.2 nathanw
59 1.28.8.2 nathanw int ivsc_intr(void *);
60 1.28.8.2 nathanw int ivsc_dma_xfer_in(struct sci_softc *dev, int len,
61 1.28.8.2 nathanw register u_char *buf, int phase);
62 1.28.8.2 nathanw int ivsc_dma_xfer_out(struct sci_softc *dev, int len,
63 1.28.8.2 nathanw register u_char *buf, int phase);
64 1.28.8.2 nathanw
65 1.28.8.2 nathanw
66 1.28.8.2 nathanw #ifdef DEBUG
67 1.28.8.2 nathanw extern int sci_debug;
68 1.28.8.2 nathanw #define QPRINTF(a) if (sci_debug > 1) printf a
69 1.28.8.2 nathanw #else
70 1.28.8.2 nathanw #define QPRINTF(a)
71 1.28.8.2 nathanw #endif
72 1.28.8.2 nathanw
73 1.28.8.2 nathanw extern int sci_data_wait;
74 1.28.8.2 nathanw
75 1.28.8.2 nathanw int ivsdma_pseudo = 1; /* 0=off, 1=on */
76 1.28.8.2 nathanw
77 1.28.8.2 nathanw struct cfattach ivsc_ca = {
78 1.28.8.2 nathanw sizeof(struct sci_softc), ivscmatch, ivscattach
79 1.28.8.2 nathanw };
80 1.28.8.2 nathanw
81 1.28.8.2 nathanw /*
82 1.28.8.2 nathanw * if this is an IVS board
83 1.28.8.2 nathanw */
84 1.28.8.2 nathanw int
85 1.28.8.2 nathanw ivscmatch(struct device *pdp, struct cfdata *cfp, void *auxp)
86 1.28.8.2 nathanw {
87 1.28.8.2 nathanw struct zbus_args *zap;
88 1.28.8.2 nathanw
89 1.28.8.2 nathanw zap = auxp;
90 1.28.8.2 nathanw
91 1.28.8.2 nathanw /*
92 1.28.8.2 nathanw * Check manufacturer and product id.
93 1.28.8.2 nathanw */
94 1.28.8.2 nathanw if (zap->manid != 2112 || /* If manufacturer is IVS */
95 1.28.8.2 nathanw (zap->prodid != 48 && /* product = Trumpcard 500 */
96 1.28.8.2 nathanw zap->prodid != 52 && /* product = Trumpcard */
97 1.28.8.2 nathanw zap->prodid != 243)) /* product = Vector SCSI */
98 1.28.8.2 nathanw return(0); /* didn't match */
99 1.28.8.2 nathanw return(1);
100 1.28.8.2 nathanw }
101 1.28.8.2 nathanw
102 1.28.8.2 nathanw void
103 1.28.8.2 nathanw ivscattach(struct device *pdp, struct device *dp, void *auxp)
104 1.28.8.2 nathanw {
105 1.28.8.2 nathanw volatile u_char *rp;
106 1.28.8.2 nathanw struct sci_softc *sc = (struct sci_softc *)dp;
107 1.28.8.2 nathanw struct zbus_args *zap;
108 1.28.8.2 nathanw struct scsipi_adapter *adapt = &sc->sc_adapter;
109 1.28.8.2 nathanw struct scsipi_channel *chan = &sc->sc_channel;
110 1.28.8.2 nathanw
111 1.28.8.2 nathanw printf("\n");
112 1.28.8.2 nathanw
113 1.28.8.2 nathanw zap = auxp;
114 1.28.8.2 nathanw
115 1.28.8.2 nathanw rp = (u_char *)zap->va + 0x40;
116 1.28.8.2 nathanw sc->sci_data = rp;
117 1.28.8.2 nathanw sc->sci_odata = rp;
118 1.28.8.2 nathanw sc->sci_icmd = rp + 2;
119 1.28.8.2 nathanw sc->sci_mode = rp + 4;
120 1.28.8.2 nathanw sc->sci_tcmd = rp + 6;
121 1.28.8.2 nathanw sc->sci_bus_csr = rp + 8;
122 1.28.8.2 nathanw sc->sci_sel_enb = rp + 8;
123 1.28.8.2 nathanw sc->sci_csr = rp + 10;
124 1.28.8.2 nathanw sc->sci_dma_send = rp + 10;
125 1.28.8.2 nathanw sc->sci_idata = rp + 12;
126 1.28.8.2 nathanw sc->sci_trecv = rp + 12;
127 1.28.8.2 nathanw sc->sci_iack = rp + 14;
128 1.28.8.2 nathanw sc->sci_irecv = rp + 14;
129 1.28.8.2 nathanw
130 1.28.8.2 nathanw if (ivsdma_pseudo == 1) {
131 1.28.8.2 nathanw sc->dma_xfer_in = ivsc_dma_xfer_in;
132 1.28.8.2 nathanw sc->dma_xfer_out = ivsc_dma_xfer_out;
133 1.28.8.2 nathanw }
134 1.28.8.2 nathanw
135 1.28.8.2 nathanw sc->sc_isr.isr_intr = ivsc_intr;
136 1.28.8.2 nathanw sc->sc_isr.isr_arg = sc;
137 1.28.8.2 nathanw sc->sc_isr.isr_ipl = 2;
138 1.28.8.2 nathanw add_isr(&sc->sc_isr);
139 1.28.8.2 nathanw
140 1.28.8.2 nathanw scireset(sc);
141 1.28.8.2 nathanw
142 1.28.8.2 nathanw /*
143 1.28.8.2 nathanw * Fill in the scsipi_adapter.
144 1.28.8.2 nathanw */
145 1.28.8.2 nathanw memset(adapt, 0, sizeof(*adapt));
146 1.28.8.2 nathanw adapt->adapt_dev = &sc->sc_dev;
147 1.28.8.2 nathanw adapt->adapt_nchannels = 1;
148 1.28.8.2 nathanw adapt->adapt_openings = 7;
149 1.28.8.2 nathanw adapt->adapt_max_periph = 1;
150 1.28.8.2 nathanw adapt->adapt_request = sci_scsipi_request;
151 1.28.8.2 nathanw adapt->adapt_minphys = sci_minphys;
152 1.28.8.2 nathanw
153 1.28.8.2 nathanw /*
154 1.28.8.2 nathanw * Fill in the scsipi_channel.
155 1.28.8.2 nathanw */
156 1.28.8.2 nathanw memset(chan, 0, sizeof(*chan));
157 1.28.8.2 nathanw chan->chan_adapter = adapt;
158 1.28.8.2 nathanw chan->chan_bustype = &scsi_bustype;
159 1.28.8.2 nathanw chan->chan_channel = 0;
160 1.28.8.2 nathanw chan->chan_ntargets = 8;
161 1.28.8.2 nathanw chan->chan_nluns = 8;
162 1.28.8.2 nathanw chan->chan_id = 7;
163 1.28.8.2 nathanw
164 1.28.8.2 nathanw /*
165 1.28.8.2 nathanw * attach all scsi units on us
166 1.28.8.2 nathanw */
167 1.28.8.2 nathanw config_found(dp, chan, scsiprint);
168 1.28.8.2 nathanw }
169 1.28.8.2 nathanw
170 1.28.8.2 nathanw int
171 1.28.8.2 nathanw ivsc_dma_xfer_in(struct sci_softc *dev, int len, register u_char *buf,
172 1.28.8.2 nathanw int phase)
173 1.28.8.2 nathanw {
174 1.28.8.2 nathanw int wait = sci_data_wait;
175 1.28.8.2 nathanw volatile register u_char *sci_dma = dev->sci_idata + 0x20;
176 1.28.8.2 nathanw volatile register u_char *sci_csr = dev->sci_csr;
177 1.28.8.2 nathanw #ifdef DEBUG
178 1.28.8.2 nathanw u_char *obp = buf;
179 1.28.8.2 nathanw #endif
180 1.28.8.2 nathanw
181 1.28.8.2 nathanw QPRINTF(("ivsc_dma_in %d, csr=%02x\n", len, *dev->sci_bus_csr));
182 1.28.8.2 nathanw
183 1.28.8.2 nathanw *dev->sci_tcmd = phase;
184 1.28.8.2 nathanw *dev->sci_mode |= SCI_MODE_DMA;
185 1.28.8.2 nathanw *dev->sci_irecv = 0;
186 1.28.8.2 nathanw
187 1.28.8.2 nathanw while (len >= 128) {
188 1.28.8.2 nathanw wait = sci_data_wait;
189 1.28.8.2 nathanw while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
190 1.28.8.2 nathanw (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) {
191 1.28.8.2 nathanw if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
192 1.28.8.2 nathanw || !(*dev->sci_bus_csr & SCI_BUS_BSY)
193 1.28.8.2 nathanw || --wait < 0) {
194 1.28.8.2 nathanw #ifdef DEBUG
195 1.28.8.2 nathanw if (sci_debug)
196 1.28.8.2 nathanw printf("ivsc_dma_in2 fail: l%d i%x w%d\n",
197 1.28.8.2 nathanw len, *dev->sci_bus_csr, wait);
198 1.28.8.2 nathanw #endif
199 1.28.8.2 nathanw *dev->sci_mode &= ~SCI_MODE_DMA;
200 1.28.8.2 nathanw return 0;
201 1.28.8.2 nathanw }
202 1.28.8.2 nathanw }
203 1.28.8.2 nathanw
204 1.28.8.2 nathanw #define R1 (*buf++ = *sci_dma)
205 1.28.8.2 nathanw R1; R1; R1; R1; R1; R1; R1; R1;
206 1.28.8.2 nathanw R1; R1; R1; R1; R1; R1; R1; R1;
207 1.28.8.2 nathanw R1; R1; R1; R1; R1; R1; R1; R1;
208 1.28.8.2 nathanw R1; R1; R1; R1; R1; R1; R1; R1;
209 1.28.8.2 nathanw R1; R1; R1; R1; R1; R1; R1; R1;
210 1.28.8.2 nathanw R1; R1; R1; R1; R1; R1; R1; R1;
211 1.28.8.2 nathanw R1; R1; R1; R1; R1; R1; R1; R1;
212 1.28.8.2 nathanw R1; R1; R1; R1; R1; R1; R1; R1;
213 1.28.8.2 nathanw R1; R1; R1; R1; R1; R1; R1; R1;
214 1.28.8.2 nathanw R1; R1; R1; R1; R1; R1; R1; R1;
215 1.28.8.2 nathanw R1; R1; R1; R1; R1; R1; R1; R1;
216 1.28.8.2 nathanw R1; R1; R1; R1; R1; R1; R1; R1;
217 1.28.8.2 nathanw R1; R1; R1; R1; R1; R1; R1; R1;
218 1.28.8.2 nathanw R1; R1; R1; R1; R1; R1; R1; R1;
219 1.28.8.2 nathanw R1; R1; R1; R1; R1; R1; R1; R1;
220 1.28.8.2 nathanw R1; R1; R1; R1; R1; R1; R1; R1;
221 1.28.8.2 nathanw len -= 128;
222 1.28.8.2 nathanw }
223 1.28.8.2 nathanw
224 1.28.8.2 nathanw while (len > 0) {
225 1.28.8.2 nathanw wait = sci_data_wait;
226 1.28.8.2 nathanw while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
227 1.28.8.2 nathanw (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) {
228 1.28.8.2 nathanw if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
229 1.28.8.2 nathanw || !(*dev->sci_bus_csr & SCI_BUS_BSY)
230 1.28.8.2 nathanw || --wait < 0) {
231 1.28.8.2 nathanw #ifdef DEBUG
232 1.28.8.2 nathanw if (sci_debug)
233 1.28.8.2 nathanw printf("ivsc_dma_in1 fail: l%d i%x w%d\n",
234 1.28.8.2 nathanw len, *dev->sci_bus_csr, wait);
235 1.28.8.2 nathanw #endif
236 1.28.8.2 nathanw *dev->sci_mode &= ~SCI_MODE_DMA;
237 1.28.8.2 nathanw return 0;
238 1.28.8.2 nathanw }
239 1.28.8.2 nathanw }
240 1.28.8.2 nathanw
241 1.28.8.2 nathanw *buf++ = *sci_dma;
242 1.28.8.2 nathanw len--;
243 1.28.8.2 nathanw }
244 1.28.8.2 nathanw
245 1.28.8.2 nathanw QPRINTF(("ivsc_dma_in {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
246 1.28.8.2 nathanw len, obp[0], obp[1], obp[2], obp[3], obp[4], obp[5],
247 1.28.8.2 nathanw obp[6], obp[7], obp[8], obp[9]));
248 1.28.8.2 nathanw
249 1.28.8.2 nathanw *dev->sci_mode &= ~SCI_MODE_DMA;
250 1.28.8.2 nathanw return 0;
251 1.28.8.2 nathanw }
252 1.28.8.2 nathanw
253 1.28.8.2 nathanw int
254 1.28.8.2 nathanw ivsc_dma_xfer_out(struct sci_softc *dev, int len, register u_char *buf,
255 1.28.8.2 nathanw int phase)
256 1.28.8.2 nathanw {
257 1.28.8.2 nathanw int wait = sci_data_wait;
258 1.28.8.2 nathanw volatile register u_char *sci_dma = dev->sci_data + 0x20;
259 1.28.8.2 nathanw volatile register u_char *sci_csr = dev->sci_csr;
260 1.28.8.2 nathanw
261 1.28.8.2 nathanw QPRINTF(("ivsc_dma_out %d, csr=%02x\n", len, *dev->sci_bus_csr));
262 1.28.8.2 nathanw
263 1.28.8.2 nathanw QPRINTF(("ivsc_dma_out {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
264 1.28.8.2 nathanw len, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5],
265 1.28.8.2 nathanw buf[6], buf[7], buf[8], buf[9]));
266 1.28.8.2 nathanw
267 1.28.8.2 nathanw *dev->sci_tcmd = phase;
268 1.28.8.2 nathanw *dev->sci_mode |= SCI_MODE_DMA;
269 1.28.8.2 nathanw *dev->sci_icmd |= SCI_ICMD_DATA;
270 1.28.8.2 nathanw *dev->sci_dma_send = 0;
271 1.28.8.2 nathanw while (len > 0) {
272 1.28.8.2 nathanw wait = sci_data_wait;
273 1.28.8.2 nathanw while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
274 1.28.8.2 nathanw (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) {
275 1.28.8.2 nathanw if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
276 1.28.8.2 nathanw || !(*dev->sci_bus_csr & SCI_BUS_BSY)
277 1.28.8.2 nathanw || --wait < 0) {
278 1.28.8.2 nathanw #ifdef DEBUG
279 1.28.8.2 nathanw if (sci_debug)
280 1.28.8.2 nathanw printf("ivsc_dma_out fail: l%d i%x w%d\n",
281 1.28.8.2 nathanw len, *dev->sci_bus_csr, wait);
282 1.28.8.2 nathanw #endif
283 1.28.8.2 nathanw *dev->sci_mode &= ~SCI_MODE_DMA;
284 1.28.8.2 nathanw return 0;
285 1.28.8.2 nathanw }
286 1.28.8.2 nathanw }
287 1.28.8.2 nathanw
288 1.28.8.2 nathanw *sci_dma = *buf++;
289 1.28.8.2 nathanw len--;
290 1.28.8.2 nathanw }
291 1.28.8.2 nathanw
292 1.28.8.2 nathanw wait = sci_data_wait;
293 1.28.8.2 nathanw while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) ==
294 1.28.8.2 nathanw SCI_CSR_PHASE_MATCH && --wait);
295 1.28.8.2 nathanw
296 1.28.8.2 nathanw
297 1.28.8.2 nathanw *dev->sci_mode &= ~SCI_MODE_DMA;
298 1.28.8.2 nathanw return 0;
299 1.28.8.2 nathanw }
300 1.28.8.2 nathanw
301 1.28.8.2 nathanw int
302 1.28.8.2 nathanw ivsc_intr(void *arg)
303 1.28.8.2 nathanw {
304 1.28.8.2 nathanw struct sci_softc *dev = arg;
305 1.28.8.2 nathanw u_char stat;
306 1.28.8.2 nathanw
307 1.28.8.2 nathanw if ((*dev->sci_csr & SCI_CSR_INT) == 0)
308 1.28.8.2 nathanw return(0);
309 1.28.8.2 nathanw stat = *dev->sci_iack;
310 1.28.8.2 nathanw /* XXXX is: something is missing here, at least a: */
311 1.28.8.2 nathanw return(1);
312 1.28.8.2 nathanw }
313