mlhsc.c revision 1.16
1 /* $NetBSD: mlhsc.c,v 1.16 1996/12/23 09:10:25 veego Exp $ */ 2 3 /* 4 * Copyright (c) 1994 Michael L. Hitch 5 * Copyright (c) 1982, 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * @(#)dma.c 37 */ 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/device.h> 42 #include <scsi/scsi_all.h> 43 #include <scsi/scsiconf.h> 44 #include <amiga/amiga/device.h> 45 #include <amiga/amiga/isr.h> 46 #include <amiga/dev/scireg.h> 47 #include <amiga/dev/scivar.h> 48 #include <amiga/dev/zbusvar.h> 49 50 void mlhscattach __P((struct device *, struct device *, void *)); 51 int mlhscmatch __P((struct device *, struct cfdata *, void *)); 52 53 int mlhsc_dma_xfer_in __P((struct sci_softc *dev, int len, 54 register u_char *buf, int phase)); 55 int mlhsc_dma_xfer_out __P((struct sci_softc *dev, int len, 56 register u_char *buf, int phase)); 57 58 struct scsi_adapter mlhsc_scsiswitch = { 59 sci_scsicmd, 60 sci_minphys, 61 0, /* no lun support */ 62 0, /* no lun support */ 63 }; 64 65 struct scsi_device mlhsc_scsidev = { 66 NULL, /* use default error handler */ 67 NULL, /* do not have a start functio */ 68 NULL, /* have no async handler */ 69 NULL, /* Use default done routine */ 70 }; 71 72 #ifdef DEBUG 73 extern int sci_debug; 74 #define QPRINTF(a) if (sci_debug > 1) printf a 75 #else 76 #define QPRINTF(a) 77 #endif 78 79 extern int sci_data_wait; 80 81 struct cfattach mlhsc_ca = { 82 sizeof(struct sci_softc), mlhscmatch, mlhscattach 83 }; 84 85 struct cfdriver mlhsc_cd = { 86 NULL, "mlhsc", DV_DULL, NULL, 0 87 }; 88 89 /* 90 * if we are my Hacker's SCSI board we are here. 91 */ 92 int 93 mlhscmatch(pdp, cfp, auxp) 94 struct device *pdp; 95 struct cfdata *cfp; 96 void *auxp; 97 { 98 struct zbus_args *zap; 99 100 zap = auxp; 101 102 /* 103 * Check manufacturer and product id. 104 */ 105 if (zap->manid == 2011 && zap->prodid == 1) 106 return(1); 107 else 108 return(0); 109 } 110 111 void 112 mlhscattach(pdp, dp, auxp) 113 struct device *pdp, *dp; 114 void *auxp; 115 { 116 volatile u_char *rp; 117 struct sci_softc *sc; 118 struct zbus_args *zap; 119 120 printf("\n"); 121 122 zap = auxp; 123 124 sc = (struct sci_softc *)dp; 125 rp = zap->va; 126 sc->sci_data = rp + 1; 127 sc->sci_odata = rp + 1; 128 sc->sci_icmd = rp + 3; 129 sc->sci_mode = rp + 5; 130 sc->sci_tcmd = rp + 7; 131 sc->sci_bus_csr = rp + 9; 132 sc->sci_sel_enb = rp + 9; 133 sc->sci_csr = rp + 11; 134 sc->sci_dma_send = rp + 11; 135 sc->sci_idata = rp + 13; 136 sc->sci_trecv = rp + 13; 137 sc->sci_iack = rp + 15; 138 sc->sci_irecv = rp + 15; 139 140 sc->dma_xfer_in = mlhsc_dma_xfer_in; 141 sc->dma_xfer_out = mlhsc_dma_xfer_out; 142 143 scireset(sc); 144 145 sc->sc_link.channel = SCSI_CHANNEL_ONLY_ONE; 146 sc->sc_link.adapter_softc = sc; 147 sc->sc_link.adapter_target = 7; 148 sc->sc_link.adapter = &mlhsc_scsiswitch; 149 sc->sc_link.device = &mlhsc_scsidev; 150 sc->sc_link.openings = 1; 151 sc->sc_link.max_target = 7; 152 TAILQ_INIT(&sc->sc_xslist); 153 154 /* 155 * attach all scsi units on us 156 */ 157 config_found(dp, &sc->sc_link, scsiprint); 158 } 159 160 int 161 mlhsc_dma_xfer_in (dev, len, buf, phase) 162 struct sci_softc *dev; 163 int len; 164 register u_char *buf; 165 int phase; 166 { 167 int wait = sci_data_wait; 168 u_char csr; 169 volatile register u_char *sci_dma = dev->sci_data + 16; 170 volatile register u_char *sci_csr = dev->sci_csr; 171 #ifdef DEBUG 172 u_char *obp = buf; 173 #endif 174 175 csr = *dev->sci_bus_csr; 176 177 QPRINTF(("mlhdma_in %d, csr=%02x\n", len, csr)); 178 179 *dev->sci_tcmd = phase; 180 *dev->sci_mode |= SCI_MODE_DMA; 181 *dev->sci_icmd = 0; 182 *dev->sci_irecv = 0; 183 while (len > 128) { 184 wait = sci_data_wait; 185 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 186 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 187 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 188 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 189 || --wait < 0) { 190 #ifdef DEBUG 191 if (sci_debug) 192 printf("mlhdma_in fail: l%d i%x w%d\n", 193 len, csr, wait); 194 #endif 195 *dev->sci_mode &= ~SCI_MODE_DMA; 196 return 0; 197 } 198 } 199 200 #define R1 (*buf++ = *sci_dma) 201 R1; R1; R1; R1; R1; R1; R1; R1; 202 R1; R1; R1; R1; R1; R1; R1; R1; 203 R1; R1; R1; R1; R1; R1; R1; R1; 204 R1; R1; R1; R1; R1; R1; R1; R1; 205 R1; R1; R1; R1; R1; R1; R1; R1; 206 R1; R1; R1; R1; R1; R1; R1; R1; 207 R1; R1; R1; R1; R1; R1; R1; R1; 208 R1; R1; R1; R1; R1; R1; R1; R1; 209 R1; R1; R1; R1; R1; R1; R1; R1; 210 R1; R1; R1; R1; R1; R1; R1; R1; 211 R1; R1; R1; R1; R1; R1; R1; R1; 212 R1; R1; R1; R1; R1; R1; R1; R1; 213 R1; R1; R1; R1; R1; R1; R1; R1; 214 R1; R1; R1; R1; R1; R1; R1; R1; 215 R1; R1; R1; R1; R1; R1; R1; R1; 216 R1; R1; R1; R1; R1; R1; R1; R1; 217 len -= 128; 218 } 219 while (len > 0) { 220 wait = sci_data_wait; 221 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 222 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 223 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 224 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 225 || --wait < 0) { 226 #ifdef DEBUG 227 if (sci_debug) 228 printf("mlhdma_in fail: l%d i%x w%d\n", 229 len, csr, wait); 230 #endif 231 *dev->sci_mode &= ~SCI_MODE_DMA; 232 return 0; 233 } 234 } 235 236 *buf++ = *sci_dma; 237 len--; 238 } 239 240 QPRINTF(("mlhdma_in {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", 241 len, obp[0], obp[1], obp[2], obp[3], obp[4], obp[5], 242 obp[6], obp[7], obp[8], obp[9])); 243 244 *dev->sci_mode &= ~SCI_MODE_DMA; 245 return 0; 246 } 247 248 int 249 mlhsc_dma_xfer_out (dev, len, buf, phase) 250 struct sci_softc *dev; 251 int len; 252 register u_char *buf; 253 int phase; 254 { 255 int wait = sci_data_wait; 256 u_char csr; 257 volatile register u_char *sci_dma = dev->sci_data + 16; 258 volatile register u_char *sci_csr = dev->sci_csr; 259 260 csr = *dev->sci_bus_csr; 261 262 QPRINTF(("mlhdma_xfer %d, csr=%02x\n", len, csr)); 263 264 QPRINTF(("mlhgdma_out {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", 265 len, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], 266 buf[6], buf[7], buf[8], buf[9])); 267 268 *dev->sci_tcmd = phase; 269 *dev->sci_mode |= SCI_MODE_DMA; 270 *dev->sci_icmd = SCI_ICMD_DATA; 271 *dev->sci_dma_send = 0; 272 while (len > 64) { 273 wait = sci_data_wait; 274 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 275 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 276 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 277 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 278 || --wait < 0) { 279 #ifdef DEBUG 280 if (sci_debug) 281 printf("mlhdma_out fail: l%d i%x w%d\n", 282 len, csr, wait); 283 #endif 284 *dev->sci_mode &= ~SCI_MODE_DMA; 285 return 0; 286 } 287 } 288 289 #define W1 (*sci_dma = *buf++) 290 W1; W1; W1; W1; W1; W1; W1; W1; 291 W1; W1; W1; W1; W1; W1; W1; W1; 292 W1; W1; W1; W1; W1; W1; W1; W1; 293 W1; W1; W1; W1; W1; W1; W1; W1; 294 W1; W1; W1; W1; W1; W1; W1; W1; 295 W1; W1; W1; W1; W1; W1; W1; W1; 296 W1; W1; W1; W1; W1; W1; W1; W1; 297 W1; W1; W1; W1; W1; W1; W1; W1; 298 len -= 64; 299 } 300 while (len > 0) { 301 wait = sci_data_wait; 302 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 303 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 304 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 305 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 306 || --wait < 0) { 307 #ifdef DEBUG 308 if (sci_debug) 309 printf("mlhdma_out fail: l%d i%x w%d\n", 310 len, csr, wait); 311 #endif 312 *dev->sci_mode &= ~SCI_MODE_DMA; 313 return 0; 314 } 315 } 316 317 *sci_dma = *buf++; 318 len--; 319 } 320 321 wait = sci_data_wait; 322 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) == 323 SCI_CSR_PHASE_MATCH && --wait); 324 325 *dev->sci_mode &= ~SCI_MODE_DMA; 326 return 0; 327 } 328
Indexes created Tue Sep 23 01:09:51 GMT 2025