mlhsc.c revision 1.19
1 /* $NetBSD: mlhsc.c,v 1.19 1998/10/10 00:28:37 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1994 Michael L. Hitch 5 * Copyright (c) 1982, 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * @(#)dma.c 37 */ 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/device.h> 42 #include <dev/scsipi/scsi_all.h> 43 #include <dev/scsipi/scsipi_all.h> 44 #include <dev/scsipi/scsiconf.h> 45 #include <amiga/amiga/device.h> 46 #include <amiga/amiga/isr.h> 47 #include <amiga/dev/scireg.h> 48 #include <amiga/dev/scivar.h> 49 #include <amiga/dev/zbusvar.h> 50 51 void mlhscattach __P((struct device *, struct device *, void *)); 52 int mlhscmatch __P((struct device *, struct cfdata *, void *)); 53 54 int mlhsc_dma_xfer_in __P((struct sci_softc *dev, int len, 55 register u_char *buf, int phase)); 56 int mlhsc_dma_xfer_out __P((struct sci_softc *dev, int len, 57 register u_char *buf, int phase)); 58 59 struct scsipi_adapter mlhsc_scsiswitch = { 60 sci_scsicmd, 61 sci_minphys, 62 NULL, /* scsipi_ioctl */ 63 }; 64 65 struct scsipi_device mlhsc_scsidev = { 66 NULL, /* use default error handler */ 67 NULL, /* do not have a start functio */ 68 NULL, /* have no async handler */ 69 NULL, /* Use default done routine */ 70 }; 71 72 #ifdef DEBUG 73 extern int sci_debug; 74 #define QPRINTF(a) if (sci_debug > 1) printf a 75 #else 76 #define QPRINTF(a) 77 #endif 78 79 extern int sci_data_wait; 80 81 struct cfattach mlhsc_ca = { 82 sizeof(struct sci_softc), mlhscmatch, mlhscattach 83 }; 84 85 /* 86 * if we are my Hacker's SCSI board we are here. 87 */ 88 int 89 mlhscmatch(pdp, cfp, auxp) 90 struct device *pdp; 91 struct cfdata *cfp; 92 void *auxp; 93 { 94 struct zbus_args *zap; 95 96 zap = auxp; 97 98 /* 99 * Check manufacturer and product id. 100 */ 101 if (zap->manid == 2011 && zap->prodid == 1) 102 return(1); 103 else 104 return(0); 105 } 106 107 void 108 mlhscattach(pdp, dp, auxp) 109 struct device *pdp, *dp; 110 void *auxp; 111 { 112 volatile u_char *rp; 113 struct sci_softc *sc; 114 struct zbus_args *zap; 115 116 printf("\n"); 117 118 zap = auxp; 119 120 sc = (struct sci_softc *)dp; 121 rp = zap->va; 122 sc->sci_data = rp + 1; 123 sc->sci_odata = rp + 1; 124 sc->sci_icmd = rp + 3; 125 sc->sci_mode = rp + 5; 126 sc->sci_tcmd = rp + 7; 127 sc->sci_bus_csr = rp + 9; 128 sc->sci_sel_enb = rp + 9; 129 sc->sci_csr = rp + 11; 130 sc->sci_dma_send = rp + 11; 131 sc->sci_idata = rp + 13; 132 sc->sci_trecv = rp + 13; 133 sc->sci_iack = rp + 15; 134 sc->sci_irecv = rp + 15; 135 136 sc->dma_xfer_in = mlhsc_dma_xfer_in; 137 sc->dma_xfer_out = mlhsc_dma_xfer_out; 138 139 scireset(sc); 140 141 sc->sc_link.scsipi_scsi.channel = SCSI_CHANNEL_ONLY_ONE; 142 sc->sc_link.adapter_softc = sc; 143 sc->sc_link.scsipi_scsi.adapter_target = 7; 144 sc->sc_link.adapter = &mlhsc_scsiswitch; 145 sc->sc_link.device = &mlhsc_scsidev; 146 sc->sc_link.openings = 1; 147 sc->sc_link.scsipi_scsi.max_target = 7; 148 sc->sc_link.type = BUS_SCSI; 149 TAILQ_INIT(&sc->sc_xslist); 150 151 /* 152 * attach all scsi units on us 153 */ 154 config_found(dp, &sc->sc_link, scsiprint); 155 } 156 157 int 158 mlhsc_dma_xfer_in (dev, len, buf, phase) 159 struct sci_softc *dev; 160 int len; 161 register u_char *buf; 162 int phase; 163 { 164 int wait = sci_data_wait; 165 u_char csr; 166 volatile register u_char *sci_dma = dev->sci_data + 16; 167 volatile register u_char *sci_csr = dev->sci_csr; 168 #ifdef DEBUG 169 u_char *obp = buf; 170 #endif 171 172 csr = *dev->sci_bus_csr; 173 174 QPRINTF(("mlhdma_in %d, csr=%02x\n", len, csr)); 175 176 *dev->sci_tcmd = phase; 177 *dev->sci_mode |= SCI_MODE_DMA; 178 *dev->sci_icmd = 0; 179 *dev->sci_irecv = 0; 180 while (len > 128) { 181 wait = sci_data_wait; 182 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 183 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 184 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 185 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 186 || --wait < 0) { 187 #ifdef DEBUG 188 if (sci_debug) 189 printf("mlhdma_in fail: l%d i%x w%d\n", 190 len, csr, wait); 191 #endif 192 *dev->sci_mode &= ~SCI_MODE_DMA; 193 return 0; 194 } 195 } 196 197 #define R1 (*buf++ = *sci_dma) 198 R1; R1; R1; R1; R1; R1; R1; R1; 199 R1; R1; R1; R1; R1; R1; R1; R1; 200 R1; R1; R1; R1; R1; R1; R1; R1; 201 R1; R1; R1; R1; R1; R1; R1; R1; 202 R1; R1; R1; R1; R1; R1; R1; R1; 203 R1; R1; R1; R1; R1; R1; R1; R1; 204 R1; R1; R1; R1; R1; R1; R1; R1; 205 R1; R1; R1; R1; R1; R1; R1; R1; 206 R1; R1; R1; R1; R1; R1; R1; R1; 207 R1; R1; R1; R1; R1; R1; R1; R1; 208 R1; R1; R1; R1; R1; R1; R1; R1; 209 R1; R1; R1; R1; R1; R1; R1; R1; 210 R1; R1; R1; R1; R1; R1; R1; R1; 211 R1; R1; R1; R1; R1; R1; R1; R1; 212 R1; R1; R1; R1; R1; R1; R1; R1; 213 R1; R1; R1; R1; R1; R1; R1; R1; 214 len -= 128; 215 } 216 while (len > 0) { 217 wait = sci_data_wait; 218 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 219 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 220 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 221 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 222 || --wait < 0) { 223 #ifdef DEBUG 224 if (sci_debug) 225 printf("mlhdma_in fail: l%d i%x w%d\n", 226 len, csr, wait); 227 #endif 228 *dev->sci_mode &= ~SCI_MODE_DMA; 229 return 0; 230 } 231 } 232 233 *buf++ = *sci_dma; 234 len--; 235 } 236 237 QPRINTF(("mlhdma_in {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", 238 len, obp[0], obp[1], obp[2], obp[3], obp[4], obp[5], 239 obp[6], obp[7], obp[8], obp[9])); 240 241 *dev->sci_mode &= ~SCI_MODE_DMA; 242 return 0; 243 } 244 245 int 246 mlhsc_dma_xfer_out (dev, len, buf, phase) 247 struct sci_softc *dev; 248 int len; 249 register u_char *buf; 250 int phase; 251 { 252 int wait = sci_data_wait; 253 u_char csr; 254 volatile register u_char *sci_dma = dev->sci_data + 16; 255 volatile register u_char *sci_csr = dev->sci_csr; 256 257 csr = *dev->sci_bus_csr; 258 259 QPRINTF(("mlhdma_xfer %d, csr=%02x\n", len, csr)); 260 261 QPRINTF(("mlhgdma_out {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", 262 len, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], 263 buf[6], buf[7], buf[8], buf[9])); 264 265 *dev->sci_tcmd = phase; 266 *dev->sci_mode |= SCI_MODE_DMA; 267 *dev->sci_icmd = SCI_ICMD_DATA; 268 *dev->sci_dma_send = 0; 269 while (len > 64) { 270 wait = sci_data_wait; 271 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 272 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 273 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 274 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 275 || --wait < 0) { 276 #ifdef DEBUG 277 if (sci_debug) 278 printf("mlhdma_out fail: l%d i%x w%d\n", 279 len, csr, wait); 280 #endif 281 *dev->sci_mode &= ~SCI_MODE_DMA; 282 return 0; 283 } 284 } 285 286 #define W1 (*sci_dma = *buf++) 287 W1; W1; W1; W1; W1; W1; W1; W1; 288 W1; W1; W1; W1; W1; W1; W1; W1; 289 W1; W1; W1; W1; W1; W1; W1; W1; 290 W1; W1; W1; W1; W1; W1; W1; W1; 291 W1; W1; W1; W1; W1; W1; W1; W1; 292 W1; W1; W1; W1; W1; W1; W1; W1; 293 W1; W1; W1; W1; W1; W1; W1; W1; 294 W1; W1; W1; W1; W1; W1; W1; W1; 295 len -= 64; 296 } 297 while (len > 0) { 298 wait = sci_data_wait; 299 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 300 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 301 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 302 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 303 || --wait < 0) { 304 #ifdef DEBUG 305 if (sci_debug) 306 printf("mlhdma_out fail: l%d i%x w%d\n", 307 len, csr, wait); 308 #endif 309 *dev->sci_mode &= ~SCI_MODE_DMA; 310 return 0; 311 } 312 } 313 314 *sci_dma = *buf++; 315 len--; 316 } 317 318 wait = sci_data_wait; 319 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) == 320 SCI_CSR_PHASE_MATCH && --wait); 321 322 *dev->sci_mode &= ~SCI_MODE_DMA; 323 return 0; 324 } 325
Indexes created Fri Oct 03 02:09:57 GMT 2025