mlhsc.c revision 1.23.8.3
1 /* $NetBSD: mlhsc.c,v 1.23.8.3 2002/10/18 02:35:02 nathanw Exp $ */ 2 3 /* 4 * Copyright (c) 1994 Michael L. Hitch 5 * Copyright (c) 1982, 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * @(#)dma.c 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: mlhsc.c,v 1.23.8.3 2002/10/18 02:35:02 nathanw Exp $"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/kernel.h> 45 #include <sys/device.h> 46 #include <dev/scsipi/scsi_all.h> 47 #include <dev/scsipi/scsipi_all.h> 48 #include <dev/scsipi/scsiconf.h> 49 #include <amiga/amiga/device.h> 50 #include <amiga/amiga/isr.h> 51 #include <amiga/dev/scireg.h> 52 #include <amiga/dev/scivar.h> 53 #include <amiga/dev/zbusvar.h> 54 55 void mlhscattach(struct device *, struct device *, void *); 56 int mlhscmatch(struct device *, struct cfdata *, void *); 57 58 int mlhsc_dma_xfer_in(struct sci_softc *dev, int len, 59 register u_char *buf, int phase); 60 int mlhsc_dma_xfer_out(struct sci_softc *dev, int len, 61 register u_char *buf, int phase); 62 63 #ifdef DEBUG 64 extern int sci_debug; 65 #define QPRINTF(a) if (sci_debug > 1) printf a 66 #else 67 #define QPRINTF(a) 68 #endif 69 70 extern int sci_data_wait; 71 72 CFATTACH_DECL(mlhsc, sizeof(struct sci_softc), 73 mlhscmatch, mlhscattach, NULL, NULL); 74 75 /* 76 * if we are my Hacker's SCSI board we are here. 77 */ 78 int 79 mlhscmatch(struct device *pdp, struct cfdata *cfp, void *auxp) 80 { 81 struct zbus_args *zap; 82 83 zap = auxp; 84 85 /* 86 * Check manufacturer and product id. 87 */ 88 if (zap->manid == 2011 && zap->prodid == 1) 89 return(1); 90 else 91 return(0); 92 } 93 94 void 95 mlhscattach(struct device *pdp, struct device *dp, void *auxp) 96 { 97 volatile u_char *rp; 98 struct sci_softc *sc = (struct sci_softc *)dp; 99 struct zbus_args *zap; 100 struct scsipi_adapter *adapt = &sc->sc_adapter; 101 struct scsipi_channel *chan = &sc->sc_channel; 102 103 printf("\n"); 104 105 zap = auxp; 106 107 sc = (struct sci_softc *)dp; 108 rp = zap->va; 109 sc->sci_data = rp + 1; 110 sc->sci_odata = rp + 1; 111 sc->sci_icmd = rp + 3; 112 sc->sci_mode = rp + 5; 113 sc->sci_tcmd = rp + 7; 114 sc->sci_bus_csr = rp + 9; 115 sc->sci_sel_enb = rp + 9; 116 sc->sci_csr = rp + 11; 117 sc->sci_dma_send = rp + 11; 118 sc->sci_idata = rp + 13; 119 sc->sci_trecv = rp + 13; 120 sc->sci_iack = rp + 15; 121 sc->sci_irecv = rp + 15; 122 123 sc->dma_xfer_in = mlhsc_dma_xfer_in; 124 sc->dma_xfer_out = mlhsc_dma_xfer_out; 125 126 scireset(sc); 127 128 /* 129 * Fill in the scsipi_adapter. 130 */ 131 memset(adapt, 0, sizeof(*adapt)); 132 adapt->adapt_dev = &sc->sc_dev; 133 adapt->adapt_nchannels = 1; 134 adapt->adapt_openings = 7; 135 adapt->adapt_max_periph = 1; 136 adapt->adapt_request = sci_scsipi_request; 137 adapt->adapt_minphys = sci_minphys; 138 139 /* 140 * Fill in the scsipi_channel. 141 */ 142 memset(chan, 0, sizeof(*chan)); 143 chan->chan_adapter = adapt; 144 chan->chan_bustype = &scsi_bustype; 145 chan->chan_channel = 0; 146 chan->chan_ntargets = 8; 147 chan->chan_nluns = 8; 148 chan->chan_id = 7; 149 150 /* 151 * attach all scsi units on us 152 */ 153 config_found(dp, chan, scsiprint); 154 } 155 156 int 157 mlhsc_dma_xfer_in(struct sci_softc *dev, int len, register u_char *buf, 158 int phase) 159 { 160 int wait = sci_data_wait; 161 u_char csr; 162 volatile register u_char *sci_dma = dev->sci_data + 16; 163 volatile register u_char *sci_csr = dev->sci_csr; 164 #ifdef DEBUG 165 u_char *obp = buf; 166 #endif 167 168 csr = *dev->sci_bus_csr; 169 170 QPRINTF(("mlhdma_in %d, csr=%02x\n", len, csr)); 171 172 *dev->sci_tcmd = phase; 173 *dev->sci_mode |= SCI_MODE_DMA; 174 *dev->sci_icmd = 0; 175 *dev->sci_irecv = 0; 176 while (len > 128) { 177 wait = sci_data_wait; 178 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 179 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 180 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 181 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 182 || --wait < 0) { 183 #ifdef DEBUG 184 if (sci_debug) 185 printf("mlhdma_in fail: l%d i%x w%d\n", 186 len, csr, wait); 187 #endif 188 *dev->sci_mode &= ~SCI_MODE_DMA; 189 return 0; 190 } 191 } 192 193 #define R1 (*buf++ = *sci_dma) 194 R1; R1; R1; R1; R1; R1; R1; R1; 195 R1; R1; R1; R1; R1; R1; R1; R1; 196 R1; R1; R1; R1; R1; R1; R1; R1; 197 R1; R1; R1; R1; R1; R1; R1; R1; 198 R1; R1; R1; R1; R1; R1; R1; R1; 199 R1; R1; R1; R1; R1; R1; R1; R1; 200 R1; R1; R1; R1; R1; R1; R1; R1; 201 R1; R1; R1; R1; R1; R1; R1; R1; 202 R1; R1; R1; R1; R1; R1; R1; R1; 203 R1; R1; R1; R1; R1; R1; R1; R1; 204 R1; R1; R1; R1; R1; R1; R1; R1; 205 R1; R1; R1; R1; R1; R1; R1; R1; 206 R1; R1; R1; R1; R1; R1; R1; R1; 207 R1; R1; R1; R1; R1; R1; R1; R1; 208 R1; R1; R1; R1; R1; R1; R1; R1; 209 R1; R1; R1; R1; R1; R1; R1; R1; 210 len -= 128; 211 } 212 while (len > 0) { 213 wait = sci_data_wait; 214 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 215 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 216 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 217 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 218 || --wait < 0) { 219 #ifdef DEBUG 220 if (sci_debug) 221 printf("mlhdma_in fail: l%d i%x w%d\n", 222 len, csr, wait); 223 #endif 224 *dev->sci_mode &= ~SCI_MODE_DMA; 225 return 0; 226 } 227 } 228 229 *buf++ = *sci_dma; 230 len--; 231 } 232 233 QPRINTF(("mlhdma_in {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", 234 len, obp[0], obp[1], obp[2], obp[3], obp[4], obp[5], 235 obp[6], obp[7], obp[8], obp[9])); 236 237 *dev->sci_mode &= ~SCI_MODE_DMA; 238 return 0; 239 } 240 241 int 242 mlhsc_dma_xfer_out(struct sci_softc *dev, int len, register u_char *buf, 243 int phase) 244 { 245 int wait = sci_data_wait; 246 u_char csr; 247 volatile register u_char *sci_dma = dev->sci_data + 16; 248 volatile register u_char *sci_csr = dev->sci_csr; 249 250 csr = *dev->sci_bus_csr; 251 252 QPRINTF(("mlhdma_xfer %d, csr=%02x\n", len, csr)); 253 254 QPRINTF(("mlhgdma_out {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", 255 len, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], 256 buf[6], buf[7], buf[8], buf[9])); 257 258 *dev->sci_tcmd = phase; 259 *dev->sci_mode |= SCI_MODE_DMA; 260 *dev->sci_icmd = SCI_ICMD_DATA; 261 *dev->sci_dma_send = 0; 262 while (len > 64) { 263 wait = sci_data_wait; 264 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 265 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 266 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 267 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 268 || --wait < 0) { 269 #ifdef DEBUG 270 if (sci_debug) 271 printf("mlhdma_out fail: l%d i%x w%d\n", 272 len, csr, wait); 273 #endif 274 *dev->sci_mode &= ~SCI_MODE_DMA; 275 return 0; 276 } 277 } 278 279 #define W1 (*sci_dma = *buf++) 280 W1; W1; W1; W1; W1; W1; W1; W1; 281 W1; W1; W1; W1; W1; W1; W1; W1; 282 W1; W1; W1; W1; W1; W1; W1; W1; 283 W1; W1; W1; W1; W1; W1; W1; W1; 284 W1; W1; W1; W1; W1; W1; W1; W1; 285 W1; W1; W1; W1; W1; W1; W1; W1; 286 W1; W1; W1; W1; W1; W1; W1; W1; 287 W1; W1; W1; W1; W1; W1; W1; W1; 288 len -= 64; 289 } 290 while (len > 0) { 291 wait = sci_data_wait; 292 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 293 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 294 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 295 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 296 || --wait < 0) { 297 #ifdef DEBUG 298 if (sci_debug) 299 printf("mlhdma_out fail: l%d i%x w%d\n", 300 len, csr, wait); 301 #endif 302 *dev->sci_mode &= ~SCI_MODE_DMA; 303 return 0; 304 } 305 } 306 307 *sci_dma = *buf++; 308 len--; 309 } 310 311 wait = sci_data_wait; 312 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) == 313 SCI_CSR_PHASE_MATCH && --wait); 314 315 *dev->sci_mode &= ~SCI_MODE_DMA; 316 return 0; 317 } 318
Indexes created Fri Oct 03 02:09:57 GMT 2025