mlhsc.c revision 1.5
1 /* $NetBSD: mlhsc.c,v 1.5 1994/12/01 17:25:28 chopps Exp $ */ 2 3 /* 4 * Copyright (c) 1994 Michael L. Hitch 5 * Copyright (c) 1982, 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * @(#)dma.c 37 */ 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/device.h> 42 #include <scsi/scsi_all.h> 43 #include <scsi/scsiconf.h> 44 #include <amiga/amiga/device.h> 45 #include <amiga/dev/scireg.h> 46 #include <amiga/dev/scivar.h> 47 #include <amiga/dev/ztwobusvar.h> 48 49 int mlhscprint __P((void *auxp, char *)); 50 void mlhscattach __P((struct device *, struct device *, void *)); 51 int mlhscmatch __P((struct device *, struct cfdata *, void *)); 52 53 int mlhsc_dma_xfer_in __P((struct sci_softc *dev, int len, 54 register u_char *buf, int phase)); 55 int mlhsc_dma_xfer_out __P((struct sci_softc *dev, int len, 56 register u_char *buf, int phase)); 57 58 struct scsi_adapter mlhsc_scsiswitch = { 59 sci_scsicmd, 60 sci_minphys, 61 0, /* no lun support */ 62 0, /* no lun support */ 63 sci_adinfo, 64 "mlhsc", 65 }; 66 67 struct scsi_device mlhsc_scsidev = { 68 NULL, /* use default error handler */ 69 NULL, /* do not have a start functio */ 70 NULL, /* have no async handler */ 71 NULL, /* Use default done routine */ 72 "mlhsc", 73 0, 74 }; 75 76 #define QPRINTF 77 78 #ifdef DEBUG 79 extern int sci_debug; 80 #endif 81 82 extern int sci_data_wait; 83 84 struct cfdriver mlhsccd = { 85 NULL, "mlhsc", (cfmatch_t)mlhscmatch, mlhscattach, 86 DV_DULL, sizeof(struct sci_softc), NULL, 0 }; 87 88 /* 89 * if we are my Hacker's SCSI board we are here. 90 */ 91 int 92 mlhscmatch(pdp, cdp, auxp) 93 struct device *pdp; 94 struct cfdata *cdp; 95 void *auxp; 96 { 97 struct ztwobus_args *zap; 98 99 zap = auxp; 100 101 /* 102 * Check manufacturer and product id. 103 */ 104 if (zap->manid == 2011 && zap->prodid == 1) 105 return(1); 106 else 107 return(0); 108 } 109 110 void 111 mlhscattach(pdp, dp, auxp) 112 struct device *pdp, *dp; 113 void *auxp; 114 { 115 volatile u_char *rp; 116 struct sci_softc *sc; 117 struct ztwobus_args *zap; 118 119 printf("\n"); 120 121 zap = auxp; 122 123 sc = (struct sci_softc *)dp; 124 rp = zap->va; 125 sc->sci_data = rp + 1; 126 sc->sci_odata = rp + 1; 127 sc->sci_icmd = rp + 3; 128 sc->sci_mode = rp + 5; 129 sc->sci_tcmd = rp + 7; 130 sc->sci_bus_csr = rp + 9; 131 sc->sci_sel_enb = rp + 9; 132 sc->sci_csr = rp + 11; 133 sc->sci_dma_send = rp + 11; 134 sc->sci_idata = rp + 13; 135 sc->sci_trecv = rp + 13; 136 sc->sci_iack = rp + 15; 137 sc->sci_irecv = rp + 15; 138 139 sc->dma_xfer_in = mlhsc_dma_xfer_in; 140 sc->dma_xfer_out = mlhsc_dma_xfer_out; 141 142 scireset(sc); 143 144 sc->sc_link.adapter_softc = sc; 145 sc->sc_link.adapter_targ = 7; 146 sc->sc_link.adapter = &mlhsc_scsiswitch; 147 sc->sc_link.device = &mlhsc_scsidev; 148 TAILQ_INIT(&sc->sc_xslist); 149 150 /* 151 * attach all scsi units on us 152 */ 153 config_found(dp, &sc->sc_link, mlhscprint); 154 } 155 156 /* 157 * print diag if pnp is NULL else just extra 158 */ 159 int 160 mlhscprint(auxp, pnp) 161 void *auxp; 162 char *pnp; 163 { 164 if (pnp == NULL) 165 return(UNCONF); 166 return(QUIET); 167 } 168 169 170 int 171 mlhsc_dma_xfer_in (dev, len, buf, phase) 172 struct sci_softc *dev; 173 int len; 174 register u_char *buf; 175 int phase; 176 { 177 int wait = sci_data_wait; 178 u_char csr; 179 u_char *obp = buf; 180 volatile register u_char *sci_dma = dev->sci_data + 16; 181 volatile register u_char *sci_csr = dev->sci_csr; 182 volatile register u_char *sci_icmd = dev->sci_icmd; 183 184 csr = *dev->sci_bus_csr; 185 186 QPRINTF(("mlhdma_in %d, csr=%02x\n", len, csr)); 187 188 *dev->sci_tcmd = phase; 189 *dev->sci_mode |= SCI_MODE_DMA; 190 *dev->sci_icmd = 0; 191 *dev->sci_irecv = 0; 192 while (len > 128) { 193 wait = sci_data_wait; 194 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 195 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 196 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 197 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 198 || --wait < 0) { 199 #ifdef DEBUG 200 if (sci_debug) 201 printf("mlhdma_in fail: l%d i%x w%d\n", 202 len, csr, wait); 203 #endif 204 *dev->sci_mode &= ~SCI_MODE_DMA; 205 return 0; 206 } 207 } 208 209 #define R1 (*buf++ = *sci_dma) 210 R1; R1; R1; R1; R1; R1; R1; R1; 211 R1; R1; R1; R1; R1; R1; R1; R1; 212 R1; R1; R1; R1; R1; R1; R1; R1; 213 R1; R1; R1; R1; R1; R1; R1; R1; 214 R1; R1; R1; R1; R1; R1; R1; R1; 215 R1; R1; R1; R1; R1; R1; R1; R1; 216 R1; R1; R1; R1; R1; R1; R1; R1; 217 R1; R1; R1; R1; R1; R1; R1; R1; 218 R1; R1; R1; R1; R1; R1; R1; R1; 219 R1; R1; R1; R1; R1; R1; R1; R1; 220 R1; R1; R1; R1; R1; R1; R1; R1; 221 R1; R1; R1; R1; R1; R1; R1; R1; 222 R1; R1; R1; R1; R1; R1; R1; R1; 223 R1; R1; R1; R1; R1; R1; R1; R1; 224 R1; R1; R1; R1; R1; R1; R1; R1; 225 R1; R1; R1; R1; R1; R1; R1; R1; 226 len -= 128; 227 } 228 while (len > 0) { 229 wait = sci_data_wait; 230 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 231 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 232 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 233 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 234 || --wait < 0) { 235 #ifdef DEBUG 236 if (sci_debug) 237 printf("mlhdma_in fail: l%d i%x w%d\n", 238 len, csr, wait); 239 #endif 240 *dev->sci_mode &= ~SCI_MODE_DMA; 241 return 0; 242 } 243 } 244 245 *buf++ = *sci_dma; 246 len--; 247 } 248 249 QPRINTF(("mlhdma_in {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", 250 len, obp[0], obp[1], obp[2], obp[3], obp[4], obp[5], 251 obp[6], obp[7], obp[8], obp[9])); 252 253 *dev->sci_mode &= ~SCI_MODE_DMA; 254 return 0; 255 } 256 257 int 258 mlhsc_dma_xfer_out (dev, len, buf, phase) 259 struct sci_softc *dev; 260 int len; 261 register u_char *buf; 262 int phase; 263 { 264 int wait = sci_data_wait; 265 u_char csr; 266 u_char *obp = buf; 267 volatile register u_char *sci_dma = dev->sci_data + 16; 268 volatile register u_char *sci_csr = dev->sci_csr; 269 volatile register u_char *sci_icmd = dev->sci_icmd; 270 271 csr = *dev->sci_bus_csr; 272 273 QPRINTF(("mlhdma_xfer %d, csr=%02x\n", len, csr)); 274 275 QPRINTF(("mlhgdma_out {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", 276 len, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], 277 buf[6], buf[7], buf[8], buf[9])); 278 279 *dev->sci_tcmd = phase; 280 *dev->sci_mode |= SCI_MODE_DMA; 281 *dev->sci_icmd = SCI_ICMD_DATA; 282 *dev->sci_dma_send = 0; 283 while (len > 64) { 284 wait = sci_data_wait; 285 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 286 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 287 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 288 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 289 || --wait < 0) { 290 #ifdef DEBUG 291 if (sci_debug) 292 printf("mlhdma_out fail: l%d i%x w%d\n", 293 len, csr, wait); 294 #endif 295 *dev->sci_mode &= ~SCI_MODE_DMA; 296 return 0; 297 } 298 } 299 300 #define W1 (*sci_dma = *buf++) 301 W1; W1; W1; W1; W1; W1; W1; W1; 302 W1; W1; W1; W1; W1; W1; W1; W1; 303 W1; W1; W1; W1; W1; W1; W1; W1; 304 W1; W1; W1; W1; W1; W1; W1; W1; 305 W1; W1; W1; W1; W1; W1; W1; W1; 306 W1; W1; W1; W1; W1; W1; W1; W1; 307 W1; W1; W1; W1; W1; W1; W1; W1; 308 W1; W1; W1; W1; W1; W1; W1; W1; 309 len -= 64; 310 } 311 while (len > 0) { 312 wait = sci_data_wait; 313 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 314 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 315 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 316 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 317 || --wait < 0) { 318 #ifdef DEBUG 319 if (sci_debug) 320 printf("mlhdma_out fail: l%d i%x w%d\n", 321 len, csr, wait); 322 #endif 323 *dev->sci_mode &= ~SCI_MODE_DMA; 324 return 0; 325 } 326 } 327 328 *sci_dma = *buf++; 329 len--; 330 } 331 332 wait = sci_data_wait; 333 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) == 334 SCI_CSR_PHASE_MATCH && --wait); 335 336 *dev->sci_mode &= ~SCI_MODE_DMA; 337 return 0; 338 } 339
Indexes created Tue Sep 23 21:09:50 GMT 2025