mlhsc.c revision 1.7
1 /* $NetBSD: mlhsc.c,v 1.7 1995/01/05 07:22:40 chopps Exp $ */ 2 3 /* 4 * Copyright (c) 1994 Michael L. Hitch 5 * Copyright (c) 1982, 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * @(#)dma.c 37 */ 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/device.h> 42 #include <scsi/scsi_all.h> 43 #include <scsi/scsiconf.h> 44 #include <amiga/amiga/device.h> 45 #include <amiga/dev/scireg.h> 46 #include <amiga/dev/scivar.h> 47 #include <amiga/dev/zbusvar.h> 48 49 int mlhscprint __P((void *auxp, char *)); 50 void mlhscattach __P((struct device *, struct device *, void *)); 51 int mlhscmatch __P((struct device *, struct cfdata *, void *)); 52 53 int mlhsc_dma_xfer_in __P((struct sci_softc *dev, int len, 54 register u_char *buf, int phase)); 55 int mlhsc_dma_xfer_out __P((struct sci_softc *dev, int len, 56 register u_char *buf, int phase)); 57 58 struct scsi_adapter mlhsc_scsiswitch = { 59 sci_scsicmd, 60 sci_minphys, 61 0, /* no lun support */ 62 0, /* no lun support */ 63 }; 64 65 struct scsi_device mlhsc_scsidev = { 66 NULL, /* use default error handler */ 67 NULL, /* do not have a start functio */ 68 NULL, /* have no async handler */ 69 NULL, /* Use default done routine */ 70 }; 71 72 #define QPRINTF 73 74 #ifdef DEBUG 75 extern int sci_debug; 76 #endif 77 78 extern int sci_data_wait; 79 80 struct cfdriver mlhsccd = { 81 NULL, "mlhsc", (cfmatch_t)mlhscmatch, mlhscattach, 82 DV_DULL, sizeof(struct sci_softc), NULL, 0 }; 83 84 /* 85 * if we are my Hacker's SCSI board we are here. 86 */ 87 int 88 mlhscmatch(pdp, cdp, auxp) 89 struct device *pdp; 90 struct cfdata *cdp; 91 void *auxp; 92 { 93 struct zbus_args *zap; 94 95 zap = auxp; 96 97 /* 98 * Check manufacturer and product id. 99 */ 100 if (zap->manid == 2011 && zap->prodid == 1) 101 return(1); 102 else 103 return(0); 104 } 105 106 void 107 mlhscattach(pdp, dp, auxp) 108 struct device *pdp, *dp; 109 void *auxp; 110 { 111 volatile u_char *rp; 112 struct sci_softc *sc; 113 struct zbus_args *zap; 114 115 printf("\n"); 116 117 zap = auxp; 118 119 sc = (struct sci_softc *)dp; 120 rp = zap->va; 121 sc->sci_data = rp + 1; 122 sc->sci_odata = rp + 1; 123 sc->sci_icmd = rp + 3; 124 sc->sci_mode = rp + 5; 125 sc->sci_tcmd = rp + 7; 126 sc->sci_bus_csr = rp + 9; 127 sc->sci_sel_enb = rp + 9; 128 sc->sci_csr = rp + 11; 129 sc->sci_dma_send = rp + 11; 130 sc->sci_idata = rp + 13; 131 sc->sci_trecv = rp + 13; 132 sc->sci_iack = rp + 15; 133 sc->sci_irecv = rp + 15; 134 135 sc->dma_xfer_in = mlhsc_dma_xfer_in; 136 sc->dma_xfer_out = mlhsc_dma_xfer_out; 137 138 scireset(sc); 139 140 sc->sc_link.adapter_softc = sc; 141 sc->sc_link.adapter_target = 7; 142 sc->sc_link.adapter = &mlhsc_scsiswitch; 143 sc->sc_link.device = &mlhsc_scsidev; 144 sc->sc_link.openings = 1; 145 TAILQ_INIT(&sc->sc_xslist); 146 147 /* 148 * attach all scsi units on us 149 */ 150 config_found(dp, &sc->sc_link, mlhscprint); 151 } 152 153 /* 154 * print diag if pnp is NULL else just extra 155 */ 156 int 157 mlhscprint(auxp, pnp) 158 void *auxp; 159 char *pnp; 160 { 161 if (pnp == NULL) 162 return(UNCONF); 163 return(QUIET); 164 } 165 166 167 int 168 mlhsc_dma_xfer_in (dev, len, buf, phase) 169 struct sci_softc *dev; 170 int len; 171 register u_char *buf; 172 int phase; 173 { 174 int wait = sci_data_wait; 175 u_char csr; 176 u_char *obp = buf; 177 volatile register u_char *sci_dma = dev->sci_data + 16; 178 volatile register u_char *sci_csr = dev->sci_csr; 179 volatile register u_char *sci_icmd = dev->sci_icmd; 180 181 csr = *dev->sci_bus_csr; 182 183 QPRINTF(("mlhdma_in %d, csr=%02x\n", len, csr)); 184 185 *dev->sci_tcmd = phase; 186 *dev->sci_mode |= SCI_MODE_DMA; 187 *dev->sci_icmd = 0; 188 *dev->sci_irecv = 0; 189 while (len > 128) { 190 wait = sci_data_wait; 191 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 192 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 193 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 194 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 195 || --wait < 0) { 196 #ifdef DEBUG 197 if (sci_debug) 198 printf("mlhdma_in fail: l%d i%x w%d\n", 199 len, csr, wait); 200 #endif 201 *dev->sci_mode &= ~SCI_MODE_DMA; 202 return 0; 203 } 204 } 205 206 #define R1 (*buf++ = *sci_dma) 207 R1; R1; R1; R1; R1; R1; R1; R1; 208 R1; R1; R1; R1; R1; R1; R1; R1; 209 R1; R1; R1; R1; R1; R1; R1; R1; 210 R1; R1; R1; R1; R1; R1; R1; R1; 211 R1; R1; R1; R1; R1; R1; R1; R1; 212 R1; R1; R1; R1; R1; R1; R1; R1; 213 R1; R1; R1; R1; R1; R1; R1; R1; 214 R1; R1; R1; R1; R1; R1; R1; R1; 215 R1; R1; R1; R1; R1; R1; R1; R1; 216 R1; R1; R1; R1; R1; R1; R1; R1; 217 R1; R1; R1; R1; R1; R1; R1; R1; 218 R1; R1; R1; R1; R1; R1; R1; R1; 219 R1; R1; R1; R1; R1; R1; R1; R1; 220 R1; R1; R1; R1; R1; R1; R1; R1; 221 R1; R1; R1; R1; R1; R1; R1; R1; 222 R1; R1; R1; R1; R1; R1; R1; R1; 223 len -= 128; 224 } 225 while (len > 0) { 226 wait = sci_data_wait; 227 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 228 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 229 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 230 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 231 || --wait < 0) { 232 #ifdef DEBUG 233 if (sci_debug) 234 printf("mlhdma_in fail: l%d i%x w%d\n", 235 len, csr, wait); 236 #endif 237 *dev->sci_mode &= ~SCI_MODE_DMA; 238 return 0; 239 } 240 } 241 242 *buf++ = *sci_dma; 243 len--; 244 } 245 246 QPRINTF(("mlhdma_in {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", 247 len, obp[0], obp[1], obp[2], obp[3], obp[4], obp[5], 248 obp[6], obp[7], obp[8], obp[9])); 249 250 *dev->sci_mode &= ~SCI_MODE_DMA; 251 return 0; 252 } 253 254 int 255 mlhsc_dma_xfer_out (dev, len, buf, phase) 256 struct sci_softc *dev; 257 int len; 258 register u_char *buf; 259 int phase; 260 { 261 int wait = sci_data_wait; 262 u_char csr; 263 u_char *obp = buf; 264 volatile register u_char *sci_dma = dev->sci_data + 16; 265 volatile register u_char *sci_csr = dev->sci_csr; 266 volatile register u_char *sci_icmd = dev->sci_icmd; 267 268 csr = *dev->sci_bus_csr; 269 270 QPRINTF(("mlhdma_xfer %d, csr=%02x\n", len, csr)); 271 272 QPRINTF(("mlhgdma_out {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", 273 len, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], 274 buf[6], buf[7], buf[8], buf[9])); 275 276 *dev->sci_tcmd = phase; 277 *dev->sci_mode |= SCI_MODE_DMA; 278 *dev->sci_icmd = SCI_ICMD_DATA; 279 *dev->sci_dma_send = 0; 280 while (len > 64) { 281 wait = sci_data_wait; 282 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 283 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 284 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 285 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 286 || --wait < 0) { 287 #ifdef DEBUG 288 if (sci_debug) 289 printf("mlhdma_out fail: l%d i%x w%d\n", 290 len, csr, wait); 291 #endif 292 *dev->sci_mode &= ~SCI_MODE_DMA; 293 return 0; 294 } 295 } 296 297 #define W1 (*sci_dma = *buf++) 298 W1; W1; W1; W1; W1; W1; W1; W1; 299 W1; W1; W1; W1; W1; W1; W1; W1; 300 W1; W1; W1; W1; W1; W1; W1; W1; 301 W1; W1; W1; W1; W1; W1; W1; W1; 302 W1; W1; W1; W1; W1; W1; W1; W1; 303 W1; W1; W1; W1; W1; W1; W1; W1; 304 W1; W1; W1; W1; W1; W1; W1; W1; 305 W1; W1; W1; W1; W1; W1; W1; W1; 306 len -= 64; 307 } 308 while (len > 0) { 309 wait = sci_data_wait; 310 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 311 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 312 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 313 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 314 || --wait < 0) { 315 #ifdef DEBUG 316 if (sci_debug) 317 printf("mlhdma_out fail: l%d i%x w%d\n", 318 len, csr, wait); 319 #endif 320 *dev->sci_mode &= ~SCI_MODE_DMA; 321 return 0; 322 } 323 } 324 325 *sci_dma = *buf++; 326 len--; 327 } 328 329 wait = sci_data_wait; 330 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) == 331 SCI_CSR_PHASE_MATCH && --wait); 332 333 *dev->sci_mode &= ~SCI_MODE_DMA; 334 return 0; 335 } 336
Indexes created Fri Oct 03 02:09:57 GMT 2025