mlhsc.c revision 1.8
1 /* $NetBSD: mlhsc.c,v 1.8 1995/02/12 19:19:18 chopps Exp $ */ 2 3 /* 4 * Copyright (c) 1994 Michael L. Hitch 5 * Copyright (c) 1982, 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * @(#)dma.c 37 */ 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/device.h> 42 #include <scsi/scsi_all.h> 43 #include <scsi/scsiconf.h> 44 #include <amiga/amiga/device.h> 45 #include <amiga/amiga/isr.h> 46 #include <amiga/dev/scireg.h> 47 #include <amiga/dev/scivar.h> 48 #include <amiga/dev/zbusvar.h> 49 50 int mlhscprint __P((void *auxp, char *)); 51 void mlhscattach __P((struct device *, struct device *, void *)); 52 int mlhscmatch __P((struct device *, struct cfdata *, void *)); 53 54 int mlhsc_dma_xfer_in __P((struct sci_softc *dev, int len, 55 register u_char *buf, int phase)); 56 int mlhsc_dma_xfer_out __P((struct sci_softc *dev, int len, 57 register u_char *buf, int phase)); 58 59 struct scsi_adapter mlhsc_scsiswitch = { 60 sci_scsicmd, 61 sci_minphys, 62 0, /* no lun support */ 63 0, /* no lun support */ 64 }; 65 66 struct scsi_device mlhsc_scsidev = { 67 NULL, /* use default error handler */ 68 NULL, /* do not have a start functio */ 69 NULL, /* have no async handler */ 70 NULL, /* Use default done routine */ 71 }; 72 73 #define QPRINTF 74 75 #ifdef DEBUG 76 extern int sci_debug; 77 #endif 78 79 extern int sci_data_wait; 80 81 struct cfdriver mlhsccd = { 82 NULL, "mlhsc", (cfmatch_t)mlhscmatch, mlhscattach, 83 DV_DULL, sizeof(struct sci_softc), NULL, 0 }; 84 85 /* 86 * if we are my Hacker's SCSI board we are here. 87 */ 88 int 89 mlhscmatch(pdp, cdp, auxp) 90 struct device *pdp; 91 struct cfdata *cdp; 92 void *auxp; 93 { 94 struct zbus_args *zap; 95 96 zap = auxp; 97 98 /* 99 * Check manufacturer and product id. 100 */ 101 if (zap->manid == 2011 && zap->prodid == 1) 102 return(1); 103 else 104 return(0); 105 } 106 107 void 108 mlhscattach(pdp, dp, auxp) 109 struct device *pdp, *dp; 110 void *auxp; 111 { 112 volatile u_char *rp; 113 struct sci_softc *sc; 114 struct zbus_args *zap; 115 116 printf("\n"); 117 118 zap = auxp; 119 120 sc = (struct sci_softc *)dp; 121 rp = zap->va; 122 sc->sci_data = rp + 1; 123 sc->sci_odata = rp + 1; 124 sc->sci_icmd = rp + 3; 125 sc->sci_mode = rp + 5; 126 sc->sci_tcmd = rp + 7; 127 sc->sci_bus_csr = rp + 9; 128 sc->sci_sel_enb = rp + 9; 129 sc->sci_csr = rp + 11; 130 sc->sci_dma_send = rp + 11; 131 sc->sci_idata = rp + 13; 132 sc->sci_trecv = rp + 13; 133 sc->sci_iack = rp + 15; 134 sc->sci_irecv = rp + 15; 135 136 sc->dma_xfer_in = mlhsc_dma_xfer_in; 137 sc->dma_xfer_out = mlhsc_dma_xfer_out; 138 139 scireset(sc); 140 141 sc->sc_link.adapter_softc = sc; 142 sc->sc_link.adapter_target = 7; 143 sc->sc_link.adapter = &mlhsc_scsiswitch; 144 sc->sc_link.device = &mlhsc_scsidev; 145 sc->sc_link.openings = 1; 146 TAILQ_INIT(&sc->sc_xslist); 147 148 /* 149 * attach all scsi units on us 150 */ 151 config_found(dp, &sc->sc_link, mlhscprint); 152 } 153 154 /* 155 * print diag if pnp is NULL else just extra 156 */ 157 int 158 mlhscprint(auxp, pnp) 159 void *auxp; 160 char *pnp; 161 { 162 if (pnp == NULL) 163 return(UNCONF); 164 return(QUIET); 165 } 166 167 168 int 169 mlhsc_dma_xfer_in (dev, len, buf, phase) 170 struct sci_softc *dev; 171 int len; 172 register u_char *buf; 173 int phase; 174 { 175 int wait = sci_data_wait; 176 u_char csr; 177 u_char *obp = buf; 178 volatile register u_char *sci_dma = dev->sci_data + 16; 179 volatile register u_char *sci_csr = dev->sci_csr; 180 volatile register u_char *sci_icmd = dev->sci_icmd; 181 182 csr = *dev->sci_bus_csr; 183 184 QPRINTF(("mlhdma_in %d, csr=%02x\n", len, csr)); 185 186 *dev->sci_tcmd = phase; 187 *dev->sci_mode |= SCI_MODE_DMA; 188 *dev->sci_icmd = 0; 189 *dev->sci_irecv = 0; 190 while (len > 128) { 191 wait = sci_data_wait; 192 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 193 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 194 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 195 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 196 || --wait < 0) { 197 #ifdef DEBUG 198 if (sci_debug) 199 printf("mlhdma_in fail: l%d i%x w%d\n", 200 len, csr, wait); 201 #endif 202 *dev->sci_mode &= ~SCI_MODE_DMA; 203 return 0; 204 } 205 } 206 207 #define R1 (*buf++ = *sci_dma) 208 R1; R1; R1; R1; R1; R1; R1; R1; 209 R1; R1; R1; R1; R1; R1; R1; R1; 210 R1; R1; R1; R1; R1; R1; R1; R1; 211 R1; R1; R1; R1; R1; R1; R1; R1; 212 R1; R1; R1; R1; R1; R1; R1; R1; 213 R1; R1; R1; R1; R1; R1; R1; R1; 214 R1; R1; R1; R1; R1; R1; R1; R1; 215 R1; R1; R1; R1; R1; R1; R1; R1; 216 R1; R1; R1; R1; R1; R1; R1; R1; 217 R1; R1; R1; R1; R1; R1; R1; R1; 218 R1; R1; R1; R1; R1; R1; R1; R1; 219 R1; R1; R1; R1; R1; R1; R1; R1; 220 R1; R1; R1; R1; R1; R1; R1; R1; 221 R1; R1; R1; R1; R1; R1; R1; R1; 222 R1; R1; R1; R1; R1; R1; R1; R1; 223 R1; R1; R1; R1; R1; R1; R1; R1; 224 len -= 128; 225 } 226 while (len > 0) { 227 wait = sci_data_wait; 228 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 229 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 230 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 231 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 232 || --wait < 0) { 233 #ifdef DEBUG 234 if (sci_debug) 235 printf("mlhdma_in fail: l%d i%x w%d\n", 236 len, csr, wait); 237 #endif 238 *dev->sci_mode &= ~SCI_MODE_DMA; 239 return 0; 240 } 241 } 242 243 *buf++ = *sci_dma; 244 len--; 245 } 246 247 QPRINTF(("mlhdma_in {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", 248 len, obp[0], obp[1], obp[2], obp[3], obp[4], obp[5], 249 obp[6], obp[7], obp[8], obp[9])); 250 251 *dev->sci_mode &= ~SCI_MODE_DMA; 252 return 0; 253 } 254 255 int 256 mlhsc_dma_xfer_out (dev, len, buf, phase) 257 struct sci_softc *dev; 258 int len; 259 register u_char *buf; 260 int phase; 261 { 262 int wait = sci_data_wait; 263 u_char csr; 264 u_char *obp = buf; 265 volatile register u_char *sci_dma = dev->sci_data + 16; 266 volatile register u_char *sci_csr = dev->sci_csr; 267 volatile register u_char *sci_icmd = dev->sci_icmd; 268 269 csr = *dev->sci_bus_csr; 270 271 QPRINTF(("mlhdma_xfer %d, csr=%02x\n", len, csr)); 272 273 QPRINTF(("mlhgdma_out {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", 274 len, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], 275 buf[6], buf[7], buf[8], buf[9])); 276 277 *dev->sci_tcmd = phase; 278 *dev->sci_mode |= SCI_MODE_DMA; 279 *dev->sci_icmd = SCI_ICMD_DATA; 280 *dev->sci_dma_send = 0; 281 while (len > 64) { 282 wait = sci_data_wait; 283 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 284 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 285 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 286 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 287 || --wait < 0) { 288 #ifdef DEBUG 289 if (sci_debug) 290 printf("mlhdma_out fail: l%d i%x w%d\n", 291 len, csr, wait); 292 #endif 293 *dev->sci_mode &= ~SCI_MODE_DMA; 294 return 0; 295 } 296 } 297 298 #define W1 (*sci_dma = *buf++) 299 W1; W1; W1; W1; W1; W1; W1; W1; 300 W1; W1; W1; W1; W1; W1; W1; W1; 301 W1; W1; W1; W1; W1; W1; W1; W1; 302 W1; W1; W1; W1; W1; W1; W1; W1; 303 W1; W1; W1; W1; W1; W1; W1; W1; 304 W1; W1; W1; W1; W1; W1; W1; W1; 305 W1; W1; W1; W1; W1; W1; W1; W1; 306 W1; W1; W1; W1; W1; W1; W1; W1; 307 len -= 64; 308 } 309 while (len > 0) { 310 wait = sci_data_wait; 311 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 312 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 313 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 314 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 315 || --wait < 0) { 316 #ifdef DEBUG 317 if (sci_debug) 318 printf("mlhdma_out fail: l%d i%x w%d\n", 319 len, csr, wait); 320 #endif 321 *dev->sci_mode &= ~SCI_MODE_DMA; 322 return 0; 323 } 324 } 325 326 *sci_dma = *buf++; 327 len--; 328 } 329 330 wait = sci_data_wait; 331 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) == 332 SCI_CSR_PHASE_MATCH && --wait); 333 334 *dev->sci_mode &= ~SCI_MODE_DMA; 335 return 0; 336 } 337
Indexes created Fri Oct 03 02:09:57 GMT 2025