otgsc.c revision 1.11
1 /* $NetBSD: otgsc.c,v 1.11 1996/04/21 21:12:16 veego Exp $ */ 2 3 /* 4 * Copyright (c) 1994 Michael L. Hitch 5 * Copyright (c) 1982, 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * @(#)csa12gdma.c 37 */ 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/device.h> 42 #include <scsi/scsi_all.h> 43 #include <scsi/scsiconf.h> 44 #include <amiga/amiga/device.h> 45 #include <amiga/amiga/isr.h> 46 #include <amiga/dev/scireg.h> 47 #include <amiga/dev/scivar.h> 48 #include <amiga/dev/zbusvar.h> 49 50 int otgscprint __P((void *auxp, char *)); 51 void otgscattach __P((struct device *, struct device *, void *)); 52 int otgscmatch __P((struct device *, void *, void *)); 53 54 int otgsc_dma_xfer_in __P((struct sci_softc *dev, int len, 55 register u_char *buf, int phase)); 56 int otgsc_dma_xfer_out __P((struct sci_softc *dev, int len, 57 register u_char *buf, int phase)); 58 int otgsc_intr __P((void *)); 59 60 struct scsi_adapter otgsc_scsiswitch = { 61 sci_scsicmd, 62 sci_minphys, 63 0, /* no lun support */ 64 0, /* no lun support */ 65 }; 66 67 struct scsi_device otgsc_scsidev = { 68 NULL, /* use default error handler */ 69 NULL, /* do not have a start functio */ 70 NULL, /* have no async handler */ 71 NULL, /* Use default done routine */ 72 }; 73 74 75 #ifdef DEBUG 76 extern int sci_debug; 77 #define QPRINTF(a) if (sci_debug > 1) printf a 78 #else 79 #define QPRINTF(a) 80 #endif 81 82 extern int sci_data_wait; 83 84 struct cfattach otgsc_ca = { 85 sizeof(struct sci_softc), otgscmatch, otgscattach 86 }; 87 88 struct cfdriver otgsc_cd = { 89 NULL, "otgsc", DV_DULL, NULL, 0 90 }; 91 92 /* 93 * if we are my Hacker's SCSI board we are here. 94 */ 95 int 96 otgscmatch(pdp, match, auxp) 97 struct device *pdp; 98 void *match, *auxp; 99 { 100 struct zbus_args *zap; 101 102 zap = auxp; 103 104 /* 105 * Check manufacturer and product id. 106 */ 107 if (zap->manid == 1058 && zap->prodid == 21) 108 return(1); 109 else 110 return(0); 111 } 112 113 void 114 otgscattach(pdp, dp, auxp) 115 struct device *pdp, *dp; 116 void *auxp; 117 { 118 volatile u_char *rp; 119 struct sci_softc *sc; 120 struct zbus_args *zap; 121 122 printf("\n"); 123 124 zap = auxp; 125 126 sc = (struct sci_softc *)dp; 127 rp = zap->va + 0x2000; 128 sc->sci_data = rp; 129 sc->sci_odata = rp; 130 sc->sci_icmd = rp + 0x10; 131 sc->sci_mode = rp + 0x20; 132 sc->sci_tcmd = rp + 0x30; 133 sc->sci_bus_csr = rp + 0x40; 134 sc->sci_sel_enb = rp + 0x40; 135 sc->sci_csr = rp + 0x50; 136 sc->sci_dma_send = rp + 0x50; 137 sc->sci_idata = rp + 0x60; 138 sc->sci_trecv = rp + 0x60; 139 sc->sci_iack = rp + 0x70; 140 sc->sci_irecv = rp + 0x70; 141 142 sc->dma_xfer_in = otgsc_dma_xfer_in; 143 sc->dma_xfer_out = otgsc_dma_xfer_out; 144 145 sc->sc_isr.isr_intr = otgsc_intr; 146 sc->sc_isr.isr_arg = sc; 147 sc->sc_isr.isr_ipl = 2; 148 add_isr(&sc->sc_isr); 149 150 scireset(sc); 151 152 sc->sc_link.adapter_softc = sc; 153 sc->sc_link.adapter_target = 7; 154 sc->sc_link.adapter = &otgsc_scsiswitch; 155 sc->sc_link.device = &otgsc_scsidev; 156 sc->sc_link.openings = 1; 157 TAILQ_INIT(&sc->sc_xslist); 158 159 /* 160 * attach all scsi units on us 161 */ 162 config_found(dp, &sc->sc_link, otgscprint); 163 } 164 165 /* 166 * print diag if pnp is NULL else just extra 167 */ 168 int 169 otgscprint(auxp, pnp) 170 void *auxp; 171 char *pnp; 172 { 173 if (pnp == NULL) 174 return(UNCONF); 175 return(QUIET); 176 } 177 178 179 int 180 otgsc_dma_xfer_in (dev, len, buf, phase) 181 struct sci_softc *dev; 182 int len; 183 register u_char *buf; 184 int phase; 185 { 186 int wait = sci_data_wait; 187 volatile register u_char *sci_dma = dev->sci_data + 0x100; 188 volatile register u_char *sci_csr = dev->sci_csr; 189 #ifdef DEBUG 190 u_char *obp = buf; 191 #endif 192 193 QPRINTF(("otgsc_dma_in %d, csr=%02x\n", len, *dev->sci_bus_csr)); 194 195 *dev->sci_tcmd = phase; 196 *dev->sci_mode |= SCI_MODE_DMA; 197 *dev->sci_icmd = 0; 198 *dev->sci_irecv = 0; 199 while (len > 0) { 200 wait = sci_data_wait; 201 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 202 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 203 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 204 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 205 || --wait < 0) { 206 #ifdef DEBUG 207 if (sci_debug) 208 printf("otgsc_dma_in fail: l%d i%x w%d\n", 209 len, *dev->sci_bus_csr, wait); 210 #endif 211 *dev->sci_mode &= ~SCI_MODE_DMA; 212 return 0; 213 } 214 } 215 216 *buf++ = *sci_dma; 217 len--; 218 } 219 220 QPRINTF(("otgsc_dma_in {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", 221 len, obp[0], obp[1], obp[2], obp[3], obp[4], obp[5], 222 obp[6], obp[7], obp[8], obp[9])); 223 224 *dev->sci_mode &= ~SCI_MODE_DMA; 225 return 0; 226 } 227 228 int 229 otgsc_dma_xfer_out (dev, len, buf, phase) 230 struct sci_softc *dev; 231 int len; 232 register u_char *buf; 233 int phase; 234 { 235 int wait = sci_data_wait; 236 volatile register u_char *sci_dma = dev->sci_data + 0x100; 237 volatile register u_char *sci_csr = dev->sci_csr; 238 239 QPRINTF(("otgsc_dma_out %d, csr=%02x\n", len, *dev->sci_bus_csr)); 240 241 QPRINTF(("otgsc_dma_out {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", 242 len, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], 243 buf[6], buf[7], buf[8], buf[9])); 244 245 *dev->sci_tcmd = phase; 246 *dev->sci_mode |= SCI_MODE_DMA; 247 *dev->sci_icmd = SCI_ICMD_DATA; 248 *dev->sci_dma_send = 0; 249 while (len > 0) { 250 wait = sci_data_wait; 251 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 252 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 253 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 254 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 255 || --wait < 0) { 256 #ifdef DEBUG 257 if (sci_debug) 258 printf("otgsc_dma_out fail: l%d i%x w%d\n", 259 len, *dev->sci_bus_csr, wait); 260 #endif 261 *dev->sci_mode &= ~SCI_MODE_DMA; 262 return 0; 263 } 264 } 265 266 *sci_dma = *buf++; 267 len--; 268 } 269 270 wait = sci_data_wait; 271 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) == 272 SCI_CSR_PHASE_MATCH && --wait); 273 274 275 *dev->sci_mode &= ~SCI_MODE_DMA; 276 return 0; 277 } 278 279 int 280 otgsc_intr(arg) 281 void *arg; 282 { 283 struct sci_softc *dev = arg; 284 u_char stat; 285 286 if ((*dev->sci_csr & SCI_CSR_INT) == 0) 287 return (1); 288 stat = *dev->sci_iack; 289 *dev->sci_mode = 0; 290 return (1); 291 } 292
Indexes created Wed Sep 24 15:09:51 GMT 2025