otgsc.c revision 1.16
1 /* $NetBSD: otgsc.c,v 1.16 1996/12/10 21:27:27 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1994 Michael L. Hitch 5 * Copyright (c) 1982, 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * @(#)csa12gdma.c 37 */ 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/device.h> 42 #include <scsi/scsi_all.h> 43 #include <scsi/scsiconf.h> 44 #include <amiga/amiga/device.h> 45 #include <amiga/amiga/isr.h> 46 #include <amiga/dev/scireg.h> 47 #include <amiga/dev/scivar.h> 48 #include <amiga/dev/zbusvar.h> 49 50 void otgscattach __P((struct device *, struct device *, void *)); 51 int otgscmatch __P((struct device *, void *, void *)); 52 53 int otgsc_dma_xfer_in __P((struct sci_softc *dev, int len, 54 register u_char *buf, int phase)); 55 int otgsc_dma_xfer_out __P((struct sci_softc *dev, int len, 56 register u_char *buf, int phase)); 57 int otgsc_intr __P((void *)); 58 59 struct scsi_adapter otgsc_scsiswitch = { 60 sci_scsicmd, 61 sci_minphys, 62 0, /* no lun support */ 63 0, /* no lun support */ 64 }; 65 66 struct scsi_device otgsc_scsidev = { 67 NULL, /* use default error handler */ 68 NULL, /* do not have a start functio */ 69 NULL, /* have no async handler */ 70 NULL, /* Use default done routine */ 71 }; 72 73 74 #ifdef DEBUG 75 extern int sci_debug; 76 #define QPRINTF(a) if (sci_debug > 1) printf a 77 #else 78 #define QPRINTF(a) 79 #endif 80 81 extern int sci_data_wait; 82 83 struct cfattach otgsc_ca = { 84 sizeof(struct sci_softc), otgscmatch, otgscattach 85 }; 86 87 struct cfdriver otgsc_cd = { 88 NULL, "otgsc", DV_DULL, NULL, 0 89 }; 90 91 /* 92 * if we are my Hacker's SCSI board we are here. 93 */ 94 int 95 otgscmatch(pdp, match, auxp) 96 struct device *pdp; 97 void *match, *auxp; 98 { 99 struct zbus_args *zap; 100 101 zap = auxp; 102 103 /* 104 * Check manufacturer and product id. 105 */ 106 if (zap->manid == 1058 && zap->prodid == 21) 107 return(1); 108 else 109 return(0); 110 } 111 112 void 113 otgscattach(pdp, dp, auxp) 114 struct device *pdp, *dp; 115 void *auxp; 116 { 117 volatile u_char *rp; 118 struct sci_softc *sc; 119 struct zbus_args *zap; 120 121 printf("\n"); 122 123 zap = auxp; 124 125 sc = (struct sci_softc *)dp; 126 rp = zap->va + 0x2000; 127 sc->sci_data = rp; 128 sc->sci_odata = rp; 129 sc->sci_icmd = rp + 0x10; 130 sc->sci_mode = rp + 0x20; 131 sc->sci_tcmd = rp + 0x30; 132 sc->sci_bus_csr = rp + 0x40; 133 sc->sci_sel_enb = rp + 0x40; 134 sc->sci_csr = rp + 0x50; 135 sc->sci_dma_send = rp + 0x50; 136 sc->sci_idata = rp + 0x60; 137 sc->sci_trecv = rp + 0x60; 138 sc->sci_iack = rp + 0x70; 139 sc->sci_irecv = rp + 0x70; 140 141 sc->dma_xfer_in = otgsc_dma_xfer_in; 142 sc->dma_xfer_out = otgsc_dma_xfer_out; 143 144 sc->sc_isr.isr_intr = otgsc_intr; 145 sc->sc_isr.isr_arg = sc; 146 sc->sc_isr.isr_ipl = 2; 147 add_isr(&sc->sc_isr); 148 149 scireset(sc); 150 151 sc->sc_link.channel = SCSI_CHANNEL_ONLY_ONE; 152 sc->sc_link.adapter_softc = sc; 153 sc->sc_link.adapter_target = 7; 154 sc->sc_link.adapter = &otgsc_scsiswitch; 155 sc->sc_link.device = &otgsc_scsidev; 156 sc->sc_link.openings = 1; 157 sc->sc_link.max_target = 7; 158 TAILQ_INIT(&sc->sc_xslist); 159 160 /* 161 * attach all scsi units on us 162 */ 163 config_found(dp, &sc->sc_link, scsiprint); 164 } 165 166 int 167 otgsc_dma_xfer_in (dev, len, buf, phase) 168 struct sci_softc *dev; 169 int len; 170 register u_char *buf; 171 int phase; 172 { 173 int wait = sci_data_wait; 174 volatile register u_char *sci_dma = dev->sci_data + 0x100; 175 volatile register u_char *sci_csr = dev->sci_csr; 176 #ifdef DEBUG 177 u_char *obp = buf; 178 #endif 179 180 QPRINTF(("otgsc_dma_in %d, csr=%02x\n", len, *dev->sci_bus_csr)); 181 182 *dev->sci_tcmd = phase; 183 *dev->sci_mode |= SCI_MODE_DMA; 184 *dev->sci_icmd = 0; 185 *dev->sci_irecv = 0; 186 while (len > 0) { 187 wait = sci_data_wait; 188 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 189 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 190 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 191 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 192 || --wait < 0) { 193 #ifdef DEBUG 194 if (sci_debug) 195 printf("otgsc_dma_in fail: l%d i%x w%d\n", 196 len, *dev->sci_bus_csr, wait); 197 #endif 198 *dev->sci_mode &= ~SCI_MODE_DMA; 199 return 0; 200 } 201 } 202 203 *buf++ = *sci_dma; 204 len--; 205 } 206 207 QPRINTF(("otgsc_dma_in {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", 208 len, obp[0], obp[1], obp[2], obp[3], obp[4], obp[5], 209 obp[6], obp[7], obp[8], obp[9])); 210 211 *dev->sci_mode &= ~SCI_MODE_DMA; 212 return 0; 213 } 214 215 int 216 otgsc_dma_xfer_out (dev, len, buf, phase) 217 struct sci_softc *dev; 218 int len; 219 register u_char *buf; 220 int phase; 221 { 222 int wait = sci_data_wait; 223 volatile register u_char *sci_dma = dev->sci_data + 0x100; 224 volatile register u_char *sci_csr = dev->sci_csr; 225 226 QPRINTF(("otgsc_dma_out %d, csr=%02x\n", len, *dev->sci_bus_csr)); 227 228 QPRINTF(("otgsc_dma_out {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", 229 len, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], 230 buf[6], buf[7], buf[8], buf[9])); 231 232 *dev->sci_tcmd = phase; 233 *dev->sci_mode |= SCI_MODE_DMA; 234 *dev->sci_icmd = SCI_ICMD_DATA; 235 *dev->sci_dma_send = 0; 236 while (len > 0) { 237 wait = sci_data_wait; 238 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 239 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 240 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 241 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 242 || --wait < 0) { 243 #ifdef DEBUG 244 if (sci_debug) 245 printf("otgsc_dma_out fail: l%d i%x w%d\n", 246 len, *dev->sci_bus_csr, wait); 247 #endif 248 *dev->sci_mode &= ~SCI_MODE_DMA; 249 return 0; 250 } 251 } 252 253 *sci_dma = *buf++; 254 len--; 255 } 256 257 wait = sci_data_wait; 258 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) == 259 SCI_CSR_PHASE_MATCH && --wait); 260 261 262 *dev->sci_mode &= ~SCI_MODE_DMA; 263 return 0; 264 } 265 266 int 267 otgsc_intr(arg) 268 void *arg; 269 { 270 struct sci_softc *dev = arg; 271 u_char stat; 272 273 if ((*dev->sci_csr & SCI_CSR_INT) == 0) 274 return (1); 275 stat = *dev->sci_iack; 276 *dev->sci_mode = 0; 277 return (1); 278 } 279
Indexes created Thu Sep 25 16:09:42 GMT 2025