otgsc.c revision 1.18
1 /* $NetBSD: otgsc.c,v 1.18 1997/08/27 11:23:13 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1994 Michael L. Hitch 5 * Copyright (c) 1982, 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * @(#)csa12gdma.c 37 */ 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/device.h> 42 #include <dev/scsipi/scsi_all.h> 43 #include <dev/scsipi/scsipi_all.h> 44 #include <dev/scsipi/scsiconf.h> 45 #include <amiga/amiga/device.h> 46 #include <amiga/amiga/isr.h> 47 #include <amiga/dev/scireg.h> 48 #include <amiga/dev/scivar.h> 49 #include <amiga/dev/zbusvar.h> 50 51 void otgscattach __P((struct device *, struct device *, void *)); 52 int otgscmatch __P((struct device *, struct cfdata *, void *)); 53 54 int otgsc_dma_xfer_in __P((struct sci_softc *dev, int len, 55 register u_char *buf, int phase)); 56 int otgsc_dma_xfer_out __P((struct sci_softc *dev, int len, 57 register u_char *buf, int phase)); 58 int otgsc_intr __P((void *)); 59 60 struct scsipi_adapter otgsc_scsiswitch = { 61 sci_scsicmd, 62 sci_minphys, 63 0, /* no lun support */ 64 0, /* no lun support */ 65 }; 66 67 struct scsipi_device otgsc_scsidev = { 68 NULL, /* use default error handler */ 69 NULL, /* do not have a start functio */ 70 NULL, /* have no async handler */ 71 NULL, /* Use default done routine */ 72 }; 73 74 75 #ifdef DEBUG 76 extern int sci_debug; 77 #define QPRINTF(a) if (sci_debug > 1) printf a 78 #else 79 #define QPRINTF(a) 80 #endif 81 82 extern int sci_data_wait; 83 84 struct cfattach otgsc_ca = { 85 sizeof(struct sci_softc), otgscmatch, otgscattach 86 }; 87 88 struct cfdriver otgsc_cd = { 89 NULL, "otgsc", DV_DULL, NULL, 0 90 }; 91 92 /* 93 * if we are my Hacker's SCSI board we are here. 94 */ 95 int 96 otgscmatch(pdp, cfp, auxp) 97 struct device *pdp; 98 struct cfdata *cfp; 99 void *auxp; 100 { 101 struct zbus_args *zap; 102 103 zap = auxp; 104 105 /* 106 * Check manufacturer and product id. 107 */ 108 if (zap->manid == 1058 && zap->prodid == 21) 109 return(1); 110 else 111 return(0); 112 } 113 114 void 115 otgscattach(pdp, dp, auxp) 116 struct device *pdp, *dp; 117 void *auxp; 118 { 119 volatile u_char *rp; 120 struct sci_softc *sc; 121 struct zbus_args *zap; 122 123 printf("\n"); 124 125 zap = auxp; 126 127 sc = (struct sci_softc *)dp; 128 rp = zap->va + 0x2000; 129 sc->sci_data = rp; 130 sc->sci_odata = rp; 131 sc->sci_icmd = rp + 0x10; 132 sc->sci_mode = rp + 0x20; 133 sc->sci_tcmd = rp + 0x30; 134 sc->sci_bus_csr = rp + 0x40; 135 sc->sci_sel_enb = rp + 0x40; 136 sc->sci_csr = rp + 0x50; 137 sc->sci_dma_send = rp + 0x50; 138 sc->sci_idata = rp + 0x60; 139 sc->sci_trecv = rp + 0x60; 140 sc->sci_iack = rp + 0x70; 141 sc->sci_irecv = rp + 0x70; 142 143 sc->dma_xfer_in = otgsc_dma_xfer_in; 144 sc->dma_xfer_out = otgsc_dma_xfer_out; 145 146 sc->sc_isr.isr_intr = otgsc_intr; 147 sc->sc_isr.isr_arg = sc; 148 sc->sc_isr.isr_ipl = 2; 149 add_isr(&sc->sc_isr); 150 151 scireset(sc); 152 153 sc->sc_link.scsipi_scsi.channel = SCSI_CHANNEL_ONLY_ONE; 154 sc->sc_link.adapter_softc = sc; 155 sc->sc_link.scsipi_scsi.adapter_target = 7; 156 sc->sc_link.adapter = &otgsc_scsiswitch; 157 sc->sc_link.device = &otgsc_scsidev; 158 sc->sc_link.openings = 1; 159 sc->sc_link.scsipi_scsi.max_target = 7; 160 sc->sc_link.type = BUS_SCSI; 161 TAILQ_INIT(&sc->sc_xslist); 162 163 /* 164 * attach all scsi units on us 165 */ 166 config_found(dp, &sc->sc_link, scsiprint); 167 } 168 169 int 170 otgsc_dma_xfer_in (dev, len, buf, phase) 171 struct sci_softc *dev; 172 int len; 173 register u_char *buf; 174 int phase; 175 { 176 int wait = sci_data_wait; 177 volatile register u_char *sci_dma = dev->sci_data + 0x100; 178 volatile register u_char *sci_csr = dev->sci_csr; 179 #ifdef DEBUG 180 u_char *obp = buf; 181 #endif 182 183 QPRINTF(("otgsc_dma_in %d, csr=%02x\n", len, *dev->sci_bus_csr)); 184 185 *dev->sci_tcmd = phase; 186 *dev->sci_mode |= SCI_MODE_DMA; 187 *dev->sci_icmd = 0; 188 *dev->sci_irecv = 0; 189 while (len > 0) { 190 wait = sci_data_wait; 191 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 192 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 193 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 194 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 195 || --wait < 0) { 196 #ifdef DEBUG 197 if (sci_debug) 198 printf("otgsc_dma_in fail: l%d i%x w%d\n", 199 len, *dev->sci_bus_csr, wait); 200 #endif 201 *dev->sci_mode &= ~SCI_MODE_DMA; 202 return 0; 203 } 204 } 205 206 *buf++ = *sci_dma; 207 len--; 208 } 209 210 QPRINTF(("otgsc_dma_in {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", 211 len, obp[0], obp[1], obp[2], obp[3], obp[4], obp[5], 212 obp[6], obp[7], obp[8], obp[9])); 213 214 *dev->sci_mode &= ~SCI_MODE_DMA; 215 return 0; 216 } 217 218 int 219 otgsc_dma_xfer_out (dev, len, buf, phase) 220 struct sci_softc *dev; 221 int len; 222 register u_char *buf; 223 int phase; 224 { 225 int wait = sci_data_wait; 226 volatile register u_char *sci_dma = dev->sci_data + 0x100; 227 volatile register u_char *sci_csr = dev->sci_csr; 228 229 QPRINTF(("otgsc_dma_out %d, csr=%02x\n", len, *dev->sci_bus_csr)); 230 231 QPRINTF(("otgsc_dma_out {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", 232 len, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], 233 buf[6], buf[7], buf[8], buf[9])); 234 235 *dev->sci_tcmd = phase; 236 *dev->sci_mode |= SCI_MODE_DMA; 237 *dev->sci_icmd = SCI_ICMD_DATA; 238 *dev->sci_dma_send = 0; 239 while (len > 0) { 240 wait = sci_data_wait; 241 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 242 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 243 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 244 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 245 || --wait < 0) { 246 #ifdef DEBUG 247 if (sci_debug) 248 printf("otgsc_dma_out fail: l%d i%x w%d\n", 249 len, *dev->sci_bus_csr, wait); 250 #endif 251 *dev->sci_mode &= ~SCI_MODE_DMA; 252 return 0; 253 } 254 } 255 256 *sci_dma = *buf++; 257 len--; 258 } 259 260 wait = sci_data_wait; 261 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) == 262 SCI_CSR_PHASE_MATCH && --wait); 263 264 265 *dev->sci_mode &= ~SCI_MODE_DMA; 266 return 0; 267 } 268 269 int 270 otgsc_intr(arg) 271 void *arg; 272 { 273 struct sci_softc *dev = arg; 274 u_char stat; 275 276 if ((*dev->sci_csr & SCI_CSR_INT) == 0) 277 return (1); 278 stat = *dev->sci_iack; 279 *dev->sci_mode = 0; 280 return (1); 281 } 282
Indexes created Thu Sep 25 16:09:42 GMT 2025