otgsc.c revision 1.20
1 /* $NetBSD: otgsc.c,v 1.20 1998/10/10 00:28:37 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1994 Michael L. Hitch 5 * Copyright (c) 1982, 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * @(#)csa12gdma.c 37 */ 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/device.h> 42 #include <dev/scsipi/scsi_all.h> 43 #include <dev/scsipi/scsipi_all.h> 44 #include <dev/scsipi/scsiconf.h> 45 #include <amiga/amiga/device.h> 46 #include <amiga/amiga/isr.h> 47 #include <amiga/dev/scireg.h> 48 #include <amiga/dev/scivar.h> 49 #include <amiga/dev/zbusvar.h> 50 51 void otgscattach __P((struct device *, struct device *, void *)); 52 int otgscmatch __P((struct device *, struct cfdata *, void *)); 53 54 int otgsc_dma_xfer_in __P((struct sci_softc *dev, int len, 55 register u_char *buf, int phase)); 56 int otgsc_dma_xfer_out __P((struct sci_softc *dev, int len, 57 register u_char *buf, int phase)); 58 int otgsc_intr __P((void *)); 59 60 struct scsipi_adapter otgsc_scsiswitch = { 61 sci_scsicmd, 62 sci_minphys, 63 NULL, /* scsipi_ioctl */ 64 }; 65 66 struct scsipi_device otgsc_scsidev = { 67 NULL, /* use default error handler */ 68 NULL, /* do not have a start functio */ 69 NULL, /* have no async handler */ 70 NULL, /* Use default done routine */ 71 }; 72 73 74 #ifdef DEBUG 75 extern int sci_debug; 76 #define QPRINTF(a) if (sci_debug > 1) printf a 77 #else 78 #define QPRINTF(a) 79 #endif 80 81 extern int sci_data_wait; 82 83 struct cfattach otgsc_ca = { 84 sizeof(struct sci_softc), otgscmatch, otgscattach 85 }; 86 87 /* 88 * if we are my Hacker's SCSI board we are here. 89 */ 90 int 91 otgscmatch(pdp, cfp, auxp) 92 struct device *pdp; 93 struct cfdata *cfp; 94 void *auxp; 95 { 96 struct zbus_args *zap; 97 98 zap = auxp; 99 100 /* 101 * Check manufacturer and product id. 102 */ 103 if (zap->manid == 1058 && zap->prodid == 21) 104 return(1); 105 else 106 return(0); 107 } 108 109 void 110 otgscattach(pdp, dp, auxp) 111 struct device *pdp, *dp; 112 void *auxp; 113 { 114 volatile u_char *rp; 115 struct sci_softc *sc; 116 struct zbus_args *zap; 117 118 printf("\n"); 119 120 zap = auxp; 121 122 sc = (struct sci_softc *)dp; 123 rp = zap->va + 0x2000; 124 sc->sci_data = rp; 125 sc->sci_odata = rp; 126 sc->sci_icmd = rp + 0x10; 127 sc->sci_mode = rp + 0x20; 128 sc->sci_tcmd = rp + 0x30; 129 sc->sci_bus_csr = rp + 0x40; 130 sc->sci_sel_enb = rp + 0x40; 131 sc->sci_csr = rp + 0x50; 132 sc->sci_dma_send = rp + 0x50; 133 sc->sci_idata = rp + 0x60; 134 sc->sci_trecv = rp + 0x60; 135 sc->sci_iack = rp + 0x70; 136 sc->sci_irecv = rp + 0x70; 137 138 sc->dma_xfer_in = otgsc_dma_xfer_in; 139 sc->dma_xfer_out = otgsc_dma_xfer_out; 140 141 sc->sc_isr.isr_intr = otgsc_intr; 142 sc->sc_isr.isr_arg = sc; 143 sc->sc_isr.isr_ipl = 2; 144 add_isr(&sc->sc_isr); 145 146 scireset(sc); 147 148 sc->sc_link.scsipi_scsi.channel = SCSI_CHANNEL_ONLY_ONE; 149 sc->sc_link.adapter_softc = sc; 150 sc->sc_link.scsipi_scsi.adapter_target = 7; 151 sc->sc_link.adapter = &otgsc_scsiswitch; 152 sc->sc_link.device = &otgsc_scsidev; 153 sc->sc_link.openings = 1; 154 sc->sc_link.scsipi_scsi.max_target = 7; 155 sc->sc_link.type = BUS_SCSI; 156 TAILQ_INIT(&sc->sc_xslist); 157 158 /* 159 * attach all scsi units on us 160 */ 161 config_found(dp, &sc->sc_link, scsiprint); 162 } 163 164 int 165 otgsc_dma_xfer_in (dev, len, buf, phase) 166 struct sci_softc *dev; 167 int len; 168 register u_char *buf; 169 int phase; 170 { 171 int wait = sci_data_wait; 172 volatile register u_char *sci_dma = dev->sci_data + 0x100; 173 volatile register u_char *sci_csr = dev->sci_csr; 174 #ifdef DEBUG 175 u_char *obp = buf; 176 #endif 177 178 QPRINTF(("otgsc_dma_in %d, csr=%02x\n", len, *dev->sci_bus_csr)); 179 180 *dev->sci_tcmd = phase; 181 *dev->sci_mode |= SCI_MODE_DMA; 182 *dev->sci_icmd = 0; 183 *dev->sci_irecv = 0; 184 while (len > 0) { 185 wait = sci_data_wait; 186 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 187 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 188 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 189 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 190 || --wait < 0) { 191 #ifdef DEBUG 192 if (sci_debug) 193 printf("otgsc_dma_in fail: l%d i%x w%d\n", 194 len, *dev->sci_bus_csr, wait); 195 #endif 196 *dev->sci_mode &= ~SCI_MODE_DMA; 197 return 0; 198 } 199 } 200 201 *buf++ = *sci_dma; 202 len--; 203 } 204 205 QPRINTF(("otgsc_dma_in {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", 206 len, obp[0], obp[1], obp[2], obp[3], obp[4], obp[5], 207 obp[6], obp[7], obp[8], obp[9])); 208 209 *dev->sci_mode &= ~SCI_MODE_DMA; 210 return 0; 211 } 212 213 int 214 otgsc_dma_xfer_out (dev, len, buf, phase) 215 struct sci_softc *dev; 216 int len; 217 register u_char *buf; 218 int phase; 219 { 220 int wait = sci_data_wait; 221 volatile register u_char *sci_dma = dev->sci_data + 0x100; 222 volatile register u_char *sci_csr = dev->sci_csr; 223 224 QPRINTF(("otgsc_dma_out %d, csr=%02x\n", len, *dev->sci_bus_csr)); 225 226 QPRINTF(("otgsc_dma_out {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", 227 len, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], 228 buf[6], buf[7], buf[8], buf[9])); 229 230 *dev->sci_tcmd = phase; 231 *dev->sci_mode |= SCI_MODE_DMA; 232 *dev->sci_icmd = SCI_ICMD_DATA; 233 *dev->sci_dma_send = 0; 234 while (len > 0) { 235 wait = sci_data_wait; 236 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 237 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 238 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 239 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 240 || --wait < 0) { 241 #ifdef DEBUG 242 if (sci_debug) 243 printf("otgsc_dma_out fail: l%d i%x w%d\n", 244 len, *dev->sci_bus_csr, wait); 245 #endif 246 *dev->sci_mode &= ~SCI_MODE_DMA; 247 return 0; 248 } 249 } 250 251 *sci_dma = *buf++; 252 len--; 253 } 254 255 wait = sci_data_wait; 256 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) == 257 SCI_CSR_PHASE_MATCH && --wait); 258 259 260 *dev->sci_mode &= ~SCI_MODE_DMA; 261 return 0; 262 } 263 264 int 265 otgsc_intr(arg) 266 void *arg; 267 { 268 struct sci_softc *dev = arg; 269 u_char stat; 270 271 if ((*dev->sci_csr & SCI_CSR_INT) == 0) 272 return (1); 273 stat = *dev->sci_iack; 274 *dev->sci_mode = 0; 275 return (1); 276 } 277
Indexes created Fri Oct 03 02:09:57 GMT 2025