otgsc.c revision 1.22
1 /* $NetBSD: otgsc.c,v 1.22 1998/12/05 19:43:38 mjacob Exp $ */ 2 3 /* 4 * Copyright (c) 1994 Michael L. Hitch 5 * Copyright (c) 1982, 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * @(#)csa12gdma.c 37 */ 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/device.h> 42 #include <dev/scsipi/scsi_all.h> 43 #include <dev/scsipi/scsipi_all.h> 44 #include <dev/scsipi/scsiconf.h> 45 #include <amiga/amiga/device.h> 46 #include <amiga/amiga/isr.h> 47 #include <amiga/dev/scireg.h> 48 #include <amiga/dev/scivar.h> 49 #include <amiga/dev/zbusvar.h> 50 51 void otgscattach __P((struct device *, struct device *, void *)); 52 int otgscmatch __P((struct device *, struct cfdata *, void *)); 53 54 int otgsc_dma_xfer_in __P((struct sci_softc *dev, int len, 55 register u_char *buf, int phase)); 56 int otgsc_dma_xfer_out __P((struct sci_softc *dev, int len, 57 register u_char *buf, int phase)); 58 int otgsc_intr __P((void *)); 59 60 struct scsipi_device otgsc_scsidev = { 61 NULL, /* use default error handler */ 62 NULL, /* do not have a start functio */ 63 NULL, /* have no async handler */ 64 NULL, /* Use default done routine */ 65 }; 66 67 68 #ifdef DEBUG 69 extern int sci_debug; 70 #define QPRINTF(a) if (sci_debug > 1) printf a 71 #else 72 #define QPRINTF(a) 73 #endif 74 75 extern int sci_data_wait; 76 77 struct cfattach otgsc_ca = { 78 sizeof(struct sci_softc), otgscmatch, otgscattach 79 }; 80 81 /* 82 * if we are my Hacker's SCSI board we are here. 83 */ 84 int 85 otgscmatch(pdp, cfp, auxp) 86 struct device *pdp; 87 struct cfdata *cfp; 88 void *auxp; 89 { 90 struct zbus_args *zap; 91 92 zap = auxp; 93 94 /* 95 * Check manufacturer and product id. 96 */ 97 if (zap->manid == 1058 && zap->prodid == 21) 98 return(1); 99 else 100 return(0); 101 } 102 103 void 104 otgscattach(pdp, dp, auxp) 105 struct device *pdp, *dp; 106 void *auxp; 107 { 108 volatile u_char *rp; 109 struct sci_softc *sc; 110 struct zbus_args *zap; 111 112 printf("\n"); 113 114 zap = auxp; 115 116 sc = (struct sci_softc *)dp; 117 rp = zap->va + 0x2000; 118 sc->sci_data = rp; 119 sc->sci_odata = rp; 120 sc->sci_icmd = rp + 0x10; 121 sc->sci_mode = rp + 0x20; 122 sc->sci_tcmd = rp + 0x30; 123 sc->sci_bus_csr = rp + 0x40; 124 sc->sci_sel_enb = rp + 0x40; 125 sc->sci_csr = rp + 0x50; 126 sc->sci_dma_send = rp + 0x50; 127 sc->sci_idata = rp + 0x60; 128 sc->sci_trecv = rp + 0x60; 129 sc->sci_iack = rp + 0x70; 130 sc->sci_irecv = rp + 0x70; 131 132 sc->dma_xfer_in = otgsc_dma_xfer_in; 133 sc->dma_xfer_out = otgsc_dma_xfer_out; 134 135 sc->sc_isr.isr_intr = otgsc_intr; 136 sc->sc_isr.isr_arg = sc; 137 sc->sc_isr.isr_ipl = 2; 138 add_isr(&sc->sc_isr); 139 140 scireset(sc); 141 142 sc->sc_adapter.scsipi_cmd = sci_scsicmd; 143 sc->sc_adapter.scsipi_minphys = sci_minphys; 144 145 sc->sc_link.scsipi_scsi.channel = SCSI_CHANNEL_ONLY_ONE; 146 sc->sc_link.adapter_softc = sc; 147 sc->sc_link.scsipi_scsi.adapter_target = 7; 148 sc->sc_link.adapter = &sc->sc_adapter; 149 sc->sc_link.device = &otgsc_scsidev; 150 sc->sc_link.openings = 1; 151 sc->sc_link.scsipi_scsi.max_target = 7; 152 sc->sc_link.scsipi_scsi.max_lun = 7; 153 sc->sc_link.type = BUS_SCSI; 154 TAILQ_INIT(&sc->sc_xslist); 155 156 /* 157 * attach all scsi units on us 158 */ 159 config_found(dp, &sc->sc_link, scsiprint); 160 } 161 162 int 163 otgsc_dma_xfer_in (dev, len, buf, phase) 164 struct sci_softc *dev; 165 int len; 166 register u_char *buf; 167 int phase; 168 { 169 int wait = sci_data_wait; 170 volatile register u_char *sci_dma = dev->sci_data + 0x100; 171 volatile register u_char *sci_csr = dev->sci_csr; 172 #ifdef DEBUG 173 u_char *obp = buf; 174 #endif 175 176 QPRINTF(("otgsc_dma_in %d, csr=%02x\n", len, *dev->sci_bus_csr)); 177 178 *dev->sci_tcmd = phase; 179 *dev->sci_mode |= SCI_MODE_DMA; 180 *dev->sci_icmd = 0; 181 *dev->sci_irecv = 0; 182 while (len > 0) { 183 wait = sci_data_wait; 184 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 185 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 186 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 187 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 188 || --wait < 0) { 189 #ifdef DEBUG 190 if (sci_debug) 191 printf("otgsc_dma_in fail: l%d i%x w%d\n", 192 len, *dev->sci_bus_csr, wait); 193 #endif 194 *dev->sci_mode &= ~SCI_MODE_DMA; 195 return 0; 196 } 197 } 198 199 *buf++ = *sci_dma; 200 len--; 201 } 202 203 QPRINTF(("otgsc_dma_in {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", 204 len, obp[0], obp[1], obp[2], obp[3], obp[4], obp[5], 205 obp[6], obp[7], obp[8], obp[9])); 206 207 *dev->sci_mode &= ~SCI_MODE_DMA; 208 return 0; 209 } 210 211 int 212 otgsc_dma_xfer_out (dev, len, buf, phase) 213 struct sci_softc *dev; 214 int len; 215 register u_char *buf; 216 int phase; 217 { 218 int wait = sci_data_wait; 219 volatile register u_char *sci_dma = dev->sci_data + 0x100; 220 volatile register u_char *sci_csr = dev->sci_csr; 221 222 QPRINTF(("otgsc_dma_out %d, csr=%02x\n", len, *dev->sci_bus_csr)); 223 224 QPRINTF(("otgsc_dma_out {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", 225 len, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], 226 buf[6], buf[7], buf[8], buf[9])); 227 228 *dev->sci_tcmd = phase; 229 *dev->sci_mode |= SCI_MODE_DMA; 230 *dev->sci_icmd = SCI_ICMD_DATA; 231 *dev->sci_dma_send = 0; 232 while (len > 0) { 233 wait = sci_data_wait; 234 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 235 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 236 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 237 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 238 || --wait < 0) { 239 #ifdef DEBUG 240 if (sci_debug) 241 printf("otgsc_dma_out fail: l%d i%x w%d\n", 242 len, *dev->sci_bus_csr, wait); 243 #endif 244 *dev->sci_mode &= ~SCI_MODE_DMA; 245 return 0; 246 } 247 } 248 249 *sci_dma = *buf++; 250 len--; 251 } 252 253 wait = sci_data_wait; 254 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) == 255 SCI_CSR_PHASE_MATCH && --wait); 256 257 258 *dev->sci_mode &= ~SCI_MODE_DMA; 259 return 0; 260 } 261 262 int 263 otgsc_intr(arg) 264 void *arg; 265 { 266 struct sci_softc *dev = arg; 267 u_char stat; 268 269 if ((*dev->sci_csr & SCI_CSR_INT) == 0) 270 return (1); 271 stat = *dev->sci_iack; 272 *dev->sci_mode = 0; 273 return (1); 274 } 275
Indexes created Wed Sep 24 05:09:52 GMT 2025