otgsc.c revision 1.25
1 /* $NetBSD: otgsc.c,v 1.25 2002/01/26 13:40:59 aymeric Exp $ */ 2 3 /* 4 * Copyright (c) 1994 Michael L. Hitch 5 * Copyright (c) 1982, 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * @(#)csa12gdma.c 37 */ 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/device.h> 42 #include <dev/scsipi/scsi_all.h> 43 #include <dev/scsipi/scsipi_all.h> 44 #include <dev/scsipi/scsiconf.h> 45 #include <amiga/amiga/device.h> 46 #include <amiga/amiga/isr.h> 47 #include <amiga/dev/scireg.h> 48 #include <amiga/dev/scivar.h> 49 #include <amiga/dev/zbusvar.h> 50 51 void otgscattach(struct device *, struct device *, void *); 52 int otgscmatch(struct device *, struct cfdata *, void *); 53 54 int otgsc_dma_xfer_in(struct sci_softc *dev, int len, 55 register u_char *buf, int phase); 56 int otgsc_dma_xfer_out(struct sci_softc *dev, int len, 57 register u_char *buf, int phase); 58 int otgsc_intr(void *); 59 60 61 #ifdef DEBUG 62 extern int sci_debug; 63 #define QPRINTF(a) if (sci_debug > 1) printf a 64 #else 65 #define QPRINTF(a) 66 #endif 67 68 extern int sci_data_wait; 69 70 struct cfattach otgsc_ca = { 71 sizeof(struct sci_softc), otgscmatch, otgscattach 72 }; 73 74 /* 75 * if we are my Hacker's SCSI board we are here. 76 */ 77 int 78 otgscmatch(struct device *pdp, struct cfdata *cfp, void *auxp) 79 { 80 struct zbus_args *zap; 81 82 zap = auxp; 83 84 /* 85 * Check manufacturer and product id. 86 */ 87 if (zap->manid == 1058 && zap->prodid == 21) 88 return(1); 89 else 90 return(0); 91 } 92 93 void 94 otgscattach(struct device *pdp, struct device *dp, void *auxp) 95 { 96 volatile u_char *rp; 97 struct sci_softc *sc = (struct sci_softc *)dp; 98 struct zbus_args *zap; 99 struct scsipi_adapter *adapt = &sc->sc_adapter; 100 struct scsipi_channel *chan = &sc->sc_channel; 101 102 printf("\n"); 103 104 zap = auxp; 105 106 sc = (struct sci_softc *)dp; 107 rp = (u_char *)zap->va + 0x2000; 108 sc->sci_data = rp; 109 sc->sci_odata = rp; 110 sc->sci_icmd = rp + 0x10; 111 sc->sci_mode = rp + 0x20; 112 sc->sci_tcmd = rp + 0x30; 113 sc->sci_bus_csr = rp + 0x40; 114 sc->sci_sel_enb = rp + 0x40; 115 sc->sci_csr = rp + 0x50; 116 sc->sci_dma_send = rp + 0x50; 117 sc->sci_idata = rp + 0x60; 118 sc->sci_trecv = rp + 0x60; 119 sc->sci_iack = rp + 0x70; 120 sc->sci_irecv = rp + 0x70; 121 122 sc->dma_xfer_in = otgsc_dma_xfer_in; 123 sc->dma_xfer_out = otgsc_dma_xfer_out; 124 125 sc->sc_isr.isr_intr = otgsc_intr; 126 sc->sc_isr.isr_arg = sc; 127 sc->sc_isr.isr_ipl = 2; 128 add_isr(&sc->sc_isr); 129 130 scireset(sc); 131 132 /* 133 * Fill in the scsipi_adapter. 134 */ 135 memset(adapt, 0, sizeof(*adapt)); 136 adapt->adapt_dev = &sc->sc_dev; 137 adapt->adapt_nchannels = 1; 138 adapt->adapt_openings = 7; 139 adapt->adapt_max_periph = 1; 140 adapt->adapt_request = sci_scsipi_request; 141 adapt->adapt_minphys = sci_minphys; 142 143 /* 144 * Fill in the scsipi_channel. 145 */ 146 memset(chan, 0, sizeof(*chan)); 147 chan->chan_adapter = adapt; 148 chan->chan_bustype = &scsi_bustype; 149 chan->chan_channel = 0; 150 chan->chan_ntargets = 8; 151 chan->chan_nluns = 8; 152 chan->chan_id = 7; 153 154 /* 155 * attach all scsi units on us 156 */ 157 config_found(dp, chan, scsiprint); 158 } 159 160 int 161 otgsc_dma_xfer_in(struct sci_softc *dev, int len, register u_char *buf, 162 int phase) 163 { 164 int wait = sci_data_wait; 165 volatile register u_char *sci_dma = dev->sci_data + 0x100; 166 volatile register u_char *sci_csr = dev->sci_csr; 167 #ifdef DEBUG 168 u_char *obp = buf; 169 #endif 170 171 QPRINTF(("otgsc_dma_in %d, csr=%02x\n", len, *dev->sci_bus_csr)); 172 173 *dev->sci_tcmd = phase; 174 *dev->sci_mode |= SCI_MODE_DMA; 175 *dev->sci_icmd = 0; 176 *dev->sci_irecv = 0; 177 while (len > 0) { 178 wait = sci_data_wait; 179 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 180 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 181 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 182 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 183 || --wait < 0) { 184 #ifdef DEBUG 185 if (sci_debug) 186 printf("otgsc_dma_in fail: l%d i%x w%d\n", 187 len, *dev->sci_bus_csr, wait); 188 #endif 189 *dev->sci_mode &= ~SCI_MODE_DMA; 190 return 0; 191 } 192 } 193 194 *buf++ = *sci_dma; 195 len--; 196 } 197 198 QPRINTF(("otgsc_dma_in {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", 199 len, obp[0], obp[1], obp[2], obp[3], obp[4], obp[5], 200 obp[6], obp[7], obp[8], obp[9])); 201 202 *dev->sci_mode &= ~SCI_MODE_DMA; 203 return 0; 204 } 205 206 int 207 otgsc_dma_xfer_out(struct sci_softc *dev, int len, register u_char *buf, 208 int phase) 209 { 210 int wait = sci_data_wait; 211 volatile register u_char *sci_dma = dev->sci_data + 0x100; 212 volatile register u_char *sci_csr = dev->sci_csr; 213 214 QPRINTF(("otgsc_dma_out %d, csr=%02x\n", len, *dev->sci_bus_csr)); 215 216 QPRINTF(("otgsc_dma_out {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", 217 len, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], 218 buf[6], buf[7], buf[8], buf[9])); 219 220 *dev->sci_tcmd = phase; 221 *dev->sci_mode |= SCI_MODE_DMA; 222 *dev->sci_icmd = SCI_ICMD_DATA; 223 *dev->sci_dma_send = 0; 224 while (len > 0) { 225 wait = sci_data_wait; 226 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 227 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 228 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 229 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 230 || --wait < 0) { 231 #ifdef DEBUG 232 if (sci_debug) 233 printf("otgsc_dma_out fail: l%d i%x w%d\n", 234 len, *dev->sci_bus_csr, wait); 235 #endif 236 *dev->sci_mode &= ~SCI_MODE_DMA; 237 return 0; 238 } 239 } 240 241 *sci_dma = *buf++; 242 len--; 243 } 244 245 wait = sci_data_wait; 246 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) == 247 SCI_CSR_PHASE_MATCH && --wait); 248 249 250 *dev->sci_mode &= ~SCI_MODE_DMA; 251 return 0; 252 } 253 254 int 255 otgsc_intr(void *arg) 256 { 257 struct sci_softc *dev = arg; 258 u_char stat; 259 260 if ((*dev->sci_csr & SCI_CSR_INT) == 0) 261 return (1); 262 stat = *dev->sci_iack; 263 *dev->sci_mode = 0; 264 return (1); 265 } 266
Indexes created Sun Sep 28 07:09:56 GMT 2025