otgsc.c revision 1.30
1 /* $NetBSD: otgsc.c,v 1.30 2004/03/28 18:59:39 mhitch Exp $ */ 2 3 /* 4 * Copyright (c) 1982, 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of the University nor the names of its contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * @(#)csa12gdma.c 32 */ 33 34 /* 35 * Copyright (c) 1994 Michael L. Hitch 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 46 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 47 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 48 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 49 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 50 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 51 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 52 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 53 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 54 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 55 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 56 * 57 * @(#)csa12gdma.c 58 */ 59 60 #include <sys/cdefs.h> 61 __KERNEL_RCSID(0, "$NetBSD: otgsc.c,v 1.30 2004/03/28 18:59:39 mhitch Exp $"); 62 63 #include <sys/param.h> 64 #include <sys/systm.h> 65 #include <sys/kernel.h> 66 #include <sys/device.h> 67 #include <dev/scsipi/scsi_all.h> 68 #include <dev/scsipi/scsipi_all.h> 69 #include <dev/scsipi/scsiconf.h> 70 #include <amiga/amiga/device.h> 71 #include <amiga/amiga/isr.h> 72 #include <amiga/dev/scireg.h> 73 #include <amiga/dev/scivar.h> 74 #include <amiga/dev/zbusvar.h> 75 76 void otgscattach(struct device *, struct device *, void *); 77 int otgscmatch(struct device *, struct cfdata *, void *); 78 79 int otgsc_dma_xfer_in(struct sci_softc *dev, int len, 80 register u_char *buf, int phase); 81 int otgsc_dma_xfer_out(struct sci_softc *dev, int len, 82 register u_char *buf, int phase); 83 int otgsc_intr(void *); 84 85 86 #ifdef DEBUG 87 extern int sci_debug; 88 #define QPRINTF(a) if (sci_debug > 1) printf a 89 #else 90 #define QPRINTF(a) 91 #endif 92 93 extern int sci_data_wait; 94 95 CFATTACH_DECL(otgsc, sizeof(struct sci_softc), 96 otgscmatch, otgscattach, NULL, NULL); 97 98 /* 99 * if we are my Hacker's SCSI board we are here. 100 */ 101 int 102 otgscmatch(struct device *pdp, struct cfdata *cfp, void *auxp) 103 { 104 struct zbus_args *zap; 105 106 zap = auxp; 107 108 /* 109 * Check manufacturer and product id. 110 */ 111 if (zap->manid == 1058 && zap->prodid == 21) 112 return(1); 113 else 114 return(0); 115 } 116 117 void 118 otgscattach(struct device *pdp, struct device *dp, void *auxp) 119 { 120 volatile u_char *rp; 121 struct sci_softc *sc = (struct sci_softc *)dp; 122 struct zbus_args *zap; 123 struct scsipi_adapter *adapt = &sc->sc_adapter; 124 struct scsipi_channel *chan = &sc->sc_channel; 125 126 printf("\n"); 127 128 zap = auxp; 129 130 sc = (struct sci_softc *)dp; 131 rp = (u_char *)zap->va + 0x2000; 132 sc->sci_data = rp; 133 sc->sci_odata = rp; 134 sc->sci_icmd = rp + 0x10; 135 sc->sci_mode = rp + 0x20; 136 sc->sci_tcmd = rp + 0x30; 137 sc->sci_bus_csr = rp + 0x40; 138 sc->sci_sel_enb = rp + 0x40; 139 sc->sci_csr = rp + 0x50; 140 sc->sci_dma_send = rp + 0x50; 141 sc->sci_idata = rp + 0x60; 142 sc->sci_trecv = rp + 0x60; 143 sc->sci_iack = rp + 0x70; 144 sc->sci_irecv = rp + 0x70; 145 146 sc->dma_xfer_in = otgsc_dma_xfer_in; 147 sc->dma_xfer_out = otgsc_dma_xfer_out; 148 149 sc->sc_isr.isr_intr = otgsc_intr; 150 sc->sc_isr.isr_arg = sc; 151 sc->sc_isr.isr_ipl = 2; 152 add_isr(&sc->sc_isr); 153 154 scireset(sc); 155 156 /* 157 * Fill in the scsipi_adapter. 158 */ 159 memset(adapt, 0, sizeof(*adapt)); 160 adapt->adapt_dev = &sc->sc_dev; 161 adapt->adapt_nchannels = 1; 162 adapt->adapt_openings = 7; 163 adapt->adapt_max_periph = 1; 164 adapt->adapt_request = sci_scsipi_request; 165 adapt->adapt_minphys = sci_minphys; 166 167 /* 168 * Fill in the scsipi_channel. 169 */ 170 memset(chan, 0, sizeof(*chan)); 171 chan->chan_adapter = adapt; 172 chan->chan_bustype = &scsi_bustype; 173 chan->chan_channel = 0; 174 chan->chan_ntargets = 8; 175 chan->chan_nluns = 8; 176 chan->chan_id = 7; 177 178 /* 179 * attach all scsi units on us 180 */ 181 config_found(dp, chan, scsiprint); 182 } 183 184 int 185 otgsc_dma_xfer_in(struct sci_softc *dev, int len, register u_char *buf, 186 int phase) 187 { 188 int wait = sci_data_wait; 189 volatile register u_char *sci_dma = dev->sci_data + 0x100; 190 volatile register u_char *sci_csr = dev->sci_csr; 191 #ifdef DEBUG 192 u_char *obp = buf; 193 #endif 194 195 QPRINTF(("otgsc_dma_in %d, csr=%02x\n", len, *dev->sci_bus_csr)); 196 197 *dev->sci_tcmd = phase; 198 *dev->sci_mode |= SCI_MODE_DMA; 199 *dev->sci_icmd = 0; 200 *dev->sci_irecv = 0; 201 while (len > 0) { 202 wait = sci_data_wait; 203 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 204 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 205 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 206 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 207 || --wait < 0) { 208 #ifdef DEBUG 209 if (sci_debug) 210 printf("otgsc_dma_in fail: l%d i%x w%d\n", 211 len, *dev->sci_bus_csr, wait); 212 #endif 213 *dev->sci_mode &= ~SCI_MODE_DMA; 214 return 0; 215 } 216 } 217 218 *buf++ = *sci_dma; 219 len--; 220 } 221 222 QPRINTF(("otgsc_dma_in {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", 223 len, obp[0], obp[1], obp[2], obp[3], obp[4], obp[5], 224 obp[6], obp[7], obp[8], obp[9])); 225 226 *dev->sci_mode &= ~SCI_MODE_DMA; 227 return 0; 228 } 229 230 int 231 otgsc_dma_xfer_out(struct sci_softc *dev, int len, register u_char *buf, 232 int phase) 233 { 234 int wait = sci_data_wait; 235 volatile register u_char *sci_dma = dev->sci_data + 0x100; 236 volatile register u_char *sci_csr = dev->sci_csr; 237 238 QPRINTF(("otgsc_dma_out %d, csr=%02x\n", len, *dev->sci_bus_csr)); 239 240 QPRINTF(("otgsc_dma_out {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", 241 len, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], 242 buf[6], buf[7], buf[8], buf[9])); 243 244 *dev->sci_tcmd = phase; 245 *dev->sci_mode |= SCI_MODE_DMA; 246 *dev->sci_icmd = SCI_ICMD_DATA; 247 *dev->sci_dma_send = 0; 248 while (len > 0) { 249 wait = sci_data_wait; 250 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 251 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 252 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 253 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 254 || --wait < 0) { 255 #ifdef DEBUG 256 if (sci_debug) 257 printf("otgsc_dma_out fail: l%d i%x w%d\n", 258 len, *dev->sci_bus_csr, wait); 259 #endif 260 *dev->sci_mode &= ~SCI_MODE_DMA; 261 return 0; 262 } 263 } 264 265 *sci_dma = *buf++; 266 len--; 267 } 268 269 wait = sci_data_wait; 270 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) == 271 SCI_CSR_PHASE_MATCH && --wait); 272 273 274 *dev->sci_mode &= ~SCI_MODE_DMA; 275 return 0; 276 } 277 278 int 279 otgsc_intr(void *arg) 280 { 281 struct sci_softc *dev = arg; 282 u_char stat; 283 284 if ((*dev->sci_csr & SCI_CSR_INT) == 0) 285 return (1); 286 stat = *dev->sci_iack; 287 *dev->sci_mode = 0; 288 return (1); 289 } 290
Indexes created Thu Sep 25 16:09:42 GMT 2025