otgsc.c revision 1.9
1 /* $NetBSD: otgsc.c,v 1.9 1995/09/16 16:11:24 chopps Exp $ */ 2 3 /* 4 * Copyright (c) 1994 Michael L. Hitch 5 * Copyright (c) 1982, 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * @(#)csa12gdma.c 37 */ 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/device.h> 42 #include <scsi/scsi_all.h> 43 #include <scsi/scsiconf.h> 44 #include <amiga/amiga/device.h> 45 #include <amiga/amiga/isr.h> 46 #include <amiga/dev/scireg.h> 47 #include <amiga/dev/scivar.h> 48 #include <amiga/dev/zbusvar.h> 49 50 int otgscprint __P((void *auxp, char *)); 51 void otgscattach __P((struct device *, struct device *, void *)); 52 int otgscmatch __P((struct device *, struct cfdata *, void *)); 53 54 int otgsc_dma_xfer_in __P((struct sci_softc *dev, int len, 55 register u_char *buf, int phase)); 56 int otgsc_dma_xfer_out __P((struct sci_softc *dev, int len, 57 register u_char *buf, int phase)); 58 int otgsc_intr __P((struct sci_softc *)); 59 60 struct scsi_adapter otgsc_scsiswitch = { 61 sci_scsicmd, 62 sci_minphys, 63 0, /* no lun support */ 64 0, /* no lun support */ 65 }; 66 67 struct scsi_device otgsc_scsidev = { 68 NULL, /* use default error handler */ 69 NULL, /* do not have a start functio */ 70 NULL, /* have no async handler */ 71 NULL, /* Use default done routine */ 72 }; 73 74 #define QPRINTF 75 76 #ifdef DEBUG 77 extern int sci_debug; 78 #endif 79 80 extern int sci_data_wait; 81 82 struct cfdriver otgsccd = { 83 NULL, "otgsc", (cfmatch_t)otgscmatch, otgscattach, 84 DV_DULL, sizeof(struct sci_softc), NULL, 0 }; 85 86 /* 87 * if we are my Hacker's SCSI board we are here. 88 */ 89 int 90 otgscmatch(pdp, cdp, auxp) 91 struct device *pdp; 92 struct cfdata *cdp; 93 void *auxp; 94 { 95 struct zbus_args *zap; 96 97 zap = auxp; 98 99 /* 100 * Check manufacturer and product id. 101 */ 102 if (zap->manid == 1058 && zap->prodid == 21) 103 return(1); 104 else 105 return(0); 106 } 107 108 void 109 otgscattach(pdp, dp, auxp) 110 struct device *pdp, *dp; 111 void *auxp; 112 { 113 volatile u_char *rp; 114 struct sci_softc *sc; 115 struct zbus_args *zap; 116 117 printf("\n"); 118 119 zap = auxp; 120 121 sc = (struct sci_softc *)dp; 122 rp = zap->va + 0x2000; 123 sc->sci_data = rp; 124 sc->sci_odata = rp; 125 sc->sci_icmd = rp + 0x10; 126 sc->sci_mode = rp + 0x20; 127 sc->sci_tcmd = rp + 0x30; 128 sc->sci_bus_csr = rp + 0x40; 129 sc->sci_sel_enb = rp + 0x40; 130 sc->sci_csr = rp + 0x50; 131 sc->sci_dma_send = rp + 0x50; 132 sc->sci_idata = rp + 0x60; 133 sc->sci_trecv = rp + 0x60; 134 sc->sci_iack = rp + 0x70; 135 sc->sci_irecv = rp + 0x70; 136 137 sc->dma_xfer_in = otgsc_dma_xfer_in; 138 sc->dma_xfer_out = otgsc_dma_xfer_out; 139 140 sc->sc_isr.isr_intr = otgsc_intr; 141 sc->sc_isr.isr_arg = sc; 142 sc->sc_isr.isr_ipl = 2; 143 add_isr(&sc->sc_isr); 144 145 scireset(sc); 146 147 sc->sc_link.adapter_softc = sc; 148 sc->sc_link.adapter_target = 7; 149 sc->sc_link.adapter = &otgsc_scsiswitch; 150 sc->sc_link.device = &otgsc_scsidev; 151 sc->sc_link.openings = 1; 152 TAILQ_INIT(&sc->sc_xslist); 153 154 /* 155 * attach all scsi units on us 156 */ 157 config_found(dp, &sc->sc_link, otgscprint); 158 } 159 160 /* 161 * print diag if pnp is NULL else just extra 162 */ 163 int 164 otgscprint(auxp, pnp) 165 void *auxp; 166 char *pnp; 167 { 168 if (pnp == NULL) 169 return(UNCONF); 170 return(QUIET); 171 } 172 173 174 int 175 otgsc_dma_xfer_in (dev, len, buf, phase) 176 struct sci_softc *dev; 177 int len; 178 register u_char *buf; 179 int phase; 180 { 181 int wait = sci_data_wait; 182 u_char csr; 183 u_char *obp = buf; 184 volatile register u_char *sci_dma = dev->sci_data + 0x100; 185 volatile register u_char *sci_csr = dev->sci_csr; 186 volatile register u_char *sci_icmd = dev->sci_icmd; 187 188 QPRINTF(("otgsc_dma_in %d, csr=%02x\n", len, *dev->sci_bus_csr)); 189 190 *dev->sci_tcmd = phase; 191 *dev->sci_mode |= SCI_MODE_DMA; 192 *dev->sci_icmd = 0; 193 *dev->sci_irecv = 0; 194 while (len > 0) { 195 wait = sci_data_wait; 196 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 197 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 198 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 199 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 200 || --wait < 0) { 201 #ifdef DEBUG 202 if (sci_debug) 203 printf("otgsc_dma_in fail: l%d i%x w%d\n", 204 len, csr, wait); 205 #endif 206 *dev->sci_mode &= ~SCI_MODE_DMA; 207 return 0; 208 } 209 } 210 211 *buf++ = *sci_dma; 212 len--; 213 } 214 215 QPRINTF(("otgsc_dma_in {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", 216 len, obp[0], obp[1], obp[2], obp[3], obp[4], obp[5], 217 obp[6], obp[7], obp[8], obp[9])); 218 219 *dev->sci_mode &= ~SCI_MODE_DMA; 220 return 0; 221 } 222 223 int 224 otgsc_dma_xfer_out (dev, len, buf, phase) 225 struct sci_softc *dev; 226 int len; 227 register u_char *buf; 228 int phase; 229 { 230 int wait = sci_data_wait; 231 u_char csr; 232 u_char *obp = buf; 233 volatile register u_char *sci_dma = dev->sci_data + 0x100; 234 volatile register u_char *sci_csr = dev->sci_csr; 235 volatile register u_char *sci_icmd = dev->sci_icmd; 236 237 QPRINTF(("otgsc_dma_out %d, csr=%02x\n", len, *dev->sci_bus_csr)); 238 239 QPRINTF(("otgsc_dma_out {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", 240 len, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], 241 buf[6], buf[7], buf[8], buf[9])); 242 243 *dev->sci_tcmd = phase; 244 *dev->sci_mode |= SCI_MODE_DMA; 245 *dev->sci_icmd = SCI_ICMD_DATA; 246 *dev->sci_dma_send = 0; 247 while (len > 0) { 248 wait = sci_data_wait; 249 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 250 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 251 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 252 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 253 || --wait < 0) { 254 #ifdef DEBUG 255 if (sci_debug) 256 printf("otgsc_dma_out fail: l%d i%x w%d\n", 257 len, csr, wait); 258 #endif 259 *dev->sci_mode &= ~SCI_MODE_DMA; 260 return 0; 261 } 262 } 263 264 *sci_dma = *buf++; 265 len--; 266 } 267 268 wait = sci_data_wait; 269 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) == 270 SCI_CSR_PHASE_MATCH && --wait); 271 272 273 *dev->sci_mode &= ~SCI_MODE_DMA; 274 return 0; 275 } 276 277 int 278 otgsc_intr(dev) 279 struct sci_softc *dev; 280 { 281 u_char stat; 282 283 if ((*dev->sci_csr & SCI_CSR_INT) == 0) 284 return (1); 285 stat = *dev->sci_iack; 286 *dev->sci_mode = 0; 287 return (1); 288 } 289
Indexes created Mon Sep 22 13:09:51 GMT 2025