sbic.c revision 1.1
1 /* 2 * Copyright (c) 1994 Christian E. Hopps 3 * Copyright (c) 1990 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * Van Jacobson of Lawrence Berkeley Laboratory. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the University of 20 * California, Berkeley and its contributors. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * @(#)scsi.c 7.5 (Berkeley) 5/4/91 38 * $Id: sbic.c,v 1.1 1994/05/08 05:53:36 chopps Exp $ 39 */ 40 41 /* 42 * AMIGA AMD 33C93 scsi adaptor driver 43 */ 44 45 /* need to know if any tapes have been configured */ 46 #include "st.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/device.h> 51 #include <sys/buf.h> 52 #include <scsi/scsi_all.h> 53 #include <scsi/scsiconf.h> 54 #include <vm/vm.h> 55 #include <vm/vm_kern.h> 56 #include <vm/vm_page.h> 57 #include <machine/pmap.h> 58 #include <machine/cpu.h> 59 #include <amiga/amiga/device.h> 60 #include <amiga/amiga/custom.h> 61 #include <amiga/dev/dmavar.h> 62 #include <amiga/dev/sbicreg.h> 63 #include <amiga/dev/sbicvar.h> 64 65 /* 66 * SCSI delays 67 * In u-seconds, primarily for state changes on the SPC. 68 */ 69 #define SBIC_CMD_WAIT 50000 /* wait per step of 'immediate' cmds */ 70 #define SBIC_DATA_WAIT 50000 /* wait per data in/out step */ 71 #define SBIC_INIT_WAIT 50000 /* wait per step (both) during init */ 72 73 #define b_cylin b_resid 74 #define SBIC_WAIT(regs, until, timeo) sbicwait(regs, until, timeo, __LINE__) 75 76 extern u_int kvtop(); 77 78 int sbicicmd __P((struct sbic_softc *, int, void *, int, void *, int,u_char)); 79 int sbicgo __P((struct sbic_softc *, struct scsi_xfer *)); 80 int sbicdmaok __P((struct sbic_softc *, struct scsi_xfer *)); 81 int sbicgetsense __P((struct sbic_softc *, struct scsi_xfer *)); 82 int sbicwait __P((sbic_regmap_p, char, int , int)); 83 int sbiccheckdmap __P((void *, u_long, u_long)); 84 int sbicselectbus __P((struct sbic_softc *, sbic_regmap_p, u_char, u_char)); 85 int sbicxfstart __P((sbic_regmap_p, int, u_char, int)); 86 int sbicxfout __P((sbic_regmap_p regs, int, void *, int)); 87 int sbicfromscsiperiod __P((struct sbic_softc *, sbic_regmap_p, int)); 88 int sbictoscsiperiod __P((struct sbic_softc *, sbic_regmap_p, int)); 89 int sbicintr __P((struct sbic_softc *)); 90 void sbicxfin __P((sbic_regmap_p regs, int, void *)); 91 void sbicxfdone __P((struct sbic_softc *, sbic_regmap_p, int)); 92 void sbicabort __P((struct sbic_softc *, sbic_regmap_p, char *)); 93 void sbicerror __P((struct sbic_softc *, sbic_regmap_p, u_char)); 94 void sbicstart __P((struct sbic_softc *)); 95 void sbicreset __P((struct sbic_softc *)); 96 void sbicsetdelay __P((int)); 97 void sbic_scsidone __P((struct sbic_softc *, int)); 98 void sbic_donextcmd __P((struct sbic_softc *)); 99 100 /* 101 * Synch xfer parameters, and timing conversions 102 */ 103 int sbic_min_period = SBIC_SYN_MIN_PERIOD; /* in cycles = f(ICLK,FSn) */ 104 int sbic_max_offset = SBIC_SYN_MAX_OFFSET; /* pure number */ 105 106 int sbic_cmd_wait = SBIC_CMD_WAIT; 107 int sbic_data_wait = SBIC_DATA_WAIT; 108 int sbic_init_wait = SBIC_INIT_WAIT; 109 110 /* 111 * was broken before.. now if you want this you get it for all drives 112 * on sbic controllers. 113 */ 114 int sbic_inhibit_sync = 1; 115 int sbic_clock_override = 0; 116 int sbic_no_dma = 0; 117 118 #ifdef DEBUG 119 #define QPRINTF(a) if (sbic_debug > 1) printf a 120 int sbic_debug = 0; 121 int sync_debug = 0; 122 int sbic_dma_debug = 0; 123 #else 124 #define QPRINTF 125 #endif 126 127 /* 128 * default minphys routine for sbic based controllers 129 */ 130 void 131 sbic_minphys(bp) 132 struct buf *bp; 133 { 134 /* 135 * no max transfer at this level 136 */ 137 } 138 139 /* 140 * must be used 141 */ 142 u_int 143 sbic_adinfo() 144 { 145 /* 146 * one request at a time please 147 */ 148 return(1); 149 } 150 151 /* 152 * used by specific sbic controller 153 * 154 * it appears that the higher level code does nothing with LUN's 155 * so I will too. I could plug it in, however so could they 156 * in scsi_scsi_cmd(). 157 */ 158 int 159 sbic_scsicmd(xs) 160 struct scsi_xfer *xs; 161 { 162 struct sbic_pending *pendp; 163 struct sbic_softc *dev; 164 struct scsi_link *slp; 165 int flags, s; 166 167 slp = xs->sc_link; 168 dev = slp->adapter_softc; 169 flags = xs->flags; 170 171 if (flags & SCSI_DATA_UIO) 172 panic("sbic: scsi data uio requested"); 173 174 if (dev->sc_xs && flags & SCSI_NOMASK) 175 panic("sbic_scsicmd: busy"); 176 177 s = splbio(); 178 pendp = &dev->sc_xsstore[slp->target][slp->lun]; 179 if (pendp->xs) { 180 splx(s); 181 return(TRY_AGAIN_LATER); 182 } 183 184 if (dev->sc_xs) { 185 pendp->xs = xs; 186 TAILQ_INSERT_TAIL(&dev->sc_xslist, pendp, link); 187 splx(s); 188 return(SUCCESSFULLY_QUEUED); 189 } 190 pendp->xs = NULL; 191 dev->sc_xs = xs; 192 splx(s); 193 194 /* 195 * nothing is pending do it now. 196 */ 197 sbic_donextcmd(dev); 198 199 if (flags & SCSI_NOMASK) 200 return(COMPLETE); 201 return(SUCCESSFULLY_QUEUED); 202 } 203 204 /* 205 * entered with dev->sc_xs pointing to the next xfer to perform 206 */ 207 void 208 sbic_donextcmd(dev) 209 struct sbic_softc *dev; 210 { 211 struct scsi_xfer *xs; 212 struct scsi_link *slp; 213 int flags, phase, stat; 214 215 xs = dev->sc_xs; 216 slp = xs->sc_link; 217 flags = xs->flags; 218 219 if (flags & SCSI_DATA_IN) 220 phase = DATA_IN_PHASE; 221 else if (flags & SCSI_DATA_OUT) 222 phase = DATA_OUT_PHASE; 223 else 224 phase = STATUS_PHASE; 225 226 if (flags & SCSI_RESET) 227 sbicreset(dev); 228 229 dev->sc_stat[0] = -1; 230 if (phase == STATUS_PHASE || flags & SCSI_NOMASK || 231 sbicdmaok(dev, xs) == 0) 232 stat = sbicicmd(dev, slp->target, xs->cmd, xs->cmdlen, 233 xs->data, xs->datalen, phase); 234 else if (sbicgo(dev, xs) == 0) 235 return; 236 else 237 stat = dev->sc_stat[0]; 238 239 sbic_scsidone(dev, stat); 240 } 241 242 void 243 sbic_scsidone(dev, stat) 244 struct sbic_softc *dev; 245 int stat; 246 { 247 struct sbic_pending *pendp; 248 struct scsi_xfer *xs; 249 int s, donext; 250 251 xs = dev->sc_xs; 252 #ifdef DIAGNOSTIC 253 if (xs == NULL) 254 panic("sbic_scsidone"); 255 #endif 256 /* 257 * is this right? 258 */ 259 xs->status = stat; 260 261 if (stat == 0 || xs->flags & SCSI_ERR_OK) 262 xs->resid = 0; 263 else { 264 switch(stat) { 265 case SCSI_CHECK: 266 if (stat = sbicgetsense(dev, xs)) 267 goto bad_sense; 268 xs->error = XS_SENSE; 269 break; 270 case SCSI_BUSY: 271 xs->error = XS_BUSY; 272 break; 273 bad_sense: 274 default: 275 xs->error = XS_DRIVER_STUFFUP; 276 QPRINTF(("sbic_scsicmd() bad %x\n", stat)); 277 break; 278 } 279 } 280 xs->flags |= ITSDONE; 281 282 /* 283 * grab next command before scsi_done() 284 * this way no single device can hog scsi resources. 285 */ 286 s = splbio(); 287 pendp = dev->sc_xslist.tqh_first; 288 if (pendp == NULL) { 289 donext = 0; 290 dev->sc_xs = NULL; 291 } else { 292 donext = 1; 293 TAILQ_REMOVE(&dev->sc_xslist, pendp, link); 294 dev->sc_xs = pendp->xs; 295 pendp->xs = NULL; 296 } 297 splx(s); 298 scsi_done(xs); 299 300 if (donext) 301 sbic_donextcmd(dev); 302 } 303 304 int 305 sbicgetsense(dev, xs) 306 struct sbic_softc *dev; 307 struct scsi_xfer *xs; 308 { 309 struct scsi_sense rqs; 310 struct scsi_link *slp; 311 int stat; 312 313 slp = xs->sc_link; 314 315 rqs.op_code = REQUEST_SENSE; 316 rqs.byte2 = slp->lun << 5; 317 rqs.length = xs->req_sense_length ? xs->req_sense_length : 318 sizeof(xs->sense); 319 rqs.unused[0] = rqs.unused[1] = rqs.control = 0; 320 321 return(sbicicmd(dev, slp->target, &rqs, sizeof(rqs), &xs->sense, 322 rqs.length, DATA_IN_PHASE)); 323 } 324 325 int 326 sbicdmaok(dev, xs) 327 struct sbic_softc *dev; 328 struct scsi_xfer *xs; 329 { 330 if (sbic_no_dma || xs->datalen & 0x1 || (u_int)xs->data & 0x3) 331 return(0); 332 /* 333 * controller supports dma to any addresses? 334 */ 335 else if ((dev->sc_flags & SBICF_BADDMA) == 0) 336 return(1); 337 /* 338 * this address is ok for dma? 339 */ 340 else if (sbiccheckdmap(xs->data, xs->datalen, dev->sc_dmamask) == 0) 341 return(1); 342 /* 343 * we have a bounce buffer? 344 */ 345 else if (dev->sc_dmabuffer) 346 return(1); 347 return(0); 348 } 349 350 351 int 352 sbicwait(regs, until, timeo, line) 353 sbic_regmap_p regs; 354 char until; 355 int timeo; 356 int line; 357 { 358 u_char val; 359 int csr; 360 361 if (timeo == 0) 362 timeo = 1000000; /* some large value.. */ 363 364 GET_SBIC_asr(regs,val); 365 while ((val & until) == 0) { 366 if (timeo-- == 0) { 367 GET_SBIC_csr(regs, csr); 368 printf("sbicwait TIMEO @%d with asr=x%x csr=x%x\n", 369 line, val, csr); 370 break; 371 } 372 DELAY(1); 373 GET_SBIC_asr(regs,val); 374 } 375 return(val); 376 } 377 378 void 379 sbicabort(dev, regs, where) 380 struct sbic_softc *dev; 381 sbic_regmap_p regs; 382 char *where; 383 { 384 u_char csr, asr; 385 386 GET_SBIC_csr(regs, csr); 387 GET_SBIC_asr(regs, asr); 388 389 printf ("%s: abort %s: csr = 0x%02x, asr = 0x%02x\n", 390 dev->sc_dev.dv_xname, where, csr, asr); 391 392 if (dev->sc_flags & SBICF_SELECTED) { 393 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 394 WAIT_CIP(regs); 395 396 GET_SBIC_asr(regs, asr); 397 if (asr & (SBIC_ASR_BSY|SBIC_ASR_LCI)) { 398 /* ok, get more drastic.. */ 399 400 SET_SBIC_cmd (regs, SBIC_CMD_RESET); 401 DELAY(25); 402 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 403 /* clears interrupt also */ 404 GET_SBIC_csr (regs, csr); 405 406 dev->sc_flags &= ~SBICF_SELECTED; 407 return; 408 } 409 410 do { 411 SBIC_WAIT (regs, SBIC_ASR_INT, 0); 412 GET_SBIC_csr (regs, csr); 413 } while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) 414 && (csr != SBIC_CSR_CMD_INVALID)); 415 416 /* lets just hope it worked.. */ 417 dev->sc_flags &= ~SBICF_SELECTED; 418 } 419 } 420 421 /* 422 * XXX Set/reset long delays. 423 * 424 * if delay == 0, reset default delays 425 * if delay < 0, set both delays to default long initialization values 426 * if delay > 0, set both delays to this value 427 * 428 * Used when a devices is expected to respond slowly (e.g. during 429 * initialization). 430 */ 431 void 432 sbicsetdelay(del) 433 int del; 434 { 435 static int saved_cmd_wait, saved_data_wait; 436 437 if (del) { 438 saved_cmd_wait = sbic_cmd_wait; 439 saved_data_wait = sbic_data_wait; 440 if (del > 0) 441 sbic_cmd_wait = sbic_data_wait = del; 442 else 443 sbic_cmd_wait = sbic_data_wait = sbic_init_wait; 444 } else { 445 sbic_cmd_wait = saved_cmd_wait; 446 sbic_data_wait = saved_data_wait; 447 } 448 } 449 450 void 451 sbicreset(dev) 452 struct sbic_softc *dev; 453 { 454 sbic_regmap_p regs; 455 u_int i, s; 456 u_char my_id, csr; 457 458 regs = dev->sc_sbicp; 459 460 if (dev->sc_flags & SBICF_ALIVE) 461 sbicabort(dev, regs, "reset"); 462 463 s = splbio(); 464 /* preserve our ID for now */ 465 GET_SBIC_myid (regs, my_id); 466 my_id &= SBIC_ID_MASK; 467 468 if (dev->sc_clkfreq < 110) 469 my_id |= SBIC_ID_FS_8_10; 470 else if (dev->sc_clkfreq < 160) 471 my_id |= SBIC_ID_FS_12_15; 472 else if (dev->sc_clkfreq < 210) 473 my_id |= SBIC_ID_FS_16_20; 474 475 my_id |= SBIC_ID_EAF /*| SBIC_ID_EHP*/ ; 476 477 SET_SBIC_myid(regs, my_id); 478 479 /* 480 * Disable interrupts (in dmainit) then reset the chip 481 */ 482 SET_SBIC_cmd(regs, SBIC_CMD_RESET); 483 DELAY(25); 484 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 485 GET_SBIC_csr(regs, csr); /* clears interrupt also */ 486 487 /* 488 * Set up various chip parameters 489 */ 490 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI 491 | SBIC_MACHINE_DMA_MODE); 492 /* 493 * don't allow (re)selection (SBIC_RID_ES) 494 * until we can handle target mode!! 495 */ 496 SET_SBIC_rselid(regs, 0); 497 SET_SBIC_syn(regs, 0); /* asynch for now */ 498 499 /* 500 * anything else was zeroed by reset 501 */ 502 splx(s); 503 504 dev->sc_flags |= SBICF_ALIVE; 505 dev->sc_flags &= ~SBICF_SELECTED; 506 } 507 508 void 509 sbicerror(dev, regs, csr) 510 struct sbic_softc *dev; 511 sbic_regmap_p regs; 512 u_char csr; 513 { 514 struct scsi_xfer *xs; 515 516 xs = dev->sc_xs; 517 518 #ifdef DIAGNOSTIC 519 if (xs == NULL) 520 panic("sbicerror"); 521 #endif 522 if (xs->flags & SCSI_SILENT) 523 return; 524 525 printf("%s: ", dev->sc_dev.dv_xname); 526 printf("csr == 0x%02i\n", csr); /* XXX */ 527 } 528 529 /* 530 * select the bus, return when selected or error. 531 */ 532 int 533 sbicselectbus(dev, regs, target, our_addr) 534 struct sbic_softc *dev; 535 sbic_regmap_p regs; 536 u_char target, our_addr; 537 { 538 u_char asr, csr, id; 539 540 QPRINTF(("sbicselectbus %d\n", target)); 541 542 /* 543 * if we're already selected, return (XXXX panic maybe?) 544 */ 545 if (dev->sc_flags & SBICF_SELECTED) 546 return(1); 547 548 /* 549 * issue select 550 */ 551 SBIC_TC_PUT(regs, 0); 552 SET_SBIC_selid(regs, target); 553 SET_SBIC_timeo(regs, SBIC_TIMEOUT(250,dev->sc_clkfreq)); 554 555 /* 556 * set sync or async 557 */ 558 if (dev->sc_sync[target].state == SYNC_DONE) 559 SET_SBIC_syn(regs, SBIC_SYN (dev->sc_sync[target].offset, 560 dev->sc_sync[target].period)); 561 else 562 SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period)); 563 564 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN); 565 566 /* 567 * wait for select (merged from seperate function may need 568 * cleanup) 569 */ 570 WAIT_CIP(regs); 571 do { 572 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 573 GET_SBIC_csr (regs, csr); 574 QPRINTF(("%02x ", csr)); 575 } while (csr != (SBIC_CSR_MIS_2|MESG_OUT_PHASE) 576 && csr != (SBIC_CSR_MIS_2|CMD_PHASE) && csr != SBIC_CSR_SEL_TIMEO); 577 578 if (csr == (SBIC_CSR_MIS_2|CMD_PHASE)) 579 dev->sc_flags |= SBICF_SELECTED; /* device ignored ATN */ 580 else if (csr == (SBIC_CSR_MIS_2|MESG_OUT_PHASE)) { 581 /* 582 * Send identify message 583 * (SCSI-2 requires an identify msg (?)) 584 */ 585 GET_SBIC_selid(regs, id); 586 587 /* 588 * handle drives that don't want to be asked 589 * whether to go sync at all. 590 */ 591 if (sbic_inhibit_sync && dev->sc_sync[id].state == SYNC_START) { 592 #ifdef DEBUG 593 if (sync_debug) 594 printf("Forcing target %d asynchronous.\n", id); 595 #endif 596 dev->sc_sync[id].offset = 0; 597 dev->sc_sync[id].period = sbic_min_period; 598 dev->sc_sync[id].state = SYNC_DONE; 599 } 600 601 602 if (dev->sc_sync[id].state != SYNC_START) 603 SEND_BYTE (regs, MSG_IDENTIFY); 604 else { 605 /* 606 * try to initiate a sync transfer. 607 * So compose the sync message we're going 608 * to send to the target 609 */ 610 611 #ifdef DEBUG 612 if (sync_debug) 613 printf("Sending sync request to target %d ... ", 614 id); 615 #endif 616 /* 617 * setup scsi message sync message request 618 */ 619 dev->sc_msg[0] = MSG_IDENTIFY; 620 dev->sc_msg[1] = MSG_EXT_MESSAGE; 621 dev->sc_msg[2] = 3; 622 dev->sc_msg[3] = MSG_SYNC_REQ; 623 dev->sc_msg[4] = sbictoscsiperiod(dev, regs, 624 sbic_min_period); 625 dev->sc_msg[5] = sbic_max_offset; 626 627 if (sbicxfstart(regs, 6, MESG_OUT_PHASE, sbic_cmd_wait)) 628 sbicxfout(regs, 6, dev->sc_msg, MESG_OUT_PHASE); 629 630 dev->sc_sync[id].state = SYNC_SENT; 631 #ifdef DEBUG 632 if (sync_debug) 633 printf ("sent\n"); 634 #endif 635 } 636 637 SBIC_WAIT (regs, SBIC_ASR_INT, 0); 638 GET_SBIC_csr (regs, csr); 639 QPRINTF(("[%02x]", csr)); 640 #ifdef DEBUG 641 if (sync_debug && dev->sc_sync[id].state == SYNC_SENT) 642 printf("csr-result of last msgout: 0x%x\n", csr); 643 #endif 644 645 if (csr != SBIC_CSR_SEL_TIMEO) 646 dev->sc_flags |= SBICF_SELECTED; 647 } 648 649 QPRINTF(("\n")); 650 651 return(csr == SBIC_CSR_SEL_TIMEO); 652 } 653 654 int 655 sbicxfstart(regs, len, phase, wait) 656 sbic_regmap_p regs; 657 int len, wait; 658 u_char phase; 659 { 660 u_char id; 661 662 if (phase == DATA_IN_PHASE || phase == MESG_IN_PHASE) { 663 GET_SBIC_selid (regs, id); 664 id |= SBIC_SID_FROM_SCSI; 665 SET_SBIC_selid (regs, id); 666 SBIC_TC_PUT (regs, (unsigned)len); 667 } else if (phase == DATA_OUT_PHASE || phase == MESG_OUT_PHASE 668 || phase == CMD_PHASE) 669 SBIC_TC_PUT (regs, (unsigned)len); 670 else 671 SBIC_TC_PUT (regs, 0); 672 QPRINTF(("sbicxfstart %d, %d, %d\n", len, phase, wait)); 673 674 return(1); 675 } 676 677 int 678 sbicxfout(regs, len, bp, phase) 679 sbic_regmap_p regs; 680 int len; 681 void *bp; 682 int phase; 683 { 684 u_char orig_csr, csr, asr, *buf; 685 int wait; 686 687 buf = bp; 688 wait = sbic_data_wait; 689 690 QPRINTF(("sbicxfout {%d} %02x %02x %02x %02x %02x " 691 "%02x %02x %02x %02x %02x\n", len, buf[0], buf[1], buf[2], 692 buf[3], buf[4], buf[5], buf[6], buf[7], buf[8], buf[9])); 693 694 GET_SBIC_csr (regs, orig_csr); 695 696 /* 697 * sigh.. WD-PROTO strikes again.. sending the command in one go 698 * causes the chip to lock up if talking to certain (misbehaving?) 699 * targets. Anyway, this procedure should work for all targets, but 700 * it's slightly slower due to the overhead 701 */ 702 WAIT_CIP (regs); 703 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 704 for (;len > 0; len--) { 705 GET_SBIC_asr (regs, asr); 706 while ((asr & SBIC_ASR_DBR) == 0) { 707 if ((asr & SBIC_ASR_INT) || --wait < 0) { 708 #ifdef DEBUG 709 if (sbic_debug) 710 printf("sbicxfout fail: l%d i%x w%d\n", 711 len, asr, wait); 712 #endif 713 return (len); 714 } 715 DELAY(1); 716 GET_SBIC_asr (regs, asr); 717 } 718 719 SET_SBIC_data (regs, *buf); 720 buf++; 721 } 722 723 QPRINTF(("sbicxfout done\n")); 724 /* 725 * this leaves with one csr to be read 726 */ 727 return(0); 728 } 729 730 void 731 sbicxfin(regs, len, bp) 732 sbic_regmap_p regs; 733 int len; 734 void *bp; 735 { 736 int wait; 737 u_char *obp, *buf; 738 u_char orig_csr, csr, asr; 739 740 wait = sbic_data_wait; 741 obp = bp; 742 buf = bp; 743 744 GET_SBIC_csr (regs, orig_csr); 745 746 QPRINTF(("sbicxfin %d, csr=%02x\n", len, orig_csr)); 747 748 WAIT_CIP (regs); 749 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 750 for (;len > 0; len--) { 751 GET_SBIC_asr (regs, asr); 752 while ((asr & SBIC_ASR_DBR) == 0) { 753 if ((asr & SBIC_ASR_INT) || --wait < 0) { 754 #ifdef DEBUG 755 if (sbic_debug) 756 printf("sbicxfin fail: l%d i%x w%d\n", 757 len, asr, wait); 758 #endif 759 return; 760 } 761 762 DELAY(1); 763 GET_SBIC_asr (regs, asr); 764 } 765 766 GET_SBIC_data (regs, *buf); 767 buf++; 768 } 769 770 QPRINTF(("sbicxfin {%d} %02x %02x %02x %02x %02x %02x " 771 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 772 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 773 774 /* this leaves with one csr to be read */ 775 } 776 777 778 /* 779 * SCSI 'immediate' command: issue a command to some SCSI device 780 * and get back an 'immediate' response (i.e., do programmed xfer 781 * to get the response data). 'cbuf' is a buffer containing a scsi 782 * command of length clen bytes. 'buf' is a buffer of length 'len' 783 * bytes for data. The transfer direction is determined by the device 784 * (i.e., by the scsi bus data xfer phase). If 'len' is zero, the 785 * command must supply no data. 'xferphase' is the bus phase the 786 * caller expects to happen after the command is issued. It should 787 * be one of DATA_IN_PHASE, DATA_OUT_PHASE or STATUS_PHASE. 788 */ 789 int 790 sbicicmd(dev, target, cbuf, clen, buf, len, xferphase) 791 struct sbic_softc *dev; 792 void *cbuf, *buf; 793 int clen, len; 794 u_char xferphase; 795 { 796 sbic_regmap_p regs; 797 u_char phase, csr, asr; 798 int wait; 799 800 regs = dev->sc_sbicp; 801 802 /* 803 * set the sbic into non-DMA mode 804 */ 805 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 806 807 retry_selection: 808 /* 809 * select the SCSI bus (it's an error if bus isn't free) 810 */ 811 if (sbicselectbus(dev, regs, target, dev->sc_scsiaddr)) 812 return(-1); 813 /* 814 * Wait for a phase change (or error) then let the device sequence 815 * us through the various SCSI phases. 816 */ 817 dev->sc_stat[0] = 0xff; 818 dev->sc_msg[0] = 0xff; 819 phase = CMD_PHASE; 820 821 new_phase: 822 wait = sbic_cmd_wait; 823 824 GET_SBIC_csr (regs, csr); 825 QPRINTF((">CSR:%02x<", csr)); 826 827 /* 828 * requesting some new phase 829 */ 830 if ((csr != 0xff) && (csr & 0xf0) && (csr & 0x08)) 831 phase = csr & PHASE; 832 else if ((csr == SBIC_CSR_DISC) || (csr == SBIC_CSR_DISC_1) 833 || (csr == SBIC_CSR_S_XFERRED)) { 834 dev->sc_flags &= ~SBICF_SELECTED; 835 GET_SBIC_cmd_phase (regs, phase); 836 if (phase == 0x60) 837 GET_SBIC_tlun (regs, dev->sc_stat[0]); 838 else 839 return(-1); 840 goto out; 841 } else { 842 sbicerror(dev, regs, csr); 843 goto abort; 844 } 845 846 switch (phase) { 847 case CMD_PHASE: 848 if (sbicxfstart (regs, clen, phase, wait)) 849 if (sbicxfout (regs, clen, cbuf, phase)) 850 goto abort; 851 phase = xferphase; 852 break; 853 case DATA_IN_PHASE: 854 if (len <= 0) 855 goto abort; 856 wait = sbic_data_wait; 857 if (sbicxfstart(regs, len, phase, wait)) 858 sbicxfin(regs, len, buf); 859 phase = STATUS_PHASE; 860 break; 861 case MESG_IN_PHASE: 862 if (sbicxfstart(regs, sizeof(dev->sc_msg), phase, wait) == 0) 863 break; 864 dev->sc_msg[0] = 0xff; 865 sbicxfin(regs, sizeof(dev->sc_msg), dev->sc_msg); 866 /* 867 * get the command completion interrupt, or we 868 * can't send a new command (LCI) 869 */ 870 SBIC_WAIT(regs, SBIC_ASR_INT, wait); 871 GET_SBIC_csr(regs, csr); 872 #ifdef DEBUG 873 if (sync_debug) 874 printf("msgin done csr 0x%x\n", csr); 875 #endif 876 /* 877 * test whether this is a reply to our sync 878 * request 879 */ 880 if (dev->sc_msg[0] == MSG_EXT_MESSAGE && dev->sc_msg[1] == 3 881 && dev->sc_msg[2] == MSG_SYNC_REQ) { 882 883 dev->sc_sync[target].period = sbicfromscsiperiod(dev, 884 regs, dev->sc_msg[3]); 885 dev->sc_sync[target].offset = dev->sc_msg[4]; 886 dev->sc_sync[target].state = SYNC_DONE; 887 SET_SBIC_syn(regs, SBIC_SYN(dev->sc_sync[target].offset, 888 dev->sc_sync[target].period)); 889 /* ACK the message */ 890 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 891 WAIT_CIP(regs); 892 phase = CMD_PHASE; /* or whatever */ 893 printf("%s: target %d now synchronous," 894 " period=%dns, offset=%d.\n", 895 dev->sc_dev.dv_xname, target, dev->sc_msg[3] * 4, 896 dev->sc_msg[4]); 897 } else if (dev->sc_msg[0] == MSG_REJECT 898 && dev->sc_sync[target].state == SYNC_SENT) { 899 #ifdef DEBUG 900 if (sync_debug) 901 printf("target %d rejected sync, going async\n", 902 target); 903 #endif 904 dev->sc_sync[target].period = sbic_min_period; 905 dev->sc_sync[target].offset = 0; 906 dev->sc_sync[target].state = SYNC_DONE; 907 SET_SBIC_syn(regs, SBIC_SYN(dev->sc_sync[target].offset, 908 dev->sc_sync[target].period)); 909 /* ACK the message */ 910 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 911 WAIT_CIP(regs); 912 phase = CMD_PHASE; /* or whatever */ 913 } else if (dev->sc_msg[0] == MSG_REJECT) { 914 /* 915 * we'll never REJECt a REJECT message.. 916 */ 917 /* ACK the message */ 918 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 919 WAIT_CIP(regs); 920 phase = CMD_PHASE; /* or whatever */ 921 } else if (dev->sc_msg[0] == MSG_CMD_COMPLETE) { 922 /* !! KLUDGE ALERT !! quite a few drives don't seem to 923 * really like the current way of sending the 924 * sync-handshake together with the ident-message, and 925 * they react by sending command-complete and 926 * disconnecting right after returning the valid sync 927 * handshake. So, all I can do is reselect the drive, 928 * and hope it won't disconnect again. I don't think 929 * this is valid behavior, but I can't help fixing a 930 * problem that apparently exists. 931 * 932 * Note: we should not get here on `normal' command 933 * completion, as that condition is handled by the 934 * high-level sel&xfer resume command used to walk 935 * thru status/cc-phase. 936 */ 937 938 #ifdef DEBUG 939 if (sync_debug) 940 printf ("GOT CMD-COMPLETE! %d acting weird.." 941 " waiting for disconnect...\n", target); 942 #endif 943 /* ACK the message */ 944 SET_SBIC_cmd (regs, SBIC_CMD_CLR_ACK); 945 WAIT_CIP(regs); 946 947 /* wait for disconnect */ 948 while (csr != SBIC_CSR_DISC && 949 csr != SBIC_CSR_DISC_1) { 950 DELAY(1); 951 GET_SBIC_csr(regs, csr); 952 } 953 #ifdef DEBUG 954 if (sync_debug) 955 printf ("ok.\nRetrying selection.\n"); 956 #endif 957 dev->sc_flags &= ~SBICF_SELECTED; 958 goto retry_selection; 959 } else { 960 #ifdef DEBUG 961 if (sbic_debug || sync_debug) 962 printf ("Rejecting message 0x%02x\n", 963 dev->sc_msg[0]); 964 #endif 965 /* prepare to reject the message, NACK */ 966 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 967 WAIT_CIP(regs); 968 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 969 WAIT_CIP(regs); 970 phase = MESG_OUT_PHASE; 971 } 972 break; 973 974 case MESG_OUT_PHASE: 975 #ifdef DEBUG 976 if (sync_debug) 977 printf ("sending REJECT msg to last msg.\n"); 978 #endif 979 /* 980 * should only get here on reject, 981 * since it's always US that 982 * initiate a sync transfer 983 */ 984 SEND_BYTE(regs, MSG_REJECT); 985 phase = STATUS_PHASE; 986 break; 987 case DATA_OUT_PHASE: 988 if (len <= 0) 989 goto abort; 990 wait = sbic_data_wait; 991 if (sbicxfstart(regs, len, phase, wait)) 992 if (sbicxfout (regs, len, buf, phase)) 993 goto abort; 994 phase = STATUS_PHASE; 995 break; 996 case STATUS_PHASE: 997 /* 998 * the sbic does the status/cmd-complete reading ok, 999 * so do this with its hi-level commands. 1000 */ 1001 SBIC_TC_PUT(regs, 0); 1002 SET_SBIC_cmd_phase(regs, 0x46); 1003 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1004 phase = BUS_FREE_PHASE; 1005 break; 1006 case BUS_FREE_PHASE: 1007 goto out; 1008 default: 1009 printf("%s: unexpected phase %d in icmd from %d\n", 1010 dev->sc_dev.dv_xname, phase, target); 1011 goto abort; 1012 } 1013 1014 /* 1015 * make sure the last command was taken, 1016 * ie. we're not hunting after an ignored command.. 1017 */ 1018 GET_SBIC_asr(regs, asr); 1019 if (asr & SBIC_ASR_LCI) 1020 goto abort; 1021 1022 /* tapes may take a loooong time.. */ 1023 while (asr & SBIC_ASR_BSY) { 1024 DELAY(1); 1025 GET_SBIC_asr(regs, asr); 1026 } 1027 1028 /* 1029 * wait for last command to complete 1030 */ 1031 SBIC_WAIT (regs, SBIC_ASR_INT, wait); 1032 1033 /* 1034 * do it again 1035 */ 1036 goto new_phase; 1037 abort: 1038 sbicabort(dev, regs, "icmd"); 1039 out: 1040 QPRINTF(("=STS:%02x=", dev->sc_stat[0])); 1041 return(dev->sc_stat[0]); 1042 } 1043 1044 /* 1045 * Finish SCSI xfer command: After the completion interrupt from 1046 * a read/write operation, sequence through the final phases in 1047 * programmed i/o. This routine is a lot like sbicicmd except we 1048 * skip (and don't allow) the select, cmd out and data in/out phases. 1049 */ 1050 void 1051 sbicxfdone(dev, regs, target) 1052 struct sbic_softc *dev; 1053 sbic_regmap_p regs; 1054 int target; 1055 { 1056 u_char phase, csr; 1057 int s; 1058 1059 QPRINTF(("{")); 1060 s = splbio(); 1061 1062 /* 1063 * have the sbic complete on its own 1064 */ 1065 SBIC_TC_PUT(regs, 0); 1066 SET_SBIC_cmd_phase(regs, 0x46); 1067 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1068 1069 do { 1070 SBIC_WAIT (regs, SBIC_ASR_INT, 0); 1071 GET_SBIC_csr (regs, csr); 1072 QPRINTF(("%02x:", csr)); 1073 } while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) 1074 && (csr != SBIC_CSR_S_XFERRED)); 1075 1076 dev->sc_flags &= ~SBICF_SELECTED; 1077 1078 GET_SBIC_cmd_phase (regs, phase); 1079 QPRINTF(("}%02x", phase)); 1080 if (phase == 0x60) 1081 GET_SBIC_tlun(regs, dev->sc_stat[0]); 1082 else 1083 sbicerror(dev, regs, csr); 1084 1085 QPRINTF(("=STS:%02x=\n", dev->sc_stat[0])); 1086 splx(s); 1087 } 1088 1089 int 1090 sbicgo(dev, xs) 1091 struct sbic_softc *dev; 1092 struct scsi_xfer *xs; 1093 { 1094 int i, dmaflags, count, tcount, target; 1095 u_char phase, csr, asr, cmd, *addr; 1096 sbic_regmap_p regs; 1097 struct dma_chain *dcp; 1098 char *dmaend; 1099 int wait; 1100 1101 target = xs->sc_link->target; 1102 count = xs->datalen; 1103 addr = xs->data; 1104 1105 regs = dev->sc_sbicp; 1106 dmaend = NULL; 1107 1108 /* 1109 * set the sbic into DMA mode 1110 */ 1111 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI | 1112 SBIC_MACHINE_DMA_MODE); 1113 1114 /* 1115 * select the SCSI bus (it's an error if bus isn't free) 1116 */ 1117 if (sbicselectbus(dev, regs, target, dev->sc_scsiaddr)) { 1118 dev->sc_dmafree(dev); 1119 return(-1); 1120 } 1121 1122 /* 1123 * Wait for a phase change (or error) then let the device 1124 * sequence us through command phase (we may have to take 1125 * a msg in/out before doing the command). If the disk has 1126 * to do a seek, it may be a long time until we get a change 1127 * to data phase so, in the absense of an explicit phase 1128 * change, we assume data phase will be coming up and tell 1129 * the SPC to start a transfer whenever it does. We'll get 1130 * a service required interrupt later if this assumption is 1131 * wrong. Otherwise we'll get a service required int when 1132 * the transfer changes to status phase. 1133 */ 1134 phase = CMD_PHASE; 1135 1136 new_phase: 1137 wait = sbic_cmd_wait; 1138 switch (phase) { 1139 case CMD_PHASE: 1140 if (sbicxfstart(regs, xs->cmdlen, phase, wait)) 1141 if (sbicxfout(regs, xs->cmdlen, xs->cmd, phase)) 1142 goto abort; 1143 break; 1144 case MESG_IN_PHASE: 1145 if (sbicxfstart(regs, sizeof(dev->sc_msg), phase, wait) == 0) 1146 break; 1147 1148 sbicxfin(regs, sizeof(dev->sc_msg), dev->sc_msg); 1149 /* 1150 * prepare to reject any mesgin, 1151 * no matter what it might be.. 1152 */ 1153 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 1154 WAIT_CIP(regs); 1155 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 1156 phase = MESG_OUT_PHASE; 1157 break; 1158 case MESG_OUT_PHASE: 1159 SEND_BYTE(regs, MSG_REJECT); 1160 phase = STATUS_PHASE; 1161 break; 1162 case DATA_IN_PHASE: 1163 case DATA_OUT_PHASE: 1164 goto out; 1165 /* 1166 * status phase can happen, if the issued read/write command 1167 * is illegal (for example, reading after EOT on tape) and the 1168 * device doesn't even go to data in/out phase. So handle this 1169 * here normally, instead of going thru abort-handling. 1170 */ 1171 case STATUS_PHASE: 1172 dev->sc_dmafree(dev); 1173 sbicxfdone(dev, regs, target); 1174 dev->sc_flags &= ~(SBICF_INDMA | SBICF_BBUF); 1175 sbic_scsidone(dev, dev->sc_stat[0]); 1176 return(0); 1177 default: 1178 printf("%s: unexpected phase %d in go from %d\n", phase, 1179 dev->sc_dev.dv_xname, target); 1180 goto abort; 1181 } 1182 1183 /* 1184 * make sure the last command was taken, 1185 * ie. we're not hunting after an ignored command.. 1186 */ 1187 GET_SBIC_asr(regs, asr); 1188 if (asr & SBIC_ASR_LCI) 1189 goto abort; 1190 1191 /* 1192 * tapes may take a loooong time.. 1193 */ 1194 while (asr & SBIC_ASR_BSY) { 1195 DELAY(1); 1196 GET_SBIC_asr(regs, asr); 1197 } 1198 1199 if (wait <= 0) 1200 goto abort; 1201 1202 /* 1203 * wait for last command to complete 1204 */ 1205 SBIC_WAIT(regs, SBIC_ASR_INT, wait); 1206 1207 GET_SBIC_csr(regs, csr); 1208 QPRINTF((">CSR:%02x<", csr)); 1209 1210 /* 1211 * requesting some new phase 1212 */ 1213 if ((csr != 0xff) && (csr & 0xf0) && (csr & 0x08)) 1214 phase = csr & PHASE; 1215 else { 1216 sbicerror(dev, regs, csr); 1217 goto abort; 1218 } 1219 /* 1220 * start again with for new phase 1221 */ 1222 goto new_phase; 1223 out: 1224 dmaflags = 0; 1225 if (xs->flags & SCSI_DATA_IN) 1226 dmaflags |= DMAGO_READ; 1227 1228 if (count > MAXPHYS) 1229 printf("sbicgo: bp->b_bcount > MAXPHYS %08x\n", count); 1230 1231 if (dev->sc_flags & SBICF_BADDMA && 1232 sbiccheckdmap(addr, count, dev->sc_dmamask)) { 1233 /* 1234 * need to bounce the dma. 1235 */ 1236 if (dmaflags & DMAGO_READ) { 1237 dev->sc_flags |= SBICF_BBUF; 1238 dev->sc_dmausrbuf = addr; 1239 dev->sc_dmausrlen = count; 1240 } else { /* write: copy to dma buffer */ 1241 bcopy (addr, dev->sc_dmabuffer, count); 1242 } 1243 addr = dev->sc_dmabuffer; /* and use dma buffer */ 1244 } 1245 1246 #ifdef DEBUG 1247 if (sbic_dma_debug & DDB_FOLLOW) 1248 printf("sbicgo(%d, %x, %x, %x)\n", dev->sc_dev.dv_unit, 1249 addr, count, dmaflags); 1250 #endif 1251 /* 1252 * Build the DMA chain 1253 */ 1254 for (dcp = dev->sc_chain; count > 0; dcp++) { 1255 dcp->dc_addr = (char *) kvtop(addr); 1256 if (count < (tcount = NBPG - ((int)addr & PGOFSET))) 1257 tcount = count; 1258 addr += tcount; 1259 count -= tcount; 1260 dcp->dc_count = tcount >> 1; 1261 1262 /* 1263 * check if contigous, if not mark new end 1264 * else increment end and count on previous. 1265 */ 1266 if (dcp->dc_addr != dmaend) 1267 dmaend = dcp->dc_addr + tcount; 1268 else { 1269 dcp--; 1270 dmaend += tcount; 1271 dcp->dc_count += tcount >> 1; 1272 } 1273 } 1274 1275 dev->sc_cur = dev->sc_chain; 1276 dev->sc_last = --dcp; 1277 dev->sc_tcnt = dev->sc_cur->dc_count << 1; 1278 1279 #ifdef DEBUG 1280 if (sbic_dma_debug & DDB_IO) { 1281 for (dcp = dev->sc_chain; dcp <= dev->sc_last; dcp++) 1282 printf(" %d: %d@%x\n", dcp-dev->sc_chain, 1283 dcp->dc_count, dcp->dc_addr); 1284 } 1285 #endif 1286 1287 /* 1288 * push the data cash 1289 */ 1290 DCIS(); 1291 1292 /* 1293 * dmago() also enables interrupts for the sbic 1294 */ 1295 i = dev->sc_dmago(dev, addr, xs->datalen, dmaflags); 1296 1297 SBIC_TC_PUT(regs, (unsigned)i); 1298 SET_SBIC_cmd(regs, SBIC_CMD_XFER_INFO); 1299 1300 return(0); 1301 1302 abort: 1303 sbicabort(dev, regs, "go"); 1304 dev->sc_dmafree(dev); 1305 return(-1); 1306 } 1307 1308 1309 int 1310 sbicintr(dev) 1311 struct sbic_softc *dev; 1312 { 1313 sbic_regmap_p regs; 1314 u_char asr, csr; 1315 int i; 1316 1317 regs = dev->sc_sbicp; 1318 1319 /* 1320 * pending interrupt? 1321 */ 1322 GET_SBIC_asr (regs, asr); 1323 if ((asr & SBIC_ASR_INT) == 0) 1324 return(0); 1325 1326 GET_SBIC_csr(regs, csr); 1327 QPRINTF(("[0x%x]", csr)); 1328 1329 if (csr == (SBIC_CSR_XFERRED|STATUS_PHASE) 1330 || csr == (SBIC_CSR_MIS|STATUS_PHASE) 1331 || csr == (SBIC_CSR_MIS_1|STATUS_PHASE) 1332 || csr == (SBIC_CSR_MIS_2|STATUS_PHASE)) { 1333 /* 1334 * this should be the normal i/o completion case. 1335 * get the status & cmd complete msg then let the 1336 * device driver look at what happened. 1337 */ 1338 sbicxfdone(dev, regs, dev->sc_xs->sc_link->target); 1339 if (dev->sc_flags & SBICF_BBUF) 1340 bcopy(dev->sc_dmabuffer, dev->sc_dmausrbuf, 1341 dev->sc_dmausrlen); 1342 dev->sc_flags &= ~(SBICF_INDMA | SBICF_BBUF); 1343 dev->sc_dmafree(dev); 1344 sbic_scsidone(dev, dev->sc_stat[0]); 1345 } else if (csr == (SBIC_CSR_XFERRED|DATA_OUT_PHASE) 1346 || csr == (SBIC_CSR_XFERRED|DATA_IN_PHASE) 1347 || csr == (SBIC_CSR_MIS|DATA_OUT_PHASE) 1348 || csr == (SBIC_CSR_MIS|DATA_IN_PHASE) 1349 || csr == (SBIC_CSR_MIS_1|DATA_OUT_PHASE) 1350 || csr == (SBIC_CSR_MIS_1|DATA_IN_PHASE) 1351 || csr == (SBIC_CSR_MIS_2|DATA_OUT_PHASE) 1352 || csr == (SBIC_CSR_MIS_2|DATA_IN_PHASE)) { 1353 /* 1354 * do scatter-gather dma 1355 * hacking the controller chip, ouch.. 1356 */ 1357 /* 1358 * set next dma addr and dec count 1359 */ 1360 dev->sc_cur->dc_addr += dev->sc_tcnt; 1361 dev->sc_cur->dc_count -= (dev->sc_tcnt >> 1); 1362 1363 if (dev->sc_cur->dc_count == 0) 1364 ++dev->sc_cur; /* advance to next segment */ 1365 1366 i = dev->sc_dmanext(dev); 1367 SBIC_TC_PUT(regs, (unsigned)i); 1368 SET_SBIC_cmd(regs, SBIC_CMD_XFER_INFO); 1369 } else { 1370 /* 1371 * Something unexpected happened -- deal with it. 1372 */ 1373 dev->sc_dmastop(dev); 1374 sbicerror(dev, regs, csr); 1375 sbicabort(dev, regs, "intr"); 1376 if (dev->sc_flags & SBICF_INDMA) { 1377 dev->sc_flags &= ~(SBICF_INDMA | SBICF_BBUF); 1378 dev->sc_dmafree(dev); 1379 sbic_scsidone(dev, -1); 1380 } 1381 } 1382 return(1); 1383 } 1384 1385 /* 1386 * Check if DMA can not be used with specified buffer 1387 */ 1388 1389 int 1390 sbiccheckdmap(bp, len, mask) 1391 void *bp; 1392 u_long len, mask; 1393 { 1394 u_char *buffer; 1395 u_long phy_buf; 1396 u_long phy_len; 1397 1398 buffer = bp; 1399 1400 if (len == 0) 1401 return(0); 1402 1403 while (len) { 1404 phy_buf = kvtop(buffer); 1405 if (len < (phy_len = NBPG - ((int) buffer & PGOFSET))) 1406 phy_len = len; 1407 if (phy_buf & mask) 1408 return(1); 1409 buffer += phy_len; 1410 len -= phy_len; 1411 } 1412 return(0); 1413 } 1414 1415 int 1416 sbictoscsiperiod(dev, regs, a) 1417 struct sbic_softc *dev; 1418 sbic_regmap_p regs; 1419 int a; 1420 { 1421 unsigned int fs; 1422 1423 /* 1424 * cycle = DIV / (2*CLK) 1425 * DIV = FS+2 1426 * best we can do is 200ns at 20Mhz, 2 cycles 1427 */ 1428 1429 GET_SBIC_myid(regs,fs); 1430 fs = (fs >>6) + 2; /* DIV */ 1431 fs = (fs * 10000) / (dev->sc_clkfreq<<1); /* Cycle, in ns */ 1432 if (a < 2) a = 8; /* map to Cycles */ 1433 return ((fs*a)>>2); /* in 4 ns units */ 1434 } 1435 1436 int 1437 sbicfromscsiperiod(dev, regs, p) 1438 struct sbic_softc *dev; 1439 sbic_regmap_p regs; 1440 int p; 1441 { 1442 register unsigned int fs, ret; 1443 1444 /* Just the inverse of the above */ 1445 1446 GET_SBIC_myid(regs,fs); 1447 fs = (fs >>6) + 2; /* DIV */ 1448 fs = (fs * 10000) / (dev->sc_clkfreq<<1); /* Cycle, in ns */ 1449 1450 ret = p << 2; /* in ns units */ 1451 ret = ret / fs; /* in Cycles */ 1452 if (ret < sbic_min_period) 1453 return(sbic_min_period); 1454 1455 /* verify rounding */ 1456 if (sbictoscsiperiod(dev, regs, ret) < p) 1457 ret++; 1458 return (ret >= 8) ? 0 : ret; 1459 } 1460 1461
Indexes created Fri Sep 26 20:09:58 GMT 2025