sbic.c revision 1.17
1 /* $NetBSD: sbic.c,v 1.17 1995/09/16 16:11:26 chopps Exp $ */ 2 3 /* 4 * Copyright (c) 1994 Christian E. Hopps 5 * Copyright (c) 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * Van Jacobson of Lawrence Berkeley Laboratory. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the University of 22 * California, Berkeley and its contributors. 23 * 4. Neither the name of the University nor the names of its contributors 24 * may be used to endorse or promote products derived from this software 25 * without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 37 * SUCH DAMAGE. 38 * 39 * @(#)scsi.c 7.5 (Berkeley) 5/4/91 40 */ 41 42 /* 43 * AMIGA AMD 33C93 scsi adaptor driver 44 */ 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/device.h> 49 #include <sys/kernel.h> /* For hz */ 50 #include <sys/disklabel.h> 51 #include <sys/dkstat.h> 52 #include <sys/buf.h> 53 #include <scsi/scsi_all.h> 54 #include <scsi/scsiconf.h> 55 #include <vm/vm.h> 56 #include <vm/vm_kern.h> 57 #include <vm/vm_page.h> 58 #include <machine/pmap.h> 59 #include <machine/cpu.h> 60 #include <amiga/amiga/device.h> 61 #include <amiga/amiga/custom.h> 62 #include <amiga/amiga/isr.h> 63 #include <amiga/dev/dmavar.h> 64 #include <amiga/dev/sbicreg.h> 65 #include <amiga/dev/sbicvar.h> 66 67 /* These are for bounce buffers */ 68 #include <amiga/amiga/cc.h> 69 #include <amiga/dev/zbusvar.h> 70 71 #include <vm/pmap.h> 72 73 /* Since I can't find this in any other header files */ 74 #define SCSI_PHASE(reg) (reg&0x07) 75 76 /* 77 * SCSI delays 78 * In u-seconds, primarily for state changes on the SPC. 79 */ 80 #define SBIC_CMD_WAIT 50000 /* wait per step of 'immediate' cmds */ 81 #define SBIC_DATA_WAIT 50000 /* wait per data in/out step */ 82 #define SBIC_INIT_WAIT 50000 /* wait per step (both) during init */ 83 84 #define b_cylin b_resid 85 #define SBIC_WAIT(regs, until, timeo) sbicwait(regs, until, timeo, __LINE__) 86 87 extern u_int kvtop(); 88 89 int sbicicmd __P((struct sbic_softc *, int, int, void *, int, void *, int)); 90 int sbicgo __P((struct sbic_softc *, struct scsi_xfer *)); 91 int sbicdmaok __P((struct sbic_softc *, struct scsi_xfer *)); 92 int sbicwait __P((sbic_regmap_p, char, int , int)); 93 int sbiccheckdmap __P((void *, u_long, u_long)); 94 int sbicselectbus __P((struct sbic_softc *, sbic_regmap_p, u_char, u_char, u_char)); 95 int sbicxfstart __P((sbic_regmap_p, int, u_char, int)); 96 int sbicxfout __P((sbic_regmap_p regs, int, void *, int)); 97 int sbicfromscsiperiod __P((struct sbic_softc *, sbic_regmap_p, int)); 98 int sbictoscsiperiod __P((struct sbic_softc *, sbic_regmap_p, int)); 99 int sbicintr __P((struct sbic_softc *)); 100 int sbicpoll __P((struct sbic_softc *)); 101 int sbicnextstate __P((struct sbic_softc *, u_char, u_char)); 102 int sbicmsgin __P((struct sbic_softc *)); 103 int sbicxfin __P((sbic_regmap_p regs, int, void *)); 104 int sbicabort __P((struct sbic_softc *, sbic_regmap_p, char *)); 105 void sbicxfdone __P((struct sbic_softc *, sbic_regmap_p, int)); 106 void sbicerror __P((struct sbic_softc *, sbic_regmap_p, u_char)); 107 void sbicstart __P((struct sbic_softc *)); 108 void sbicreset __P((struct sbic_softc *)); 109 void sbic_scsidone __P((struct sbic_acb *, int)); 110 void sbic_sched __P((struct sbic_softc *)); 111 void sbic_save_ptrs __P((struct sbic_softc *, sbic_regmap_p,int,int)); 112 void sbic_load_ptrs __P((struct sbic_softc *, sbic_regmap_p,int,int)); 113 114 /* 115 * Synch xfer parameters, and timing conversions 116 */ 117 int sbic_min_period = SBIC_SYN_MIN_PERIOD; /* in cycles = f(ICLK,FSn) */ 118 int sbic_max_offset = SBIC_SYN_MAX_OFFSET; /* pure number */ 119 120 int sbic_cmd_wait = SBIC_CMD_WAIT; 121 int sbic_data_wait = SBIC_DATA_WAIT; 122 int sbic_init_wait = SBIC_INIT_WAIT; 123 124 /* 125 * was broken before.. now if you want this you get it for all drives 126 * on sbic controllers. 127 */ 128 int sbic_inhibit_sync = 0; 129 int sbic_enable_reselect = 1; 130 int sbic_clock_override = 0; 131 int sbic_no_dma = 0; 132 int sbic_parallel_operations = 1; 133 134 #ifdef DEBUG 135 sbic_regmap_p debug_sbic_regs; 136 int sbicdma_ops = 0; /* total DMA operations */ 137 int sbicdma_bounces = 0; /* number operations using bounce buffer */ 138 int sbicdma_hits = 0; /* number of DMA chains that were contiguous */ 139 int sbicdma_misses = 0; /* number of DMA chains that were not contiguous */ 140 int sbicdma_saves = 0; 141 #define QPRINTF(a) if (sbic_debug > 1) printf a 142 int sbic_debug = 0; 143 int sync_debug = 0; 144 int sbic_dma_debug = 0; 145 int reselect_debug = 0; 146 int report_sense = 0; 147 int data_pointer_debug = 0; 148 u_char debug_asr, debug_csr, routine; 149 void sbictimeout __P((struct sbic_softc *dev)); 150 151 #define CSR_TRACE_SIZE 32 152 #if CSR_TRACE_SIZE 153 #define CSR_TRACE(w,c,a,x) do { \ 154 int s = splbio(); \ 155 csr_trace[csr_traceptr].whr = (w); csr_trace[csr_traceptr].csr = (c); \ 156 csr_trace[csr_traceptr].asr = (a); csr_trace[csr_traceptr].xtn = (x); \ 157 dma_cachectl(&csr_trace[csr_traceptr], sizeof(csr_trace[0])); \ 158 csr_traceptr = (csr_traceptr + 1) & (CSR_TRACE_SIZE - 1); \ 159 /* dma_cachectl(&csr_traceptr, sizeof(csr_traceptr));*/ \ 160 splx(s); \ 161 } while (0) 162 int csr_traceptr; 163 int csr_tracesize = CSR_TRACE_SIZE; 164 struct { 165 u_char whr; 166 u_char csr; 167 u_char asr; 168 u_char xtn; 169 } csr_trace[CSR_TRACE_SIZE]; 170 #else 171 #define CSR_TRACE 172 #endif 173 174 #define SBIC_TRACE_SIZE 0 175 #if SBIC_TRACE_SIZE 176 #define SBIC_TRACE(dev) do { \ 177 int s = splbio(); \ 178 sbic_trace[sbic_traceptr].sp = &s; \ 179 sbic_trace[sbic_traceptr].line = __LINE__; \ 180 sbic_trace[sbic_traceptr].sr = s; \ 181 sbic_trace[sbic_traceptr].csr = csr_traceptr; \ 182 dma_cachectl(&sbic_trace[sbic_traceptr], sizeof(sbic_trace[0])); \ 183 sbic_traceptr = (sbic_traceptr + 1) & (SBIC_TRACE_SIZE - 1); \ 184 dma_cachectl(&sbic_traceptr, sizeof(sbic_traceptr)); \ 185 if (dev) dma_cachectl(dev, sizeof(*dev)); \ 186 splx(s); \ 187 } while (0) 188 int sbic_traceptr; 189 int sbic_tracesize = SBIC_TRACE_SIZE; 190 struct { 191 void *sp; 192 u_short line; 193 u_short sr; 194 int csr; 195 } sbic_trace[SBIC_TRACE_SIZE]; 196 #else 197 #define SBIC_TRACE 198 #endif 199 200 #else 201 #define QPRINTF 202 #define CSR_TRACE 203 #define SBIC_TRACE 204 #endif 205 206 /* 207 * default minphys routine for sbic based controllers 208 */ 209 void 210 sbic_minphys(bp) 211 struct buf *bp; 212 { 213 214 /* 215 * No max transfer at this level. 216 */ 217 minphys(bp); 218 } 219 220 /* 221 * Save DMA pointers. Take into account partial transfer. Shut down DMA. 222 */ 223 void 224 sbic_save_ptrs(dev, regs, target, lun) 225 struct sbic_softc *dev; 226 sbic_regmap_p regs; 227 int target, lun; 228 { 229 int count, asr, csr, s; 230 unsigned long ptr; 231 char *vptr; 232 struct sbic_acb* acb; 233 234 extern vm_offset_t vm_first_phys; 235 236 SBIC_TRACE(dev); 237 if( !dev->sc_cur ) return; 238 if( !(dev->sc_flags & SBICF_INDMA) ) return; /* DMA not active */ 239 240 s = splbio(); 241 242 acb = dev->sc_nexus; 243 count = -1; 244 do { 245 GET_SBIC_asr(regs, asr); 246 if( asr & SBIC_ASR_DBR ) { 247 printf("sbic_save_ptrs: asr %02x canceled!\n", asr); 248 splx(s); 249 SBIC_TRACE(dev); 250 return; 251 } 252 } while( asr & (SBIC_ASR_BSY|SBIC_ASR_CIP) ); 253 254 /* Save important state */ 255 /* must be done before dmastop */ 256 acb->sc_dmacmd = dev->sc_dmacmd; 257 SBIC_TC_GET(regs, count); 258 259 /* Shut down DMA ====CAREFUL==== */ 260 dev->sc_dmastop(dev); 261 dev->sc_flags &= ~SBICF_INDMA; 262 SBIC_TC_PUT(regs, 0); 263 264 #ifdef DEBUG 265 if(!count && sbic_debug) printf("%dcount0",target); 266 if(data_pointer_debug == -1) 267 printf("SBIC saving target %d data pointers from (%x,%x)%xASR:%02x", 268 target, dev->sc_cur->dc_addr, dev->sc_cur->dc_count, 269 acb->sc_dmacmd, asr); 270 #endif 271 272 /* Fixup partial xfers */ 273 acb->sc_kv.dc_addr += (dev->sc_tcnt - count); 274 acb->sc_kv.dc_count -= (dev->sc_tcnt - count); 275 acb->sc_pa.dc_addr += (dev->sc_tcnt - count); 276 acb->sc_pa.dc_count -= ((dev->sc_tcnt - count)>>1); 277 278 acb->sc_tcnt = dev->sc_tcnt = count; 279 #ifdef DEBUG 280 if(data_pointer_debug) 281 printf(" at (%x,%x):%x\n", 282 dev->sc_cur->dc_addr, dev->sc_cur->dc_count,count); 283 sbicdma_saves++; 284 #endif 285 splx(s); 286 SBIC_TRACE(dev); 287 } 288 289 290 /* 291 * DOES NOT RESTART DMA!!! 292 */ 293 void sbic_load_ptrs(dev, regs, target, lun) 294 struct sbic_softc *dev; 295 sbic_regmap_p regs; 296 int target, lun; 297 { 298 int i, s, asr, count; 299 char* vaddr, * paddr; 300 struct sbic_acb *acb; 301 302 SBIC_TRACE(dev); 303 acb = dev->sc_nexus; 304 if( !acb->sc_kv.dc_count ) { 305 /* No data to xfer */ 306 SBIC_TRACE(dev); 307 return; 308 } 309 310 s = splbio(); 311 312 dev->sc_last = dev->sc_cur = &acb->sc_pa; 313 dev->sc_tcnt = acb->sc_tcnt; 314 dev->sc_dmacmd = acb->sc_dmacmd; 315 316 #ifdef DEBUG 317 sbicdma_ops++; 318 #endif 319 if( !dev->sc_tcnt ) { 320 /* sc_tcnt == 0 implies end of segment */ 321 322 /* do kvm to pa mappings */ 323 paddr = acb->sc_pa.dc_addr = 324 (char *) kvtop(acb->sc_kv.dc_addr); 325 326 vaddr = acb->sc_kv.dc_addr; 327 count = acb->sc_kv.dc_count; 328 for(count = (NBPG - ((int)vaddr & PGOFSET)); 329 count < acb->sc_kv.dc_count 330 && (char*)kvtop(vaddr + count + 4) == paddr + count + 4; 331 count += NBPG); 332 /* If it's all contiguous... */ 333 if(count > acb->sc_kv.dc_count ) { 334 count = acb->sc_kv.dc_count; 335 #ifdef DEBUG 336 sbicdma_hits++; 337 #endif 338 } else { 339 #ifdef DEBUG 340 sbicdma_misses++; 341 #endif 342 } 343 acb->sc_tcnt = count; 344 acb->sc_pa.dc_count = count >> 1; 345 346 #ifdef DEBUG 347 if(data_pointer_debug) 348 printf("DMA recalc:kv(%x,%x)pa(%x,%x)\n", 349 acb->sc_kv.dc_addr, 350 acb->sc_kv.dc_count, 351 acb->sc_pa.dc_addr, 352 acb->sc_tcnt); 353 #endif 354 } 355 splx(s); 356 #ifdef DEBUG 357 if(data_pointer_debug) 358 printf("SBIC restoring target %d data pointers at (%x,%x)%x\n", 359 target, dev->sc_cur->dc_addr, dev->sc_cur->dc_count, 360 dev->sc_dmacmd); 361 #endif 362 SBIC_TRACE(dev); 363 } 364 365 /* 366 * used by specific sbic controller 367 * 368 * it appears that the higher level code does nothing with LUN's 369 * so I will too. I could plug it in, however so could they 370 * in scsi_scsi_cmd(). 371 */ 372 int 373 sbic_scsicmd(xs) 374 struct scsi_xfer *xs; 375 { 376 struct sbic_acb *acb; 377 struct sbic_softc *dev; 378 struct scsi_link *slp; 379 int flags, s, stat; 380 381 slp = xs->sc_link; 382 dev = slp->adapter_softc; 383 SBIC_TRACE(dev); 384 flags = xs->flags; 385 386 if (flags & SCSI_DATA_UIO) 387 panic("sbic: scsi data uio requested"); 388 389 if (dev->sc_nexus && flags & SCSI_POLL) 390 panic("sbic_scsicmd: busy"); 391 392 if (slp->target == slp->adapter_target) 393 return ESCAPE_NOT_SUPPORTED; 394 395 s = splbio(); 396 acb = dev->free_list.tqh_first; 397 if (acb) 398 TAILQ_REMOVE(&dev->free_list, acb, chain); 399 splx(s); 400 401 if (acb == NULL) { 402 #ifdef DEBUG 403 printf("sbic_scsicmd: unable to queue request for target %d\n", 404 slp->target); 405 #ifdef DDB 406 Debugger(); 407 #endif 408 #endif 409 xs->error = XS_DRIVER_STUFFUP; 410 SBIC_TRACE(dev); 411 return(TRY_AGAIN_LATER); 412 } 413 414 acb->flags = ACB_ACTIVE; 415 if (flags & SCSI_DATA_IN) 416 acb->flags |= ACB_DATAIN; 417 acb->xs = xs; 418 bcopy(xs->cmd, &acb->cmd, xs->cmdlen); 419 acb->clen = xs->cmdlen; 420 acb->sc_kv.dc_addr = xs->data; 421 acb->sc_kv.dc_count = xs->datalen; 422 acb->pa_addr = xs->data ? (char *)kvtop(xs->data) : 0; /* XXXX check */ 423 424 if (flags & SCSI_POLL) { 425 s = splbio(); 426 /* 427 * This has major side effects -- it locks up the machine 428 */ 429 430 dev->sc_flags |= SBICF_ICMD; 431 do { 432 while(dev->sc_nexus) 433 sbicpoll(dev); 434 dev->sc_nexus = acb; 435 dev->sc_stat[0] = -1; 436 dev->sc_xs = xs; 437 dev->target = slp->target; 438 dev->lun = slp->lun; 439 stat = sbicicmd(dev, slp->target, slp->lun, 440 &acb->cmd, acb->clen, 441 acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 442 } while (dev->sc_nexus != acb); 443 sbic_scsidone(acb, stat); 444 445 splx(s); 446 SBIC_TRACE(dev); 447 return(COMPLETE); 448 } 449 450 s = splbio(); 451 TAILQ_INSERT_TAIL(&dev->ready_list, acb, chain); 452 453 if (dev->sc_nexus) { 454 splx(s); 455 SBIC_TRACE(dev); 456 return(SUCCESSFULLY_QUEUED); 457 } 458 459 /* 460 * nothing is active, try to start it now. 461 */ 462 sbic_sched(dev); 463 splx(s); 464 465 SBIC_TRACE(dev); 466 /* TODO: add sbic_poll to do SCSI_POLL operations */ 467 #if 0 468 if (flags & SCSI_POLL) 469 return(COMPLETE); 470 #endif 471 return(SUCCESSFULLY_QUEUED); 472 } 473 474 /* 475 * attempt to start the next available command 476 */ 477 void 478 sbic_sched(dev) 479 struct sbic_softc *dev; 480 { 481 struct scsi_xfer *xs; 482 struct scsi_link *slp; 483 struct sbic_acb *acb; 484 int flags, /*phase,*/ stat, i; 485 486 SBIC_TRACE(dev); 487 if (dev->sc_nexus) 488 return; /* a command is current active */ 489 490 SBIC_TRACE(dev); 491 for (acb = dev->ready_list.tqh_first; acb; acb = acb->chain.tqe_next) { 492 slp = acb->xs->sc_link; 493 i = slp->target; 494 if (!(dev->sc_tinfo[i].lubusy & (1 << slp->lun))) { 495 struct sbic_tinfo *ti = &dev->sc_tinfo[i]; 496 497 TAILQ_REMOVE(&dev->ready_list, acb, chain); 498 dev->sc_nexus = acb; 499 slp = acb->xs->sc_link; 500 ti = &dev->sc_tinfo[slp->target]; 501 ti->lubusy |= (1 << slp->lun); 502 acb->sc_pa.dc_addr = acb->pa_addr; /* XXXX check */ 503 break; 504 } 505 } 506 507 SBIC_TRACE(dev); 508 if (acb == NULL) 509 return; /* did not find an available command */ 510 511 dev->sc_xs = xs = acb->xs; 512 slp = xs->sc_link; 513 flags = xs->flags; 514 515 if (flags & SCSI_RESET) 516 sbicreset(dev); 517 518 #ifdef DEBUG 519 if( data_pointer_debug > 1 ) 520 printf("sbic_sched(%d,%d)\n",slp->target,slp->lun); 521 #endif 522 dev->sc_stat[0] = -1; 523 dev->target = slp->target; 524 dev->lun = slp->lun; 525 if ( flags & SCSI_POLL || ( !sbic_parallel_operations 526 && (/*phase == STATUS_PHASE ||*/ 527 sbicdmaok(dev, xs) == 0) ) ) 528 stat = sbicicmd(dev, slp->target, slp->lun, &acb->cmd, 529 acb->clen, acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 530 else if (sbicgo(dev, xs) == 0) { 531 SBIC_TRACE(dev); 532 return; 533 } else 534 stat = dev->sc_stat[0]; 535 536 sbic_scsidone(acb, stat); 537 SBIC_TRACE(dev); 538 } 539 540 void 541 sbic_scsidone(acb, stat) 542 struct sbic_acb *acb; 543 int stat; 544 { 545 struct scsi_xfer *xs; 546 struct scsi_link *slp; 547 struct sbic_softc *dev; 548 int s, dosched = 0; 549 550 xs = acb->xs; 551 slp = xs->sc_link; 552 dev = slp->adapter_softc; 553 SBIC_TRACE(dev); 554 #ifdef DIAGNOSTIC 555 if (acb == NULL || xs == NULL) { 556 printf("sbic_scsidone -- (%d,%d) no scsi_xfer\n", 557 dev->target, dev->lun); 558 #ifdef DDB 559 Debugger(); 560 #endif 561 return; 562 } 563 #endif 564 #if 1 565 if (((struct device *)(slp->device_softc))->dv_unit < dk_ndrive) 566 ++dk_xfer[((struct device *)(slp->device_softc))->dv_unit]; 567 #endif 568 /* 569 * is this right? 570 */ 571 xs->status = stat; 572 573 #ifdef DEBUG 574 if( data_pointer_debug > 1 ) 575 printf("scsidone: (%d,%d)->(%d,%d)%02x\n", 576 slp->target, slp->lun, 577 dev->target, dev->lun, stat); 578 if( xs->sc_link->target == dev->sc_link.adapter_target ) 579 panic("target == hostid"); 580 #endif 581 582 if (xs->error == XS_NOERROR && !(acb->flags & ACB_CHKSENSE)) { 583 if (stat == SCSI_CHECK) { 584 /* Schedule a REQUEST SENSE */ 585 struct scsi_sense *ss = (void *)&acb->cmd; 586 #ifdef DEBUG 587 if (report_sense) 588 printf("sbic_scsidone: autosense %02x targ %d lun %d", 589 acb->cmd.opcode, slp->target, slp->lun); 590 #endif 591 bzero(ss, sizeof(*ss)); 592 ss->opcode = REQUEST_SENSE; 593 ss->byte2 = slp->lun << 5; 594 ss->length = sizeof(struct scsi_sense_data); 595 acb->clen = sizeof(*ss); 596 acb->sc_kv.dc_addr = (char *)&xs->sense; 597 acb->sc_kv.dc_count = sizeof(struct scsi_sense_data); 598 acb->pa_addr = (char *)kvtop(&xs->sense); /* XXX check */ 599 acb->flags = ACB_ACTIVE | ACB_CHKSENSE | ACB_DATAIN; 600 TAILQ_INSERT_HEAD(&dev->ready_list, acb, chain); 601 dev->sc_tinfo[slp->target].lubusy &= 602 ~(1 << slp->lun); 603 dev->sc_tinfo[slp->target].senses++; 604 if (dev->sc_nexus == acb) { 605 dev->sc_nexus = NULL; 606 dev->sc_xs = NULL; 607 sbic_sched(dev); 608 } 609 SBIC_TRACE(dev); 610 return; 611 } 612 } 613 if (xs->error == XS_NOERROR && (acb->flags & ACB_CHKSENSE)) { 614 xs->error = XS_SENSE; 615 #ifdef DEBUG 616 if (report_sense) 617 printf(" => %02x %02x\n", xs->sense.extended_flags, 618 xs->sense.extended_extra_bytes[3]); 619 #endif 620 } else { 621 xs->resid = 0; /* XXXX */ 622 } 623 #if whataboutthisone 624 case SCSI_BUSY: 625 xs->error = XS_BUSY; 626 break; 627 #endif 628 xs->flags |= ITSDONE; 629 630 /* 631 * Remove the ACB from whatever queue it's on. We have to do a bit of 632 * a hack to figure out which queue it's on. Note that it is *not* 633 * necessary to cdr down the ready queue, but we must cdr down the 634 * nexus queue and see if it's there, so we can mark the unit as no 635 * longer busy. This code is sickening, but it works. 636 */ 637 if (acb == dev->sc_nexus) { 638 dev->sc_nexus = NULL; 639 dev->sc_xs = NULL; 640 dev->sc_tinfo[slp->target].lubusy &= ~(1<<slp->lun); 641 if (dev->ready_list.tqh_first) 642 dosched = 1; /* start next command */ 643 } else if (dev->ready_list.tqh_last == &acb->chain.tqe_next) { 644 TAILQ_REMOVE(&dev->ready_list, acb, chain); 645 } else { 646 register struct sbic_acb *acb2; 647 for (acb2 = dev->nexus_list.tqh_first; acb2; 648 acb2 = acb2->chain.tqe_next) { 649 if (acb2 == acb) { 650 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 651 dev->sc_tinfo[slp->target].lubusy 652 &= ~(1<<slp->lun); 653 break; 654 } 655 } 656 if (acb2) 657 ; 658 else if (acb->chain.tqe_next) { 659 TAILQ_REMOVE(&dev->ready_list, acb, chain); 660 } else { 661 printf("%s: can't find matching acb\n", 662 dev->sc_dev.dv_xname); 663 #ifdef DDB 664 Debugger(); 665 #endif 666 } 667 } 668 /* Put it on the free list. */ 669 acb->flags = ACB_FREE; 670 TAILQ_INSERT_HEAD(&dev->free_list, acb, chain); 671 672 dev->sc_tinfo[slp->target].cmds++; 673 674 scsi_done(xs); 675 676 if (dosched) 677 sbic_sched(dev); 678 SBIC_TRACE(dev); 679 } 680 681 int 682 sbicdmaok(dev, xs) 683 struct sbic_softc *dev; 684 struct scsi_xfer *xs; 685 { 686 if (sbic_no_dma || xs->datalen & 0x1 || (u_int)xs->data & 0x3) 687 return(0); 688 /* 689 * controller supports dma to any addresses? 690 */ 691 else if ((dev->sc_flags & SBICF_BADDMA) == 0) 692 return(1); 693 /* 694 * this address is ok for dma? 695 */ 696 else if (sbiccheckdmap(xs->data, xs->datalen, dev->sc_dmamask) == 0) 697 return(1); 698 /* 699 * we have a bounce buffer? 700 */ 701 else if (dev->sc_tinfo[xs->sc_link->target].bounce) 702 return(1); 703 /* 704 * try to get one 705 */ 706 else if (dev->sc_tinfo[xs->sc_link->target].bounce 707 = (char *)alloc_z2mem(MAXPHYS)) { 708 if (isztwomem(dev->sc_tinfo[xs->sc_link->target].bounce)) 709 printf("alloc ZII target %d bounce pa 0x%x\n", 710 xs->sc_link->target, 711 kvtop(dev->sc_tinfo[xs->sc_link->target].bounce)); 712 else if (dev->sc_tinfo[xs->sc_link->target].bounce) 713 printf("alloc CHIP target %d bounce pa 0x%x\n", 714 xs->sc_link->target, 715 PREP_DMA_MEM(dev->sc_tinfo[xs->sc_link->target].bounce)); 716 return(1); 717 } 718 719 return(0); 720 } 721 722 723 int 724 sbicwait(regs, until, timeo, line) 725 sbic_regmap_p regs; 726 char until; 727 int timeo; 728 int line; 729 { 730 u_char val; 731 int csr; 732 733 SBIC_TRACE((struct sbic_softc *)0); 734 if (timeo == 0) 735 timeo = 1000000; /* some large value.. */ 736 737 GET_SBIC_asr(regs,val); 738 while ((val & until) == 0) { 739 if (timeo-- == 0) { 740 GET_SBIC_csr(regs, csr); 741 printf("sbicwait TIMEO @%d with asr=x%x csr=x%x\n", 742 line, val, csr); 743 #if defined(DDB) && defined(DEBUG) 744 Debugger(); 745 #endif 746 return(val); /* Maybe I should abort */ 747 break; 748 } 749 DELAY(1); 750 GET_SBIC_asr(regs,val); 751 } 752 SBIC_TRACE((struct sbic_softc *)0); 753 return(val); 754 } 755 756 int 757 sbicabort(dev, regs, where) 758 struct sbic_softc *dev; 759 sbic_regmap_p regs; 760 char *where; 761 { 762 u_char csr, asr; 763 764 GET_SBIC_asr(regs, asr); 765 GET_SBIC_csr(regs, csr); 766 767 printf ("%s: abort %s: csr = 0x%02x, asr = 0x%02x\n", 768 dev->sc_dev.dv_xname, where, csr, asr); 769 770 771 #if 0 772 /* Clean up running command */ 773 if (dev->sc_nexus != NULL) { 774 dev->sc_nexus->xs->error = XS_DRIVER_STUFFUP; 775 sbic_scsidone(dev->sc_nexus, dev->sc_stat[0]); 776 } 777 while (acb = dev->nexus_list.tqh_first) { 778 acb->xs->error = XS_DRIVER_STUFFUP; 779 sbic_scsidone(acb, -1 /*acb->stat[0]*/); 780 } 781 #endif 782 783 /* Clean up chip itself */ 784 if (dev->sc_flags & SBICF_SELECTED) { 785 while( asr & SBIC_ASR_DBR ) { 786 /* sbic is jammed w/data. need to clear it */ 787 /* But we don't know what direction it needs to go */ 788 GET_SBIC_data(regs, asr); 789 printf("%s: abort %s: clearing data buffer 0x%02x\n", 790 dev->sc_dev.dv_xname, where, asr); 791 GET_SBIC_asr(regs, asr); 792 if( asr & SBIC_ASR_DBR ) /* Not the read direction, then */ 793 SET_SBIC_data(regs, asr); 794 GET_SBIC_asr(regs, asr); 795 } 796 WAIT_CIP(regs); 797 printf("%s: sbicabort - sending ABORT command\n", dev->sc_dev.dv_xname); 798 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 799 WAIT_CIP(regs); 800 801 GET_SBIC_asr(regs, asr); 802 if (asr & (SBIC_ASR_BSY|SBIC_ASR_LCI)) { 803 /* ok, get more drastic.. */ 804 805 printf("%s: sbicabort - asr %x, trying to reset\n", dev->sc_dev.dv_xname, asr); 806 sbicreset(dev); 807 dev->sc_flags &= ~SBICF_SELECTED; 808 return -1; 809 } 810 printf("%s: sbicabort - sending DISC command\n", dev->sc_dev.dv_xname); 811 SET_SBIC_cmd(regs, SBIC_CMD_DISC); 812 813 do { 814 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0); 815 GET_SBIC_csr (regs, csr); 816 CSR_TRACE('a',csr,asr,0); 817 } while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) 818 && (csr != SBIC_CSR_CMD_INVALID)); 819 820 /* lets just hope it worked.. */ 821 dev->sc_flags &= ~SBICF_SELECTED; 822 } 823 return -1; 824 } 825 826 827 /* 828 * Initialize driver-private structures 829 */ 830 831 void 832 sbicinit(dev) 833 struct sbic_softc *dev; 834 { 835 sbic_regmap_p regs; 836 u_int my_id, i, s; 837 u_char csr; 838 struct sbic_acb *acb; 839 840 regs = dev->sc_sbicp; 841 842 if ((dev->sc_flags & SBICF_ALIVE) == 0) { 843 TAILQ_INIT(&dev->ready_list); 844 TAILQ_INIT(&dev->nexus_list); 845 TAILQ_INIT(&dev->free_list); 846 dev->sc_nexus = NULL; 847 dev->sc_xs = NULL; 848 acb = dev->sc_acb; 849 bzero(acb, sizeof(dev->sc_acb)); 850 for (i = 0; i < sizeof(dev->sc_acb) / sizeof(*acb); i++) { 851 TAILQ_INSERT_TAIL(&dev->free_list, acb, chain); 852 acb++; 853 } 854 bzero(dev->sc_tinfo, sizeof(dev->sc_tinfo)); 855 #ifdef DEBUG 856 /* make sure timeout is really not needed */ 857 timeout((void *)sbictimeout, dev, 30 * hz); 858 #endif 859 860 } else panic("sbic: reinitializing driver!"); 861 862 dev->sc_flags |= SBICF_ALIVE; 863 dev->sc_flags &= ~SBICF_SELECTED; 864 865 sbicreset(dev); 866 } 867 868 void 869 sbicreset(dev) 870 struct sbic_softc *dev; 871 { 872 sbic_regmap_p regs; 873 u_int my_id, i, s; 874 u_char csr; 875 struct sbic_acb *acb; 876 877 regs = dev->sc_sbicp; 878 #if 0 879 if (dev->sc_flags & SBICF_ALIVE) { 880 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 881 WAIT_CIP(regs); 882 } 883 #else 884 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 885 WAIT_CIP(regs); 886 #endif 887 s = splbio(); 888 my_id = dev->sc_link.adapter_target & SBIC_ID_MASK; 889 890 /* Enable advanced mode */ 891 my_id |= SBIC_ID_EAF /*| SBIC_ID_EHP*/ ; 892 SET_SBIC_myid(regs, my_id); 893 894 /* 895 * Disable interrupts (in dmainit) then reset the chip 896 */ 897 SET_SBIC_cmd(regs, SBIC_CMD_RESET); 898 DELAY(25); 899 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 900 GET_SBIC_csr(regs, csr); /* clears interrupt also */ 901 902 if (dev->sc_clkfreq < 110) 903 my_id |= SBIC_ID_FS_8_10; 904 else if (dev->sc_clkfreq < 160) 905 my_id |= SBIC_ID_FS_12_15; 906 else if (dev->sc_clkfreq < 210) 907 my_id |= SBIC_ID_FS_16_20; 908 909 SET_SBIC_myid(regs, my_id); 910 911 /* 912 * Set up various chip parameters 913 */ 914 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI /* | SBIC_CTL_HSP */ 915 | SBIC_MACHINE_DMA_MODE); 916 /* 917 * don't allow (re)selection (SBIC_RID_ES) 918 * until we can handle target mode!! 919 */ 920 SET_SBIC_rselid(regs, SBIC_RID_ER); 921 SET_SBIC_syn(regs, 0); /* asynch for now */ 922 923 /* 924 * anything else was zeroed by reset 925 */ 926 splx(s); 927 928 #if 0 929 if ((dev->sc_flags & SBICF_ALIVE) == 0) { 930 TAILQ_INIT(&dev->ready_list); 931 TAILQ_INIT(&dev->nexus_list); 932 TAILQ_INIT(&dev->free_list); 933 dev->sc_nexus = NULL; 934 dev->sc_xs = NULL; 935 acb = dev->sc_acb; 936 bzero(acb, sizeof(dev->sc_acb)); 937 for (i = 0; i < sizeof(dev->sc_acb) / sizeof(*acb); i++) { 938 TAILQ_INSERT_TAIL(&dev->free_list, acb, chain); 939 acb++; 940 } 941 bzero(dev->sc_tinfo, sizeof(dev->sc_tinfo)); 942 } else { 943 if (dev->sc_nexus != NULL) { 944 dev->sc_nexus->xs->error = XS_DRIVER_STUFFUP; 945 sbic_scsidone(dev->sc_nexus, dev->sc_stat[0]); 946 } 947 while (acb = dev->nexus_list.tqh_first) { 948 acb->xs->error = XS_DRIVER_STUFFUP; 949 sbic_scsidone(acb, -1 /*acb->stat[0]*/); 950 } 951 } 952 953 dev->sc_flags |= SBICF_ALIVE; 954 #endif 955 dev->sc_flags &= ~SBICF_SELECTED; 956 } 957 958 void 959 sbicerror(dev, regs, csr) 960 struct sbic_softc *dev; 961 sbic_regmap_p regs; 962 u_char csr; 963 { 964 struct scsi_xfer *xs; 965 966 xs = dev->sc_xs; 967 968 #ifdef DIAGNOSTIC 969 if (xs == NULL) 970 panic("sbicerror"); 971 #endif 972 if (xs->flags & SCSI_SILENT) 973 return; 974 975 printf("%s: ", dev->sc_dev.dv_xname); 976 printf("csr == 0x%02x\n", csr); /* XXX */ 977 } 978 979 /* 980 * select the bus, return when selected or error. 981 */ 982 int 983 sbicselectbus(dev, regs, target, lun, our_addr) 984 struct sbic_softc *dev; 985 sbic_regmap_p regs; 986 u_char target, lun, our_addr; 987 { 988 u_char asr, csr, id; 989 990 SBIC_TRACE(dev); 991 QPRINTF(("sbicselectbus %d\n", target)); 992 993 /* 994 * if we're already selected, return (XXXX panic maybe?) 995 */ 996 if (dev->sc_flags & SBICF_SELECTED) { 997 SBIC_TRACE(dev); 998 return(1); 999 } 1000 1001 /* 1002 * issue select 1003 */ 1004 SBIC_TC_PUT(regs, 0); 1005 SET_SBIC_selid(regs, target); 1006 SET_SBIC_timeo(regs, SBIC_TIMEOUT(250,dev->sc_clkfreq)); 1007 1008 /* 1009 * set sync or async 1010 */ 1011 if (dev->sc_sync[target].state == SYNC_DONE) 1012 SET_SBIC_syn(regs, SBIC_SYN (dev->sc_sync[target].offset, 1013 dev->sc_sync[target].period)); 1014 else 1015 SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period)); 1016 1017 GET_SBIC_asr(regs, asr); 1018 if( asr & (SBIC_ASR_INT|SBIC_ASR_BSY) ) { 1019 /* This means we got ourselves reselected upon */ 1020 /* printf("sbicselectbus: INT/BSY asr %02x\n", asr);*/ 1021 #ifdef DDB 1022 /* Debugger();*/ 1023 #endif 1024 SBIC_TRACE(dev); 1025 return 1; 1026 } 1027 1028 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN); 1029 1030 /* 1031 * wait for select (merged from seperate function may need 1032 * cleanup) 1033 */ 1034 WAIT_CIP(regs); 1035 do { 1036 asr = SBIC_WAIT(regs, SBIC_ASR_INT | SBIC_ASR_LCI, 0); 1037 if (asr & SBIC_ASR_LCI) { 1038 #ifdef DEBUG 1039 if (reselect_debug) 1040 printf("sbicselectbus: late LCI asr %02x\n", asr); 1041 #endif 1042 SBIC_TRACE(dev); 1043 return 1; 1044 } 1045 GET_SBIC_csr (regs, csr); 1046 CSR_TRACE('s',csr,asr,target); 1047 QPRINTF(("%02x ", csr)); 1048 if( csr == SBIC_CSR_RSLT_NI || csr == SBIC_CSR_RSLT_IFY) { 1049 #ifdef DEBUG 1050 if(reselect_debug) 1051 printf("sbicselectbus: reselected asr %02x\n", asr); 1052 #endif 1053 /* We need to handle this now so we don't lock up later */ 1054 sbicnextstate(dev, csr, asr); 1055 SBIC_TRACE(dev); 1056 return 1; 1057 } 1058 if( csr == SBIC_CSR_SLT || csr == SBIC_CSR_SLT_ATN) { 1059 panic("sbicselectbus: target issued select!"); 1060 return 1; 1061 } 1062 } while (csr != (SBIC_CSR_MIS_2|MESG_OUT_PHASE) 1063 && csr != (SBIC_CSR_MIS_2|CMD_PHASE) && csr != SBIC_CSR_SEL_TIMEO); 1064 1065 /* Enable (or not) reselection */ 1066 if(!sbic_enable_reselect && dev->nexus_list.tqh_first == NULL) 1067 SET_SBIC_rselid (regs, 0); 1068 else 1069 SET_SBIC_rselid (regs, SBIC_RID_ER); 1070 1071 if (csr == (SBIC_CSR_MIS_2|CMD_PHASE)) { 1072 dev->sc_flags |= SBICF_SELECTED; /* device ignored ATN */ 1073 GET_SBIC_selid(regs, id); 1074 dev->target = id; 1075 GET_SBIC_tlun(regs,dev->lun); 1076 if( dev->lun & SBIC_TLUN_VALID ) 1077 dev->lun &= SBIC_TLUN_MASK; 1078 else 1079 dev->lun = lun; 1080 } else if (csr == (SBIC_CSR_MIS_2|MESG_OUT_PHASE)) { 1081 /* 1082 * Send identify message 1083 * (SCSI-2 requires an identify msg (?)) 1084 */ 1085 GET_SBIC_selid(regs, id); 1086 dev->target = id; 1087 GET_SBIC_tlun(regs,dev->lun); 1088 if( dev->lun & SBIC_TLUN_VALID ) 1089 dev->lun &= SBIC_TLUN_MASK; 1090 else 1091 dev->lun = lun; 1092 /* 1093 * handle drives that don't want to be asked 1094 * whether to go sync at all. 1095 */ 1096 if (sbic_inhibit_sync && dev->sc_sync[id].state == SYNC_START) { 1097 #ifdef DEBUG 1098 if (sync_debug) 1099 printf("Forcing target %d asynchronous.\n", id); 1100 #endif 1101 dev->sc_sync[id].offset = 0; 1102 dev->sc_sync[id].period = sbic_min_period; 1103 dev->sc_sync[id].state = SYNC_DONE; 1104 } 1105 1106 1107 if (dev->sc_sync[id].state != SYNC_START){ 1108 if( dev->sc_xs->flags & SCSI_POLL 1109 || (dev->sc_flags & SBICF_ICMD) 1110 || !sbic_enable_reselect ) 1111 SEND_BYTE (regs, MSG_IDENTIFY | lun); 1112 else 1113 SEND_BYTE (regs, MSG_IDENTIFY_DR | lun); 1114 } else { 1115 /* 1116 * try to initiate a sync transfer. 1117 * So compose the sync message we're going 1118 * to send to the target 1119 */ 1120 1121 #ifdef DEBUG 1122 if (sync_debug) 1123 printf("Sending sync request to target %d ... ", 1124 id); 1125 #endif 1126 /* 1127 * setup scsi message sync message request 1128 */ 1129 dev->sc_msg[0] = MSG_IDENTIFY | lun; 1130 dev->sc_msg[1] = MSG_EXT_MESSAGE; 1131 dev->sc_msg[2] = 3; 1132 dev->sc_msg[3] = MSG_SYNC_REQ; 1133 dev->sc_msg[4] = sbictoscsiperiod(dev, regs, 1134 sbic_min_period); 1135 dev->sc_msg[5] = sbic_max_offset; 1136 1137 if (sbicxfstart(regs, 6, MESG_OUT_PHASE, sbic_cmd_wait)) 1138 sbicxfout(regs, 6, dev->sc_msg, MESG_OUT_PHASE); 1139 1140 dev->sc_sync[id].state = SYNC_SENT; 1141 #ifdef DEBUG 1142 if (sync_debug) 1143 printf ("sent\n"); 1144 #endif 1145 } 1146 1147 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0); 1148 GET_SBIC_csr (regs, csr); 1149 CSR_TRACE('y',csr,asr,target); 1150 QPRINTF(("[%02x]", csr)); 1151 #ifdef DEBUG 1152 if (sync_debug && dev->sc_sync[id].state == SYNC_SENT) 1153 printf("csr-result of last msgout: 0x%x\n", csr); 1154 #endif 1155 1156 if (csr != SBIC_CSR_SEL_TIMEO) 1157 dev->sc_flags |= SBICF_SELECTED; 1158 } 1159 if (csr == SBIC_CSR_SEL_TIMEO) 1160 dev->sc_xs->error = XS_SELTIMEOUT; 1161 1162 QPRINTF(("\n")); 1163 1164 SBIC_TRACE(dev); 1165 return(csr == SBIC_CSR_SEL_TIMEO); 1166 } 1167 1168 int 1169 sbicxfstart(regs, len, phase, wait) 1170 sbic_regmap_p regs; 1171 int len, wait; 1172 u_char phase; 1173 { 1174 u_char id; 1175 1176 switch (phase) { 1177 case DATA_IN_PHASE: 1178 case MESG_IN_PHASE: 1179 GET_SBIC_selid (regs, id); 1180 id |= SBIC_SID_FROM_SCSI; 1181 SET_SBIC_selid (regs, id); 1182 SBIC_TC_PUT (regs, (unsigned)len); 1183 break; 1184 case DATA_OUT_PHASE: 1185 case MESG_OUT_PHASE: 1186 case CMD_PHASE: 1187 GET_SBIC_selid (regs, id); 1188 id &= ~SBIC_SID_FROM_SCSI; 1189 SET_SBIC_selid (regs, id); 1190 SBIC_TC_PUT (regs, (unsigned)len); 1191 break; 1192 default: 1193 SBIC_TC_PUT (regs, 0); 1194 } 1195 QPRINTF(("sbicxfstart %d, %d, %d\n", len, phase, wait)); 1196 1197 return(1); 1198 } 1199 1200 int 1201 sbicxfout(regs, len, bp, phase) 1202 sbic_regmap_p regs; 1203 int len; 1204 void *bp; 1205 int phase; 1206 { 1207 u_char orig_csr, csr, asr, *buf; 1208 int wait; 1209 1210 buf = bp; 1211 wait = sbic_data_wait; 1212 1213 QPRINTF(("sbicxfout {%d} %02x %02x %02x %02x %02x " 1214 "%02x %02x %02x %02x %02x\n", len, buf[0], buf[1], buf[2], 1215 buf[3], buf[4], buf[5], buf[6], buf[7], buf[8], buf[9])); 1216 1217 GET_SBIC_csr (regs, orig_csr); 1218 CSR_TRACE('>',orig_csr,0,0); 1219 1220 /* 1221 * sigh.. WD-PROTO strikes again.. sending the command in one go 1222 * causes the chip to lock up if talking to certain (misbehaving?) 1223 * targets. Anyway, this procedure should work for all targets, but 1224 * it's slightly slower due to the overhead 1225 */ 1226 WAIT_CIP (regs); 1227 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1228 for (;len > 0; len--) { 1229 GET_SBIC_asr (regs, asr); 1230 while ((asr & SBIC_ASR_DBR) == 0) { 1231 if ((asr & SBIC_ASR_INT) || --wait < 0) { 1232 #ifdef DEBUG 1233 if (sbic_debug) 1234 printf("sbicxfout fail: l%d i%x w%d\n", 1235 len, asr, wait); 1236 #endif 1237 return (len); 1238 } 1239 /* DELAY(1);*/ 1240 GET_SBIC_asr (regs, asr); 1241 } 1242 1243 SET_SBIC_data (regs, *buf); 1244 buf++; 1245 } 1246 SBIC_TC_GET(regs, len); 1247 QPRINTF(("sbicxfout done %d bytes\n", len)); 1248 /* 1249 * this leaves with one csr to be read 1250 */ 1251 return(0); 1252 } 1253 1254 /* returns # bytes left to read */ 1255 int 1256 sbicxfin(regs, len, bp) 1257 sbic_regmap_p regs; 1258 int len; 1259 void *bp; 1260 { 1261 int wait, read; 1262 u_char *obp, *buf; 1263 u_char orig_csr, csr, asr; 1264 1265 wait = sbic_data_wait; 1266 obp = bp; 1267 buf = bp; 1268 1269 GET_SBIC_csr (regs, orig_csr); 1270 CSR_TRACE('<',orig_csr,0,0); 1271 1272 QPRINTF(("sbicxfin %d, csr=%02x\n", len, orig_csr)); 1273 1274 WAIT_CIP (regs); 1275 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1276 for (;len > 0; len--) { 1277 GET_SBIC_asr (regs, asr); 1278 if((asr & SBIC_ASR_PE)) { 1279 #ifdef DEBUG 1280 printf("sbicxfin parity error: l%d i%x w%d\n", 1281 len, asr, wait); 1282 /* return ((unsigned long)buf - (unsigned long)bp); */ 1283 #ifdef DDB 1284 Debugger(); 1285 #endif 1286 #endif 1287 } 1288 while ((asr & SBIC_ASR_DBR) == 0) { 1289 if ((asr & SBIC_ASR_INT) || --wait < 0) { 1290 #ifdef DEBUG 1291 if (sbic_debug) { 1292 QPRINTF(("sbicxfin fail:{%d} %02x %02x %02x %02x %02x %02x " 1293 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1294 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1295 printf("sbicxfin fail: l%d i%x w%d\n", 1296 len, asr, wait); 1297 } 1298 #endif 1299 return len; 1300 } 1301 1302 if( ! asr & SBIC_ASR_BSY ) { 1303 GET_SBIC_csr(regs, csr); 1304 CSR_TRACE('<',csr,asr,len); 1305 QPRINTF(("[CSR%02xASR%02x]", csr, asr)); 1306 } 1307 1308 /* DELAY(1);*/ 1309 GET_SBIC_asr (regs, asr); 1310 } 1311 1312 GET_SBIC_data (regs, *buf); 1313 /* QPRINTF(("asr=%02x, csr=%02x, data=%02x\n", asr, csr, *buf));*/ 1314 buf++; 1315 } 1316 1317 QPRINTF(("sbicxfin {%d} %02x %02x %02x %02x %02x %02x " 1318 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1319 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1320 1321 /* this leaves with one csr to be read */ 1322 return len; 1323 } 1324 1325 /* 1326 * SCSI 'immediate' command: issue a command to some SCSI device 1327 * and get back an 'immediate' response (i.e., do programmed xfer 1328 * to get the response data). 'cbuf' is a buffer containing a scsi 1329 * command of length clen bytes. 'buf' is a buffer of length 'len' 1330 * bytes for data. The transfer direction is determined by the device 1331 * (i.e., by the scsi bus data xfer phase). If 'len' is zero, the 1332 * command must supply no data. 1333 */ 1334 int 1335 sbicicmd(dev, target, lun, cbuf, clen, buf, len) 1336 struct sbic_softc *dev; 1337 void *cbuf, *buf; 1338 int clen, len; 1339 { 1340 sbic_regmap_p regs; 1341 u_char phase, csr, asr; 1342 int wait, newtarget, cmd_sent, parity_err; 1343 struct sbic_acb *acb; 1344 1345 int discon; 1346 int i; 1347 1348 #define CSR_LOG_BUF_SIZE 0 1349 #if CSR_LOG_BUF_SIZE 1350 int bufptr; 1351 int csrbuf[CSR_LOG_BUF_SIZE]; 1352 bufptr=0; 1353 #endif 1354 1355 SBIC_TRACE(dev); 1356 regs = dev->sc_sbicp; 1357 acb = dev->sc_nexus; 1358 1359 /* Make sure pointers are OK */ 1360 dev->sc_last = dev->sc_cur = &acb->sc_pa; 1361 dev->sc_tcnt = acb->sc_tcnt = 0; 1362 acb->sc_pa.dc_count = 0; /* No DMA */ 1363 acb->sc_kv.dc_addr = buf; 1364 acb->sc_kv.dc_count = len; 1365 1366 #ifdef DEBUG 1367 routine = 3; 1368 debug_sbic_regs = regs; /* store this to allow debug calls */ 1369 if( data_pointer_debug > 1 ) 1370 printf("sbicicmd(%d,%d):%d\n", target, lun, 1371 acb->sc_kv.dc_count); 1372 #endif 1373 1374 /* 1375 * set the sbic into non-DMA mode 1376 */ 1377 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI /*| SBIC_CTL_HSP*/); 1378 1379 dev->sc_stat[0] = 0xff; 1380 dev->sc_msg[0] = 0xff; 1381 i = 1; /* pre-load */ 1382 1383 /* We're stealing the SCSI bus */ 1384 dev->sc_flags |= SBICF_ICMD; 1385 1386 do { 1387 /* 1388 * select the SCSI bus (it's an error if bus isn't free) 1389 */ 1390 if (!( dev->sc_flags & SBICF_SELECTED ) 1391 && sbicselectbus(dev, regs, target, lun, dev->sc_scsiaddr)) { 1392 /*printf("sbicicmd trying to select busy bus!\n");*/ 1393 dev->sc_flags &= ~SBICF_ICMD; 1394 return(-1); 1395 } 1396 1397 /* 1398 * Wait for a phase change (or error) then let the device sequence 1399 * us through the various SCSI phases. 1400 */ 1401 1402 wait = sbic_cmd_wait; 1403 1404 asr = GET_SBIC_asr (regs, asr); 1405 GET_SBIC_csr (regs, csr); 1406 CSR_TRACE('I',csr,asr,target); 1407 QPRINTF((">ASR:%02xCSR:%02x<", asr, csr)); 1408 1409 #if CSR_LOG_BUF_SIZE 1410 csrbuf[bufptr++] = csr; 1411 #endif 1412 1413 1414 switch (csr) { 1415 case SBIC_CSR_S_XFERRED: 1416 case SBIC_CSR_DISC: 1417 case SBIC_CSR_DISC_1: 1418 dev->sc_flags &= ~SBICF_SELECTED; 1419 GET_SBIC_cmd_phase (regs, phase); 1420 if (phase == 0x60) { 1421 GET_SBIC_tlun (regs, dev->sc_stat[0]); 1422 i = 0; /* done */ 1423 /* break; /* Bypass all the state gobldygook */ 1424 } else { 1425 #ifdef DEBUG 1426 if(reselect_debug>1) 1427 printf("sbicicmd: handling disconnect\n"); 1428 #endif 1429 i = SBIC_STATE_DISCONNECT; 1430 } 1431 break; 1432 1433 case SBIC_CSR_XFERRED|CMD_PHASE: 1434 case SBIC_CSR_MIS|CMD_PHASE: 1435 case SBIC_CSR_MIS_1|CMD_PHASE: 1436 case SBIC_CSR_MIS_2|CMD_PHASE: 1437 if (sbicxfstart(regs, clen, CMD_PHASE, sbic_cmd_wait)) 1438 if (sbicxfout(regs, clen, 1439 cbuf, CMD_PHASE)) 1440 i = sbicabort(dev, regs,"icmd sending cmd"); 1441 #if 0 1442 GET_SBIC_csr(regs, csr); /* Lets us reload tcount */ 1443 WAIT_CIP(regs); 1444 GET_SBIC_asr(regs, asr); 1445 CSR_TRACE('I',csr,asr,target); 1446 if( asr & (SBIC_ASR_BSY|SBIC_ASR_LCI|SBIC_ASR_CIP) ) 1447 printf("next: cmd sent asr %02x, csr %02x\n", 1448 asr, csr); 1449 #endif 1450 break; 1451 1452 #if 0 1453 case SBIC_CSR_XFERRED|DATA_OUT_PHASE: 1454 case SBIC_CSR_XFERRED|DATA_IN_PHASE: 1455 case SBIC_CSR_MIS|DATA_OUT_PHASE: 1456 case SBIC_CSR_MIS|DATA_IN_PHASE: 1457 case SBIC_CSR_MIS_1|DATA_OUT_PHASE: 1458 case SBIC_CSR_MIS_1|DATA_IN_PHASE: 1459 case SBIC_CSR_MIS_2|DATA_OUT_PHASE: 1460 case SBIC_CSR_MIS_2|DATA_IN_PHASE: 1461 if (acb->sc_kv.dc_count <= 0) 1462 i = sbicabort(dev, regs, "icmd out of data"); 1463 else { 1464 wait = sbic_data_wait; 1465 if (sbicxfstart(regs, 1466 acb->sc_kv.dc_count, 1467 SBIC_PHASE(csr), wait)) 1468 if (csr & 0x01) 1469 /* data in? */ 1470 i=sbicxfin(regs, 1471 acb->sc_kv.dc_count, 1472 acb->sc_kv.dc_addr); 1473 else 1474 i=sbicxfout(regs, 1475 acb->sc_kv.dc_count, 1476 acb->sc_kv.dc_addr, 1477 SBIC_PHASE(csr)); 1478 acb->sc_kv.dc_addr += 1479 (acb->sc_kv.dc_count - i); 1480 acb->sc_kv.dc_count = i; 1481 i = 1; 1482 } 1483 break; 1484 1485 #endif 1486 case SBIC_CSR_XFERRED|STATUS_PHASE: 1487 case SBIC_CSR_MIS|STATUS_PHASE: 1488 case SBIC_CSR_MIS_1|STATUS_PHASE: 1489 case SBIC_CSR_MIS_2|STATUS_PHASE: 1490 /* 1491 * the sbic does the status/cmd-complete reading ok, 1492 * so do this with its hi-level commands. 1493 */ 1494 #ifdef DEBUG 1495 if(sbic_debug) 1496 printf("SBICICMD status phase\n"); 1497 #endif 1498 SBIC_TC_PUT(regs, 0); 1499 SET_SBIC_cmd_phase(regs, 0x46); 1500 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1501 break; 1502 1503 #if THIS_IS_A_RESERVED_STATE 1504 case BUS_FREE_PHASE: /* This is not legal */ 1505 if( dev->sc_stat[0] != 0xff ) 1506 goto out; 1507 break; 1508 #endif 1509 1510 default: 1511 i = sbicnextstate(dev, csr, asr); 1512 } 1513 1514 /* 1515 * make sure the last command was taken, 1516 * ie. we're not hunting after an ignored command.. 1517 */ 1518 GET_SBIC_asr(regs, asr); 1519 1520 /* tapes may take a loooong time.. */ 1521 while (asr & SBIC_ASR_BSY){ 1522 if(asr & SBIC_ASR_DBR) { 1523 printf("sbicicmd: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", 1524 csr,asr); 1525 #ifdef DDB 1526 Debugger(); 1527 #endif 1528 /* SBIC is jammed */ 1529 /* DUNNO which direction */ 1530 /* Try old direction */ 1531 GET_SBIC_data(regs,i); 1532 GET_SBIC_asr(regs, asr); 1533 if( asr & SBIC_ASR_DBR) /* Wants us to write */ 1534 SET_SBIC_data(regs,i); 1535 } 1536 GET_SBIC_asr(regs, asr); 1537 } 1538 1539 /* 1540 * wait for last command to complete 1541 */ 1542 if (asr & SBIC_ASR_LCI) { 1543 printf("sbicicmd: last command ignored\n"); 1544 } 1545 else if( i == 1 ) /* Bsy */ 1546 SBIC_WAIT (regs, SBIC_ASR_INT, wait); 1547 1548 /* 1549 * do it again 1550 */ 1551 } while ( i > 0 && dev->sc_stat[0] == 0xff); 1552 1553 /* Sometimes we need to do an extra read of the CSR */ 1554 GET_SBIC_csr(regs, csr); 1555 CSR_TRACE('I',csr,asr,0xff); 1556 1557 #if CSR_LOG_BUF_SIZE 1558 if(reselect_debug>1) 1559 for(i=0; i<bufptr; i++) 1560 printf("CSR:%02x", csrbuf[i]); 1561 #endif 1562 1563 #ifdef DEBUG 1564 if(data_pointer_debug > 1) 1565 printf("sbicicmd done(%d,%d):%d =%d=\n", 1566 dev->target, lun, 1567 acb->sc_kv.dc_count, 1568 dev->sc_stat[0]); 1569 #endif 1570 1571 QPRINTF(("=STS:%02x=", dev->sc_stat[0])); 1572 dev->sc_flags &= ~SBICF_ICMD; 1573 1574 SBIC_TRACE(dev); 1575 return(dev->sc_stat[0]); 1576 } 1577 1578 /* 1579 * Finish SCSI xfer command: After the completion interrupt from 1580 * a read/write operation, sequence through the final phases in 1581 * programmed i/o. This routine is a lot like sbicicmd except we 1582 * skip (and don't allow) the select, cmd out and data in/out phases. 1583 */ 1584 void 1585 sbicxfdone(dev, regs, target) 1586 struct sbic_softc *dev; 1587 sbic_regmap_p regs; 1588 int target; 1589 { 1590 u_char phase, asr, csr; 1591 int s; 1592 1593 SBIC_TRACE(dev); 1594 QPRINTF(("{")); 1595 s = splbio(); 1596 1597 /* 1598 * have the sbic complete on its own 1599 */ 1600 SBIC_TC_PUT(regs, 0); 1601 SET_SBIC_cmd_phase(regs, 0x46); 1602 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1603 1604 do { 1605 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0); 1606 GET_SBIC_csr (regs, csr); 1607 CSR_TRACE('f',csr,asr,target); 1608 QPRINTF(("%02x:", csr)); 1609 } while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) 1610 && (csr != SBIC_CSR_S_XFERRED)); 1611 1612 dev->sc_flags &= ~SBICF_SELECTED; 1613 1614 GET_SBIC_cmd_phase (regs, phase); 1615 QPRINTF(("}%02x", phase)); 1616 if (phase == 0x60) 1617 GET_SBIC_tlun(regs, dev->sc_stat[0]); 1618 else 1619 sbicerror(dev, regs, csr); 1620 1621 QPRINTF(("=STS:%02x=\n", dev->sc_stat[0])); 1622 splx(s); 1623 SBIC_TRACE(dev); 1624 } 1625 1626 /* 1627 * No DMA chains 1628 */ 1629 1630 int 1631 sbicgo(dev, xs) 1632 struct sbic_softc *dev; 1633 struct scsi_xfer *xs; 1634 { 1635 int i, dmaflags, count, wait, usedma; 1636 u_char csr, asr, cmd, *addr; 1637 sbic_regmap_p regs; 1638 struct sbic_acb *acb; 1639 1640 SBIC_TRACE(dev); 1641 dev->target = xs->sc_link->target; 1642 dev->lun = xs->sc_link->lun; 1643 acb = dev->sc_nexus; 1644 regs = dev->sc_sbicp; 1645 1646 usedma = sbicdmaok(dev, xs); 1647 #ifdef DEBUG 1648 routine = 1; 1649 debug_sbic_regs = regs; /* store this to allow debug calls */ 1650 if( data_pointer_debug > 1 ) 1651 printf("sbicgo(%d,%d)\n", dev->target, dev->lun); 1652 #endif 1653 1654 /* 1655 * set the sbic into DMA mode 1656 */ 1657 if( usedma ) 1658 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI | 1659 SBIC_MACHINE_DMA_MODE); 1660 else 1661 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1662 1663 1664 /* 1665 * select the SCSI bus (it's an error if bus isn't free) 1666 */ 1667 if (sbicselectbus(dev, regs, dev->target, dev->lun, 1668 dev->sc_scsiaddr)) { 1669 /* printf("sbicgo: Trying to select busy bus!\n"); */ 1670 SBIC_TRACE(dev); 1671 return(0); /* Not done: needs to be rescheduled */ 1672 } 1673 dev->sc_stat[0] = 0xff; 1674 1675 /* 1676 * Calculate DMA chains now 1677 */ 1678 1679 dmaflags = 0; 1680 if (acb->flags & ACB_DATAIN) 1681 dmaflags |= DMAGO_READ; 1682 1683 1684 /* 1685 * Deal w/bounce buffers. 1686 */ 1687 1688 addr = acb->sc_kv.dc_addr; 1689 count = acb->sc_kv.dc_count; 1690 if (count && (char *)kvtop(addr) != acb->sc_pa.dc_addr) { /* XXXX check */ 1691 printf("sbic: DMA buffer mapping changed %x->%x\n", 1692 acb->sc_pa.dc_addr, kvtop(addr)); 1693 #ifdef DDB 1694 Debugger(); 1695 #endif 1696 } 1697 1698 #ifdef DEBUG 1699 ++sbicdma_ops; /* count total DMA operations */ 1700 #endif 1701 if (count && usedma && dev->sc_flags & SBICF_BADDMA && 1702 sbiccheckdmap(addr, count, dev->sc_dmamask)) { 1703 /* 1704 * need to bounce the dma. 1705 */ 1706 if (dmaflags & DMAGO_READ) { 1707 acb->flags |= ACB_BBUF; 1708 acb->sc_dmausrbuf = addr; 1709 acb->sc_dmausrlen = count; 1710 acb->sc_usrbufpa = (u_char *)kvtop(addr); 1711 if(!dev->sc_tinfo[dev->target].bounce) { 1712 printf("sbicgo: HELP! no bounce allocated for %d\n", 1713 dev->target); 1714 printf("xfer: (%x->%x,%x)\n", acb->sc_dmausrbuf, 1715 acb->sc_usrbufpa, acb->sc_dmausrlen); 1716 dev->sc_tinfo[xs->sc_link->target].bounce 1717 = (char *)alloc_z2mem(MAXPHYS); 1718 if (isztwomem(dev->sc_tinfo[xs->sc_link->target].bounce)) 1719 printf("alloc ZII target %d bounce pa 0x%x\n", 1720 xs->sc_link->target, 1721 kvtop(dev->sc_tinfo[xs->sc_link->target].bounce)); 1722 else if (dev->sc_tinfo[xs->sc_link->target].bounce) 1723 printf("alloc CHIP target %d bounce pa 0x%x\n", 1724 xs->sc_link->target, 1725 PREP_DMA_MEM(dev->sc_tinfo[xs->sc_link->target].bounce)); 1726 1727 printf("Allocating %d bounce at %x\n", 1728 dev->target, 1729 kvtop(dev->sc_tinfo[dev->target].bounce)); 1730 } 1731 } else { /* write: copy to dma buffer */ 1732 #ifdef DEBUG 1733 if(data_pointer_debug) 1734 printf("sbicgo: copying %x bytes to target %d bounce %x\n", 1735 count, dev->target, 1736 kvtop(dev->sc_tinfo[dev->target].bounce)); 1737 #endif 1738 bcopy (addr, dev->sc_tinfo[dev->target].bounce, count); 1739 } 1740 addr = dev->sc_tinfo[dev->target].bounce;/* and use dma buffer */ 1741 acb->sc_kv.dc_addr = addr; 1742 #ifdef DEBUG 1743 ++sbicdma_bounces; /* count number of bounced */ 1744 #endif 1745 } 1746 1747 /* 1748 * Allocate the DMA chain 1749 */ 1750 1751 /* Set start KVM addresses */ 1752 #if 0 1753 acb->sc_kv.dc_addr = addr; 1754 acb->sc_kv.dc_count = count; 1755 #endif 1756 1757 /* Mark end of segment */ 1758 acb->sc_tcnt = dev->sc_tcnt = 0; 1759 acb->sc_pa.dc_count = 0; 1760 1761 sbic_load_ptrs(dev, regs, dev->target, dev->lun); 1762 SBIC_TRACE(dev); 1763 /* Enable interrupts but don't do any DMA */ 1764 dev->sc_enintr(dev); 1765 if (usedma) { 1766 dev->sc_tcnt = dev->sc_dmago(dev, acb->sc_pa.dc_addr, 1767 acb->sc_pa.dc_count, 1768 dmaflags); 1769 #ifdef DEBUG 1770 dev->sc_dmatimo = 1; 1771 #endif 1772 } else 1773 dev->sc_dmacmd = 0; /* Don't use DMA */ 1774 dev->sc_flags |= SBICF_INDMA; 1775 /* SBIC_TC_PUT(regs, dev->sc_tcnt); /* XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX */ 1776 SBIC_TRACE(dev); 1777 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 1778 1779 /* 1780 * push the data cache ( I think this won't work (EH)) 1781 */ 1782 #if defined(M68040) 1783 if (mmutype == MMU_68040 && usedma && count) { 1784 dma_cachectl(addr, count); 1785 if (((u_int)addr & 0xF) || (((u_int)addr + count) & 0xF)) 1786 dev->sc_flags |= SBICF_DCFLUSH; 1787 } 1788 #endif 1789 1790 /* 1791 * enintr() also enables interrupts for the sbic 1792 */ 1793 #ifdef DEBUG 1794 if( data_pointer_debug > 1 ) 1795 printf("sbicgo dmago:%d(%x:%x)\n", 1796 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 1797 debug_asr = asr; 1798 debug_csr = csr; 1799 #endif 1800 1801 /* 1802 * Lets cycle a while then let the interrupt handler take over 1803 */ 1804 1805 asr = GET_SBIC_asr(regs, asr); 1806 do { 1807 GET_SBIC_csr(regs, csr); 1808 CSR_TRACE('g',csr,asr,dev->target); 1809 #ifdef DEBUG 1810 debug_csr = csr; 1811 routine = 1; 1812 #endif 1813 QPRINTF(("go[0x%x]", csr)); 1814 1815 i = sbicnextstate(dev, csr, asr); 1816 1817 WAIT_CIP(regs); 1818 GET_SBIC_asr(regs, asr); 1819 #ifdef DEBUG 1820 debug_asr = asr; 1821 #endif 1822 if(asr & SBIC_ASR_LCI) printf("sbicgo: LCI asr:%02x csr:%02x\n", 1823 asr,csr); 1824 } while( i == SBIC_STATE_RUNNING 1825 && asr & (SBIC_ASR_INT|SBIC_ASR_LCI) ); 1826 1827 CSR_TRACE('g',csr,asr,i<<4); 1828 SBIC_TRACE(dev); 1829 if (i == SBIC_STATE_DONE && dev->sc_stat[0] == 0xff) printf("sbicgo: done & stat = 0xff\n"); 1830 if (i == SBIC_STATE_DONE && dev->sc_stat[0] != 0xff) { 1831 /* if( i == SBIC_STATE_DONE && dev->sc_stat[0] ) { */ 1832 /* Did we really finish that fast? */ 1833 return 1; 1834 } 1835 return 0; 1836 } 1837 1838 1839 int 1840 sbicintr(dev) 1841 struct sbic_softc *dev; 1842 { 1843 sbic_regmap_p regs; 1844 struct dma_chain *df, *dl; 1845 u_char asr, csr, *tmpaddr; 1846 struct sbic_acb *acb; 1847 int i, newtarget, newlun; 1848 unsigned tcnt; 1849 1850 regs = dev->sc_sbicp; 1851 1852 /* 1853 * pending interrupt? 1854 */ 1855 GET_SBIC_asr (regs, asr); 1856 if ((asr & SBIC_ASR_INT) == 0) 1857 return(0); 1858 1859 SBIC_TRACE(dev); 1860 do { 1861 GET_SBIC_csr(regs, csr); 1862 CSR_TRACE('i',csr,asr,dev->target); 1863 #ifdef DEBUG 1864 debug_csr = csr; 1865 routine = 2; 1866 #endif 1867 QPRINTF(("intr[0x%x]", csr)); 1868 1869 i = sbicnextstate(dev, csr, asr); 1870 1871 WAIT_CIP(regs); 1872 GET_SBIC_asr(regs, asr); 1873 #ifdef DEBUG 1874 debug_asr = asr; 1875 #endif 1876 #if 0 1877 if(asr & SBIC_ASR_LCI) printf("sbicintr: LCI asr:%02x csr:%02x\n", 1878 asr,csr); 1879 #endif 1880 } while(i == SBIC_STATE_RUNNING && 1881 asr & (SBIC_ASR_INT|SBIC_ASR_LCI)); 1882 CSR_TRACE('i',csr,asr,i<<4); 1883 SBIC_TRACE(dev); 1884 return(1); 1885 } 1886 1887 /* 1888 * Run commands and wait for disconnect 1889 */ 1890 int 1891 sbicpoll(dev) 1892 struct sbic_softc *dev; 1893 { 1894 sbic_regmap_p regs; 1895 u_char asr, csr; 1896 struct sbic_pending* pendp; 1897 int i; 1898 unsigned tcnt; 1899 1900 SBIC_TRACE(dev); 1901 regs = dev->sc_sbicp; 1902 1903 do { 1904 GET_SBIC_asr (regs, asr); 1905 #ifdef DEBUG 1906 debug_asr = asr; 1907 #endif 1908 GET_SBIC_csr(regs, csr); 1909 CSR_TRACE('p',csr,asr,dev->target); 1910 #ifdef DEBUG 1911 debug_csr = csr; 1912 routine = 2; 1913 #endif 1914 QPRINTF(("poll[0x%x]", csr)); 1915 1916 i = sbicnextstate(dev, csr, asr); 1917 1918 WAIT_CIP(regs); 1919 GET_SBIC_asr(regs, asr); 1920 /* tapes may take a loooong time.. */ 1921 while (asr & SBIC_ASR_BSY){ 1922 if(asr & SBIC_ASR_DBR) { 1923 printf("sbipoll: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", 1924 csr,asr); 1925 #ifdef DDB 1926 Debugger(); 1927 #endif 1928 /* SBIC is jammed */ 1929 /* DUNNO which direction */ 1930 /* Try old direction */ 1931 GET_SBIC_data(regs,i); 1932 GET_SBIC_asr(regs, asr); 1933 if( asr & SBIC_ASR_DBR) /* Wants us to write */ 1934 SET_SBIC_data(regs,i); 1935 } 1936 GET_SBIC_asr(regs, asr); 1937 } 1938 1939 if(asr & SBIC_ASR_LCI) printf("sbicpoll: LCI asr:%02x csr:%02x\n", 1940 asr,csr); 1941 else if( i == 1 ) /* BSY */ 1942 SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait); 1943 } while(i == SBIC_STATE_RUNNING); 1944 CSR_TRACE('p',csr,asr,i<<4); 1945 SBIC_TRACE(dev); 1946 return(1); 1947 } 1948 1949 /* 1950 * Handle a single msgin 1951 */ 1952 1953 int 1954 sbicmsgin(dev) 1955 struct sbic_softc *dev; 1956 { 1957 sbic_regmap_p regs; 1958 int recvlen; 1959 u_char asr, csr, *tmpaddr; 1960 1961 regs = dev->sc_sbicp; 1962 1963 dev->sc_msg[0] = 0xff; 1964 dev->sc_msg[1] = 0xff; 1965 1966 GET_SBIC_asr(regs, asr); 1967 #ifdef DEBUG 1968 if(reselect_debug>1) 1969 printf("sbicmsgin asr=%02x\n", asr); 1970 #endif 1971 1972 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 1973 1974 GET_SBIC_selid (regs, csr); 1975 SET_SBIC_selid (regs, csr | SBIC_SID_FROM_SCSI); 1976 1977 SBIC_TC_PUT(regs, 0); 1978 tmpaddr = dev->sc_msg; 1979 recvlen = 1; 1980 do { 1981 while( recvlen-- ) { 1982 asr = GET_SBIC_asr(regs, asr); 1983 GET_SBIC_csr(regs, csr); 1984 QPRINTF(("sbicmsgin ready to go (csr,asr)=(%02x,%02x)\n", 1985 csr, asr)); 1986 1987 RECV_BYTE(regs, *tmpaddr); 1988 CSR_TRACE('m',csr,asr,*tmpaddr); 1989 #if 1 1990 /* 1991 * get the command completion interrupt, or we 1992 * can't send a new command (LCI) 1993 */ 1994 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1995 GET_SBIC_csr(regs, csr); 1996 CSR_TRACE('X',csr,asr,dev->target); 1997 #else 1998 WAIT_CIP(regs); 1999 do { 2000 GET_SBIC_asr(regs, asr); 2001 csr = 0xff; 2002 GET_SBIC_csr(regs, csr); 2003 CSR_TRACE('X',csr,asr,dev->target); 2004 if( csr == 0xff ) 2005 printf("sbicmsgin waiting: csr %02x asr %02x\n", csr, asr); 2006 } while( csr == 0xff ); 2007 #endif 2008 #ifdef DEBUG 2009 if(reselect_debug>1) 2010 printf("sbicmsgin: got %02x csr %02x asr %02x\n", 2011 *tmpaddr, csr, asr); 2012 #endif 2013 #if do_parity_check 2014 if( asr & SBIC_ASR_PE ) { 2015 printf ("Parity error"); 2016 /* This code simply does not work. */ 2017 WAIT_CIP(regs); 2018 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2019 WAIT_CIP(regs); 2020 GET_SBIC_asr(regs, asr); 2021 WAIT_CIP(regs); 2022 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2023 WAIT_CIP(regs); 2024 if( !(asr & SBIC_ASR_LCI) ) 2025 /* Target wants to send garbled msg*/ 2026 continue; 2027 printf("--fixing\n"); 2028 /* loop until a msgout phase occurs on target */ 2029 while(csr & 0x07 != MESG_OUT_PHASE) { 2030 while( asr & SBIC_ASR_BSY && 2031 !(asr & SBIC_ASR_DBR|SBIC_ASR_INT) ) 2032 GET_SBIC_asr(regs, asr); 2033 if( asr & SBIC_ASR_DBR ) 2034 panic("msgin: jammed again!\n"); 2035 GET_SBIC_csr(regs, csr); 2036 CSR_TRACE('e',csr,asr,dev->target); 2037 if( csr & 0x07 != MESG_OUT_PHASE ) { 2038 sbicnextstate(dev, csr, asr); 2039 sbic_save_ptrs(dev, regs, 2040 dev->target, 2041 dev->lun); 2042 } 2043 } 2044 /* Should be msg out by now */ 2045 SEND_BYTE(regs, MSG_PARITY_ERROR); 2046 } 2047 else 2048 #endif 2049 tmpaddr++; 2050 2051 if(recvlen) { 2052 /* Clear ACK */ 2053 WAIT_CIP(regs); 2054 GET_SBIC_asr(regs, asr); 2055 GET_SBIC_csr(regs, csr); 2056 CSR_TRACE('X',csr,asr,dev->target); 2057 QPRINTF(("sbicmsgin pre byte CLR_ACK (csr,asr)=(%02x,%02x)\n", 2058 csr, asr)); 2059 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2060 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2061 } 2062 2063 }; 2064 2065 if(dev->sc_msg[0] == 0xff) { 2066 printf("sbicmsgin: sbic swallowed our message\n"); 2067 break; 2068 } 2069 #ifdef DEBUG 2070 if (sync_debug) 2071 printf("msgin done csr 0x%x asr 0x%x msg 0x%x\n", 2072 csr, asr, dev->sc_msg[0]); 2073 #endif 2074 /* 2075 * test whether this is a reply to our sync 2076 * request 2077 */ 2078 if (MSG_ISIDENTIFY(dev->sc_msg[0])) { 2079 QPRINTF(("IFFY")); 2080 #if 0 2081 /* There is an implied load-ptrs here */ 2082 sbic_load_ptrs(dev, regs, dev->target, dev->lun); 2083 #endif 2084 /* Got IFFY msg -- ack it */ 2085 } else if (dev->sc_msg[0] == MSG_REJECT 2086 && dev->sc_sync[dev->target].state == SYNC_SENT) { 2087 QPRINTF(("REJECT of SYN")); 2088 #ifdef DEBUG 2089 if (sync_debug) 2090 printf("target %d rejected sync, going async\n", 2091 dev->target); 2092 #endif 2093 dev->sc_sync[dev->target].period = sbic_min_period; 2094 dev->sc_sync[dev->target].offset = 0; 2095 dev->sc_sync[dev->target].state = SYNC_DONE; 2096 SET_SBIC_syn(regs, 2097 SBIC_SYN(dev->sc_sync[dev->target].offset, 2098 dev->sc_sync[dev->target].period)); 2099 } else if ((dev->sc_msg[0] == MSG_REJECT)) { 2100 QPRINTF(("REJECT")); 2101 /* 2102 * we'll never REJECt a REJECT message.. 2103 */ 2104 } else if ((dev->sc_msg[0] == MSG_SAVE_DATA_PTR)) { 2105 QPRINTF(("MSG_SAVE_DATA_PTR")); 2106 /* 2107 * don't reject this either. 2108 */ 2109 } else if ((dev->sc_msg[0] == MSG_DISCONNECT)) { 2110 QPRINTF(("DISCONNECT")); 2111 #ifdef DEBUG 2112 if( reselect_debug>1 && dev->sc_msg[0] == MSG_DISCONNECT ) 2113 printf("sbicmsgin: got disconnect msg %s\n", 2114 (dev->sc_flags & SBICF_ICMD)?"rejecting":""); 2115 #endif 2116 if( dev->sc_flags & SBICF_ICMD ) { 2117 /* We're in immediate mode. Prevent disconnects. */ 2118 /* prepare to reject the message, NACK */ 2119 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2120 WAIT_CIP(regs); 2121 } 2122 } else if (dev->sc_msg[0] == MSG_CMD_COMPLETE ) { 2123 QPRINTF(("CMD_COMPLETE")); 2124 /* !! KLUDGE ALERT !! quite a few drives don't seem to 2125 * really like the current way of sending the 2126 * sync-handshake together with the ident-message, and 2127 * they react by sending command-complete and 2128 * disconnecting right after returning the valid sync 2129 * handshake. So, all I can do is reselect the drive, 2130 * and hope it won't disconnect again. I don't think 2131 * this is valid behavior, but I can't help fixing a 2132 * problem that apparently exists. 2133 * 2134 * Note: we should not get here on `normal' command 2135 * completion, as that condition is handled by the 2136 * high-level sel&xfer resume command used to walk 2137 * thru status/cc-phase. 2138 */ 2139 2140 #ifdef DEBUG 2141 if (sync_debug) 2142 printf ("GOT MSG %d! target %d acting weird.." 2143 " waiting for disconnect...\n", 2144 dev->sc_msg[0], dev->target); 2145 #endif 2146 /* Check to see if sbic is handling this */ 2147 GET_SBIC_asr(regs, asr); 2148 if(asr & SBIC_ASR_BSY) 2149 return SBIC_STATE_RUNNING; 2150 2151 /* Let's try this: Assume it works and set status to 00 */ 2152 dev->sc_stat[0] = 0; 2153 } else if (dev->sc_msg[0] == MSG_EXT_MESSAGE 2154 && tmpaddr == &dev->sc_msg[1]) { 2155 QPRINTF(("ExtMSG\n")); 2156 /* Read in whole extended message */ 2157 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2158 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2159 GET_SBIC_asr(regs, asr); 2160 GET_SBIC_csr(regs, csr); 2161 QPRINTF(("CLR ACK asr %02x, csr %02x\n", asr, csr)); 2162 RECV_BYTE(regs, *tmpaddr); 2163 CSR_TRACE('x',csr,asr,*tmpaddr); 2164 /* Wait for command completion IRQ */ 2165 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2166 recvlen = *tmpaddr++; 2167 QPRINTF(("Recving ext msg, asr %02x csr %02x len %02x\n", 2168 asr, csr, recvlen)); 2169 } else if (dev->sc_msg[0] == MSG_EXT_MESSAGE && dev->sc_msg[1] == 3 2170 && dev->sc_msg[2] == MSG_SYNC_REQ) { 2171 QPRINTF(("SYN")); 2172 dev->sc_sync[dev->target].period = 2173 sbicfromscsiperiod(dev, 2174 regs, dev->sc_msg[3]); 2175 dev->sc_sync[dev->target].offset = dev->sc_msg[4]; 2176 dev->sc_sync[dev->target].state = SYNC_DONE; 2177 SET_SBIC_syn(regs, 2178 SBIC_SYN(dev->sc_sync[dev->target].offset, 2179 dev->sc_sync[dev->target].period)); 2180 printf("%s: target %d now synchronous," 2181 " period=%dns, offset=%d.\n", 2182 dev->sc_dev.dv_xname, dev->target, 2183 dev->sc_msg[3] * 4, dev->sc_msg[4]); 2184 } else { 2185 #ifdef DEBUG 2186 if (sbic_debug || sync_debug) 2187 printf ("sbicmsgin: Rejecting message 0x%02x\n", 2188 dev->sc_msg[0]); 2189 #endif 2190 /* prepare to reject the message, NACK */ 2191 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2192 WAIT_CIP(regs); 2193 } 2194 /* Clear ACK */ 2195 WAIT_CIP(regs); 2196 GET_SBIC_asr(regs, asr); 2197 GET_SBIC_csr(regs, csr); 2198 CSR_TRACE('X',csr,asr,dev->target); 2199 QPRINTF(("sbicmsgin pre CLR_ACK (csr,asr)=(%02x,%02x)%d\n", 2200 csr, asr, recvlen)); 2201 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2202 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2203 } 2204 #if 0 2205 while((csr == SBIC_CSR_MSGIN_W_ACK) 2206 || (SBIC_PHASE(csr) == MESG_IN_PHASE)); 2207 #else 2208 while (recvlen>0); 2209 #endif 2210 2211 QPRINTF(("sbicmsgin finished: csr %02x, asr %02x\n",csr, asr)); 2212 2213 /* Should still have one CSR to read */ 2214 return SBIC_STATE_RUNNING; 2215 } 2216 2217 2218 /* 2219 * sbicnextstate() 2220 * return: 2221 * 0 == done 2222 * 1 == working 2223 * 2 == disconnected 2224 * -1 == error 2225 */ 2226 int 2227 sbicnextstate(dev, csr, asr) 2228 struct sbic_softc *dev; 2229 u_char csr, asr; 2230 { 2231 sbic_regmap_p regs; 2232 struct dma_chain *df, *dl; 2233 struct sbic_acb *acb; 2234 int i, newtarget, newlun, wait; 2235 unsigned tcnt; 2236 2237 SBIC_TRACE(dev); 2238 regs = dev->sc_sbicp; 2239 acb = dev->sc_nexus; 2240 2241 QPRINTF(("next[%02x,%02x]",asr,csr)); 2242 2243 switch (csr) { 2244 case SBIC_CSR_XFERRED|CMD_PHASE: 2245 case SBIC_CSR_MIS|CMD_PHASE: 2246 case SBIC_CSR_MIS_1|CMD_PHASE: 2247 case SBIC_CSR_MIS_2|CMD_PHASE: 2248 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 2249 if (sbicxfstart(regs, acb->clen, CMD_PHASE, sbic_cmd_wait)) 2250 if (sbicxfout(regs, acb->clen, 2251 &acb->cmd, CMD_PHASE)) 2252 goto abort; 2253 break; 2254 2255 case SBIC_CSR_XFERRED|STATUS_PHASE: 2256 case SBIC_CSR_MIS|STATUS_PHASE: 2257 case SBIC_CSR_MIS_1|STATUS_PHASE: 2258 case SBIC_CSR_MIS_2|STATUS_PHASE: 2259 /* 2260 * this should be the normal i/o completion case. 2261 * get the status & cmd complete msg then let the 2262 * device driver look at what happened. 2263 */ 2264 sbicxfdone(dev,regs,dev->target); 2265 /* 2266 * check for overlapping cache line, flush if so 2267 */ 2268 #ifdef M68040 2269 if (dev->sc_flags & SBICF_DCFLUSH) { 2270 #if 0 2271 printf("sbic: 68040 DMA cache flush needs fixing? %x:%x\n", 2272 dev->sc_xs->data, dev->sc_xs->datalen); 2273 #endif 2274 } 2275 #endif 2276 #ifdef DEBUG 2277 if( data_pointer_debug > 1 ) 2278 printf("next dmastop: %d(%x:%x)\n", 2279 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 2280 dev->sc_dmatimo = 0; 2281 #endif 2282 dev->sc_dmastop(dev); /* was dmafree */ 2283 if (acb->flags & ACB_BBUF) { 2284 if ((u_char *)kvtop(acb->sc_dmausrbuf) != acb->sc_usrbufpa) 2285 printf("%s: WARNING - buffer mapping changed %x->%x\n", 2286 dev->sc_dev.dv_xname, acb->sc_usrbufpa, 2287 kvtop(acb->sc_dmausrbuf)); 2288 #ifdef DEBUG 2289 if(data_pointer_debug) 2290 printf("sbicgo:copying %x bytes from target %d bounce %x\n", 2291 acb->sc_dmausrlen, 2292 dev->target, 2293 kvtop(dev->sc_tinfo[dev->target].bounce)); 2294 #endif 2295 bcopy(dev->sc_tinfo[dev->target].bounce, 2296 acb->sc_dmausrbuf, 2297 acb->sc_dmausrlen); 2298 } 2299 dev->sc_flags &= ~(SBICF_INDMA | SBICF_DCFLUSH); 2300 sbic_scsidone(acb, dev->sc_stat[0]); 2301 SBIC_TRACE(dev); 2302 return SBIC_STATE_DONE; 2303 2304 case SBIC_CSR_XFERRED|DATA_OUT_PHASE: 2305 case SBIC_CSR_XFERRED|DATA_IN_PHASE: 2306 case SBIC_CSR_MIS|DATA_OUT_PHASE: 2307 case SBIC_CSR_MIS|DATA_IN_PHASE: 2308 case SBIC_CSR_MIS_1|DATA_OUT_PHASE: 2309 case SBIC_CSR_MIS_1|DATA_IN_PHASE: 2310 case SBIC_CSR_MIS_2|DATA_OUT_PHASE: 2311 case SBIC_CSR_MIS_2|DATA_IN_PHASE: 2312 if( dev->sc_xs->flags & SCSI_POLL || dev->sc_flags & SBICF_ICMD 2313 || acb->sc_dmacmd == 0 ) { 2314 /* Do PIO */ 2315 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2316 if (acb->sc_kv.dc_count <= 0) { 2317 printf("sbicnextstate:xfer count %d asr%x csr%x\n", 2318 acb->sc_kv.dc_count, asr, csr); 2319 goto abort; 2320 } 2321 wait = sbic_data_wait; 2322 if( sbicxfstart(regs, 2323 acb->sc_kv.dc_count, 2324 SBIC_PHASE(csr), wait)) 2325 if( SBIC_PHASE(csr) == DATA_IN_PHASE ) 2326 /* data in? */ 2327 i=sbicxfin(regs, 2328 acb->sc_kv.dc_count, 2329 acb->sc_kv.dc_addr); 2330 else 2331 i=sbicxfout(regs, 2332 acb->sc_kv.dc_count, 2333 acb->sc_kv.dc_addr, 2334 SBIC_PHASE(csr)); 2335 acb->sc_kv.dc_addr += 2336 (acb->sc_kv.dc_count - i); 2337 acb->sc_kv.dc_count = i; 2338 } else { 2339 if (acb->sc_kv.dc_count <= 0) { 2340 printf("sbicnextstate:xfer count %d asr%x csr%x\n", 2341 acb->sc_kv.dc_count, asr, csr); 2342 goto abort; 2343 } 2344 /* 2345 * do scatter-gather dma 2346 * hacking the controller chip, ouch.. 2347 */ 2348 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI | 2349 SBIC_MACHINE_DMA_MODE); 2350 /* 2351 * set next dma addr and dec count 2352 */ 2353 #if 0 2354 SBIC_TC_GET(regs, tcnt); 2355 dev->sc_cur->dc_count -= ((dev->sc_tcnt - tcnt) >> 1); 2356 dev->sc_cur->dc_addr += (dev->sc_tcnt - tcnt); 2357 dev->sc_tcnt = acb->sc_tcnt = tcnt; 2358 #else 2359 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 2360 sbic_load_ptrs(dev, regs, dev->target, dev->lun); 2361 #endif 2362 #ifdef DEBUG 2363 if( data_pointer_debug > 1 ) 2364 printf("next dmanext: %d(%x:%x)\n", 2365 dev->target,dev->sc_cur->dc_addr, 2366 dev->sc_tcnt); 2367 dev->sc_dmatimo = 1; 2368 #endif 2369 dev->sc_tcnt = dev->sc_dmanext(dev); 2370 SBIC_TC_PUT(regs, (unsigned)dev->sc_tcnt); 2371 SET_SBIC_cmd(regs, SBIC_CMD_XFER_INFO); 2372 dev->sc_flags |= SBICF_INDMA; 2373 } 2374 break; 2375 2376 case SBIC_CSR_XFERRED|MESG_IN_PHASE: 2377 case SBIC_CSR_MIS|MESG_IN_PHASE: 2378 case SBIC_CSR_MIS_1|MESG_IN_PHASE: 2379 case SBIC_CSR_MIS_2|MESG_IN_PHASE: 2380 SBIC_TRACE(dev); 2381 return sbicmsgin(dev); 2382 2383 case SBIC_CSR_MSGIN_W_ACK: 2384 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); /* Dunno what I'm ACKing */ 2385 printf("Acking unknown msgin CSR:%02x",csr); 2386 break; 2387 2388 case SBIC_CSR_XFERRED|MESG_OUT_PHASE: 2389 case SBIC_CSR_MIS|MESG_OUT_PHASE: 2390 case SBIC_CSR_MIS_1|MESG_OUT_PHASE: 2391 case SBIC_CSR_MIS_2|MESG_OUT_PHASE: 2392 #ifdef DEBUG 2393 if (sync_debug) 2394 printf ("sending REJECT msg to last msg.\n"); 2395 #endif 2396 2397 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 2398 /* 2399 * should only get here on reject, 2400 * since it's always US that 2401 * initiate a sync transfer 2402 */ 2403 SEND_BYTE(regs, MSG_REJECT); 2404 WAIT_CIP(regs); 2405 if( asr & (SBIC_ASR_BSY|SBIC_ASR_LCI|SBIC_ASR_CIP) ) 2406 printf("next: REJECT sent asr %02x\n", asr); 2407 SBIC_TRACE(dev); 2408 return SBIC_STATE_RUNNING; 2409 2410 case SBIC_CSR_DISC: 2411 case SBIC_CSR_DISC_1: 2412 dev->sc_flags &= ~(SBICF_INDMA|SBICF_SELECTED); 2413 2414 /* Try to schedule another target */ 2415 #ifdef DEBUG 2416 if(reselect_debug>1) 2417 printf("sbicnext target %d disconnected\n", dev->target); 2418 #endif 2419 TAILQ_INSERT_HEAD(&dev->nexus_list, acb, chain); 2420 ++dev->sc_tinfo[dev->target].dconns; 2421 dev->sc_nexus = NULL; 2422 dev->sc_xs = NULL; 2423 2424 if( acb->xs->flags & SCSI_POLL 2425 || (dev->sc_flags & SBICF_ICMD) 2426 || !sbic_parallel_operations ) { 2427 SBIC_TRACE(dev); 2428 return SBIC_STATE_DISCONNECT; 2429 } 2430 sbic_sched(dev); 2431 SBIC_TRACE(dev); 2432 return SBIC_STATE_DISCONNECT; 2433 2434 case SBIC_CSR_RSLT_NI: 2435 case SBIC_CSR_RSLT_IFY: 2436 GET_SBIC_rselid(regs, newtarget); 2437 /* check SBIC_RID_SIV? */ 2438 newtarget &= SBIC_RID_MASK; 2439 if (csr == SBIC_CSR_RSLT_IFY) { 2440 /* Read IFY msg to avoid lockup */ 2441 GET_SBIC_data(regs, newlun); 2442 WAIT_CIP(regs); 2443 newlun &= SBIC_TLUN_MASK; 2444 CSR_TRACE('r',csr,asr,newtarget); 2445 } else { 2446 /* Need to get IFY message */ 2447 for (newlun = 256; newlun; --newlun) { 2448 GET_SBIC_asr(regs, asr); 2449 if (asr & SBIC_ASR_INT) 2450 break; 2451 delay(1); 2452 } 2453 newlun = 0; /* XXXX */ 2454 if ((asr & SBIC_ASR_INT) == 0) { 2455 #ifdef DEBUG 2456 if (reselect_debug) 2457 printf("RSLT_NI - no IFFY message? asr %x\n", asr); 2458 #endif 2459 } else { 2460 GET_SBIC_csr(regs,csr); 2461 CSR_TRACE('n',csr,asr,newtarget); 2462 if (csr == SBIC_CSR_MIS|MESG_IN_PHASE || 2463 csr == SBIC_CSR_MIS_1|MESG_IN_PHASE || 2464 csr == SBIC_CSR_MIS_2|MESG_IN_PHASE) { 2465 sbicmsgin(dev); 2466 newlun = dev->sc_msg[0] & 7; 2467 } else { 2468 printf("RSLT_NI - not MESG_IN_PHASE %x\n", 2469 csr); 2470 } 2471 } 2472 } 2473 #ifdef DEBUG 2474 if(reselect_debug>1 || (reselect_debug && csr==SBIC_CSR_RSLT_NI)) 2475 printf("sbicnext: reselect %s from targ %d lun %d\n", 2476 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", 2477 newtarget, newlun); 2478 #endif 2479 if (dev->sc_nexus) { 2480 #ifdef DEBUG 2481 if (reselect_debug > 1) 2482 printf("%s: reselect %s with active command\n", 2483 dev->sc_dev.dv_xname, 2484 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY"); 2485 #ifdef DDB 2486 /* Debugger();*/ 2487 #endif 2488 #endif 2489 TAILQ_INSERT_HEAD(&dev->ready_list, dev->sc_nexus, chain); 2490 dev->sc_tinfo[dev->target].lubusy &= ~(1 << dev->lun); 2491 dev->sc_nexus = NULL; 2492 dev->sc_xs = NULL; 2493 } 2494 /* Reload sync values for this target */ 2495 if (dev->sc_sync[newtarget].state == SYNC_DONE) 2496 SET_SBIC_syn(regs, SBIC_SYN (dev->sc_sync[newtarget].offset, 2497 dev->sc_sync[newtarget].period)); 2498 else 2499 SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period)); 2500 for (acb = dev->nexus_list.tqh_first; acb; 2501 acb = acb->chain.tqe_next) { 2502 if (acb->xs->sc_link->target != newtarget || 2503 acb->xs->sc_link->lun != newlun) 2504 continue; 2505 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 2506 dev->sc_nexus = acb; 2507 dev->sc_xs = acb->xs; 2508 dev->sc_flags |= SBICF_SELECTED; 2509 dev->target = newtarget; 2510 dev->lun = newlun; 2511 break; 2512 } 2513 if (acb == NULL) { 2514 printf("%s: reselect %s targ %d not in nexus_list %x\n", 2515 dev->sc_dev.dv_xname, 2516 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", newtarget, 2517 &dev->nexus_list.tqh_first); 2518 panic("bad reselect in sbic"); 2519 } 2520 if (csr == SBIC_CSR_RSLT_IFY) 2521 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2522 break; 2523 2524 default: 2525 abort: 2526 /* 2527 * Something unexpected happened -- deal with it. 2528 */ 2529 printf("sbicnextstate: aborting csr %02x asr %02x\n", csr, asr); 2530 #ifdef DDB 2531 Debugger(); 2532 #endif 2533 #ifdef DEBUG 2534 if( data_pointer_debug > 1 ) 2535 printf("next dmastop: %d(%x:%x)\n", 2536 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 2537 dev->sc_dmatimo = 0; 2538 #endif 2539 dev->sc_dmastop(dev); 2540 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2541 sbicerror(dev, regs, csr); 2542 sbicabort(dev, regs, "next"); 2543 if (dev->sc_flags & SBICF_INDMA) { 2544 /* 2545 * check for overlapping cache line, flush if so 2546 */ 2547 #ifdef M68040 2548 if (dev->sc_flags & SBICF_DCFLUSH) { 2549 #if 0 2550 printf("sibc: 68040 DMA cache flush needs fixing? %x:%x\n", 2551 dev->sc_xs->data, dev->sc_xs->datalen); 2552 #endif 2553 } 2554 #endif 2555 dev->sc_flags &= 2556 ~(SBICF_INDMA | SBICF_DCFLUSH); 2557 #ifdef DEBUG 2558 if( data_pointer_debug > 1 ) 2559 printf("next dmastop: %d(%x:%x)\n", 2560 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 2561 dev->sc_dmatimo = 0; 2562 #endif 2563 dev->sc_dmastop(dev); 2564 sbic_scsidone(acb, -1); 2565 } 2566 SBIC_TRACE(dev); 2567 return SBIC_STATE_ERROR; 2568 } 2569 2570 SBIC_TRACE(dev); 2571 return(SBIC_STATE_RUNNING); 2572 } 2573 2574 2575 /* 2576 * Check if DMA can not be used with specified buffer 2577 */ 2578 2579 int 2580 sbiccheckdmap(bp, len, mask) 2581 void *bp; 2582 u_long len, mask; 2583 { 2584 u_char *buffer; 2585 u_long phy_buf; 2586 u_long phy_len; 2587 2588 buffer = bp; 2589 2590 if (len == 0) 2591 return(0); 2592 2593 while (len) { 2594 phy_buf = kvtop(buffer); 2595 if (len < (phy_len = NBPG - ((int) buffer & PGOFSET))) 2596 phy_len = len; 2597 if (phy_buf & mask) 2598 return(1); 2599 buffer += phy_len; 2600 len -= phy_len; 2601 } 2602 return(0); 2603 } 2604 2605 int 2606 sbictoscsiperiod(dev, regs, a) 2607 struct sbic_softc *dev; 2608 sbic_regmap_p regs; 2609 int a; 2610 { 2611 unsigned int fs; 2612 2613 /* 2614 * cycle = DIV / (2*CLK) 2615 * DIV = FS+2 2616 * best we can do is 200ns at 20Mhz, 2 cycles 2617 */ 2618 2619 GET_SBIC_myid(regs,fs); 2620 fs = (fs >>6) + 2; /* DIV */ 2621 fs = (fs * 10000) / (dev->sc_clkfreq<<1); /* Cycle, in ns */ 2622 if (a < 2) a = 8; /* map to Cycles */ 2623 return ((fs*a)>>2); /* in 4 ns units */ 2624 } 2625 2626 int 2627 sbicfromscsiperiod(dev, regs, p) 2628 struct sbic_softc *dev; 2629 sbic_regmap_p regs; 2630 int p; 2631 { 2632 register unsigned int fs, ret; 2633 2634 /* Just the inverse of the above */ 2635 2636 GET_SBIC_myid(regs,fs); 2637 fs = (fs >>6) + 2; /* DIV */ 2638 fs = (fs * 10000) / (dev->sc_clkfreq<<1); /* Cycle, in ns */ 2639 2640 ret = p << 2; /* in ns units */ 2641 ret = ret / fs; /* in Cycles */ 2642 if (ret < sbic_min_period) 2643 return(sbic_min_period); 2644 2645 /* verify rounding */ 2646 if (sbictoscsiperiod(dev, regs, ret) < p) 2647 ret++; 2648 return (ret >= 8) ? 0 : ret; 2649 } 2650 2651 #ifdef DEBUG 2652 2653 void sbicdumpstate() 2654 { 2655 u_char csr, asr; 2656 2657 GET_SBIC_asr(debug_sbic_regs,asr); 2658 GET_SBIC_csr(debug_sbic_regs,csr); 2659 printf("%s: asr:csr(%02x:%02x)->(%02x:%02x)\n", 2660 (routine==1)?"sbicgo": 2661 (routine==2)?"sbicintr": 2662 (routine==3)?"sbicicmd": 2663 (routine==4)?"sbicnext":"unknown", 2664 debug_asr, debug_csr, asr, csr); 2665 2666 } 2667 2668 void sbictimeout(dev) 2669 struct sbic_softc *dev; 2670 { 2671 int s, asr; 2672 2673 s = splbio(); 2674 if (dev->sc_dmatimo) { 2675 if (dev->sc_dmatimo > 1) { 2676 printf("%s: dma timeout #%d\n", 2677 dev->sc_dev.dv_xname, dev->sc_dmatimo - 1); 2678 GET_SBIC_asr(dev->sc_sbicp, asr); 2679 if( asr & SBIC_ASR_INT ) { 2680 /* We need to service a missed IRQ */ 2681 printf("Servicing a missed int:(%02x,%02x)->(%02x,??)\n", 2682 debug_asr, debug_csr, asr); 2683 sbicintr(dev); 2684 } 2685 sbicdumpstate(); 2686 } 2687 dev->sc_dmatimo++; 2688 } 2689 splx(s); 2690 timeout((void *)sbictimeout, dev, 30 * hz); 2691 } 2692 2693 void 2694 sbic_dump_acb(acb) 2695 struct sbic_acb *acb; 2696 { 2697 u_char *b = (u_char *) &acb->cmd; 2698 int i; 2699 2700 printf("acb@%x ", acb); 2701 if (acb->xs == NULL) { 2702 printf("<unused>\n"); 2703 return; 2704 } 2705 printf("(%d:%d) flags %2x clen %2d cmd ", acb->xs->sc_link->target, 2706 acb->xs->sc_link->lun, acb->flags, acb->clen); 2707 for (i = acb->clen; i; --i) 2708 printf(" %02x", *b++); 2709 printf("\n"); 2710 printf(" xs: %08x data %8x:%04x ", acb->xs, acb->xs->data, 2711 acb->xs->datalen); 2712 printf("va %8x:%04x ", acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 2713 printf("pa %8x:%04x tcnt %x\n", acb->sc_pa.dc_addr, acb->sc_pa.dc_count, 2714 acb->sc_tcnt); 2715 } 2716 2717 void 2718 sbic_dump(dev) 2719 struct sbic_softc *dev; 2720 { 2721 sbic_regmap_p regs; 2722 u_char csr, asr; 2723 struct sbic_acb *acb; 2724 int s; 2725 int i; 2726 2727 s = splbio(); 2728 regs = dev->sc_sbicp; 2729 #if CSR_TRACE_SIZE 2730 printf("csr trace: "); 2731 i = csr_traceptr; 2732 do { 2733 printf("%c%02x%02x%02x ", csr_trace[i].whr, 2734 csr_trace[i].csr, csr_trace[i].asr, csr_trace[i].xtn); 2735 switch(csr_trace[i].whr) { 2736 case 'g': 2737 printf("go "); break; 2738 case 's': 2739 printf("select "); break; 2740 case 'y': 2741 printf("select+ "); break; 2742 case 'i': 2743 printf("intr "); break; 2744 case 'f': 2745 printf("finish "); break; 2746 case '>': 2747 printf("out "); break; 2748 case '<': 2749 printf("in "); break; 2750 case 'm': 2751 printf("msgin "); break; 2752 case 'x': 2753 printf("msginx "); break; 2754 case 'X': 2755 printf("msginX "); break; 2756 case 'r': 2757 printf("reselect "); break; 2758 case 'I': 2759 printf("icmd "); break; 2760 case 'a': 2761 printf("abort "); break; 2762 default: 2763 printf("? "); 2764 } 2765 switch(csr_trace[i].csr) { 2766 case 0x11: 2767 printf("INITIATOR"); break; 2768 case 0x16: 2769 printf("S_XFERRED"); break; 2770 case 0x20: 2771 printf("MSGIN_ACK"); break; 2772 case 0x41: 2773 printf("DISC"); break; 2774 case 0x42: 2775 printf("SEL_TIMEO"); break; 2776 case 0x80: 2777 printf("RSLT_NI"); break; 2778 case 0x81: 2779 printf("RSLT_IFY"); break; 2780 case 0x85: 2781 printf("DISC_1"); break; 2782 case 0x18: case 0x19: case 0x1a: 2783 case 0x1b: case 0x1e: case 0x1f: 2784 case 0x28: case 0x29: case 0x2a: 2785 case 0x2b: case 0x2e: case 0x2f: 2786 case 0x48: case 0x49: case 0x4a: 2787 case 0x4b: case 0x4e: case 0x4f: 2788 case 0x88: case 0x89: case 0x8a: 2789 case 0x8b: case 0x8e: case 0x8f: 2790 switch(csr_trace[i].csr & 0xf0) { 2791 case 0x10: 2792 printf("DONE_"); break; 2793 case 0x20: 2794 printf("STOP_"); break; 2795 case 0x40: 2796 printf("ERR_"); break; 2797 case 0x80: 2798 printf("REQ_"); break; 2799 } 2800 switch(csr_trace[i].csr & 7) { 2801 case 0: 2802 printf("DATA_OUT"); break; 2803 case 1: 2804 printf("DATA_IN"); break; 2805 case 2: 2806 printf("CMD"); break; 2807 case 3: 2808 printf("STATUS"); break; 2809 case 6: 2810 printf("MSG_OUT"); break; 2811 case 7: 2812 printf("MSG_IN"); break; 2813 default: 2814 printf("invld phs"); 2815 } 2816 break; 2817 default: printf("****"); break; 2818 } 2819 if (csr_trace[i].asr & SBIC_ASR_INT) 2820 printf(" ASR_INT"); 2821 if (csr_trace[i].asr & SBIC_ASR_LCI) 2822 printf(" ASR_LCI"); 2823 if (csr_trace[i].asr & SBIC_ASR_BSY) 2824 printf(" ASR_BSY"); 2825 if (csr_trace[i].asr & SBIC_ASR_CIP) 2826 printf(" ASR_CIP"); 2827 printf("\n"); 2828 i = (i + 1) & (CSR_TRACE_SIZE - 1); 2829 } while (i != csr_traceptr); 2830 #endif 2831 GET_SBIC_asr(regs, asr); 2832 if ((asr & SBIC_ASR_INT) == 0) 2833 GET_SBIC_csr(regs, csr); 2834 else 2835 csr = 0; 2836 printf("%s@%x regs %x asr %x csr %x\n", dev->sc_dev.dv_xname, 2837 dev, regs, asr, csr); 2838 if (acb = dev->free_list.tqh_first) { 2839 printf("Free list:\n"); 2840 while (acb) { 2841 sbic_dump_acb(acb); 2842 acb = acb->chain.tqe_next; 2843 } 2844 } 2845 if (acb = dev->ready_list.tqh_first) { 2846 printf("Ready list:\n"); 2847 while (acb) { 2848 sbic_dump_acb(acb); 2849 acb = acb->chain.tqe_next; 2850 } 2851 } 2852 if (acb = dev->nexus_list.tqh_first) { 2853 printf("Nexus list:\n"); 2854 while (acb) { 2855 sbic_dump_acb(acb); 2856 acb = acb->chain.tqe_next; 2857 } 2858 } 2859 if (dev->sc_nexus) { 2860 printf("nexus:\n"); 2861 sbic_dump_acb(dev->sc_nexus); 2862 } 2863 printf("sc_xs %x targ %d lun %d flags %x tcnt %x dmacmd %x mask %x\n", 2864 dev->sc_xs, dev->target, dev->lun, dev->sc_flags, dev->sc_tcnt, 2865 dev->sc_dmacmd, dev->sc_dmamask); 2866 for (i = 0; i < 8; ++i) { 2867 if (dev->sc_tinfo[i].cmds > 2) { 2868 printf("tgt %d: cmds %d disc %d senses %d lubusy %x\n", 2869 i, dev->sc_tinfo[i].cmds, 2870 dev->sc_tinfo[i].dconns, 2871 dev->sc_tinfo[i].senses, 2872 dev->sc_tinfo[i].lubusy); 2873 } 2874 } 2875 splx(s); 2876 } 2877 2878 #endif 2879
Indexes created Fri Sep 26 20:09:58 GMT 2025