sbic.c revision 1.19.2.1
1 /* $NetBSD: sbic.c,v 1.19.2.1 1995/11/24 07:51:17 chopps Exp $ */ 2 3 /* 4 * Copyright (c) 1994 Christian E. Hopps 5 * Copyright (c) 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * Van Jacobson of Lawrence Berkeley Laboratory. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the University of 22 * California, Berkeley and its contributors. 23 * 4. Neither the name of the University nor the names of its contributors 24 * may be used to endorse or promote products derived from this software 25 * without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 37 * SUCH DAMAGE. 38 * 39 * @(#)scsi.c 7.5 (Berkeley) 5/4/91 40 */ 41 42 /* 43 * AMIGA AMD 33C93 scsi adaptor driver 44 */ 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/device.h> 49 #include <sys/kernel.h> /* For hz */ 50 #include <sys/disklabel.h> 51 #include <sys/dkstat.h> 52 #include <sys/buf.h> 53 #include <scsi/scsi_all.h> 54 #include <scsi/scsiconf.h> 55 #include <vm/vm.h> 56 #include <vm/vm_kern.h> 57 #include <vm/vm_page.h> 58 #include <machine/pmap.h> 59 #include <machine/cpu.h> 60 #include <amiga/amiga/device.h> 61 #include <amiga/amiga/custom.h> 62 #include <amiga/amiga/isr.h> 63 #include <amiga/dev/dmavar.h> 64 #include <amiga/dev/sbicreg.h> 65 #include <amiga/dev/sbicvar.h> 66 67 /* These are for bounce buffers */ 68 #include <amiga/amiga/cc.h> 69 #include <amiga/dev/zbusvar.h> 70 71 #include <vm/pmap.h> 72 73 /* Since I can't find this in any other header files */ 74 #define SCSI_PHASE(reg) (reg&0x07) 75 76 /* 77 * SCSI delays 78 * In u-seconds, primarily for state changes on the SPC. 79 */ 80 #define SBIC_CMD_WAIT 50000 /* wait per step of 'immediate' cmds */ 81 #define SBIC_DATA_WAIT 50000 /* wait per data in/out step */ 82 #define SBIC_INIT_WAIT 50000 /* wait per step (both) during init */ 83 84 #define b_cylin b_resid 85 #define SBIC_WAIT(regs, until, timeo) sbicwait(regs, until, timeo, __LINE__) 86 87 extern u_int kvtop(); 88 89 int sbicicmd __P((struct sbic_softc *, int, int, void *, int, void *, int)); 90 int sbicgo __P((struct sbic_softc *, struct scsi_xfer *)); 91 int sbicdmaok __P((struct sbic_softc *, struct scsi_xfer *)); 92 int sbicwait __P((sbic_regmap_p, char, int , int)); 93 int sbiccheckdmap __P((void *, u_long, u_long)); 94 int sbicselectbus __P((struct sbic_softc *, sbic_regmap_p, u_char, u_char, u_char)); 95 int sbicxfstart __P((sbic_regmap_p, int, u_char, int)); 96 int sbicxfout __P((sbic_regmap_p regs, int, void *, int)); 97 int sbicfromscsiperiod __P((struct sbic_softc *, sbic_regmap_p, int)); 98 int sbictoscsiperiod __P((struct sbic_softc *, sbic_regmap_p, int)); 99 int sbicintr __P((struct sbic_softc *)); 100 int sbicpoll __P((struct sbic_softc *)); 101 int sbicnextstate __P((struct sbic_softc *, u_char, u_char)); 102 int sbicmsgin __P((struct sbic_softc *)); 103 int sbicxfin __P((sbic_regmap_p regs, int, void *)); 104 int sbicabort __P((struct sbic_softc *, sbic_regmap_p, char *)); 105 void sbicxfdone __P((struct sbic_softc *, sbic_regmap_p, int)); 106 void sbicerror __P((struct sbic_softc *, sbic_regmap_p, u_char)); 107 void sbicstart __P((struct sbic_softc *)); 108 void sbicreset __P((struct sbic_softc *)); 109 void sbic_scsidone __P((struct sbic_acb *, int)); 110 void sbic_sched __P((struct sbic_softc *)); 111 void sbic_save_ptrs __P((struct sbic_softc *, sbic_regmap_p,int,int)); 112 void sbic_load_ptrs __P((struct sbic_softc *, sbic_regmap_p,int,int)); 113 114 /* 115 * Synch xfer parameters, and timing conversions 116 */ 117 int sbic_min_period = SBIC_SYN_MIN_PERIOD; /* in cycles = f(ICLK,FSn) */ 118 int sbic_max_offset = SBIC_SYN_MAX_OFFSET; /* pure number */ 119 120 int sbic_cmd_wait = SBIC_CMD_WAIT; 121 int sbic_data_wait = SBIC_DATA_WAIT; 122 int sbic_init_wait = SBIC_INIT_WAIT; 123 124 /* 125 * was broken before.. now if you want this you get it for all drives 126 * on sbic controllers. 127 */ 128 u_char sbic_inhibit_sync[8]; 129 int sbic_enable_reselect = 1; 130 int sbic_clock_override = 0; 131 int sbic_no_dma = 0; 132 int sbic_parallel_operations = 1; 133 134 #ifdef DEBUG 135 sbic_regmap_p debug_sbic_regs; 136 int sbicdma_ops = 0; /* total DMA operations */ 137 int sbicdma_bounces = 0; /* number operations using bounce buffer */ 138 int sbicdma_hits = 0; /* number of DMA chains that were contiguous */ 139 int sbicdma_misses = 0; /* number of DMA chains that were not contiguous */ 140 int sbicdma_saves = 0; 141 #define QPRINTF(a) if (sbic_debug > 1) printf a 142 int sbic_debug = 0; 143 int sync_debug = 0; 144 int sbic_dma_debug = 0; 145 int reselect_debug = 0; 146 int report_sense = 0; 147 int data_pointer_debug = 0; 148 u_char debug_asr, debug_csr, routine; 149 void sbictimeout __P((struct sbic_softc *dev)); 150 void sbic_dump __P((struct sbic_softc *dev)); 151 152 #define CSR_TRACE_SIZE 32 153 #if CSR_TRACE_SIZE 154 #define CSR_TRACE(w,c,a,x) do { \ 155 int s = splbio(); \ 156 csr_trace[csr_traceptr].whr = (w); csr_trace[csr_traceptr].csr = (c); \ 157 csr_trace[csr_traceptr].asr = (a); csr_trace[csr_traceptr].xtn = (x); \ 158 dma_cachectl(&csr_trace[csr_traceptr], sizeof(csr_trace[0])); \ 159 csr_traceptr = (csr_traceptr + 1) & (CSR_TRACE_SIZE - 1); \ 160 /* dma_cachectl(&csr_traceptr, sizeof(csr_traceptr));*/ \ 161 splx(s); \ 162 } while (0) 163 int csr_traceptr; 164 int csr_tracesize = CSR_TRACE_SIZE; 165 struct { 166 u_char whr; 167 u_char csr; 168 u_char asr; 169 u_char xtn; 170 } csr_trace[CSR_TRACE_SIZE]; 171 #else 172 #define CSR_TRACE 173 #endif 174 175 #define SBIC_TRACE_SIZE 0 176 #if SBIC_TRACE_SIZE 177 #define SBIC_TRACE(dev) do { \ 178 int s = splbio(); \ 179 sbic_trace[sbic_traceptr].sp = &s; \ 180 sbic_trace[sbic_traceptr].line = __LINE__; \ 181 sbic_trace[sbic_traceptr].sr = s; \ 182 sbic_trace[sbic_traceptr].csr = csr_traceptr; \ 183 dma_cachectl(&sbic_trace[sbic_traceptr], sizeof(sbic_trace[0])); \ 184 sbic_traceptr = (sbic_traceptr + 1) & (SBIC_TRACE_SIZE - 1); \ 185 dma_cachectl(&sbic_traceptr, sizeof(sbic_traceptr)); \ 186 if (dev) dma_cachectl(dev, sizeof(*dev)); \ 187 splx(s); \ 188 } while (0) 189 int sbic_traceptr; 190 int sbic_tracesize = SBIC_TRACE_SIZE; 191 struct { 192 void *sp; 193 u_short line; 194 u_short sr; 195 int csr; 196 } sbic_trace[SBIC_TRACE_SIZE]; 197 #else 198 #define SBIC_TRACE 199 #endif 200 201 #else 202 #define QPRINTF 203 #define CSR_TRACE 204 #define SBIC_TRACE 205 #endif 206 207 /* 208 * default minphys routine for sbic based controllers 209 */ 210 void 211 sbic_minphys(bp) 212 struct buf *bp; 213 { 214 215 /* 216 * No max transfer at this level. 217 */ 218 minphys(bp); 219 } 220 221 /* 222 * Save DMA pointers. Take into account partial transfer. Shut down DMA. 223 */ 224 void 225 sbic_save_ptrs(dev, regs, target, lun) 226 struct sbic_softc *dev; 227 sbic_regmap_p regs; 228 int target, lun; 229 { 230 int count, asr, csr, s; 231 unsigned long ptr; 232 char *vptr; 233 struct sbic_acb* acb; 234 235 extern vm_offset_t vm_first_phys; 236 237 SBIC_TRACE(dev); 238 if( !dev->sc_cur ) return; 239 if( !(dev->sc_flags & SBICF_INDMA) ) return; /* DMA not active */ 240 241 s = splbio(); 242 243 acb = dev->sc_nexus; 244 count = -1; 245 do { 246 GET_SBIC_asr(regs, asr); 247 if( asr & SBIC_ASR_DBR ) { 248 printf("sbic_save_ptrs: asr %02x canceled!\n", asr); 249 splx(s); 250 SBIC_TRACE(dev); 251 return; 252 } 253 } while( asr & (SBIC_ASR_BSY|SBIC_ASR_CIP) ); 254 255 /* Save important state */ 256 /* must be done before dmastop */ 257 acb->sc_dmacmd = dev->sc_dmacmd; 258 SBIC_TC_GET(regs, count); 259 260 /* Shut down DMA ====CAREFUL==== */ 261 dev->sc_dmastop(dev); 262 dev->sc_flags &= ~SBICF_INDMA; 263 SBIC_TC_PUT(regs, 0); 264 265 #ifdef DEBUG 266 if(!count && sbic_debug) printf("%dcount0",target); 267 if(data_pointer_debug == -1) 268 printf("SBIC saving target %d data pointers from (%x,%x)%xASR:%02x", 269 target, dev->sc_cur->dc_addr, dev->sc_cur->dc_count, 270 acb->sc_dmacmd, asr); 271 #endif 272 273 /* Fixup partial xfers */ 274 acb->sc_kv.dc_addr += (dev->sc_tcnt - count); 275 acb->sc_kv.dc_count -= (dev->sc_tcnt - count); 276 acb->sc_pa.dc_addr += (dev->sc_tcnt - count); 277 acb->sc_pa.dc_count -= ((dev->sc_tcnt - count)>>1); 278 279 acb->sc_tcnt = dev->sc_tcnt = count; 280 #ifdef DEBUG 281 if(data_pointer_debug) 282 printf(" at (%x,%x):%x\n", 283 dev->sc_cur->dc_addr, dev->sc_cur->dc_count,count); 284 sbicdma_saves++; 285 #endif 286 splx(s); 287 SBIC_TRACE(dev); 288 } 289 290 291 /* 292 * DOES NOT RESTART DMA!!! 293 */ 294 void sbic_load_ptrs(dev, regs, target, lun) 295 struct sbic_softc *dev; 296 sbic_regmap_p regs; 297 int target, lun; 298 { 299 int i, s, asr, count; 300 char* vaddr, * paddr; 301 struct sbic_acb *acb; 302 303 SBIC_TRACE(dev); 304 acb = dev->sc_nexus; 305 if( !acb->sc_kv.dc_count ) { 306 /* No data to xfer */ 307 SBIC_TRACE(dev); 308 return; 309 } 310 311 s = splbio(); 312 313 dev->sc_last = dev->sc_cur = &acb->sc_pa; 314 dev->sc_tcnt = acb->sc_tcnt; 315 dev->sc_dmacmd = acb->sc_dmacmd; 316 317 #ifdef DEBUG 318 sbicdma_ops++; 319 #endif 320 if( !dev->sc_tcnt ) { 321 /* sc_tcnt == 0 implies end of segment */ 322 323 /* do kvm to pa mappings */ 324 paddr = acb->sc_pa.dc_addr = 325 (char *) kvtop(acb->sc_kv.dc_addr); 326 327 vaddr = acb->sc_kv.dc_addr; 328 count = acb->sc_kv.dc_count; 329 for(count = (NBPG - ((int)vaddr & PGOFSET)); 330 count < acb->sc_kv.dc_count 331 && (char*)kvtop(vaddr + count + 4) == paddr + count + 4; 332 count += NBPG); 333 /* If it's all contiguous... */ 334 if(count > acb->sc_kv.dc_count ) { 335 count = acb->sc_kv.dc_count; 336 #ifdef DEBUG 337 sbicdma_hits++; 338 #endif 339 } else { 340 #ifdef DEBUG 341 sbicdma_misses++; 342 #endif 343 } 344 acb->sc_tcnt = count; 345 acb->sc_pa.dc_count = count >> 1; 346 347 #ifdef DEBUG 348 if(data_pointer_debug) 349 printf("DMA recalc:kv(%x,%x)pa(%x,%x)\n", 350 acb->sc_kv.dc_addr, 351 acb->sc_kv.dc_count, 352 acb->sc_pa.dc_addr, 353 acb->sc_tcnt); 354 #endif 355 } 356 splx(s); 357 #ifdef DEBUG 358 if(data_pointer_debug) 359 printf("SBIC restoring target %d data pointers at (%x,%x)%x\n", 360 target, dev->sc_cur->dc_addr, dev->sc_cur->dc_count, 361 dev->sc_dmacmd); 362 #endif 363 SBIC_TRACE(dev); 364 } 365 366 /* 367 * used by specific sbic controller 368 * 369 * it appears that the higher level code does nothing with LUN's 370 * so I will too. I could plug it in, however so could they 371 * in scsi_scsi_cmd(). 372 */ 373 int 374 sbic_scsicmd(xs) 375 struct scsi_xfer *xs; 376 { 377 struct sbic_acb *acb; 378 struct sbic_softc *dev; 379 struct scsi_link *slp; 380 int flags, s, stat; 381 382 slp = xs->sc_link; 383 dev = slp->adapter_softc; 384 SBIC_TRACE(dev); 385 flags = xs->flags; 386 387 if (flags & SCSI_DATA_UIO) 388 panic("sbic: scsi data uio requested"); 389 390 if (dev->sc_nexus && flags & SCSI_POLL) 391 panic("sbic_scsicmd: busy"); 392 393 if (slp->target == slp->adapter_target) 394 return ESCAPE_NOT_SUPPORTED; 395 396 s = splbio(); 397 acb = dev->free_list.tqh_first; 398 if (acb) 399 TAILQ_REMOVE(&dev->free_list, acb, chain); 400 splx(s); 401 402 if (acb == NULL) { 403 #ifdef DEBUG 404 printf("sbic_scsicmd: unable to queue request for target %d\n", 405 slp->target); 406 #ifdef DDB 407 Debugger(); 408 #endif 409 #endif 410 xs->error = XS_DRIVER_STUFFUP; 411 SBIC_TRACE(dev); 412 return(TRY_AGAIN_LATER); 413 } 414 415 acb->flags = ACB_ACTIVE; 416 if (flags & SCSI_DATA_IN) 417 acb->flags |= ACB_DATAIN; 418 acb->xs = xs; 419 bcopy(xs->cmd, &acb->cmd, xs->cmdlen); 420 acb->clen = xs->cmdlen; 421 acb->sc_kv.dc_addr = xs->data; 422 acb->sc_kv.dc_count = xs->datalen; 423 acb->pa_addr = xs->data ? (char *)kvtop(xs->data) : 0; /* XXXX check */ 424 425 if (flags & SCSI_POLL) { 426 s = splbio(); 427 /* 428 * This has major side effects -- it locks up the machine 429 */ 430 431 dev->sc_flags |= SBICF_ICMD; 432 do { 433 while(dev->sc_nexus) 434 sbicpoll(dev); 435 dev->sc_nexus = acb; 436 dev->sc_stat[0] = -1; 437 dev->sc_xs = xs; 438 dev->target = slp->target; 439 dev->lun = slp->lun; 440 stat = sbicicmd(dev, slp->target, slp->lun, 441 &acb->cmd, acb->clen, 442 acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 443 } while (dev->sc_nexus != acb); 444 sbic_scsidone(acb, stat); 445 446 splx(s); 447 SBIC_TRACE(dev); 448 return(COMPLETE); 449 } 450 451 s = splbio(); 452 TAILQ_INSERT_TAIL(&dev->ready_list, acb, chain); 453 454 if (dev->sc_nexus) { 455 splx(s); 456 SBIC_TRACE(dev); 457 return(SUCCESSFULLY_QUEUED); 458 } 459 460 /* 461 * nothing is active, try to start it now. 462 */ 463 sbic_sched(dev); 464 splx(s); 465 466 SBIC_TRACE(dev); 467 /* TODO: add sbic_poll to do SCSI_POLL operations */ 468 #if 0 469 if (flags & SCSI_POLL) 470 return(COMPLETE); 471 #endif 472 return(SUCCESSFULLY_QUEUED); 473 } 474 475 /* 476 * attempt to start the next available command 477 */ 478 void 479 sbic_sched(dev) 480 struct sbic_softc *dev; 481 { 482 struct scsi_xfer *xs; 483 struct scsi_link *slp; 484 struct sbic_acb *acb; 485 int flags, /*phase,*/ stat, i; 486 487 SBIC_TRACE(dev); 488 if (dev->sc_nexus) 489 return; /* a command is current active */ 490 491 SBIC_TRACE(dev); 492 for (acb = dev->ready_list.tqh_first; acb; acb = acb->chain.tqe_next) { 493 slp = acb->xs->sc_link; 494 i = slp->target; 495 if (!(dev->sc_tinfo[i].lubusy & (1 << slp->lun))) { 496 struct sbic_tinfo *ti = &dev->sc_tinfo[i]; 497 498 TAILQ_REMOVE(&dev->ready_list, acb, chain); 499 dev->sc_nexus = acb; 500 slp = acb->xs->sc_link; 501 ti = &dev->sc_tinfo[slp->target]; 502 ti->lubusy |= (1 << slp->lun); 503 acb->sc_pa.dc_addr = acb->pa_addr; /* XXXX check */ 504 break; 505 } 506 } 507 508 SBIC_TRACE(dev); 509 if (acb == NULL) 510 return; /* did not find an available command */ 511 512 dev->sc_xs = xs = acb->xs; 513 slp = xs->sc_link; 514 flags = xs->flags; 515 516 if (flags & SCSI_RESET) 517 sbicreset(dev); 518 519 #ifdef DEBUG 520 if( data_pointer_debug > 1 ) 521 printf("sbic_sched(%d,%d)\n",slp->target,slp->lun); 522 #endif 523 dev->sc_stat[0] = -1; 524 dev->target = slp->target; 525 dev->lun = slp->lun; 526 if ( flags & SCSI_POLL || ( !sbic_parallel_operations 527 && (/*phase == STATUS_PHASE ||*/ 528 sbicdmaok(dev, xs) == 0) ) ) 529 stat = sbicicmd(dev, slp->target, slp->lun, &acb->cmd, 530 acb->clen, acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 531 else if (sbicgo(dev, xs) == 0) { 532 SBIC_TRACE(dev); 533 return; 534 } else 535 stat = dev->sc_stat[0]; 536 537 sbic_scsidone(acb, stat); 538 SBIC_TRACE(dev); 539 } 540 541 void 542 sbic_scsidone(acb, stat) 543 struct sbic_acb *acb; 544 int stat; 545 { 546 struct scsi_xfer *xs; 547 struct scsi_link *slp; 548 struct sbic_softc *dev; 549 int s, dosched = 0; 550 551 xs = acb->xs; 552 slp = xs->sc_link; 553 dev = slp->adapter_softc; 554 SBIC_TRACE(dev); 555 #ifdef DIAGNOSTIC 556 if (acb == NULL || xs == NULL) { 557 printf("sbic_scsidone -- (%d,%d) no scsi_xfer\n", 558 dev->target, dev->lun); 559 #ifdef DDB 560 Debugger(); 561 #endif 562 return; 563 } 564 #endif 565 if (slp->device_softc && 566 ((struct device *)(slp->device_softc))->dv_unit < dk_ndrive) 567 ++dk_xfer[((struct device *)(slp->device_softc))->dv_unit]; 568 /* 569 * is this right? 570 */ 571 xs->status = stat; 572 573 #ifdef DEBUG 574 if( data_pointer_debug > 1 ) 575 printf("scsidone: (%d,%d)->(%d,%d)%02x\n", 576 slp->target, slp->lun, 577 dev->target, dev->lun, stat); 578 if( xs->sc_link->target == dev->sc_link.adapter_target ) 579 panic("target == hostid"); 580 #endif 581 582 if (xs->error == XS_NOERROR && !(acb->flags & ACB_CHKSENSE)) { 583 if (stat == SCSI_CHECK) { 584 /* Schedule a REQUEST SENSE */ 585 struct scsi_sense *ss = (void *)&acb->cmd; 586 #ifdef DEBUG 587 if (report_sense) 588 printf("sbic_scsidone: autosense %02x targ %d lun %d", 589 acb->cmd.opcode, slp->target, slp->lun); 590 #endif 591 bzero(ss, sizeof(*ss)); 592 ss->opcode = REQUEST_SENSE; 593 ss->byte2 = slp->lun << 5; 594 ss->length = sizeof(struct scsi_sense_data); 595 acb->clen = sizeof(*ss); 596 acb->sc_kv.dc_addr = (char *)&xs->sense; 597 acb->sc_kv.dc_count = sizeof(struct scsi_sense_data); 598 acb->pa_addr = (char *)kvtop(&xs->sense); /* XXX check */ 599 acb->flags = ACB_ACTIVE | ACB_CHKSENSE | ACB_DATAIN; 600 TAILQ_INSERT_HEAD(&dev->ready_list, acb, chain); 601 dev->sc_tinfo[slp->target].lubusy &= 602 ~(1 << slp->lun); 603 dev->sc_tinfo[slp->target].senses++; 604 if (dev->sc_nexus == acb) { 605 dev->sc_nexus = NULL; 606 dev->sc_xs = NULL; 607 sbic_sched(dev); 608 } 609 SBIC_TRACE(dev); 610 return; 611 } 612 } 613 if (xs->error == XS_NOERROR && (acb->flags & ACB_CHKSENSE)) { 614 xs->error = XS_SENSE; 615 #ifdef DEBUG 616 if (report_sense) 617 printf(" => %02x %02x\n", xs->sense.extended_flags, 618 xs->sense.extended_extra_bytes[3]); 619 #endif 620 } else { 621 xs->resid = 0; /* XXXX */ 622 } 623 #if whataboutthisone 624 case SCSI_BUSY: 625 xs->error = XS_BUSY; 626 break; 627 #endif 628 xs->flags |= ITSDONE; 629 630 /* 631 * Remove the ACB from whatever queue it's on. We have to do a bit of 632 * a hack to figure out which queue it's on. Note that it is *not* 633 * necessary to cdr down the ready queue, but we must cdr down the 634 * nexus queue and see if it's there, so we can mark the unit as no 635 * longer busy. This code is sickening, but it works. 636 */ 637 if (acb == dev->sc_nexus) { 638 dev->sc_nexus = NULL; 639 dev->sc_xs = NULL; 640 dev->sc_tinfo[slp->target].lubusy &= ~(1<<slp->lun); 641 if (dev->ready_list.tqh_first) 642 dosched = 1; /* start next command */ 643 } else if (dev->ready_list.tqh_last == &acb->chain.tqe_next) { 644 TAILQ_REMOVE(&dev->ready_list, acb, chain); 645 } else { 646 register struct sbic_acb *acb2; 647 for (acb2 = dev->nexus_list.tqh_first; acb2; 648 acb2 = acb2->chain.tqe_next) { 649 if (acb2 == acb) { 650 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 651 dev->sc_tinfo[slp->target].lubusy 652 &= ~(1<<slp->lun); 653 break; 654 } 655 } 656 if (acb2) 657 ; 658 else if (acb->chain.tqe_next) { 659 TAILQ_REMOVE(&dev->ready_list, acb, chain); 660 } else { 661 printf("%s: can't find matching acb\n", 662 dev->sc_dev.dv_xname); 663 #ifdef DDB 664 Debugger(); 665 #endif 666 } 667 } 668 /* Put it on the free list. */ 669 acb->flags = ACB_FREE; 670 TAILQ_INSERT_HEAD(&dev->free_list, acb, chain); 671 672 dev->sc_tinfo[slp->target].cmds++; 673 674 scsi_done(xs); 675 676 if (dosched) 677 sbic_sched(dev); 678 SBIC_TRACE(dev); 679 } 680 681 int 682 sbicdmaok(dev, xs) 683 struct sbic_softc *dev; 684 struct scsi_xfer *xs; 685 { 686 if (sbic_no_dma || xs->datalen & 0x1 || (u_int)xs->data & 0x3) 687 return(0); 688 /* 689 * controller supports dma to any addresses? 690 */ 691 else if ((dev->sc_flags & SBICF_BADDMA) == 0) 692 return(1); 693 /* 694 * this address is ok for dma? 695 */ 696 else if (sbiccheckdmap(xs->data, xs->datalen, dev->sc_dmamask) == 0) 697 return(1); 698 /* 699 * we have a bounce buffer? 700 */ 701 else if (dev->sc_tinfo[xs->sc_link->target].bounce) 702 return(1); 703 /* 704 * try to get one 705 */ 706 else if (dev->sc_tinfo[xs->sc_link->target].bounce 707 = (char *)alloc_z2mem(MAXPHYS)) { 708 if (isztwomem(dev->sc_tinfo[xs->sc_link->target].bounce)) 709 printf("alloc ZII target %d bounce pa 0x%x\n", 710 xs->sc_link->target, 711 kvtop(dev->sc_tinfo[xs->sc_link->target].bounce)); 712 else if (dev->sc_tinfo[xs->sc_link->target].bounce) 713 printf("alloc CHIP target %d bounce pa 0x%x\n", 714 xs->sc_link->target, 715 PREP_DMA_MEM(dev->sc_tinfo[xs->sc_link->target].bounce)); 716 return(1); 717 } 718 719 return(0); 720 } 721 722 723 int 724 sbicwait(regs, until, timeo, line) 725 sbic_regmap_p regs; 726 char until; 727 int timeo; 728 int line; 729 { 730 u_char val; 731 int csr; 732 733 SBIC_TRACE((struct sbic_softc *)0); 734 if (timeo == 0) 735 timeo = 1000000; /* some large value.. */ 736 737 GET_SBIC_asr(regs,val); 738 while ((val & until) == 0) { 739 if (timeo-- == 0) { 740 GET_SBIC_csr(regs, csr); 741 printf("sbicwait TIMEO @%d with asr=x%x csr=x%x\n", 742 line, val, csr); 743 #if defined(DDB) && defined(DEBUG) 744 Debugger(); 745 #endif 746 return(val); /* Maybe I should abort */ 747 break; 748 } 749 DELAY(1); 750 GET_SBIC_asr(regs,val); 751 } 752 SBIC_TRACE((struct sbic_softc *)0); 753 return(val); 754 } 755 756 int 757 sbicabort(dev, regs, where) 758 struct sbic_softc *dev; 759 sbic_regmap_p regs; 760 char *where; 761 { 762 u_char csr, asr; 763 764 GET_SBIC_asr(regs, asr); 765 GET_SBIC_csr(regs, csr); 766 767 printf ("%s: abort %s: csr = 0x%02x, asr = 0x%02x\n", 768 dev->sc_dev.dv_xname, where, csr, asr); 769 770 771 #if 0 772 /* Clean up running command */ 773 if (dev->sc_nexus != NULL) { 774 dev->sc_nexus->xs->error = XS_DRIVER_STUFFUP; 775 sbic_scsidone(dev->sc_nexus, dev->sc_stat[0]); 776 } 777 while (acb = dev->nexus_list.tqh_first) { 778 acb->xs->error = XS_DRIVER_STUFFUP; 779 sbic_scsidone(acb, -1 /*acb->stat[0]*/); 780 } 781 #endif 782 783 /* Clean up chip itself */ 784 if (dev->sc_flags & SBICF_SELECTED) { 785 while( asr & SBIC_ASR_DBR ) { 786 /* sbic is jammed w/data. need to clear it */ 787 /* But we don't know what direction it needs to go */ 788 GET_SBIC_data(regs, asr); 789 printf("%s: abort %s: clearing data buffer 0x%02x\n", 790 dev->sc_dev.dv_xname, where, asr); 791 GET_SBIC_asr(regs, asr); 792 if( asr & SBIC_ASR_DBR ) /* Not the read direction, then */ 793 SET_SBIC_data(regs, asr); 794 GET_SBIC_asr(regs, asr); 795 } 796 WAIT_CIP(regs); 797 printf("%s: sbicabort - sending ABORT command\n", dev->sc_dev.dv_xname); 798 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 799 WAIT_CIP(regs); 800 801 GET_SBIC_asr(regs, asr); 802 if (asr & (SBIC_ASR_BSY|SBIC_ASR_LCI)) { 803 /* ok, get more drastic.. */ 804 805 printf("%s: sbicabort - asr %x, trying to reset\n", dev->sc_dev.dv_xname, asr); 806 sbicreset(dev); 807 dev->sc_flags &= ~SBICF_SELECTED; 808 return -1; 809 } 810 printf("%s: sbicabort - sending DISC command\n", dev->sc_dev.dv_xname); 811 SET_SBIC_cmd(regs, SBIC_CMD_DISC); 812 813 do { 814 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0); 815 GET_SBIC_csr (regs, csr); 816 CSR_TRACE('a',csr,asr,0); 817 } while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) 818 && (csr != SBIC_CSR_CMD_INVALID)); 819 820 /* lets just hope it worked.. */ 821 dev->sc_flags &= ~SBICF_SELECTED; 822 } 823 return -1; 824 } 825 826 827 /* 828 * Initialize driver-private structures 829 */ 830 831 void 832 sbicinit(dev) 833 struct sbic_softc *dev; 834 { 835 sbic_regmap_p regs; 836 u_int my_id, i, s; 837 u_char csr; 838 struct sbic_acb *acb; 839 u_int inhibit_sync; 840 841 extern u_long scsi_nosync; 842 extern int shift_nosync; 843 844 regs = dev->sc_sbicp; 845 846 if ((dev->sc_flags & SBICF_ALIVE) == 0) { 847 TAILQ_INIT(&dev->ready_list); 848 TAILQ_INIT(&dev->nexus_list); 849 TAILQ_INIT(&dev->free_list); 850 dev->sc_nexus = NULL; 851 dev->sc_xs = NULL; 852 acb = dev->sc_acb; 853 bzero(acb, sizeof(dev->sc_acb)); 854 for (i = 0; i < sizeof(dev->sc_acb) / sizeof(*acb); i++) { 855 TAILQ_INSERT_TAIL(&dev->free_list, acb, chain); 856 acb++; 857 } 858 bzero(dev->sc_tinfo, sizeof(dev->sc_tinfo)); 859 #ifdef DEBUG 860 /* make sure timeout is really not needed */ 861 timeout((void *)sbictimeout, dev, 30 * hz); 862 #endif 863 864 } else panic("sbic: reinitializing driver!"); 865 866 dev->sc_flags |= SBICF_ALIVE; 867 dev->sc_flags &= ~SBICF_SELECTED; 868 869 /* initialize inhibit array */ 870 if (scsi_nosync) { 871 inhibit_sync = (scsi_nosync >> shift_nosync) & 0xff; 872 shift_nosync += 8; 873 #ifdef DEBUG 874 if (inhibit_sync) 875 printf("%s: Inhibiting synchronous transfer %02x\n", 876 dev->sc_dev.dv_xname, inhibit_sync); 877 #endif 878 for (i = 0; i < 8; ++i) 879 if (inhibit_sync & (1 << i)) 880 sbic_inhibit_sync[i] = 1; 881 } 882 883 sbicreset(dev); 884 } 885 886 void 887 sbicreset(dev) 888 struct sbic_softc *dev; 889 { 890 sbic_regmap_p regs; 891 u_int my_id, i, s; 892 u_char csr; 893 struct sbic_acb *acb; 894 895 regs = dev->sc_sbicp; 896 #if 0 897 if (dev->sc_flags & SBICF_ALIVE) { 898 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 899 WAIT_CIP(regs); 900 } 901 #else 902 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 903 WAIT_CIP(regs); 904 #endif 905 s = splbio(); 906 my_id = dev->sc_link.adapter_target & SBIC_ID_MASK; 907 908 /* Enable advanced mode */ 909 my_id |= SBIC_ID_EAF /*| SBIC_ID_EHP*/ ; 910 SET_SBIC_myid(regs, my_id); 911 912 /* 913 * Disable interrupts (in dmainit) then reset the chip 914 */ 915 SET_SBIC_cmd(regs, SBIC_CMD_RESET); 916 DELAY(25); 917 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 918 GET_SBIC_csr(regs, csr); /* clears interrupt also */ 919 920 if (dev->sc_clkfreq < 110) 921 my_id |= SBIC_ID_FS_8_10; 922 else if (dev->sc_clkfreq < 160) 923 my_id |= SBIC_ID_FS_12_15; 924 else if (dev->sc_clkfreq < 210) 925 my_id |= SBIC_ID_FS_16_20; 926 927 SET_SBIC_myid(regs, my_id); 928 929 /* 930 * Set up various chip parameters 931 */ 932 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI /* | SBIC_CTL_HSP */ 933 | SBIC_MACHINE_DMA_MODE); 934 /* 935 * don't allow (re)selection (SBIC_RID_ES) 936 * until we can handle target mode!! 937 */ 938 SET_SBIC_rselid(regs, SBIC_RID_ER); 939 SET_SBIC_syn(regs, 0); /* asynch for now */ 940 941 /* 942 * anything else was zeroed by reset 943 */ 944 splx(s); 945 946 #if 0 947 if ((dev->sc_flags & SBICF_ALIVE) == 0) { 948 TAILQ_INIT(&dev->ready_list); 949 TAILQ_INIT(&dev->nexus_list); 950 TAILQ_INIT(&dev->free_list); 951 dev->sc_nexus = NULL; 952 dev->sc_xs = NULL; 953 acb = dev->sc_acb; 954 bzero(acb, sizeof(dev->sc_acb)); 955 for (i = 0; i < sizeof(dev->sc_acb) / sizeof(*acb); i++) { 956 TAILQ_INSERT_TAIL(&dev->free_list, acb, chain); 957 acb++; 958 } 959 bzero(dev->sc_tinfo, sizeof(dev->sc_tinfo)); 960 } else { 961 if (dev->sc_nexus != NULL) { 962 dev->sc_nexus->xs->error = XS_DRIVER_STUFFUP; 963 sbic_scsidone(dev->sc_nexus, dev->sc_stat[0]); 964 } 965 while (acb = dev->nexus_list.tqh_first) { 966 acb->xs->error = XS_DRIVER_STUFFUP; 967 sbic_scsidone(acb, -1 /*acb->stat[0]*/); 968 } 969 } 970 971 dev->sc_flags |= SBICF_ALIVE; 972 #endif 973 dev->sc_flags &= ~SBICF_SELECTED; 974 } 975 976 void 977 sbicerror(dev, regs, csr) 978 struct sbic_softc *dev; 979 sbic_regmap_p regs; 980 u_char csr; 981 { 982 struct scsi_xfer *xs; 983 984 xs = dev->sc_xs; 985 986 #ifdef DIAGNOSTIC 987 if (xs == NULL) 988 panic("sbicerror"); 989 #endif 990 if (xs->flags & SCSI_SILENT) 991 return; 992 993 printf("%s: ", dev->sc_dev.dv_xname); 994 printf("csr == 0x%02x\n", csr); /* XXX */ 995 } 996 997 /* 998 * select the bus, return when selected or error. 999 */ 1000 int 1001 sbicselectbus(dev, regs, target, lun, our_addr) 1002 struct sbic_softc *dev; 1003 sbic_regmap_p regs; 1004 u_char target, lun, our_addr; 1005 { 1006 u_char asr, csr, id; 1007 1008 SBIC_TRACE(dev); 1009 QPRINTF(("sbicselectbus %d\n", target)); 1010 1011 /* 1012 * if we're already selected, return (XXXX panic maybe?) 1013 */ 1014 if (dev->sc_flags & SBICF_SELECTED) { 1015 SBIC_TRACE(dev); 1016 return(1); 1017 } 1018 1019 /* 1020 * issue select 1021 */ 1022 SBIC_TC_PUT(regs, 0); 1023 SET_SBIC_selid(regs, target); 1024 SET_SBIC_timeo(regs, SBIC_TIMEOUT(250,dev->sc_clkfreq)); 1025 1026 /* 1027 * set sync or async 1028 */ 1029 if (dev->sc_sync[target].state == SYNC_DONE) 1030 SET_SBIC_syn(regs, SBIC_SYN (dev->sc_sync[target].offset, 1031 dev->sc_sync[target].period)); 1032 else 1033 SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period)); 1034 1035 GET_SBIC_asr(regs, asr); 1036 if( asr & (SBIC_ASR_INT|SBIC_ASR_BSY) ) { 1037 /* This means we got ourselves reselected upon */ 1038 /* printf("sbicselectbus: INT/BSY asr %02x\n", asr);*/ 1039 #ifdef DDB 1040 /* Debugger();*/ 1041 #endif 1042 SBIC_TRACE(dev); 1043 return 1; 1044 } 1045 1046 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN); 1047 1048 /* 1049 * wait for select (merged from seperate function may need 1050 * cleanup) 1051 */ 1052 WAIT_CIP(regs); 1053 do { 1054 asr = SBIC_WAIT(regs, SBIC_ASR_INT | SBIC_ASR_LCI, 0); 1055 if (asr & SBIC_ASR_LCI) { 1056 #ifdef DEBUG 1057 if (reselect_debug) 1058 printf("sbicselectbus: late LCI asr %02x\n", asr); 1059 #endif 1060 SBIC_TRACE(dev); 1061 return 1; 1062 } 1063 GET_SBIC_csr (regs, csr); 1064 CSR_TRACE('s',csr,asr,target); 1065 QPRINTF(("%02x ", csr)); 1066 if( csr == SBIC_CSR_RSLT_NI || csr == SBIC_CSR_RSLT_IFY) { 1067 #ifdef DEBUG 1068 if(reselect_debug) 1069 printf("sbicselectbus: reselected asr %02x\n", asr); 1070 #endif 1071 /* We need to handle this now so we don't lock up later */ 1072 sbicnextstate(dev, csr, asr); 1073 SBIC_TRACE(dev); 1074 return 1; 1075 } 1076 if( csr == SBIC_CSR_SLT || csr == SBIC_CSR_SLT_ATN) { 1077 panic("sbicselectbus: target issued select!"); 1078 return 1; 1079 } 1080 } while (csr != (SBIC_CSR_MIS_2|MESG_OUT_PHASE) 1081 && csr != (SBIC_CSR_MIS_2|CMD_PHASE) && csr != SBIC_CSR_SEL_TIMEO); 1082 1083 /* Enable (or not) reselection */ 1084 if(!sbic_enable_reselect && dev->nexus_list.tqh_first == NULL) 1085 SET_SBIC_rselid (regs, 0); 1086 else 1087 SET_SBIC_rselid (regs, SBIC_RID_ER); 1088 1089 if (csr == (SBIC_CSR_MIS_2|CMD_PHASE)) { 1090 dev->sc_flags |= SBICF_SELECTED; /* device ignored ATN */ 1091 GET_SBIC_selid(regs, id); 1092 dev->target = id; 1093 GET_SBIC_tlun(regs,dev->lun); 1094 if( dev->lun & SBIC_TLUN_VALID ) 1095 dev->lun &= SBIC_TLUN_MASK; 1096 else 1097 dev->lun = lun; 1098 } else if (csr == (SBIC_CSR_MIS_2|MESG_OUT_PHASE)) { 1099 /* 1100 * Send identify message 1101 * (SCSI-2 requires an identify msg (?)) 1102 */ 1103 GET_SBIC_selid(regs, id); 1104 dev->target = id; 1105 GET_SBIC_tlun(regs,dev->lun); 1106 if( dev->lun & SBIC_TLUN_VALID ) 1107 dev->lun &= SBIC_TLUN_MASK; 1108 else 1109 dev->lun = lun; 1110 /* 1111 * handle drives that don't want to be asked 1112 * whether to go sync at all. 1113 */ 1114 if (sbic_inhibit_sync[id] 1115 && dev->sc_sync[id].state == SYNC_START) { 1116 #ifdef DEBUG 1117 if (sync_debug) 1118 printf("Forcing target %d asynchronous.\n", id); 1119 #endif 1120 dev->sc_sync[id].offset = 0; 1121 dev->sc_sync[id].period = sbic_min_period; 1122 dev->sc_sync[id].state = SYNC_DONE; 1123 } 1124 1125 1126 if (dev->sc_sync[id].state != SYNC_START){ 1127 if( dev->sc_xs->flags & SCSI_POLL 1128 || (dev->sc_flags & SBICF_ICMD) 1129 || !sbic_enable_reselect ) 1130 SEND_BYTE (regs, MSG_IDENTIFY | lun); 1131 else 1132 SEND_BYTE (regs, MSG_IDENTIFY_DR | lun); 1133 } else { 1134 /* 1135 * try to initiate a sync transfer. 1136 * So compose the sync message we're going 1137 * to send to the target 1138 */ 1139 1140 #ifdef DEBUG 1141 if (sync_debug) 1142 printf("Sending sync request to target %d ... ", 1143 id); 1144 #endif 1145 /* 1146 * setup scsi message sync message request 1147 */ 1148 dev->sc_msg[0] = MSG_IDENTIFY | lun; 1149 dev->sc_msg[1] = MSG_EXT_MESSAGE; 1150 dev->sc_msg[2] = 3; 1151 dev->sc_msg[3] = MSG_SYNC_REQ; 1152 dev->sc_msg[4] = sbictoscsiperiod(dev, regs, 1153 sbic_min_period); 1154 dev->sc_msg[5] = sbic_max_offset; 1155 1156 if (sbicxfstart(regs, 6, MESG_OUT_PHASE, sbic_cmd_wait)) 1157 sbicxfout(regs, 6, dev->sc_msg, MESG_OUT_PHASE); 1158 1159 dev->sc_sync[id].state = SYNC_SENT; 1160 #ifdef DEBUG 1161 if (sync_debug) 1162 printf ("sent\n"); 1163 #endif 1164 } 1165 1166 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0); 1167 GET_SBIC_csr (regs, csr); 1168 CSR_TRACE('y',csr,asr,target); 1169 QPRINTF(("[%02x]", csr)); 1170 #ifdef DEBUG 1171 if (sync_debug && dev->sc_sync[id].state == SYNC_SENT) 1172 printf("csr-result of last msgout: 0x%x\n", csr); 1173 #endif 1174 1175 if (csr != SBIC_CSR_SEL_TIMEO) 1176 dev->sc_flags |= SBICF_SELECTED; 1177 } 1178 if (csr == SBIC_CSR_SEL_TIMEO) 1179 dev->sc_xs->error = XS_SELTIMEOUT; 1180 1181 QPRINTF(("\n")); 1182 1183 SBIC_TRACE(dev); 1184 return(csr == SBIC_CSR_SEL_TIMEO); 1185 } 1186 1187 int 1188 sbicxfstart(regs, len, phase, wait) 1189 sbic_regmap_p regs; 1190 int len, wait; 1191 u_char phase; 1192 { 1193 u_char id; 1194 1195 switch (phase) { 1196 case DATA_IN_PHASE: 1197 case MESG_IN_PHASE: 1198 GET_SBIC_selid (regs, id); 1199 id |= SBIC_SID_FROM_SCSI; 1200 SET_SBIC_selid (regs, id); 1201 SBIC_TC_PUT (regs, (unsigned)len); 1202 break; 1203 case DATA_OUT_PHASE: 1204 case MESG_OUT_PHASE: 1205 case CMD_PHASE: 1206 GET_SBIC_selid (regs, id); 1207 id &= ~SBIC_SID_FROM_SCSI; 1208 SET_SBIC_selid (regs, id); 1209 SBIC_TC_PUT (regs, (unsigned)len); 1210 break; 1211 default: 1212 SBIC_TC_PUT (regs, 0); 1213 } 1214 QPRINTF(("sbicxfstart %d, %d, %d\n", len, phase, wait)); 1215 1216 return(1); 1217 } 1218 1219 int 1220 sbicxfout(regs, len, bp, phase) 1221 sbic_regmap_p regs; 1222 int len; 1223 void *bp; 1224 int phase; 1225 { 1226 u_char orig_csr, csr, asr, *buf; 1227 int wait; 1228 1229 buf = bp; 1230 wait = sbic_data_wait; 1231 1232 QPRINTF(("sbicxfout {%d} %02x %02x %02x %02x %02x " 1233 "%02x %02x %02x %02x %02x\n", len, buf[0], buf[1], buf[2], 1234 buf[3], buf[4], buf[5], buf[6], buf[7], buf[8], buf[9])); 1235 1236 GET_SBIC_csr (regs, orig_csr); 1237 CSR_TRACE('>',orig_csr,0,0); 1238 1239 /* 1240 * sigh.. WD-PROTO strikes again.. sending the command in one go 1241 * causes the chip to lock up if talking to certain (misbehaving?) 1242 * targets. Anyway, this procedure should work for all targets, but 1243 * it's slightly slower due to the overhead 1244 */ 1245 WAIT_CIP (regs); 1246 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1247 for (;len > 0; len--) { 1248 GET_SBIC_asr (regs, asr); 1249 while ((asr & SBIC_ASR_DBR) == 0) { 1250 if ((asr & SBIC_ASR_INT) || --wait < 0) { 1251 #ifdef DEBUG 1252 if (sbic_debug) 1253 printf("sbicxfout fail: l%d i%x w%d\n", 1254 len, asr, wait); 1255 #endif 1256 return (len); 1257 } 1258 /* DELAY(1);*/ 1259 GET_SBIC_asr (regs, asr); 1260 } 1261 1262 SET_SBIC_data (regs, *buf); 1263 buf++; 1264 } 1265 SBIC_TC_GET(regs, len); 1266 QPRINTF(("sbicxfout done %d bytes\n", len)); 1267 /* 1268 * this leaves with one csr to be read 1269 */ 1270 return(0); 1271 } 1272 1273 /* returns # bytes left to read */ 1274 int 1275 sbicxfin(regs, len, bp) 1276 sbic_regmap_p regs; 1277 int len; 1278 void *bp; 1279 { 1280 int wait, read; 1281 u_char *obp, *buf; 1282 u_char orig_csr, csr, asr; 1283 1284 wait = sbic_data_wait; 1285 obp = bp; 1286 buf = bp; 1287 1288 GET_SBIC_csr (regs, orig_csr); 1289 CSR_TRACE('<',orig_csr,0,0); 1290 1291 QPRINTF(("sbicxfin %d, csr=%02x\n", len, orig_csr)); 1292 1293 WAIT_CIP (regs); 1294 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1295 for (;len > 0; len--) { 1296 GET_SBIC_asr (regs, asr); 1297 if((asr & SBIC_ASR_PE)) { 1298 #ifdef DEBUG 1299 printf("sbicxfin parity error: l%d i%x w%d\n", 1300 len, asr, wait); 1301 /* return ((unsigned long)buf - (unsigned long)bp); */ 1302 #ifdef DDB 1303 Debugger(); 1304 #endif 1305 #endif 1306 } 1307 while ((asr & SBIC_ASR_DBR) == 0) { 1308 if ((asr & SBIC_ASR_INT) || --wait < 0) { 1309 #ifdef DEBUG 1310 if (sbic_debug) { 1311 QPRINTF(("sbicxfin fail:{%d} %02x %02x %02x %02x %02x %02x " 1312 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1313 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1314 printf("sbicxfin fail: l%d i%x w%d\n", 1315 len, asr, wait); 1316 } 1317 #endif 1318 return len; 1319 } 1320 1321 if( ! asr & SBIC_ASR_BSY ) { 1322 GET_SBIC_csr(regs, csr); 1323 CSR_TRACE('<',csr,asr,len); 1324 QPRINTF(("[CSR%02xASR%02x]", csr, asr)); 1325 } 1326 1327 /* DELAY(1);*/ 1328 GET_SBIC_asr (regs, asr); 1329 } 1330 1331 GET_SBIC_data (regs, *buf); 1332 /* QPRINTF(("asr=%02x, csr=%02x, data=%02x\n", asr, csr, *buf));*/ 1333 buf++; 1334 } 1335 1336 QPRINTF(("sbicxfin {%d} %02x %02x %02x %02x %02x %02x " 1337 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1338 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1339 1340 /* this leaves with one csr to be read */ 1341 return len; 1342 } 1343 1344 /* 1345 * SCSI 'immediate' command: issue a command to some SCSI device 1346 * and get back an 'immediate' response (i.e., do programmed xfer 1347 * to get the response data). 'cbuf' is a buffer containing a scsi 1348 * command of length clen bytes. 'buf' is a buffer of length 'len' 1349 * bytes for data. The transfer direction is determined by the device 1350 * (i.e., by the scsi bus data xfer phase). If 'len' is zero, the 1351 * command must supply no data. 1352 */ 1353 int 1354 sbicicmd(dev, target, lun, cbuf, clen, buf, len) 1355 struct sbic_softc *dev; 1356 void *cbuf, *buf; 1357 int clen, len; 1358 { 1359 sbic_regmap_p regs; 1360 u_char phase, csr, asr; 1361 int wait, newtarget, cmd_sent, parity_err; 1362 struct sbic_acb *acb; 1363 1364 int discon; 1365 int i; 1366 1367 #define CSR_LOG_BUF_SIZE 0 1368 #if CSR_LOG_BUF_SIZE 1369 int bufptr; 1370 int csrbuf[CSR_LOG_BUF_SIZE]; 1371 bufptr=0; 1372 #endif 1373 1374 SBIC_TRACE(dev); 1375 regs = dev->sc_sbicp; 1376 acb = dev->sc_nexus; 1377 1378 /* Make sure pointers are OK */ 1379 dev->sc_last = dev->sc_cur = &acb->sc_pa; 1380 dev->sc_tcnt = acb->sc_tcnt = 0; 1381 acb->sc_pa.dc_count = 0; /* No DMA */ 1382 acb->sc_kv.dc_addr = buf; 1383 acb->sc_kv.dc_count = len; 1384 1385 #ifdef DEBUG 1386 routine = 3; 1387 debug_sbic_regs = regs; /* store this to allow debug calls */ 1388 if( data_pointer_debug > 1 ) 1389 printf("sbicicmd(%d,%d):%d\n", target, lun, 1390 acb->sc_kv.dc_count); 1391 #endif 1392 1393 /* 1394 * set the sbic into non-DMA mode 1395 */ 1396 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI /*| SBIC_CTL_HSP*/); 1397 1398 dev->sc_stat[0] = 0xff; 1399 dev->sc_msg[0] = 0xff; 1400 i = 1; /* pre-load */ 1401 1402 /* We're stealing the SCSI bus */ 1403 dev->sc_flags |= SBICF_ICMD; 1404 1405 do { 1406 /* 1407 * select the SCSI bus (it's an error if bus isn't free) 1408 */ 1409 if (!( dev->sc_flags & SBICF_SELECTED ) 1410 && sbicselectbus(dev, regs, target, lun, dev->sc_scsiaddr)) { 1411 /*printf("sbicicmd trying to select busy bus!\n");*/ 1412 dev->sc_flags &= ~SBICF_ICMD; 1413 return(-1); 1414 } 1415 1416 /* 1417 * Wait for a phase change (or error) then let the device sequence 1418 * us through the various SCSI phases. 1419 */ 1420 1421 wait = sbic_cmd_wait; 1422 1423 asr = GET_SBIC_asr (regs, asr); 1424 GET_SBIC_csr (regs, csr); 1425 CSR_TRACE('I',csr,asr,target); 1426 QPRINTF((">ASR:%02xCSR:%02x<", asr, csr)); 1427 1428 #if CSR_LOG_BUF_SIZE 1429 csrbuf[bufptr++] = csr; 1430 #endif 1431 1432 1433 switch (csr) { 1434 case SBIC_CSR_S_XFERRED: 1435 case SBIC_CSR_DISC: 1436 case SBIC_CSR_DISC_1: 1437 dev->sc_flags &= ~SBICF_SELECTED; 1438 GET_SBIC_cmd_phase (regs, phase); 1439 if (phase == 0x60) { 1440 GET_SBIC_tlun (regs, dev->sc_stat[0]); 1441 i = 0; /* done */ 1442 /* break; /* Bypass all the state gobldygook */ 1443 } else { 1444 #ifdef DEBUG 1445 if(reselect_debug>1) 1446 printf("sbicicmd: handling disconnect\n"); 1447 #endif 1448 i = SBIC_STATE_DISCONNECT; 1449 } 1450 break; 1451 1452 case SBIC_CSR_XFERRED|CMD_PHASE: 1453 case SBIC_CSR_MIS|CMD_PHASE: 1454 case SBIC_CSR_MIS_1|CMD_PHASE: 1455 case SBIC_CSR_MIS_2|CMD_PHASE: 1456 if (sbicxfstart(regs, clen, CMD_PHASE, sbic_cmd_wait)) 1457 if (sbicxfout(regs, clen, 1458 cbuf, CMD_PHASE)) 1459 i = sbicabort(dev, regs,"icmd sending cmd"); 1460 #if 0 1461 GET_SBIC_csr(regs, csr); /* Lets us reload tcount */ 1462 WAIT_CIP(regs); 1463 GET_SBIC_asr(regs, asr); 1464 CSR_TRACE('I',csr,asr,target); 1465 if( asr & (SBIC_ASR_BSY|SBIC_ASR_LCI|SBIC_ASR_CIP) ) 1466 printf("next: cmd sent asr %02x, csr %02x\n", 1467 asr, csr); 1468 #endif 1469 break; 1470 1471 #if 0 1472 case SBIC_CSR_XFERRED|DATA_OUT_PHASE: 1473 case SBIC_CSR_XFERRED|DATA_IN_PHASE: 1474 case SBIC_CSR_MIS|DATA_OUT_PHASE: 1475 case SBIC_CSR_MIS|DATA_IN_PHASE: 1476 case SBIC_CSR_MIS_1|DATA_OUT_PHASE: 1477 case SBIC_CSR_MIS_1|DATA_IN_PHASE: 1478 case SBIC_CSR_MIS_2|DATA_OUT_PHASE: 1479 case SBIC_CSR_MIS_2|DATA_IN_PHASE: 1480 if (acb->sc_kv.dc_count <= 0) 1481 i = sbicabort(dev, regs, "icmd out of data"); 1482 else { 1483 wait = sbic_data_wait; 1484 if (sbicxfstart(regs, 1485 acb->sc_kv.dc_count, 1486 SBIC_PHASE(csr), wait)) 1487 if (csr & 0x01) 1488 /* data in? */ 1489 i=sbicxfin(regs, 1490 acb->sc_kv.dc_count, 1491 acb->sc_kv.dc_addr); 1492 else 1493 i=sbicxfout(regs, 1494 acb->sc_kv.dc_count, 1495 acb->sc_kv.dc_addr, 1496 SBIC_PHASE(csr)); 1497 acb->sc_kv.dc_addr += 1498 (acb->sc_kv.dc_count - i); 1499 acb->sc_kv.dc_count = i; 1500 i = 1; 1501 } 1502 break; 1503 1504 #endif 1505 case SBIC_CSR_XFERRED|STATUS_PHASE: 1506 case SBIC_CSR_MIS|STATUS_PHASE: 1507 case SBIC_CSR_MIS_1|STATUS_PHASE: 1508 case SBIC_CSR_MIS_2|STATUS_PHASE: 1509 /* 1510 * the sbic does the status/cmd-complete reading ok, 1511 * so do this with its hi-level commands. 1512 */ 1513 #ifdef DEBUG 1514 if(sbic_debug) 1515 printf("SBICICMD status phase\n"); 1516 #endif 1517 SBIC_TC_PUT(regs, 0); 1518 SET_SBIC_cmd_phase(regs, 0x46); 1519 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1520 break; 1521 1522 #if THIS_IS_A_RESERVED_STATE 1523 case BUS_FREE_PHASE: /* This is not legal */ 1524 if( dev->sc_stat[0] != 0xff ) 1525 goto out; 1526 break; 1527 #endif 1528 1529 default: 1530 i = sbicnextstate(dev, csr, asr); 1531 } 1532 1533 /* 1534 * make sure the last command was taken, 1535 * ie. we're not hunting after an ignored command.. 1536 */ 1537 GET_SBIC_asr(regs, asr); 1538 1539 /* tapes may take a loooong time.. */ 1540 while (asr & SBIC_ASR_BSY){ 1541 if(asr & SBIC_ASR_DBR) { 1542 printf("sbicicmd: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", 1543 csr,asr); 1544 #ifdef DDB 1545 Debugger(); 1546 #endif 1547 /* SBIC is jammed */ 1548 /* DUNNO which direction */ 1549 /* Try old direction */ 1550 GET_SBIC_data(regs,i); 1551 GET_SBIC_asr(regs, asr); 1552 if( asr & SBIC_ASR_DBR) /* Wants us to write */ 1553 SET_SBIC_data(regs,i); 1554 } 1555 GET_SBIC_asr(regs, asr); 1556 } 1557 1558 /* 1559 * wait for last command to complete 1560 */ 1561 if (asr & SBIC_ASR_LCI) { 1562 printf("sbicicmd: last command ignored\n"); 1563 } 1564 else if( i == 1 ) /* Bsy */ 1565 SBIC_WAIT (regs, SBIC_ASR_INT, wait); 1566 1567 /* 1568 * do it again 1569 */ 1570 } while ( i > 0 && dev->sc_stat[0] == 0xff); 1571 1572 /* Sometimes we need to do an extra read of the CSR */ 1573 GET_SBIC_csr(regs, csr); 1574 CSR_TRACE('I',csr,asr,0xff); 1575 1576 #if CSR_LOG_BUF_SIZE 1577 if(reselect_debug>1) 1578 for(i=0; i<bufptr; i++) 1579 printf("CSR:%02x", csrbuf[i]); 1580 #endif 1581 1582 #ifdef DEBUG 1583 if(data_pointer_debug > 1) 1584 printf("sbicicmd done(%d,%d):%d =%d=\n", 1585 dev->target, lun, 1586 acb->sc_kv.dc_count, 1587 dev->sc_stat[0]); 1588 #endif 1589 1590 QPRINTF(("=STS:%02x=", dev->sc_stat[0])); 1591 dev->sc_flags &= ~SBICF_ICMD; 1592 1593 SBIC_TRACE(dev); 1594 return(dev->sc_stat[0]); 1595 } 1596 1597 /* 1598 * Finish SCSI xfer command: After the completion interrupt from 1599 * a read/write operation, sequence through the final phases in 1600 * programmed i/o. This routine is a lot like sbicicmd except we 1601 * skip (and don't allow) the select, cmd out and data in/out phases. 1602 */ 1603 void 1604 sbicxfdone(dev, regs, target) 1605 struct sbic_softc *dev; 1606 sbic_regmap_p regs; 1607 int target; 1608 { 1609 u_char phase, asr, csr; 1610 int s; 1611 1612 SBIC_TRACE(dev); 1613 QPRINTF(("{")); 1614 s = splbio(); 1615 1616 /* 1617 * have the sbic complete on its own 1618 */ 1619 SBIC_TC_PUT(regs, 0); 1620 SET_SBIC_cmd_phase(regs, 0x46); 1621 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1622 1623 do { 1624 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0); 1625 GET_SBIC_csr (regs, csr); 1626 CSR_TRACE('f',csr,asr,target); 1627 QPRINTF(("%02x:", csr)); 1628 } while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) 1629 && (csr != SBIC_CSR_S_XFERRED)); 1630 1631 dev->sc_flags &= ~SBICF_SELECTED; 1632 1633 GET_SBIC_cmd_phase (regs, phase); 1634 QPRINTF(("}%02x", phase)); 1635 if (phase == 0x60) 1636 GET_SBIC_tlun(regs, dev->sc_stat[0]); 1637 else 1638 sbicerror(dev, regs, csr); 1639 1640 QPRINTF(("=STS:%02x=\n", dev->sc_stat[0])); 1641 splx(s); 1642 SBIC_TRACE(dev); 1643 } 1644 1645 /* 1646 * No DMA chains 1647 */ 1648 1649 int 1650 sbicgo(dev, xs) 1651 struct sbic_softc *dev; 1652 struct scsi_xfer *xs; 1653 { 1654 int i, dmaflags, count, wait, usedma; 1655 u_char csr, asr, cmd, *addr; 1656 sbic_regmap_p regs; 1657 struct sbic_acb *acb; 1658 1659 SBIC_TRACE(dev); 1660 dev->target = xs->sc_link->target; 1661 dev->lun = xs->sc_link->lun; 1662 acb = dev->sc_nexus; 1663 regs = dev->sc_sbicp; 1664 1665 usedma = sbicdmaok(dev, xs); 1666 #ifdef DEBUG 1667 routine = 1; 1668 debug_sbic_regs = regs; /* store this to allow debug calls */ 1669 if( data_pointer_debug > 1 ) 1670 printf("sbicgo(%d,%d)\n", dev->target, dev->lun); 1671 #endif 1672 1673 /* 1674 * set the sbic into DMA mode 1675 */ 1676 if( usedma ) 1677 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI | 1678 SBIC_MACHINE_DMA_MODE); 1679 else 1680 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1681 1682 1683 /* 1684 * select the SCSI bus (it's an error if bus isn't free) 1685 */ 1686 if (sbicselectbus(dev, regs, dev->target, dev->lun, 1687 dev->sc_scsiaddr)) { 1688 /* printf("sbicgo: Trying to select busy bus!\n"); */ 1689 SBIC_TRACE(dev); 1690 return(0); /* Not done: needs to be rescheduled */ 1691 } 1692 dev->sc_stat[0] = 0xff; 1693 1694 /* 1695 * Calculate DMA chains now 1696 */ 1697 1698 dmaflags = 0; 1699 if (acb->flags & ACB_DATAIN) 1700 dmaflags |= DMAGO_READ; 1701 1702 1703 /* 1704 * Deal w/bounce buffers. 1705 */ 1706 1707 addr = acb->sc_kv.dc_addr; 1708 count = acb->sc_kv.dc_count; 1709 if (count && (char *)kvtop(addr) != acb->sc_pa.dc_addr) { /* XXXX check */ 1710 printf("sbic: DMA buffer mapping changed %x->%x\n", 1711 acb->sc_pa.dc_addr, kvtop(addr)); 1712 #ifdef DDB 1713 Debugger(); 1714 #endif 1715 } 1716 1717 #ifdef DEBUG 1718 ++sbicdma_ops; /* count total DMA operations */ 1719 #endif 1720 if (count && usedma && dev->sc_flags & SBICF_BADDMA && 1721 sbiccheckdmap(addr, count, dev->sc_dmamask)) { 1722 /* 1723 * need to bounce the dma. 1724 */ 1725 if (dmaflags & DMAGO_READ) { 1726 acb->flags |= ACB_BBUF; 1727 acb->sc_dmausrbuf = addr; 1728 acb->sc_dmausrlen = count; 1729 acb->sc_usrbufpa = (u_char *)kvtop(addr); 1730 if(!dev->sc_tinfo[dev->target].bounce) { 1731 printf("sbicgo: HELP! no bounce allocated for %d\n", 1732 dev->target); 1733 printf("xfer: (%x->%x,%x)\n", acb->sc_dmausrbuf, 1734 acb->sc_usrbufpa, acb->sc_dmausrlen); 1735 dev->sc_tinfo[xs->sc_link->target].bounce 1736 = (char *)alloc_z2mem(MAXPHYS); 1737 if (isztwomem(dev->sc_tinfo[xs->sc_link->target].bounce)) 1738 printf("alloc ZII target %d bounce pa 0x%x\n", 1739 xs->sc_link->target, 1740 kvtop(dev->sc_tinfo[xs->sc_link->target].bounce)); 1741 else if (dev->sc_tinfo[xs->sc_link->target].bounce) 1742 printf("alloc CHIP target %d bounce pa 0x%x\n", 1743 xs->sc_link->target, 1744 PREP_DMA_MEM(dev->sc_tinfo[xs->sc_link->target].bounce)); 1745 1746 printf("Allocating %d bounce at %x\n", 1747 dev->target, 1748 kvtop(dev->sc_tinfo[dev->target].bounce)); 1749 } 1750 } else { /* write: copy to dma buffer */ 1751 #ifdef DEBUG 1752 if(data_pointer_debug) 1753 printf("sbicgo: copying %x bytes to target %d bounce %x\n", 1754 count, dev->target, 1755 kvtop(dev->sc_tinfo[dev->target].bounce)); 1756 #endif 1757 bcopy (addr, dev->sc_tinfo[dev->target].bounce, count); 1758 } 1759 addr = dev->sc_tinfo[dev->target].bounce;/* and use dma buffer */ 1760 acb->sc_kv.dc_addr = addr; 1761 #ifdef DEBUG 1762 ++sbicdma_bounces; /* count number of bounced */ 1763 #endif 1764 } 1765 1766 /* 1767 * Allocate the DMA chain 1768 */ 1769 1770 /* Set start KVM addresses */ 1771 #if 0 1772 acb->sc_kv.dc_addr = addr; 1773 acb->sc_kv.dc_count = count; 1774 #endif 1775 1776 /* Mark end of segment */ 1777 acb->sc_tcnt = dev->sc_tcnt = 0; 1778 acb->sc_pa.dc_count = 0; 1779 1780 sbic_load_ptrs(dev, regs, dev->target, dev->lun); 1781 SBIC_TRACE(dev); 1782 /* Enable interrupts but don't do any DMA */ 1783 dev->sc_enintr(dev); 1784 if (usedma) { 1785 dev->sc_tcnt = dev->sc_dmago(dev, acb->sc_pa.dc_addr, 1786 acb->sc_pa.dc_count, 1787 dmaflags); 1788 #ifdef DEBUG 1789 dev->sc_dmatimo = dev->sc_tcnt ? 1 : 0; 1790 #endif 1791 } else 1792 dev->sc_dmacmd = 0; /* Don't use DMA */ 1793 dev->sc_flags |= SBICF_INDMA; 1794 /* SBIC_TC_PUT(regs, dev->sc_tcnt); /* XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX */ 1795 SBIC_TRACE(dev); 1796 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 1797 1798 /* 1799 * push the data cache ( I think this won't work (EH)) 1800 */ 1801 #if defined(M68040) 1802 if (mmutype == MMU_68040 && usedma && count) { 1803 dma_cachectl(addr, count); 1804 if (((u_int)addr & 0xF) || (((u_int)addr + count) & 0xF)) 1805 dev->sc_flags |= SBICF_DCFLUSH; 1806 } 1807 #endif 1808 1809 /* 1810 * enintr() also enables interrupts for the sbic 1811 */ 1812 #ifdef DEBUG 1813 if( data_pointer_debug > 1 ) 1814 printf("sbicgo dmago:%d(%x:%x)\n", 1815 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 1816 debug_asr = asr; 1817 debug_csr = csr; 1818 #endif 1819 1820 /* 1821 * Lets cycle a while then let the interrupt handler take over 1822 */ 1823 1824 asr = GET_SBIC_asr(regs, asr); 1825 do { 1826 GET_SBIC_csr(regs, csr); 1827 CSR_TRACE('g',csr,asr,dev->target); 1828 #ifdef DEBUG 1829 debug_csr = csr; 1830 routine = 1; 1831 #endif 1832 QPRINTF(("go[0x%x]", csr)); 1833 1834 i = sbicnextstate(dev, csr, asr); 1835 1836 WAIT_CIP(regs); 1837 GET_SBIC_asr(regs, asr); 1838 #ifdef DEBUG 1839 debug_asr = asr; 1840 #endif 1841 if(asr & SBIC_ASR_LCI) printf("sbicgo: LCI asr:%02x csr:%02x\n", 1842 asr,csr); 1843 } while( i == SBIC_STATE_RUNNING 1844 && asr & (SBIC_ASR_INT|SBIC_ASR_LCI) ); 1845 1846 CSR_TRACE('g',csr,asr,i<<4); 1847 SBIC_TRACE(dev); 1848 if (i == SBIC_STATE_DONE && dev->sc_stat[0] == 0xff) printf("sbicgo: done & stat = 0xff\n"); 1849 if (i == SBIC_STATE_DONE && dev->sc_stat[0] != 0xff) { 1850 /* if( i == SBIC_STATE_DONE && dev->sc_stat[0] ) { */ 1851 /* Did we really finish that fast? */ 1852 return 1; 1853 } 1854 return 0; 1855 } 1856 1857 1858 int 1859 sbicintr(dev) 1860 struct sbic_softc *dev; 1861 { 1862 sbic_regmap_p regs; 1863 struct dma_chain *df, *dl; 1864 u_char asr, csr, *tmpaddr; 1865 struct sbic_acb *acb; 1866 int i, newtarget, newlun; 1867 unsigned tcnt; 1868 1869 regs = dev->sc_sbicp; 1870 1871 /* 1872 * pending interrupt? 1873 */ 1874 GET_SBIC_asr (regs, asr); 1875 if ((asr & SBIC_ASR_INT) == 0) 1876 return(0); 1877 1878 SBIC_TRACE(dev); 1879 do { 1880 GET_SBIC_csr(regs, csr); 1881 CSR_TRACE('i',csr,asr,dev->target); 1882 #ifdef DEBUG 1883 debug_csr = csr; 1884 routine = 2; 1885 #endif 1886 QPRINTF(("intr[0x%x]", csr)); 1887 1888 i = sbicnextstate(dev, csr, asr); 1889 1890 WAIT_CIP(regs); 1891 GET_SBIC_asr(regs, asr); 1892 #ifdef DEBUG 1893 debug_asr = asr; 1894 #endif 1895 #if 0 1896 if(asr & SBIC_ASR_LCI) printf("sbicintr: LCI asr:%02x csr:%02x\n", 1897 asr,csr); 1898 #endif 1899 } while(i == SBIC_STATE_RUNNING && 1900 asr & (SBIC_ASR_INT|SBIC_ASR_LCI)); 1901 CSR_TRACE('i',csr,asr,i<<4); 1902 SBIC_TRACE(dev); 1903 return(1); 1904 } 1905 1906 /* 1907 * Run commands and wait for disconnect 1908 */ 1909 int 1910 sbicpoll(dev) 1911 struct sbic_softc *dev; 1912 { 1913 sbic_regmap_p regs; 1914 u_char asr, csr; 1915 struct sbic_pending* pendp; 1916 int i; 1917 unsigned tcnt; 1918 1919 SBIC_TRACE(dev); 1920 regs = dev->sc_sbicp; 1921 1922 do { 1923 GET_SBIC_asr (regs, asr); 1924 #ifdef DEBUG 1925 debug_asr = asr; 1926 #endif 1927 GET_SBIC_csr(regs, csr); 1928 CSR_TRACE('p',csr,asr,dev->target); 1929 #ifdef DEBUG 1930 debug_csr = csr; 1931 routine = 2; 1932 #endif 1933 QPRINTF(("poll[0x%x]", csr)); 1934 1935 i = sbicnextstate(dev, csr, asr); 1936 1937 WAIT_CIP(regs); 1938 GET_SBIC_asr(regs, asr); 1939 /* tapes may take a loooong time.. */ 1940 while (asr & SBIC_ASR_BSY){ 1941 if(asr & SBIC_ASR_DBR) { 1942 printf("sbipoll: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", 1943 csr,asr); 1944 #ifdef DDB 1945 Debugger(); 1946 #endif 1947 /* SBIC is jammed */ 1948 /* DUNNO which direction */ 1949 /* Try old direction */ 1950 GET_SBIC_data(regs,i); 1951 GET_SBIC_asr(regs, asr); 1952 if( asr & SBIC_ASR_DBR) /* Wants us to write */ 1953 SET_SBIC_data(regs,i); 1954 } 1955 GET_SBIC_asr(regs, asr); 1956 } 1957 1958 if(asr & SBIC_ASR_LCI) printf("sbicpoll: LCI asr:%02x csr:%02x\n", 1959 asr,csr); 1960 else if( i == 1 ) /* BSY */ 1961 SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait); 1962 } while(i == SBIC_STATE_RUNNING); 1963 CSR_TRACE('p',csr,asr,i<<4); 1964 SBIC_TRACE(dev); 1965 return(1); 1966 } 1967 1968 /* 1969 * Handle a single msgin 1970 */ 1971 1972 int 1973 sbicmsgin(dev) 1974 struct sbic_softc *dev; 1975 { 1976 sbic_regmap_p regs; 1977 int recvlen; 1978 u_char asr, csr, *tmpaddr; 1979 1980 regs = dev->sc_sbicp; 1981 1982 dev->sc_msg[0] = 0xff; 1983 dev->sc_msg[1] = 0xff; 1984 1985 GET_SBIC_asr(regs, asr); 1986 #ifdef DEBUG 1987 if(reselect_debug>1) 1988 printf("sbicmsgin asr=%02x\n", asr); 1989 #endif 1990 1991 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 1992 1993 GET_SBIC_selid (regs, csr); 1994 SET_SBIC_selid (regs, csr | SBIC_SID_FROM_SCSI); 1995 1996 SBIC_TC_PUT(regs, 0); 1997 tmpaddr = dev->sc_msg; 1998 recvlen = 1; 1999 do { 2000 while( recvlen-- ) { 2001 asr = GET_SBIC_asr(regs, asr); 2002 GET_SBIC_csr(regs, csr); 2003 QPRINTF(("sbicmsgin ready to go (csr,asr)=(%02x,%02x)\n", 2004 csr, asr)); 2005 2006 RECV_BYTE(regs, *tmpaddr); 2007 CSR_TRACE('m',csr,asr,*tmpaddr); 2008 #if 1 2009 /* 2010 * get the command completion interrupt, or we 2011 * can't send a new command (LCI) 2012 */ 2013 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2014 GET_SBIC_csr(regs, csr); 2015 CSR_TRACE('X',csr,asr,dev->target); 2016 #else 2017 WAIT_CIP(regs); 2018 do { 2019 GET_SBIC_asr(regs, asr); 2020 csr = 0xff; 2021 GET_SBIC_csr(regs, csr); 2022 CSR_TRACE('X',csr,asr,dev->target); 2023 if( csr == 0xff ) 2024 printf("sbicmsgin waiting: csr %02x asr %02x\n", csr, asr); 2025 } while( csr == 0xff ); 2026 #endif 2027 #ifdef DEBUG 2028 if(reselect_debug>1) 2029 printf("sbicmsgin: got %02x csr %02x asr %02x\n", 2030 *tmpaddr, csr, asr); 2031 #endif 2032 #if do_parity_check 2033 if( asr & SBIC_ASR_PE ) { 2034 printf ("Parity error"); 2035 /* This code simply does not work. */ 2036 WAIT_CIP(regs); 2037 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2038 WAIT_CIP(regs); 2039 GET_SBIC_asr(regs, asr); 2040 WAIT_CIP(regs); 2041 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2042 WAIT_CIP(regs); 2043 if( !(asr & SBIC_ASR_LCI) ) 2044 /* Target wants to send garbled msg*/ 2045 continue; 2046 printf("--fixing\n"); 2047 /* loop until a msgout phase occurs on target */ 2048 while(csr & 0x07 != MESG_OUT_PHASE) { 2049 while( asr & SBIC_ASR_BSY && 2050 !(asr & SBIC_ASR_DBR|SBIC_ASR_INT) ) 2051 GET_SBIC_asr(regs, asr); 2052 if( asr & SBIC_ASR_DBR ) 2053 panic("msgin: jammed again!\n"); 2054 GET_SBIC_csr(regs, csr); 2055 CSR_TRACE('e',csr,asr,dev->target); 2056 if( csr & 0x07 != MESG_OUT_PHASE ) { 2057 sbicnextstate(dev, csr, asr); 2058 sbic_save_ptrs(dev, regs, 2059 dev->target, 2060 dev->lun); 2061 } 2062 } 2063 /* Should be msg out by now */ 2064 SEND_BYTE(regs, MSG_PARITY_ERROR); 2065 } 2066 else 2067 #endif 2068 tmpaddr++; 2069 2070 if(recvlen) { 2071 /* Clear ACK */ 2072 WAIT_CIP(regs); 2073 GET_SBIC_asr(regs, asr); 2074 GET_SBIC_csr(regs, csr); 2075 CSR_TRACE('X',csr,asr,dev->target); 2076 QPRINTF(("sbicmsgin pre byte CLR_ACK (csr,asr)=(%02x,%02x)\n", 2077 csr, asr)); 2078 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2079 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2080 } 2081 2082 }; 2083 2084 if(dev->sc_msg[0] == 0xff) { 2085 printf("sbicmsgin: sbic swallowed our message\n"); 2086 break; 2087 } 2088 #ifdef DEBUG 2089 if (sync_debug) 2090 printf("msgin done csr 0x%x asr 0x%x msg 0x%x\n", 2091 csr, asr, dev->sc_msg[0]); 2092 #endif 2093 /* 2094 * test whether this is a reply to our sync 2095 * request 2096 */ 2097 if (MSG_ISIDENTIFY(dev->sc_msg[0])) { 2098 QPRINTF(("IFFY")); 2099 #if 0 2100 /* There is an implied load-ptrs here */ 2101 sbic_load_ptrs(dev, regs, dev->target, dev->lun); 2102 #endif 2103 /* Got IFFY msg -- ack it */ 2104 } else if (dev->sc_msg[0] == MSG_REJECT 2105 && dev->sc_sync[dev->target].state == SYNC_SENT) { 2106 QPRINTF(("REJECT of SYN")); 2107 #ifdef DEBUG 2108 if (sync_debug) 2109 printf("target %d rejected sync, going async\n", 2110 dev->target); 2111 #endif 2112 dev->sc_sync[dev->target].period = sbic_min_period; 2113 dev->sc_sync[dev->target].offset = 0; 2114 dev->sc_sync[dev->target].state = SYNC_DONE; 2115 SET_SBIC_syn(regs, 2116 SBIC_SYN(dev->sc_sync[dev->target].offset, 2117 dev->sc_sync[dev->target].period)); 2118 } else if ((dev->sc_msg[0] == MSG_REJECT)) { 2119 QPRINTF(("REJECT")); 2120 /* 2121 * we'll never REJECt a REJECT message.. 2122 */ 2123 } else if ((dev->sc_msg[0] == MSG_SAVE_DATA_PTR)) { 2124 QPRINTF(("MSG_SAVE_DATA_PTR")); 2125 /* 2126 * don't reject this either. 2127 */ 2128 } else if ((dev->sc_msg[0] == MSG_DISCONNECT)) { 2129 QPRINTF(("DISCONNECT")); 2130 #ifdef DEBUG 2131 if( reselect_debug>1 && dev->sc_msg[0] == MSG_DISCONNECT ) 2132 printf("sbicmsgin: got disconnect msg %s\n", 2133 (dev->sc_flags & SBICF_ICMD)?"rejecting":""); 2134 #endif 2135 if( dev->sc_flags & SBICF_ICMD ) { 2136 /* We're in immediate mode. Prevent disconnects. */ 2137 /* prepare to reject the message, NACK */ 2138 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2139 WAIT_CIP(regs); 2140 } 2141 } else if (dev->sc_msg[0] == MSG_CMD_COMPLETE ) { 2142 QPRINTF(("CMD_COMPLETE")); 2143 /* !! KLUDGE ALERT !! quite a few drives don't seem to 2144 * really like the current way of sending the 2145 * sync-handshake together with the ident-message, and 2146 * they react by sending command-complete and 2147 * disconnecting right after returning the valid sync 2148 * handshake. So, all I can do is reselect the drive, 2149 * and hope it won't disconnect again. I don't think 2150 * this is valid behavior, but I can't help fixing a 2151 * problem that apparently exists. 2152 * 2153 * Note: we should not get here on `normal' command 2154 * completion, as that condition is handled by the 2155 * high-level sel&xfer resume command used to walk 2156 * thru status/cc-phase. 2157 */ 2158 2159 #ifdef DEBUG 2160 if (sync_debug) 2161 printf ("GOT MSG %d! target %d acting weird.." 2162 " waiting for disconnect...\n", 2163 dev->sc_msg[0], dev->target); 2164 #endif 2165 /* Check to see if sbic is handling this */ 2166 GET_SBIC_asr(regs, asr); 2167 if(asr & SBIC_ASR_BSY) 2168 return SBIC_STATE_RUNNING; 2169 2170 /* Let's try this: Assume it works and set status to 00 */ 2171 dev->sc_stat[0] = 0; 2172 } else if (dev->sc_msg[0] == MSG_EXT_MESSAGE 2173 && tmpaddr == &dev->sc_msg[1]) { 2174 QPRINTF(("ExtMSG\n")); 2175 /* Read in whole extended message */ 2176 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2177 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2178 GET_SBIC_asr(regs, asr); 2179 GET_SBIC_csr(regs, csr); 2180 QPRINTF(("CLR ACK asr %02x, csr %02x\n", asr, csr)); 2181 RECV_BYTE(regs, *tmpaddr); 2182 CSR_TRACE('x',csr,asr,*tmpaddr); 2183 /* Wait for command completion IRQ */ 2184 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2185 recvlen = *tmpaddr++; 2186 QPRINTF(("Recving ext msg, asr %02x csr %02x len %02x\n", 2187 asr, csr, recvlen)); 2188 } else if (dev->sc_msg[0] == MSG_EXT_MESSAGE && dev->sc_msg[1] == 3 2189 && dev->sc_msg[2] == MSG_SYNC_REQ) { 2190 QPRINTF(("SYN")); 2191 dev->sc_sync[dev->target].period = 2192 sbicfromscsiperiod(dev, 2193 regs, dev->sc_msg[3]); 2194 dev->sc_sync[dev->target].offset = dev->sc_msg[4]; 2195 dev->sc_sync[dev->target].state = SYNC_DONE; 2196 SET_SBIC_syn(regs, 2197 SBIC_SYN(dev->sc_sync[dev->target].offset, 2198 dev->sc_sync[dev->target].period)); 2199 printf("%s: target %d now synchronous," 2200 " period=%dns, offset=%d.\n", 2201 dev->sc_dev.dv_xname, dev->target, 2202 dev->sc_msg[3] * 4, dev->sc_msg[4]); 2203 } else { 2204 #ifdef DEBUG 2205 if (sbic_debug || sync_debug) 2206 printf ("sbicmsgin: Rejecting message 0x%02x\n", 2207 dev->sc_msg[0]); 2208 #endif 2209 /* prepare to reject the message, NACK */ 2210 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2211 WAIT_CIP(regs); 2212 } 2213 /* Clear ACK */ 2214 WAIT_CIP(regs); 2215 GET_SBIC_asr(regs, asr); 2216 GET_SBIC_csr(regs, csr); 2217 CSR_TRACE('X',csr,asr,dev->target); 2218 QPRINTF(("sbicmsgin pre CLR_ACK (csr,asr)=(%02x,%02x)%d\n", 2219 csr, asr, recvlen)); 2220 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2221 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2222 } 2223 #if 0 2224 while((csr == SBIC_CSR_MSGIN_W_ACK) 2225 || (SBIC_PHASE(csr) == MESG_IN_PHASE)); 2226 #else 2227 while (recvlen>0); 2228 #endif 2229 2230 QPRINTF(("sbicmsgin finished: csr %02x, asr %02x\n",csr, asr)); 2231 2232 /* Should still have one CSR to read */ 2233 return SBIC_STATE_RUNNING; 2234 } 2235 2236 2237 /* 2238 * sbicnextstate() 2239 * return: 2240 * 0 == done 2241 * 1 == working 2242 * 2 == disconnected 2243 * -1 == error 2244 */ 2245 int 2246 sbicnextstate(dev, csr, asr) 2247 struct sbic_softc *dev; 2248 u_char csr, asr; 2249 { 2250 sbic_regmap_p regs; 2251 struct dma_chain *df, *dl; 2252 struct sbic_acb *acb; 2253 int i, newtarget, newlun, wait; 2254 unsigned tcnt; 2255 2256 SBIC_TRACE(dev); 2257 regs = dev->sc_sbicp; 2258 acb = dev->sc_nexus; 2259 2260 QPRINTF(("next[%02x,%02x]",asr,csr)); 2261 2262 switch (csr) { 2263 case SBIC_CSR_XFERRED|CMD_PHASE: 2264 case SBIC_CSR_MIS|CMD_PHASE: 2265 case SBIC_CSR_MIS_1|CMD_PHASE: 2266 case SBIC_CSR_MIS_2|CMD_PHASE: 2267 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 2268 if (sbicxfstart(regs, acb->clen, CMD_PHASE, sbic_cmd_wait)) 2269 if (sbicxfout(regs, acb->clen, 2270 &acb->cmd, CMD_PHASE)) 2271 goto abort; 2272 break; 2273 2274 case SBIC_CSR_XFERRED|STATUS_PHASE: 2275 case SBIC_CSR_MIS|STATUS_PHASE: 2276 case SBIC_CSR_MIS_1|STATUS_PHASE: 2277 case SBIC_CSR_MIS_2|STATUS_PHASE: 2278 /* 2279 * this should be the normal i/o completion case. 2280 * get the status & cmd complete msg then let the 2281 * device driver look at what happened. 2282 */ 2283 sbicxfdone(dev,regs,dev->target); 2284 /* 2285 * check for overlapping cache line, flush if so 2286 */ 2287 #ifdef M68040 2288 if (dev->sc_flags & SBICF_DCFLUSH) { 2289 #if 0 2290 printf("sbic: 68040 DMA cache flush needs fixing? %x:%x\n", 2291 dev->sc_xs->data, dev->sc_xs->datalen); 2292 #endif 2293 } 2294 #endif 2295 #ifdef DEBUG 2296 if( data_pointer_debug > 1 ) 2297 printf("next dmastop: %d(%x:%x)\n", 2298 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 2299 dev->sc_dmatimo = 0; 2300 #endif 2301 dev->sc_dmastop(dev); /* was dmafree */ 2302 if (acb->flags & ACB_BBUF) { 2303 if ((u_char *)kvtop(acb->sc_dmausrbuf) != acb->sc_usrbufpa) 2304 printf("%s: WARNING - buffer mapping changed %x->%x\n", 2305 dev->sc_dev.dv_xname, acb->sc_usrbufpa, 2306 kvtop(acb->sc_dmausrbuf)); 2307 #ifdef DEBUG 2308 if(data_pointer_debug) 2309 printf("sbicgo:copying %x bytes from target %d bounce %x\n", 2310 acb->sc_dmausrlen, 2311 dev->target, 2312 kvtop(dev->sc_tinfo[dev->target].bounce)); 2313 #endif 2314 bcopy(dev->sc_tinfo[dev->target].bounce, 2315 acb->sc_dmausrbuf, 2316 acb->sc_dmausrlen); 2317 } 2318 dev->sc_flags &= ~(SBICF_INDMA | SBICF_DCFLUSH); 2319 sbic_scsidone(acb, dev->sc_stat[0]); 2320 SBIC_TRACE(dev); 2321 return SBIC_STATE_DONE; 2322 2323 case SBIC_CSR_XFERRED|DATA_OUT_PHASE: 2324 case SBIC_CSR_XFERRED|DATA_IN_PHASE: 2325 case SBIC_CSR_MIS|DATA_OUT_PHASE: 2326 case SBIC_CSR_MIS|DATA_IN_PHASE: 2327 case SBIC_CSR_MIS_1|DATA_OUT_PHASE: 2328 case SBIC_CSR_MIS_1|DATA_IN_PHASE: 2329 case SBIC_CSR_MIS_2|DATA_OUT_PHASE: 2330 case SBIC_CSR_MIS_2|DATA_IN_PHASE: 2331 if( dev->sc_xs->flags & SCSI_POLL || dev->sc_flags & SBICF_ICMD 2332 || acb->sc_dmacmd == 0 ) { 2333 /* Do PIO */ 2334 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2335 if (acb->sc_kv.dc_count <= 0) { 2336 printf("sbicnextstate:xfer count %d asr%x csr%x\n", 2337 acb->sc_kv.dc_count, asr, csr); 2338 goto abort; 2339 } 2340 wait = sbic_data_wait; 2341 if( sbicxfstart(regs, 2342 acb->sc_kv.dc_count, 2343 SBIC_PHASE(csr), wait)) 2344 if( SBIC_PHASE(csr) == DATA_IN_PHASE ) 2345 /* data in? */ 2346 i=sbicxfin(regs, 2347 acb->sc_kv.dc_count, 2348 acb->sc_kv.dc_addr); 2349 else 2350 i=sbicxfout(regs, 2351 acb->sc_kv.dc_count, 2352 acb->sc_kv.dc_addr, 2353 SBIC_PHASE(csr)); 2354 acb->sc_kv.dc_addr += 2355 (acb->sc_kv.dc_count - i); 2356 acb->sc_kv.dc_count = i; 2357 } else { 2358 if (acb->sc_kv.dc_count <= 0) { 2359 printf("sbicnextstate:xfer count %d asr%x csr%x\n", 2360 acb->sc_kv.dc_count, asr, csr); 2361 goto abort; 2362 } 2363 /* 2364 * do scatter-gather dma 2365 * hacking the controller chip, ouch.. 2366 */ 2367 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI | 2368 SBIC_MACHINE_DMA_MODE); 2369 /* 2370 * set next dma addr and dec count 2371 */ 2372 #if 0 2373 SBIC_TC_GET(regs, tcnt); 2374 dev->sc_cur->dc_count -= ((dev->sc_tcnt - tcnt) >> 1); 2375 dev->sc_cur->dc_addr += (dev->sc_tcnt - tcnt); 2376 dev->sc_tcnt = acb->sc_tcnt = tcnt; 2377 #else 2378 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 2379 sbic_load_ptrs(dev, regs, dev->target, dev->lun); 2380 #endif 2381 #ifdef DEBUG 2382 if( data_pointer_debug > 1 ) 2383 printf("next dmanext: %d(%x:%x)\n", 2384 dev->target,dev->sc_cur->dc_addr, 2385 dev->sc_tcnt); 2386 dev->sc_dmatimo = 1; 2387 #endif 2388 dev->sc_tcnt = dev->sc_dmanext(dev); 2389 SBIC_TC_PUT(regs, (unsigned)dev->sc_tcnt); 2390 SET_SBIC_cmd(regs, SBIC_CMD_XFER_INFO); 2391 dev->sc_flags |= SBICF_INDMA; 2392 } 2393 break; 2394 2395 case SBIC_CSR_XFERRED|MESG_IN_PHASE: 2396 case SBIC_CSR_MIS|MESG_IN_PHASE: 2397 case SBIC_CSR_MIS_1|MESG_IN_PHASE: 2398 case SBIC_CSR_MIS_2|MESG_IN_PHASE: 2399 SBIC_TRACE(dev); 2400 return sbicmsgin(dev); 2401 2402 case SBIC_CSR_MSGIN_W_ACK: 2403 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); /* Dunno what I'm ACKing */ 2404 printf("Acking unknown msgin CSR:%02x",csr); 2405 break; 2406 2407 case SBIC_CSR_XFERRED|MESG_OUT_PHASE: 2408 case SBIC_CSR_MIS|MESG_OUT_PHASE: 2409 case SBIC_CSR_MIS_1|MESG_OUT_PHASE: 2410 case SBIC_CSR_MIS_2|MESG_OUT_PHASE: 2411 #ifdef DEBUG 2412 if (sync_debug) 2413 printf ("sending REJECT msg to last msg.\n"); 2414 #endif 2415 2416 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 2417 /* 2418 * should only get here on reject, 2419 * since it's always US that 2420 * initiate a sync transfer 2421 */ 2422 SEND_BYTE(regs, MSG_REJECT); 2423 WAIT_CIP(regs); 2424 if( asr & (SBIC_ASR_BSY|SBIC_ASR_LCI|SBIC_ASR_CIP) ) 2425 printf("next: REJECT sent asr %02x\n", asr); 2426 SBIC_TRACE(dev); 2427 return SBIC_STATE_RUNNING; 2428 2429 case SBIC_CSR_DISC: 2430 case SBIC_CSR_DISC_1: 2431 dev->sc_flags &= ~(SBICF_INDMA|SBICF_SELECTED); 2432 2433 /* Try to schedule another target */ 2434 #ifdef DEBUG 2435 if(reselect_debug>1) 2436 printf("sbicnext target %d disconnected\n", dev->target); 2437 #endif 2438 TAILQ_INSERT_HEAD(&dev->nexus_list, acb, chain); 2439 ++dev->sc_tinfo[dev->target].dconns; 2440 dev->sc_nexus = NULL; 2441 dev->sc_xs = NULL; 2442 2443 if( acb->xs->flags & SCSI_POLL 2444 || (dev->sc_flags & SBICF_ICMD) 2445 || !sbic_parallel_operations ) { 2446 SBIC_TRACE(dev); 2447 return SBIC_STATE_DISCONNECT; 2448 } 2449 sbic_sched(dev); 2450 SBIC_TRACE(dev); 2451 return SBIC_STATE_DISCONNECT; 2452 2453 case SBIC_CSR_RSLT_NI: 2454 case SBIC_CSR_RSLT_IFY: 2455 GET_SBIC_rselid(regs, newtarget); 2456 /* check SBIC_RID_SIV? */ 2457 newtarget &= SBIC_RID_MASK; 2458 if (csr == SBIC_CSR_RSLT_IFY) { 2459 /* Read IFY msg to avoid lockup */ 2460 GET_SBIC_data(regs, newlun); 2461 WAIT_CIP(regs); 2462 newlun &= SBIC_TLUN_MASK; 2463 CSR_TRACE('r',csr,asr,newtarget); 2464 } else { 2465 /* Need to get IFY message */ 2466 for (newlun = 256; newlun; --newlun) { 2467 GET_SBIC_asr(regs, asr); 2468 if (asr & SBIC_ASR_INT) 2469 break; 2470 delay(1); 2471 } 2472 newlun = 0; /* XXXX */ 2473 if ((asr & SBIC_ASR_INT) == 0) { 2474 #ifdef DEBUG 2475 if (reselect_debug) 2476 printf("RSLT_NI - no IFFY message? asr %x\n", asr); 2477 #endif 2478 } else { 2479 GET_SBIC_csr(regs,csr); 2480 CSR_TRACE('n',csr,asr,newtarget); 2481 if (csr == SBIC_CSR_MIS|MESG_IN_PHASE || 2482 csr == SBIC_CSR_MIS_1|MESG_IN_PHASE || 2483 csr == SBIC_CSR_MIS_2|MESG_IN_PHASE) { 2484 sbicmsgin(dev); 2485 newlun = dev->sc_msg[0] & 7; 2486 } else { 2487 printf("RSLT_NI - not MESG_IN_PHASE %x\n", 2488 csr); 2489 } 2490 } 2491 } 2492 #ifdef DEBUG 2493 if(reselect_debug>1 || (reselect_debug && csr==SBIC_CSR_RSLT_NI)) 2494 printf("sbicnext: reselect %s from targ %d lun %d\n", 2495 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", 2496 newtarget, newlun); 2497 #endif 2498 if (dev->sc_nexus) { 2499 #ifdef DEBUG 2500 if (reselect_debug > 1) 2501 printf("%s: reselect %s with active command\n", 2502 dev->sc_dev.dv_xname, 2503 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY"); 2504 #ifdef DDB 2505 /* Debugger();*/ 2506 #endif 2507 #endif 2508 TAILQ_INSERT_HEAD(&dev->ready_list, dev->sc_nexus, chain); 2509 dev->sc_tinfo[dev->target].lubusy &= ~(1 << dev->lun); 2510 dev->sc_nexus = NULL; 2511 dev->sc_xs = NULL; 2512 } 2513 /* Reload sync values for this target */ 2514 if (dev->sc_sync[newtarget].state == SYNC_DONE) 2515 SET_SBIC_syn(regs, SBIC_SYN (dev->sc_sync[newtarget].offset, 2516 dev->sc_sync[newtarget].period)); 2517 else 2518 SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period)); 2519 for (acb = dev->nexus_list.tqh_first; acb; 2520 acb = acb->chain.tqe_next) { 2521 if (acb->xs->sc_link->target != newtarget || 2522 acb->xs->sc_link->lun != newlun) 2523 continue; 2524 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 2525 dev->sc_nexus = acb; 2526 dev->sc_xs = acb->xs; 2527 dev->sc_flags |= SBICF_SELECTED; 2528 dev->target = newtarget; 2529 dev->lun = newlun; 2530 break; 2531 } 2532 if (acb == NULL) { 2533 printf("%s: reselect %s targ %d not in nexus_list %x\n", 2534 dev->sc_dev.dv_xname, 2535 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", newtarget, 2536 &dev->nexus_list.tqh_first); 2537 panic("bad reselect in sbic"); 2538 } 2539 if (csr == SBIC_CSR_RSLT_IFY) 2540 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2541 break; 2542 2543 default: 2544 abort: 2545 /* 2546 * Something unexpected happened -- deal with it. 2547 */ 2548 printf("sbicnextstate: aborting csr %02x asr %02x\n", csr, asr); 2549 #ifdef DDB 2550 Debugger(); 2551 #endif 2552 #ifdef DEBUG 2553 if( data_pointer_debug > 1 ) 2554 printf("next dmastop: %d(%x:%x)\n", 2555 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 2556 dev->sc_dmatimo = 0; 2557 #endif 2558 dev->sc_dmastop(dev); 2559 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2560 sbicerror(dev, regs, csr); 2561 sbicabort(dev, regs, "next"); 2562 if (dev->sc_flags & SBICF_INDMA) { 2563 /* 2564 * check for overlapping cache line, flush if so 2565 */ 2566 #ifdef M68040 2567 if (dev->sc_flags & SBICF_DCFLUSH) { 2568 #if 0 2569 printf("sibc: 68040 DMA cache flush needs fixing? %x:%x\n", 2570 dev->sc_xs->data, dev->sc_xs->datalen); 2571 #endif 2572 } 2573 #endif 2574 dev->sc_flags &= 2575 ~(SBICF_INDMA | SBICF_DCFLUSH); 2576 #ifdef DEBUG 2577 if( data_pointer_debug > 1 ) 2578 printf("next dmastop: %d(%x:%x)\n", 2579 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 2580 dev->sc_dmatimo = 0; 2581 #endif 2582 dev->sc_dmastop(dev); 2583 sbic_scsidone(acb, -1); 2584 } 2585 SBIC_TRACE(dev); 2586 return SBIC_STATE_ERROR; 2587 } 2588 2589 SBIC_TRACE(dev); 2590 return(SBIC_STATE_RUNNING); 2591 } 2592 2593 2594 /* 2595 * Check if DMA can not be used with specified buffer 2596 */ 2597 2598 int 2599 sbiccheckdmap(bp, len, mask) 2600 void *bp; 2601 u_long len, mask; 2602 { 2603 u_char *buffer; 2604 u_long phy_buf; 2605 u_long phy_len; 2606 2607 buffer = bp; 2608 2609 if (len == 0) 2610 return(0); 2611 2612 while (len) { 2613 phy_buf = kvtop(buffer); 2614 if (len < (phy_len = NBPG - ((int) buffer & PGOFSET))) 2615 phy_len = len; 2616 if (phy_buf & mask) 2617 return(1); 2618 buffer += phy_len; 2619 len -= phy_len; 2620 } 2621 return(0); 2622 } 2623 2624 int 2625 sbictoscsiperiod(dev, regs, a) 2626 struct sbic_softc *dev; 2627 sbic_regmap_p regs; 2628 int a; 2629 { 2630 unsigned int fs; 2631 2632 /* 2633 * cycle = DIV / (2*CLK) 2634 * DIV = FS+2 2635 * best we can do is 200ns at 20Mhz, 2 cycles 2636 */ 2637 2638 GET_SBIC_myid(regs,fs); 2639 fs = (fs >>6) + 2; /* DIV */ 2640 fs = (fs * 10000) / (dev->sc_clkfreq<<1); /* Cycle, in ns */ 2641 if (a < 2) a = 8; /* map to Cycles */ 2642 return ((fs*a)>>2); /* in 4 ns units */ 2643 } 2644 2645 int 2646 sbicfromscsiperiod(dev, regs, p) 2647 struct sbic_softc *dev; 2648 sbic_regmap_p regs; 2649 int p; 2650 { 2651 register unsigned int fs, ret; 2652 2653 /* Just the inverse of the above */ 2654 2655 GET_SBIC_myid(regs,fs); 2656 fs = (fs >>6) + 2; /* DIV */ 2657 fs = (fs * 10000) / (dev->sc_clkfreq<<1); /* Cycle, in ns */ 2658 2659 ret = p << 2; /* in ns units */ 2660 ret = ret / fs; /* in Cycles */ 2661 if (ret < sbic_min_period) 2662 return(sbic_min_period); 2663 2664 /* verify rounding */ 2665 if (sbictoscsiperiod(dev, regs, ret) < p) 2666 ret++; 2667 return (ret >= 8) ? 0 : ret; 2668 } 2669 2670 #ifdef DEBUG 2671 2672 void sbicdumpstate() 2673 { 2674 u_char csr, asr; 2675 2676 GET_SBIC_asr(debug_sbic_regs,asr); 2677 GET_SBIC_csr(debug_sbic_regs,csr); 2678 printf("%s: asr:csr(%02x:%02x)->(%02x:%02x)\n", 2679 (routine==1)?"sbicgo": 2680 (routine==2)?"sbicintr": 2681 (routine==3)?"sbicicmd": 2682 (routine==4)?"sbicnext":"unknown", 2683 debug_asr, debug_csr, asr, csr); 2684 2685 } 2686 2687 void sbictimeout(dev) 2688 struct sbic_softc *dev; 2689 { 2690 int s, asr; 2691 2692 s = splbio(); 2693 if (dev->sc_dmatimo) { 2694 if (dev->sc_dmatimo > 1) { 2695 printf("%s: dma timeout #%d\n", 2696 dev->sc_dev.dv_xname, dev->sc_dmatimo - 1); 2697 GET_SBIC_asr(dev->sc_sbicp, asr); 2698 if( asr & SBIC_ASR_INT ) { 2699 /* We need to service a missed IRQ */ 2700 printf("Servicing a missed int:(%02x,%02x)->(%02x,??)\n", 2701 debug_asr, debug_csr, asr); 2702 sbicintr(dev); 2703 } 2704 sbicdumpstate(); 2705 } 2706 dev->sc_dmatimo++; 2707 } 2708 splx(s); 2709 timeout((void *)sbictimeout, dev, 30 * hz); 2710 } 2711 2712 void 2713 sbic_dump_acb(acb) 2714 struct sbic_acb *acb; 2715 { 2716 u_char *b = (u_char *) &acb->cmd; 2717 int i; 2718 2719 printf("acb@%x ", acb); 2720 if (acb->xs == NULL) { 2721 printf("<unused>\n"); 2722 return; 2723 } 2724 printf("(%d:%d) flags %2x clen %2d cmd ", acb->xs->sc_link->target, 2725 acb->xs->sc_link->lun, acb->flags, acb->clen); 2726 for (i = acb->clen; i; --i) 2727 printf(" %02x", *b++); 2728 printf("\n"); 2729 printf(" xs: %08x data %8x:%04x ", acb->xs, acb->xs->data, 2730 acb->xs->datalen); 2731 printf("va %8x:%04x ", acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 2732 printf("pa %8x:%04x tcnt %x\n", acb->sc_pa.dc_addr, acb->sc_pa.dc_count, 2733 acb->sc_tcnt); 2734 } 2735 2736 void 2737 sbic_dump(dev) 2738 struct sbic_softc *dev; 2739 { 2740 sbic_regmap_p regs; 2741 u_char csr, asr; 2742 struct sbic_acb *acb; 2743 int s; 2744 int i; 2745 2746 s = splbio(); 2747 regs = dev->sc_sbicp; 2748 #if CSR_TRACE_SIZE 2749 printf("csr trace: "); 2750 i = csr_traceptr; 2751 do { 2752 printf("%c%02x%02x%02x ", csr_trace[i].whr, 2753 csr_trace[i].csr, csr_trace[i].asr, csr_trace[i].xtn); 2754 switch(csr_trace[i].whr) { 2755 case 'g': 2756 printf("go "); break; 2757 case 's': 2758 printf("select "); break; 2759 case 'y': 2760 printf("select+ "); break; 2761 case 'i': 2762 printf("intr "); break; 2763 case 'f': 2764 printf("finish "); break; 2765 case '>': 2766 printf("out "); break; 2767 case '<': 2768 printf("in "); break; 2769 case 'm': 2770 printf("msgin "); break; 2771 case 'x': 2772 printf("msginx "); break; 2773 case 'X': 2774 printf("msginX "); break; 2775 case 'r': 2776 printf("reselect "); break; 2777 case 'I': 2778 printf("icmd "); break; 2779 case 'a': 2780 printf("abort "); break; 2781 default: 2782 printf("? "); 2783 } 2784 switch(csr_trace[i].csr) { 2785 case 0x11: 2786 printf("INITIATOR"); break; 2787 case 0x16: 2788 printf("S_XFERRED"); break; 2789 case 0x20: 2790 printf("MSGIN_ACK"); break; 2791 case 0x41: 2792 printf("DISC"); break; 2793 case 0x42: 2794 printf("SEL_TIMEO"); break; 2795 case 0x80: 2796 printf("RSLT_NI"); break; 2797 case 0x81: 2798 printf("RSLT_IFY"); break; 2799 case 0x85: 2800 printf("DISC_1"); break; 2801 case 0x18: case 0x19: case 0x1a: 2802 case 0x1b: case 0x1e: case 0x1f: 2803 case 0x28: case 0x29: case 0x2a: 2804 case 0x2b: case 0x2e: case 0x2f: 2805 case 0x48: case 0x49: case 0x4a: 2806 case 0x4b: case 0x4e: case 0x4f: 2807 case 0x88: case 0x89: case 0x8a: 2808 case 0x8b: case 0x8e: case 0x8f: 2809 switch(csr_trace[i].csr & 0xf0) { 2810 case 0x10: 2811 printf("DONE_"); break; 2812 case 0x20: 2813 printf("STOP_"); break; 2814 case 0x40: 2815 printf("ERR_"); break; 2816 case 0x80: 2817 printf("REQ_"); break; 2818 } 2819 switch(csr_trace[i].csr & 7) { 2820 case 0: 2821 printf("DATA_OUT"); break; 2822 case 1: 2823 printf("DATA_IN"); break; 2824 case 2: 2825 printf("CMD"); break; 2826 case 3: 2827 printf("STATUS"); break; 2828 case 6: 2829 printf("MSG_OUT"); break; 2830 case 7: 2831 printf("MSG_IN"); break; 2832 default: 2833 printf("invld phs"); 2834 } 2835 break; 2836 default: printf("****"); break; 2837 } 2838 if (csr_trace[i].asr & SBIC_ASR_INT) 2839 printf(" ASR_INT"); 2840 if (csr_trace[i].asr & SBIC_ASR_LCI) 2841 printf(" ASR_LCI"); 2842 if (csr_trace[i].asr & SBIC_ASR_BSY) 2843 printf(" ASR_BSY"); 2844 if (csr_trace[i].asr & SBIC_ASR_CIP) 2845 printf(" ASR_CIP"); 2846 printf("\n"); 2847 i = (i + 1) & (CSR_TRACE_SIZE - 1); 2848 } while (i != csr_traceptr); 2849 #endif 2850 GET_SBIC_asr(regs, asr); 2851 if ((asr & SBIC_ASR_INT) == 0) 2852 GET_SBIC_csr(regs, csr); 2853 else 2854 csr = 0; 2855 printf("%s@%x regs %x asr %x csr %x\n", dev->sc_dev.dv_xname, 2856 dev, regs, asr, csr); 2857 if (acb = dev->free_list.tqh_first) { 2858 printf("Free list:\n"); 2859 while (acb) { 2860 sbic_dump_acb(acb); 2861 acb = acb->chain.tqe_next; 2862 } 2863 } 2864 if (acb = dev->ready_list.tqh_first) { 2865 printf("Ready list:\n"); 2866 while (acb) { 2867 sbic_dump_acb(acb); 2868 acb = acb->chain.tqe_next; 2869 } 2870 } 2871 if (acb = dev->nexus_list.tqh_first) { 2872 printf("Nexus list:\n"); 2873 while (acb) { 2874 sbic_dump_acb(acb); 2875 acb = acb->chain.tqe_next; 2876 } 2877 } 2878 if (dev->sc_nexus) { 2879 printf("nexus:\n"); 2880 sbic_dump_acb(dev->sc_nexus); 2881 } 2882 printf("sc_xs %x targ %d lun %d flags %x tcnt %x dmacmd %x mask %x\n", 2883 dev->sc_xs, dev->target, dev->lun, dev->sc_flags, dev->sc_tcnt, 2884 dev->sc_dmacmd, dev->sc_dmamask); 2885 for (i = 0; i < 8; ++i) { 2886 if (dev->sc_tinfo[i].cmds > 2) { 2887 printf("tgt %d: cmds %d disc %d senses %d lubusy %x\n", 2888 i, dev->sc_tinfo[i].cmds, 2889 dev->sc_tinfo[i].dconns, 2890 dev->sc_tinfo[i].senses, 2891 dev->sc_tinfo[i].lubusy); 2892 } 2893 } 2894 splx(s); 2895 } 2896 2897 #endif 2898
Indexes created Thu Oct 02 14:10:14 GMT 2025