sbic.c revision 1.2
1 /* 2 * Copyright (c) 1994 Christian E. Hopps 3 * Copyright (c) 1990 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * Van Jacobson of Lawrence Berkeley Laboratory. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the University of 20 * California, Berkeley and its contributors. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * @(#)scsi.c 7.5 (Berkeley) 5/4/91 38 * $Id: sbic.c,v 1.2 1994/05/12 06:43:09 chopps Exp $ 39 */ 40 41 /* 42 * AMIGA AMD 33C93 scsi adaptor driver 43 */ 44 45 /* need to know if any tapes have been configured */ 46 #include "st.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/device.h> 51 #include <sys/buf.h> 52 #include <scsi/scsi_all.h> 53 #include <scsi/scsiconf.h> 54 #include <vm/vm.h> 55 #include <vm/vm_kern.h> 56 #include <vm/vm_page.h> 57 #include <machine/pmap.h> 58 #include <machine/cpu.h> 59 #include <amiga/amiga/device.h> 60 #include <amiga/amiga/custom.h> 61 #include <amiga/dev/dmavar.h> 62 #include <amiga/dev/sbicreg.h> 63 #include <amiga/dev/sbicvar.h> 64 65 /* 66 * SCSI delays 67 * In u-seconds, primarily for state changes on the SPC. 68 */ 69 #define SBIC_CMD_WAIT 50000 /* wait per step of 'immediate' cmds */ 70 #define SBIC_DATA_WAIT 50000 /* wait per data in/out step */ 71 #define SBIC_INIT_WAIT 50000 /* wait per step (both) during init */ 72 73 #define b_cylin b_resid 74 #define SBIC_WAIT(regs, until, timeo) sbicwait(regs, until, timeo, __LINE__) 75 76 extern u_int kvtop(); 77 78 int sbicicmd __P((struct sbic_softc *, int, void *, int, void *, int,u_char)); 79 int sbicgo __P((struct sbic_softc *, struct scsi_xfer *)); 80 int sbicdmaok __P((struct sbic_softc *, struct scsi_xfer *)); 81 int sbicgetsense __P((struct sbic_softc *, struct scsi_xfer *)); 82 int sbicwait __P((sbic_regmap_p, char, int , int)); 83 int sbiccheckdmap __P((void *, u_long, u_long)); 84 int sbicselectbus __P((struct sbic_softc *, sbic_regmap_p, u_char, u_char)); 85 int sbicxfstart __P((sbic_regmap_p, int, u_char, int)); 86 int sbicxfout __P((sbic_regmap_p regs, int, void *, int)); 87 int sbicfromscsiperiod __P((struct sbic_softc *, sbic_regmap_p, int)); 88 int sbictoscsiperiod __P((struct sbic_softc *, sbic_regmap_p, int)); 89 int sbicintr __P((struct sbic_softc *)); 90 void sbicxfin __P((sbic_regmap_p regs, int, void *)); 91 void sbicxfdone __P((struct sbic_softc *, sbic_regmap_p, int)); 92 void sbicabort __P((struct sbic_softc *, sbic_regmap_p, char *)); 93 void sbicerror __P((struct sbic_softc *, sbic_regmap_p, u_char)); 94 void sbicstart __P((struct sbic_softc *)); 95 void sbicreset __P((struct sbic_softc *)); 96 void sbicsetdelay __P((int)); 97 void sbic_scsidone __P((struct sbic_softc *, int)); 98 void sbic_donextcmd __P((struct sbic_softc *)); 99 100 /* 101 * Synch xfer parameters, and timing conversions 102 */ 103 int sbic_min_period = SBIC_SYN_MIN_PERIOD; /* in cycles = f(ICLK,FSn) */ 104 int sbic_max_offset = SBIC_SYN_MAX_OFFSET; /* pure number */ 105 106 int sbic_cmd_wait = SBIC_CMD_WAIT; 107 int sbic_data_wait = SBIC_DATA_WAIT; 108 int sbic_init_wait = SBIC_INIT_WAIT; 109 110 /* 111 * was broken before.. now if you want this you get it for all drives 112 * on sbic controllers. 113 */ 114 int sbic_inhibit_sync = 1; 115 int sbic_clock_override = 0; 116 int sbic_no_dma = 0; 117 118 #ifdef DEBUG 119 #define QPRINTF(a) if (sbic_debug > 1) printf a 120 int sbic_debug = 0; 121 int sync_debug = 0; 122 int sbic_dma_debug = 0; 123 #else 124 #define QPRINTF 125 #endif 126 127 /* 128 * default minphys routine for sbic based controllers 129 */ 130 void 131 sbic_minphys(bp) 132 struct buf *bp; 133 { 134 /* 135 * no max transfer at this level 136 */ 137 } 138 139 /* 140 * must be used 141 */ 142 u_int 143 sbic_adinfo() 144 { 145 /* 146 * one request at a time please 147 */ 148 return(1); 149 } 150 151 /* 152 * used by specific sbic controller 153 * 154 * it appears that the higher level code does nothing with LUN's 155 * so I will too. I could plug it in, however so could they 156 * in scsi_scsi_cmd(). 157 */ 158 int 159 sbic_scsicmd(xs) 160 struct scsi_xfer *xs; 161 { 162 struct sbic_pending *pendp; 163 struct sbic_softc *dev; 164 struct scsi_link *slp; 165 int flags, s; 166 167 slp = xs->sc_link; 168 dev = slp->adapter_softc; 169 flags = xs->flags; 170 171 if (flags & SCSI_DATA_UIO) 172 panic("sbic: scsi data uio requested"); 173 174 if (dev->sc_xs && flags & SCSI_NOMASK) 175 panic("sbic_scsicmd: busy"); 176 177 s = splbio(); 178 pendp = &dev->sc_xsstore[slp->target][slp->lun]; 179 if (pendp->xs) { 180 splx(s); 181 return(TRY_AGAIN_LATER); 182 } 183 184 if (dev->sc_xs) { 185 pendp->xs = xs; 186 TAILQ_INSERT_TAIL(&dev->sc_xslist, pendp, link); 187 splx(s); 188 return(SUCCESSFULLY_QUEUED); 189 } 190 pendp->xs = NULL; 191 dev->sc_xs = xs; 192 splx(s); 193 194 /* 195 * nothing is pending do it now. 196 */ 197 sbic_donextcmd(dev); 198 199 if (flags & SCSI_NOMASK) 200 return(COMPLETE); 201 return(SUCCESSFULLY_QUEUED); 202 } 203 204 /* 205 * entered with dev->sc_xs pointing to the next xfer to perform 206 */ 207 void 208 sbic_donextcmd(dev) 209 struct sbic_softc *dev; 210 { 211 struct scsi_xfer *xs; 212 struct scsi_link *slp; 213 int flags, phase, stat; 214 215 xs = dev->sc_xs; 216 slp = xs->sc_link; 217 flags = xs->flags; 218 219 if (flags & SCSI_DATA_IN) 220 phase = DATA_IN_PHASE; 221 else if (flags & SCSI_DATA_OUT) 222 phase = DATA_OUT_PHASE; 223 else 224 phase = STATUS_PHASE; 225 226 if (flags & SCSI_RESET) 227 sbicreset(dev); 228 229 dev->sc_stat[0] = -1; 230 if (phase == STATUS_PHASE || flags & SCSI_NOMASK || 231 sbicdmaok(dev, xs) == 0) 232 stat = sbicicmd(dev, slp->target, xs->cmd, xs->cmdlen, 233 xs->data, xs->datalen, phase); 234 else if (sbicgo(dev, xs) == 0) 235 return; 236 else 237 stat = dev->sc_stat[0]; 238 239 sbic_scsidone(dev, stat); 240 } 241 242 void 243 sbic_scsidone(dev, stat) 244 struct sbic_softc *dev; 245 int stat; 246 { 247 struct sbic_pending *pendp; 248 struct scsi_xfer *xs; 249 int s, donext; 250 251 xs = dev->sc_xs; 252 #ifdef DIAGNOSTIC 253 if (xs == NULL) 254 panic("sbic_scsidone"); 255 #endif 256 /* 257 * is this right? 258 */ 259 xs->status = stat; 260 261 if (stat == 0 || xs->flags & SCSI_ERR_OK) 262 xs->resid = 0; 263 else { 264 switch(stat) { 265 case SCSI_CHECK: 266 if (stat = sbicgetsense(dev, xs)) 267 goto bad_sense; 268 xs->error = XS_SENSE; 269 break; 270 case SCSI_BUSY: 271 xs->error = XS_BUSY; 272 break; 273 bad_sense: 274 default: 275 xs->error = XS_DRIVER_STUFFUP; 276 QPRINTF(("sbic_scsicmd() bad %x\n", stat)); 277 break; 278 } 279 } 280 xs->flags |= ITSDONE; 281 282 /* 283 * grab next command before scsi_done() 284 * this way no single device can hog scsi resources. 285 */ 286 s = splbio(); 287 pendp = dev->sc_xslist.tqh_first; 288 if (pendp == NULL) { 289 donext = 0; 290 dev->sc_xs = NULL; 291 } else { 292 donext = 1; 293 TAILQ_REMOVE(&dev->sc_xslist, pendp, link); 294 dev->sc_xs = pendp->xs; 295 pendp->xs = NULL; 296 } 297 splx(s); 298 scsi_done(xs); 299 300 if (donext) 301 sbic_donextcmd(dev); 302 } 303 304 int 305 sbicgetsense(dev, xs) 306 struct sbic_softc *dev; 307 struct scsi_xfer *xs; 308 { 309 struct scsi_sense rqs; 310 struct scsi_link *slp; 311 int stat; 312 313 slp = xs->sc_link; 314 315 rqs.op_code = REQUEST_SENSE; 316 rqs.byte2 = slp->lun << 5; 317 #ifdef not_yet 318 rqs.length = xs->req_sense_length ? xs->req_sense_length : 319 sizeof(xs->sense); 320 #else 321 rqs.length = sizeof(xs->sense); 322 #endif 323 324 rqs.unused[0] = rqs.unused[1] = rqs.control = 0; 325 326 return(sbicicmd(dev, slp->target, &rqs, sizeof(rqs), &xs->sense, 327 rqs.length, DATA_IN_PHASE)); 328 } 329 330 int 331 sbicdmaok(dev, xs) 332 struct sbic_softc *dev; 333 struct scsi_xfer *xs; 334 { 335 if (sbic_no_dma || xs->datalen & 0x1 || (u_int)xs->data & 0x3) 336 return(0); 337 /* 338 * controller supports dma to any addresses? 339 */ 340 else if ((dev->sc_flags & SBICF_BADDMA) == 0) 341 return(1); 342 /* 343 * this address is ok for dma? 344 */ 345 else if (sbiccheckdmap(xs->data, xs->datalen, dev->sc_dmamask) == 0) 346 return(1); 347 /* 348 * we have a bounce buffer? 349 */ 350 else if (dev->sc_dmabuffer) 351 return(1); 352 return(0); 353 } 354 355 356 int 357 sbicwait(regs, until, timeo, line) 358 sbic_regmap_p regs; 359 char until; 360 int timeo; 361 int line; 362 { 363 u_char val; 364 int csr; 365 366 if (timeo == 0) 367 timeo = 1000000; /* some large value.. */ 368 369 GET_SBIC_asr(regs,val); 370 while ((val & until) == 0) { 371 if (timeo-- == 0) { 372 GET_SBIC_csr(regs, csr); 373 printf("sbicwait TIMEO @%d with asr=x%x csr=x%x\n", 374 line, val, csr); 375 break; 376 } 377 DELAY(1); 378 GET_SBIC_asr(regs,val); 379 } 380 return(val); 381 } 382 383 void 384 sbicabort(dev, regs, where) 385 struct sbic_softc *dev; 386 sbic_regmap_p regs; 387 char *where; 388 { 389 u_char csr, asr; 390 391 GET_SBIC_csr(regs, csr); 392 GET_SBIC_asr(regs, asr); 393 394 printf ("%s: abort %s: csr = 0x%02x, asr = 0x%02x\n", 395 dev->sc_dev.dv_xname, where, csr, asr); 396 397 if (dev->sc_flags & SBICF_SELECTED) { 398 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 399 WAIT_CIP(regs); 400 401 GET_SBIC_asr(regs, asr); 402 if (asr & (SBIC_ASR_BSY|SBIC_ASR_LCI)) { 403 /* ok, get more drastic.. */ 404 405 SET_SBIC_cmd (regs, SBIC_CMD_RESET); 406 DELAY(25); 407 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 408 /* clears interrupt also */ 409 GET_SBIC_csr (regs, csr); 410 411 dev->sc_flags &= ~SBICF_SELECTED; 412 return; 413 } 414 415 do { 416 SBIC_WAIT (regs, SBIC_ASR_INT, 0); 417 GET_SBIC_csr (regs, csr); 418 } while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) 419 && (csr != SBIC_CSR_CMD_INVALID)); 420 421 /* lets just hope it worked.. */ 422 dev->sc_flags &= ~SBICF_SELECTED; 423 } 424 } 425 426 /* 427 * XXX Set/reset long delays. 428 * 429 * if delay == 0, reset default delays 430 * if delay < 0, set both delays to default long initialization values 431 * if delay > 0, set both delays to this value 432 * 433 * Used when a devices is expected to respond slowly (e.g. during 434 * initialization). 435 */ 436 void 437 sbicsetdelay(del) 438 int del; 439 { 440 static int saved_cmd_wait, saved_data_wait; 441 442 if (del) { 443 saved_cmd_wait = sbic_cmd_wait; 444 saved_data_wait = sbic_data_wait; 445 if (del > 0) 446 sbic_cmd_wait = sbic_data_wait = del; 447 else 448 sbic_cmd_wait = sbic_data_wait = sbic_init_wait; 449 } else { 450 sbic_cmd_wait = saved_cmd_wait; 451 sbic_data_wait = saved_data_wait; 452 } 453 } 454 455 void 456 sbicreset(dev) 457 struct sbic_softc *dev; 458 { 459 sbic_regmap_p regs; 460 u_int i, s; 461 u_char my_id, csr; 462 463 regs = dev->sc_sbicp; 464 465 if (dev->sc_flags & SBICF_ALIVE) 466 sbicabort(dev, regs, "reset"); 467 468 s = splbio(); 469 /* preserve our ID for now */ 470 GET_SBIC_myid (regs, my_id); 471 my_id &= SBIC_ID_MASK; 472 473 if (dev->sc_clkfreq < 110) 474 my_id |= SBIC_ID_FS_8_10; 475 else if (dev->sc_clkfreq < 160) 476 my_id |= SBIC_ID_FS_12_15; 477 else if (dev->sc_clkfreq < 210) 478 my_id |= SBIC_ID_FS_16_20; 479 480 my_id |= SBIC_ID_EAF /*| SBIC_ID_EHP*/ ; 481 482 SET_SBIC_myid(regs, my_id); 483 484 /* 485 * Disable interrupts (in dmainit) then reset the chip 486 */ 487 SET_SBIC_cmd(regs, SBIC_CMD_RESET); 488 DELAY(25); 489 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 490 GET_SBIC_csr(regs, csr); /* clears interrupt also */ 491 492 /* 493 * Set up various chip parameters 494 */ 495 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI 496 | SBIC_MACHINE_DMA_MODE); 497 /* 498 * don't allow (re)selection (SBIC_RID_ES) 499 * until we can handle target mode!! 500 */ 501 SET_SBIC_rselid(regs, 0); 502 SET_SBIC_syn(regs, 0); /* asynch for now */ 503 504 /* 505 * anything else was zeroed by reset 506 */ 507 splx(s); 508 509 dev->sc_flags |= SBICF_ALIVE; 510 dev->sc_flags &= ~SBICF_SELECTED; 511 } 512 513 void 514 sbicerror(dev, regs, csr) 515 struct sbic_softc *dev; 516 sbic_regmap_p regs; 517 u_char csr; 518 { 519 struct scsi_xfer *xs; 520 521 xs = dev->sc_xs; 522 523 #ifdef DIAGNOSTIC 524 if (xs == NULL) 525 panic("sbicerror"); 526 #endif 527 if (xs->flags & SCSI_SILENT) 528 return; 529 530 printf("%s: ", dev->sc_dev.dv_xname); 531 printf("csr == 0x%02i\n", csr); /* XXX */ 532 } 533 534 /* 535 * select the bus, return when selected or error. 536 */ 537 int 538 sbicselectbus(dev, regs, target, our_addr) 539 struct sbic_softc *dev; 540 sbic_regmap_p regs; 541 u_char target, our_addr; 542 { 543 u_char asr, csr, id; 544 545 QPRINTF(("sbicselectbus %d\n", target)); 546 547 /* 548 * if we're already selected, return (XXXX panic maybe?) 549 */ 550 if (dev->sc_flags & SBICF_SELECTED) 551 return(1); 552 553 /* 554 * issue select 555 */ 556 SBIC_TC_PUT(regs, 0); 557 SET_SBIC_selid(regs, target); 558 SET_SBIC_timeo(regs, SBIC_TIMEOUT(250,dev->sc_clkfreq)); 559 560 /* 561 * set sync or async 562 */ 563 if (dev->sc_sync[target].state == SYNC_DONE) 564 SET_SBIC_syn(regs, SBIC_SYN (dev->sc_sync[target].offset, 565 dev->sc_sync[target].period)); 566 else 567 SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period)); 568 569 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN); 570 571 /* 572 * wait for select (merged from seperate function may need 573 * cleanup) 574 */ 575 WAIT_CIP(regs); 576 do { 577 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 578 GET_SBIC_csr (regs, csr); 579 QPRINTF(("%02x ", csr)); 580 } while (csr != (SBIC_CSR_MIS_2|MESG_OUT_PHASE) 581 && csr != (SBIC_CSR_MIS_2|CMD_PHASE) && csr != SBIC_CSR_SEL_TIMEO); 582 583 if (csr == (SBIC_CSR_MIS_2|CMD_PHASE)) 584 dev->sc_flags |= SBICF_SELECTED; /* device ignored ATN */ 585 else if (csr == (SBIC_CSR_MIS_2|MESG_OUT_PHASE)) { 586 /* 587 * Send identify message 588 * (SCSI-2 requires an identify msg (?)) 589 */ 590 GET_SBIC_selid(regs, id); 591 592 /* 593 * handle drives that don't want to be asked 594 * whether to go sync at all. 595 */ 596 if (sbic_inhibit_sync && dev->sc_sync[id].state == SYNC_START) { 597 #ifdef DEBUG 598 if (sync_debug) 599 printf("Forcing target %d asynchronous.\n", id); 600 #endif 601 dev->sc_sync[id].offset = 0; 602 dev->sc_sync[id].period = sbic_min_period; 603 dev->sc_sync[id].state = SYNC_DONE; 604 } 605 606 607 if (dev->sc_sync[id].state != SYNC_START) 608 SEND_BYTE (regs, MSG_IDENTIFY); 609 else { 610 /* 611 * try to initiate a sync transfer. 612 * So compose the sync message we're going 613 * to send to the target 614 */ 615 616 #ifdef DEBUG 617 if (sync_debug) 618 printf("Sending sync request to target %d ... ", 619 id); 620 #endif 621 /* 622 * setup scsi message sync message request 623 */ 624 dev->sc_msg[0] = MSG_IDENTIFY; 625 dev->sc_msg[1] = MSG_EXT_MESSAGE; 626 dev->sc_msg[2] = 3; 627 dev->sc_msg[3] = MSG_SYNC_REQ; 628 dev->sc_msg[4] = sbictoscsiperiod(dev, regs, 629 sbic_min_period); 630 dev->sc_msg[5] = sbic_max_offset; 631 632 if (sbicxfstart(regs, 6, MESG_OUT_PHASE, sbic_cmd_wait)) 633 sbicxfout(regs, 6, dev->sc_msg, MESG_OUT_PHASE); 634 635 dev->sc_sync[id].state = SYNC_SENT; 636 #ifdef DEBUG 637 if (sync_debug) 638 printf ("sent\n"); 639 #endif 640 } 641 642 SBIC_WAIT (regs, SBIC_ASR_INT, 0); 643 GET_SBIC_csr (regs, csr); 644 QPRINTF(("[%02x]", csr)); 645 #ifdef DEBUG 646 if (sync_debug && dev->sc_sync[id].state == SYNC_SENT) 647 printf("csr-result of last msgout: 0x%x\n", csr); 648 #endif 649 650 if (csr != SBIC_CSR_SEL_TIMEO) 651 dev->sc_flags |= SBICF_SELECTED; 652 } 653 654 QPRINTF(("\n")); 655 656 return(csr == SBIC_CSR_SEL_TIMEO); 657 } 658 659 int 660 sbicxfstart(regs, len, phase, wait) 661 sbic_regmap_p regs; 662 int len, wait; 663 u_char phase; 664 { 665 u_char id; 666 667 if (phase == DATA_IN_PHASE || phase == MESG_IN_PHASE) { 668 GET_SBIC_selid (regs, id); 669 id |= SBIC_SID_FROM_SCSI; 670 SET_SBIC_selid (regs, id); 671 SBIC_TC_PUT (regs, (unsigned)len); 672 } else if (phase == DATA_OUT_PHASE || phase == MESG_OUT_PHASE 673 || phase == CMD_PHASE) 674 SBIC_TC_PUT (regs, (unsigned)len); 675 else 676 SBIC_TC_PUT (regs, 0); 677 QPRINTF(("sbicxfstart %d, %d, %d\n", len, phase, wait)); 678 679 return(1); 680 } 681 682 int 683 sbicxfout(regs, len, bp, phase) 684 sbic_regmap_p regs; 685 int len; 686 void *bp; 687 int phase; 688 { 689 u_char orig_csr, csr, asr, *buf; 690 int wait; 691 692 buf = bp; 693 wait = sbic_data_wait; 694 695 QPRINTF(("sbicxfout {%d} %02x %02x %02x %02x %02x " 696 "%02x %02x %02x %02x %02x\n", len, buf[0], buf[1], buf[2], 697 buf[3], buf[4], buf[5], buf[6], buf[7], buf[8], buf[9])); 698 699 GET_SBIC_csr (regs, orig_csr); 700 701 /* 702 * sigh.. WD-PROTO strikes again.. sending the command in one go 703 * causes the chip to lock up if talking to certain (misbehaving?) 704 * targets. Anyway, this procedure should work for all targets, but 705 * it's slightly slower due to the overhead 706 */ 707 WAIT_CIP (regs); 708 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 709 for (;len > 0; len--) { 710 GET_SBIC_asr (regs, asr); 711 while ((asr & SBIC_ASR_DBR) == 0) { 712 if ((asr & SBIC_ASR_INT) || --wait < 0) { 713 #ifdef DEBUG 714 if (sbic_debug) 715 printf("sbicxfout fail: l%d i%x w%d\n", 716 len, asr, wait); 717 #endif 718 return (len); 719 } 720 DELAY(1); 721 GET_SBIC_asr (regs, asr); 722 } 723 724 SET_SBIC_data (regs, *buf); 725 buf++; 726 } 727 728 QPRINTF(("sbicxfout done\n")); 729 /* 730 * this leaves with one csr to be read 731 */ 732 return(0); 733 } 734 735 void 736 sbicxfin(regs, len, bp) 737 sbic_regmap_p regs; 738 int len; 739 void *bp; 740 { 741 int wait; 742 u_char *obp, *buf; 743 u_char orig_csr, csr, asr; 744 745 wait = sbic_data_wait; 746 obp = bp; 747 buf = bp; 748 749 GET_SBIC_csr (regs, orig_csr); 750 751 QPRINTF(("sbicxfin %d, csr=%02x\n", len, orig_csr)); 752 753 WAIT_CIP (regs); 754 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 755 for (;len > 0; len--) { 756 GET_SBIC_asr (regs, asr); 757 while ((asr & SBIC_ASR_DBR) == 0) { 758 if ((asr & SBIC_ASR_INT) || --wait < 0) { 759 #ifdef DEBUG 760 if (sbic_debug) 761 printf("sbicxfin fail: l%d i%x w%d\n", 762 len, asr, wait); 763 #endif 764 return; 765 } 766 767 DELAY(1); 768 GET_SBIC_asr (regs, asr); 769 } 770 771 GET_SBIC_data (regs, *buf); 772 buf++; 773 } 774 775 QPRINTF(("sbicxfin {%d} %02x %02x %02x %02x %02x %02x " 776 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 777 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 778 779 /* this leaves with one csr to be read */ 780 } 781 782 783 /* 784 * SCSI 'immediate' command: issue a command to some SCSI device 785 * and get back an 'immediate' response (i.e., do programmed xfer 786 * to get the response data). 'cbuf' is a buffer containing a scsi 787 * command of length clen bytes. 'buf' is a buffer of length 'len' 788 * bytes for data. The transfer direction is determined by the device 789 * (i.e., by the scsi bus data xfer phase). If 'len' is zero, the 790 * command must supply no data. 'xferphase' is the bus phase the 791 * caller expects to happen after the command is issued. It should 792 * be one of DATA_IN_PHASE, DATA_OUT_PHASE or STATUS_PHASE. 793 */ 794 int 795 sbicicmd(dev, target, cbuf, clen, buf, len, xferphase) 796 struct sbic_softc *dev; 797 void *cbuf, *buf; 798 int clen, len; 799 u_char xferphase; 800 { 801 sbic_regmap_p regs; 802 u_char phase, csr, asr; 803 int wait; 804 805 regs = dev->sc_sbicp; 806 807 /* 808 * set the sbic into non-DMA mode 809 */ 810 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 811 812 retry_selection: 813 /* 814 * select the SCSI bus (it's an error if bus isn't free) 815 */ 816 if (sbicselectbus(dev, regs, target, dev->sc_scsiaddr)) 817 return(-1); 818 /* 819 * Wait for a phase change (or error) then let the device sequence 820 * us through the various SCSI phases. 821 */ 822 dev->sc_stat[0] = 0xff; 823 dev->sc_msg[0] = 0xff; 824 phase = CMD_PHASE; 825 826 new_phase: 827 wait = sbic_cmd_wait; 828 829 GET_SBIC_csr (regs, csr); 830 QPRINTF((">CSR:%02x<", csr)); 831 832 /* 833 * requesting some new phase 834 */ 835 if ((csr != 0xff) && (csr & 0xf0) && (csr & 0x08)) 836 phase = csr & PHASE; 837 else if ((csr == SBIC_CSR_DISC) || (csr == SBIC_CSR_DISC_1) 838 || (csr == SBIC_CSR_S_XFERRED)) { 839 dev->sc_flags &= ~SBICF_SELECTED; 840 GET_SBIC_cmd_phase (regs, phase); 841 if (phase == 0x60) 842 GET_SBIC_tlun (regs, dev->sc_stat[0]); 843 else 844 return(-1); 845 goto out; 846 } else { 847 sbicerror(dev, regs, csr); 848 goto abort; 849 } 850 851 switch (phase) { 852 case CMD_PHASE: 853 if (sbicxfstart (regs, clen, phase, wait)) 854 if (sbicxfout (regs, clen, cbuf, phase)) 855 goto abort; 856 phase = xferphase; 857 break; 858 case DATA_IN_PHASE: 859 if (len <= 0) 860 goto abort; 861 wait = sbic_data_wait; 862 if (sbicxfstart(regs, len, phase, wait)) 863 sbicxfin(regs, len, buf); 864 phase = STATUS_PHASE; 865 break; 866 case MESG_IN_PHASE: 867 if (sbicxfstart(regs, sizeof(dev->sc_msg), phase, wait) == 0) 868 break; 869 dev->sc_msg[0] = 0xff; 870 sbicxfin(regs, sizeof(dev->sc_msg), dev->sc_msg); 871 /* 872 * get the command completion interrupt, or we 873 * can't send a new command (LCI) 874 */ 875 SBIC_WAIT(regs, SBIC_ASR_INT, wait); 876 GET_SBIC_csr(regs, csr); 877 #ifdef DEBUG 878 if (sync_debug) 879 printf("msgin done csr 0x%x\n", csr); 880 #endif 881 /* 882 * test whether this is a reply to our sync 883 * request 884 */ 885 if (dev->sc_msg[0] == MSG_EXT_MESSAGE && dev->sc_msg[1] == 3 886 && dev->sc_msg[2] == MSG_SYNC_REQ) { 887 888 dev->sc_sync[target].period = sbicfromscsiperiod(dev, 889 regs, dev->sc_msg[3]); 890 dev->sc_sync[target].offset = dev->sc_msg[4]; 891 dev->sc_sync[target].state = SYNC_DONE; 892 SET_SBIC_syn(regs, SBIC_SYN(dev->sc_sync[target].offset, 893 dev->sc_sync[target].period)); 894 /* ACK the message */ 895 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 896 WAIT_CIP(regs); 897 phase = CMD_PHASE; /* or whatever */ 898 printf("%s: target %d now synchronous," 899 " period=%dns, offset=%d.\n", 900 dev->sc_dev.dv_xname, target, dev->sc_msg[3] * 4, 901 dev->sc_msg[4]); 902 } else if (dev->sc_msg[0] == MSG_REJECT 903 && dev->sc_sync[target].state == SYNC_SENT) { 904 #ifdef DEBUG 905 if (sync_debug) 906 printf("target %d rejected sync, going async\n", 907 target); 908 #endif 909 dev->sc_sync[target].period = sbic_min_period; 910 dev->sc_sync[target].offset = 0; 911 dev->sc_sync[target].state = SYNC_DONE; 912 SET_SBIC_syn(regs, SBIC_SYN(dev->sc_sync[target].offset, 913 dev->sc_sync[target].period)); 914 /* ACK the message */ 915 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 916 WAIT_CIP(regs); 917 phase = CMD_PHASE; /* or whatever */ 918 } else if (dev->sc_msg[0] == MSG_REJECT) { 919 /* 920 * we'll never REJECt a REJECT message.. 921 */ 922 /* ACK the message */ 923 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 924 WAIT_CIP(regs); 925 phase = CMD_PHASE; /* or whatever */ 926 } else if (dev->sc_msg[0] == MSG_CMD_COMPLETE) { 927 /* !! KLUDGE ALERT !! quite a few drives don't seem to 928 * really like the current way of sending the 929 * sync-handshake together with the ident-message, and 930 * they react by sending command-complete and 931 * disconnecting right after returning the valid sync 932 * handshake. So, all I can do is reselect the drive, 933 * and hope it won't disconnect again. I don't think 934 * this is valid behavior, but I can't help fixing a 935 * problem that apparently exists. 936 * 937 * Note: we should not get here on `normal' command 938 * completion, as that condition is handled by the 939 * high-level sel&xfer resume command used to walk 940 * thru status/cc-phase. 941 */ 942 943 #ifdef DEBUG 944 if (sync_debug) 945 printf ("GOT CMD-COMPLETE! %d acting weird.." 946 " waiting for disconnect...\n", target); 947 #endif 948 /* ACK the message */ 949 SET_SBIC_cmd (regs, SBIC_CMD_CLR_ACK); 950 WAIT_CIP(regs); 951 952 /* wait for disconnect */ 953 while (csr != SBIC_CSR_DISC && 954 csr != SBIC_CSR_DISC_1) { 955 DELAY(1); 956 GET_SBIC_csr(regs, csr); 957 } 958 #ifdef DEBUG 959 if (sync_debug) 960 printf ("ok.\nRetrying selection.\n"); 961 #endif 962 dev->sc_flags &= ~SBICF_SELECTED; 963 goto retry_selection; 964 } else { 965 #ifdef DEBUG 966 if (sbic_debug || sync_debug) 967 printf ("Rejecting message 0x%02x\n", 968 dev->sc_msg[0]); 969 #endif 970 /* prepare to reject the message, NACK */ 971 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 972 WAIT_CIP(regs); 973 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 974 WAIT_CIP(regs); 975 phase = MESG_OUT_PHASE; 976 } 977 break; 978 979 case MESG_OUT_PHASE: 980 #ifdef DEBUG 981 if (sync_debug) 982 printf ("sending REJECT msg to last msg.\n"); 983 #endif 984 /* 985 * should only get here on reject, 986 * since it's always US that 987 * initiate a sync transfer 988 */ 989 SEND_BYTE(regs, MSG_REJECT); 990 phase = STATUS_PHASE; 991 break; 992 case DATA_OUT_PHASE: 993 if (len <= 0) 994 goto abort; 995 wait = sbic_data_wait; 996 if (sbicxfstart(regs, len, phase, wait)) 997 if (sbicxfout (regs, len, buf, phase)) 998 goto abort; 999 phase = STATUS_PHASE; 1000 break; 1001 case STATUS_PHASE: 1002 /* 1003 * the sbic does the status/cmd-complete reading ok, 1004 * so do this with its hi-level commands. 1005 */ 1006 SBIC_TC_PUT(regs, 0); 1007 SET_SBIC_cmd_phase(regs, 0x46); 1008 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1009 phase = BUS_FREE_PHASE; 1010 break; 1011 case BUS_FREE_PHASE: 1012 goto out; 1013 default: 1014 printf("%s: unexpected phase %d in icmd from %d\n", 1015 dev->sc_dev.dv_xname, phase, target); 1016 goto abort; 1017 } 1018 1019 /* 1020 * make sure the last command was taken, 1021 * ie. we're not hunting after an ignored command.. 1022 */ 1023 GET_SBIC_asr(regs, asr); 1024 if (asr & SBIC_ASR_LCI) 1025 goto abort; 1026 1027 /* tapes may take a loooong time.. */ 1028 while (asr & SBIC_ASR_BSY) { 1029 DELAY(1); 1030 GET_SBIC_asr(regs, asr); 1031 } 1032 1033 /* 1034 * wait for last command to complete 1035 */ 1036 SBIC_WAIT (regs, SBIC_ASR_INT, wait); 1037 1038 /* 1039 * do it again 1040 */ 1041 goto new_phase; 1042 abort: 1043 sbicabort(dev, regs, "icmd"); 1044 out: 1045 QPRINTF(("=STS:%02x=", dev->sc_stat[0])); 1046 return(dev->sc_stat[0]); 1047 } 1048 1049 /* 1050 * Finish SCSI xfer command: After the completion interrupt from 1051 * a read/write operation, sequence through the final phases in 1052 * programmed i/o. This routine is a lot like sbicicmd except we 1053 * skip (and don't allow) the select, cmd out and data in/out phases. 1054 */ 1055 void 1056 sbicxfdone(dev, regs, target) 1057 struct sbic_softc *dev; 1058 sbic_regmap_p regs; 1059 int target; 1060 { 1061 u_char phase, csr; 1062 int s; 1063 1064 QPRINTF(("{")); 1065 s = splbio(); 1066 1067 /* 1068 * have the sbic complete on its own 1069 */ 1070 SBIC_TC_PUT(regs, 0); 1071 SET_SBIC_cmd_phase(regs, 0x46); 1072 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1073 1074 do { 1075 SBIC_WAIT (regs, SBIC_ASR_INT, 0); 1076 GET_SBIC_csr (regs, csr); 1077 QPRINTF(("%02x:", csr)); 1078 } while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) 1079 && (csr != SBIC_CSR_S_XFERRED)); 1080 1081 dev->sc_flags &= ~SBICF_SELECTED; 1082 1083 GET_SBIC_cmd_phase (regs, phase); 1084 QPRINTF(("}%02x", phase)); 1085 if (phase == 0x60) 1086 GET_SBIC_tlun(regs, dev->sc_stat[0]); 1087 else 1088 sbicerror(dev, regs, csr); 1089 1090 QPRINTF(("=STS:%02x=\n", dev->sc_stat[0])); 1091 splx(s); 1092 } 1093 1094 int 1095 sbicgo(dev, xs) 1096 struct sbic_softc *dev; 1097 struct scsi_xfer *xs; 1098 { 1099 int i, dmaflags, count, tcount, target; 1100 u_char phase, csr, asr, cmd, *addr; 1101 sbic_regmap_p regs; 1102 struct dma_chain *dcp; 1103 char *dmaend; 1104 int wait; 1105 1106 target = xs->sc_link->target; 1107 count = xs->datalen; 1108 addr = xs->data; 1109 1110 regs = dev->sc_sbicp; 1111 dmaend = NULL; 1112 1113 /* 1114 * set the sbic into DMA mode 1115 */ 1116 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI | 1117 SBIC_MACHINE_DMA_MODE); 1118 1119 /* 1120 * select the SCSI bus (it's an error if bus isn't free) 1121 */ 1122 if (sbicselectbus(dev, regs, target, dev->sc_scsiaddr)) { 1123 dev->sc_dmafree(dev); 1124 return(-1); 1125 } 1126 1127 /* 1128 * Wait for a phase change (or error) then let the device 1129 * sequence us through command phase (we may have to take 1130 * a msg in/out before doing the command). If the disk has 1131 * to do a seek, it may be a long time until we get a change 1132 * to data phase so, in the absense of an explicit phase 1133 * change, we assume data phase will be coming up and tell 1134 * the SPC to start a transfer whenever it does. We'll get 1135 * a service required interrupt later if this assumption is 1136 * wrong. Otherwise we'll get a service required int when 1137 * the transfer changes to status phase. 1138 */ 1139 phase = CMD_PHASE; 1140 1141 new_phase: 1142 wait = sbic_cmd_wait; 1143 switch (phase) { 1144 case CMD_PHASE: 1145 if (sbicxfstart(regs, xs->cmdlen, phase, wait)) 1146 if (sbicxfout(regs, xs->cmdlen, xs->cmd, phase)) 1147 goto abort; 1148 break; 1149 case MESG_IN_PHASE: 1150 if (sbicxfstart(regs, sizeof(dev->sc_msg), phase, wait) == 0) 1151 break; 1152 1153 sbicxfin(regs, sizeof(dev->sc_msg), dev->sc_msg); 1154 /* 1155 * prepare to reject any mesgin, 1156 * no matter what it might be.. 1157 */ 1158 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 1159 WAIT_CIP(regs); 1160 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 1161 phase = MESG_OUT_PHASE; 1162 break; 1163 case MESG_OUT_PHASE: 1164 SEND_BYTE(regs, MSG_REJECT); 1165 phase = STATUS_PHASE; 1166 break; 1167 case DATA_IN_PHASE: 1168 case DATA_OUT_PHASE: 1169 goto out; 1170 /* 1171 * status phase can happen, if the issued read/write command 1172 * is illegal (for example, reading after EOT on tape) and the 1173 * device doesn't even go to data in/out phase. So handle this 1174 * here normally, instead of going thru abort-handling. 1175 */ 1176 case STATUS_PHASE: 1177 dev->sc_dmafree(dev); 1178 sbicxfdone(dev, regs, target); 1179 dev->sc_flags &= ~(SBICF_INDMA | SBICF_BBUF); 1180 sbic_scsidone(dev, dev->sc_stat[0]); 1181 return(0); 1182 default: 1183 printf("%s: unexpected phase %d in go from %d\n", phase, 1184 dev->sc_dev.dv_xname, target); 1185 goto abort; 1186 } 1187 1188 /* 1189 * make sure the last command was taken, 1190 * ie. we're not hunting after an ignored command.. 1191 */ 1192 GET_SBIC_asr(regs, asr); 1193 if (asr & SBIC_ASR_LCI) 1194 goto abort; 1195 1196 /* 1197 * tapes may take a loooong time.. 1198 */ 1199 while (asr & SBIC_ASR_BSY) { 1200 DELAY(1); 1201 GET_SBIC_asr(regs, asr); 1202 } 1203 1204 if (wait <= 0) 1205 goto abort; 1206 1207 /* 1208 * wait for last command to complete 1209 */ 1210 SBIC_WAIT(regs, SBIC_ASR_INT, wait); 1211 1212 GET_SBIC_csr(regs, csr); 1213 QPRINTF((">CSR:%02x<", csr)); 1214 1215 /* 1216 * requesting some new phase 1217 */ 1218 if ((csr != 0xff) && (csr & 0xf0) && (csr & 0x08)) 1219 phase = csr & PHASE; 1220 else { 1221 sbicerror(dev, regs, csr); 1222 goto abort; 1223 } 1224 /* 1225 * start again with for new phase 1226 */ 1227 goto new_phase; 1228 out: 1229 dmaflags = 0; 1230 if (xs->flags & SCSI_DATA_IN) 1231 dmaflags |= DMAGO_READ; 1232 1233 if (count > MAXPHYS) 1234 printf("sbicgo: bp->b_bcount > MAXPHYS %08x\n", count); 1235 1236 if (dev->sc_flags & SBICF_BADDMA && 1237 sbiccheckdmap(addr, count, dev->sc_dmamask)) { 1238 /* 1239 * need to bounce the dma. 1240 */ 1241 if (dmaflags & DMAGO_READ) { 1242 dev->sc_flags |= SBICF_BBUF; 1243 dev->sc_dmausrbuf = addr; 1244 dev->sc_dmausrlen = count; 1245 } else { /* write: copy to dma buffer */ 1246 bcopy (addr, dev->sc_dmabuffer, count); 1247 } 1248 addr = dev->sc_dmabuffer; /* and use dma buffer */ 1249 } 1250 1251 #ifdef DEBUG 1252 if (sbic_dma_debug & DDB_FOLLOW) 1253 printf("sbicgo(%d, %x, %x, %x)\n", dev->sc_dev.dv_unit, 1254 addr, count, dmaflags); 1255 #endif 1256 /* 1257 * Build the DMA chain 1258 */ 1259 for (dcp = dev->sc_chain; count > 0; dcp++) { 1260 dcp->dc_addr = (char *) kvtop(addr); 1261 if (count < (tcount = NBPG - ((int)addr & PGOFSET))) 1262 tcount = count; 1263 addr += tcount; 1264 count -= tcount; 1265 dcp->dc_count = tcount >> 1; 1266 1267 /* 1268 * check if contigous, if not mark new end 1269 * else increment end and count on previous. 1270 */ 1271 if (dcp->dc_addr != dmaend) 1272 dmaend = dcp->dc_addr + tcount; 1273 else { 1274 dcp--; 1275 dmaend += tcount; 1276 dcp->dc_count += tcount >> 1; 1277 } 1278 } 1279 1280 dev->sc_cur = dev->sc_chain; 1281 dev->sc_last = --dcp; 1282 dev->sc_tcnt = dev->sc_cur->dc_count << 1; 1283 1284 #ifdef DEBUG 1285 if (sbic_dma_debug & DDB_IO) { 1286 for (dcp = dev->sc_chain; dcp <= dev->sc_last; dcp++) 1287 printf(" %d: %d@%x\n", dcp-dev->sc_chain, 1288 dcp->dc_count, dcp->dc_addr); 1289 } 1290 #endif 1291 1292 /* 1293 * push the data cash 1294 */ 1295 DCIS(); 1296 1297 /* 1298 * dmago() also enables interrupts for the sbic 1299 */ 1300 i = dev->sc_dmago(dev, addr, xs->datalen, dmaflags); 1301 1302 SBIC_TC_PUT(regs, (unsigned)i); 1303 SET_SBIC_cmd(regs, SBIC_CMD_XFER_INFO); 1304 1305 return(0); 1306 1307 abort: 1308 sbicabort(dev, regs, "go"); 1309 dev->sc_dmafree(dev); 1310 return(-1); 1311 } 1312 1313 1314 int 1315 sbicintr(dev) 1316 struct sbic_softc *dev; 1317 { 1318 sbic_regmap_p regs; 1319 u_char asr, csr; 1320 int i; 1321 1322 regs = dev->sc_sbicp; 1323 1324 /* 1325 * pending interrupt? 1326 */ 1327 GET_SBIC_asr (regs, asr); 1328 if ((asr & SBIC_ASR_INT) == 0) 1329 return(0); 1330 1331 GET_SBIC_csr(regs, csr); 1332 QPRINTF(("[0x%x]", csr)); 1333 1334 if (csr == (SBIC_CSR_XFERRED|STATUS_PHASE) 1335 || csr == (SBIC_CSR_MIS|STATUS_PHASE) 1336 || csr == (SBIC_CSR_MIS_1|STATUS_PHASE) 1337 || csr == (SBIC_CSR_MIS_2|STATUS_PHASE)) { 1338 /* 1339 * this should be the normal i/o completion case. 1340 * get the status & cmd complete msg then let the 1341 * device driver look at what happened. 1342 */ 1343 sbicxfdone(dev, regs, dev->sc_xs->sc_link->target); 1344 if (dev->sc_flags & SBICF_BBUF) 1345 bcopy(dev->sc_dmabuffer, dev->sc_dmausrbuf, 1346 dev->sc_dmausrlen); 1347 dev->sc_flags &= ~(SBICF_INDMA | SBICF_BBUF); 1348 dev->sc_dmafree(dev); 1349 sbic_scsidone(dev, dev->sc_stat[0]); 1350 } else if (csr == (SBIC_CSR_XFERRED|DATA_OUT_PHASE) 1351 || csr == (SBIC_CSR_XFERRED|DATA_IN_PHASE) 1352 || csr == (SBIC_CSR_MIS|DATA_OUT_PHASE) 1353 || csr == (SBIC_CSR_MIS|DATA_IN_PHASE) 1354 || csr == (SBIC_CSR_MIS_1|DATA_OUT_PHASE) 1355 || csr == (SBIC_CSR_MIS_1|DATA_IN_PHASE) 1356 || csr == (SBIC_CSR_MIS_2|DATA_OUT_PHASE) 1357 || csr == (SBIC_CSR_MIS_2|DATA_IN_PHASE)) { 1358 /* 1359 * do scatter-gather dma 1360 * hacking the controller chip, ouch.. 1361 */ 1362 /* 1363 * set next dma addr and dec count 1364 */ 1365 dev->sc_cur->dc_addr += dev->sc_tcnt; 1366 dev->sc_cur->dc_count -= (dev->sc_tcnt >> 1); 1367 1368 if (dev->sc_cur->dc_count == 0) 1369 ++dev->sc_cur; /* advance to next segment */ 1370 1371 i = dev->sc_dmanext(dev); 1372 SBIC_TC_PUT(regs, (unsigned)i); 1373 SET_SBIC_cmd(regs, SBIC_CMD_XFER_INFO); 1374 } else { 1375 /* 1376 * Something unexpected happened -- deal with it. 1377 */ 1378 dev->sc_dmastop(dev); 1379 sbicerror(dev, regs, csr); 1380 sbicabort(dev, regs, "intr"); 1381 if (dev->sc_flags & SBICF_INDMA) { 1382 dev->sc_flags &= ~(SBICF_INDMA | SBICF_BBUF); 1383 dev->sc_dmafree(dev); 1384 sbic_scsidone(dev, -1); 1385 } 1386 } 1387 return(1); 1388 } 1389 1390 /* 1391 * Check if DMA can not be used with specified buffer 1392 */ 1393 1394 int 1395 sbiccheckdmap(bp, len, mask) 1396 void *bp; 1397 u_long len, mask; 1398 { 1399 u_char *buffer; 1400 u_long phy_buf; 1401 u_long phy_len; 1402 1403 buffer = bp; 1404 1405 if (len == 0) 1406 return(0); 1407 1408 while (len) { 1409 phy_buf = kvtop(buffer); 1410 if (len < (phy_len = NBPG - ((int) buffer & PGOFSET))) 1411 phy_len = len; 1412 if (phy_buf & mask) 1413 return(1); 1414 buffer += phy_len; 1415 len -= phy_len; 1416 } 1417 return(0); 1418 } 1419 1420 int 1421 sbictoscsiperiod(dev, regs, a) 1422 struct sbic_softc *dev; 1423 sbic_regmap_p regs; 1424 int a; 1425 { 1426 unsigned int fs; 1427 1428 /* 1429 * cycle = DIV / (2*CLK) 1430 * DIV = FS+2 1431 * best we can do is 200ns at 20Mhz, 2 cycles 1432 */ 1433 1434 GET_SBIC_myid(regs,fs); 1435 fs = (fs >>6) + 2; /* DIV */ 1436 fs = (fs * 10000) / (dev->sc_clkfreq<<1); /* Cycle, in ns */ 1437 if (a < 2) a = 8; /* map to Cycles */ 1438 return ((fs*a)>>2); /* in 4 ns units */ 1439 } 1440 1441 int 1442 sbicfromscsiperiod(dev, regs, p) 1443 struct sbic_softc *dev; 1444 sbic_regmap_p regs; 1445 int p; 1446 { 1447 register unsigned int fs, ret; 1448 1449 /* Just the inverse of the above */ 1450 1451 GET_SBIC_myid(regs,fs); 1452 fs = (fs >>6) + 2; /* DIV */ 1453 fs = (fs * 10000) / (dev->sc_clkfreq<<1); /* Cycle, in ns */ 1454 1455 ret = p << 2; /* in ns units */ 1456 ret = ret / fs; /* in Cycles */ 1457 if (ret < sbic_min_period) 1458 return(sbic_min_period); 1459 1460 /* verify rounding */ 1461 if (sbictoscsiperiod(dev, regs, ret) < p) 1462 ret++; 1463 return (ret >= 8) ? 0 : ret; 1464 } 1465 1466
Indexes created Fri Sep 26 20:09:58 GMT 2025