sbic.c revision 1.22
1 /* $NetBSD: sbic.c,v 1.22 1996/03/23 15:09:54 is Exp $ */ 2 3 /* 4 * Copyright (c) 1994 Christian E. Hopps 5 * Copyright (c) 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * Van Jacobson of Lawrence Berkeley Laboratory. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the University of 22 * California, Berkeley and its contributors. 23 * 4. Neither the name of the University nor the names of its contributors 24 * may be used to endorse or promote products derived from this software 25 * without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 37 * SUCH DAMAGE. 38 * 39 * @(#)scsi.c 7.5 (Berkeley) 5/4/91 40 */ 41 42 /* 43 * AMIGA AMD 33C93 scsi adaptor driver 44 */ 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/device.h> 49 #include <sys/kernel.h> /* For hz */ 50 #include <sys/disklabel.h> 51 #include <sys/dkstat.h> 52 #include <sys/buf.h> 53 #include <scsi/scsi_all.h> 54 #include <scsi/scsiconf.h> 55 #include <vm/vm.h> 56 #include <vm/vm_kern.h> 57 #include <vm/vm_page.h> 58 #include <machine/pmap.h> 59 #include <machine/cpu.h> 60 #include <amiga/amiga/device.h> 61 #include <amiga/amiga/custom.h> 62 #include <amiga/amiga/isr.h> 63 #include <amiga/dev/dmavar.h> 64 #include <amiga/dev/sbicreg.h> 65 #include <amiga/dev/sbicvar.h> 66 67 /* These are for bounce buffers */ 68 #include <amiga/amiga/cc.h> 69 #include <amiga/dev/zbusvar.h> 70 71 #include <vm/pmap.h> 72 73 /* Since I can't find this in any other header files */ 74 #define SCSI_PHASE(reg) (reg&0x07) 75 76 /* 77 * SCSI delays 78 * In u-seconds, primarily for state changes on the SPC. 79 */ 80 #define SBIC_CMD_WAIT 50000 /* wait per step of 'immediate' cmds */ 81 #define SBIC_DATA_WAIT 50000 /* wait per data in/out step */ 82 #define SBIC_INIT_WAIT 50000 /* wait per step (both) during init */ 83 84 #define b_cylin b_resid 85 #define SBIC_WAIT(regs, until, timeo) sbicwait(regs, until, timeo, __LINE__) 86 87 extern u_int kvtop(); 88 89 int sbicicmd __P((struct sbic_softc *, int, int, void *, int, void *, int)); 90 int sbicgo __P((struct sbic_softc *, struct scsi_xfer *)); 91 int sbicdmaok __P((struct sbic_softc *, struct scsi_xfer *)); 92 int sbicwait __P((sbic_regmap_p, char, int , int)); 93 int sbiccheckdmap __P((void *, u_long, u_long)); 94 int sbicselectbus __P((struct sbic_softc *, sbic_regmap_p, u_char, u_char, u_char)); 95 int sbicxfstart __P((sbic_regmap_p, int, u_char, int)); 96 int sbicxfout __P((sbic_regmap_p regs, int, void *, int)); 97 int sbicfromscsiperiod __P((struct sbic_softc *, sbic_regmap_p, int)); 98 int sbictoscsiperiod __P((struct sbic_softc *, sbic_regmap_p, int)); 99 int sbicintr __P((struct sbic_softc *)); 100 int sbicpoll __P((struct sbic_softc *)); 101 int sbicnextstate __P((struct sbic_softc *, u_char, u_char)); 102 int sbicmsgin __P((struct sbic_softc *)); 103 int sbicxfin __P((sbic_regmap_p regs, int, void *)); 104 int sbicabort __P((struct sbic_softc *, sbic_regmap_p, char *)); 105 void sbicxfdone __P((struct sbic_softc *, sbic_regmap_p, int)); 106 void sbicerror __P((struct sbic_softc *, sbic_regmap_p, u_char)); 107 void sbicstart __P((struct sbic_softc *)); 108 void sbicreset __P((struct sbic_softc *)); 109 void sbic_scsidone __P((struct sbic_acb *, int)); 110 void sbic_sched __P((struct sbic_softc *)); 111 void sbic_save_ptrs __P((struct sbic_softc *, sbic_regmap_p,int,int)); 112 void sbic_load_ptrs __P((struct sbic_softc *, sbic_regmap_p,int,int)); 113 114 /* 115 * Synch xfer parameters, and timing conversions 116 */ 117 int sbic_min_period = SBIC_SYN_MIN_PERIOD; /* in cycles = f(ICLK,FSn) */ 118 int sbic_max_offset = SBIC_SYN_MAX_OFFSET; /* pure number */ 119 120 int sbic_cmd_wait = SBIC_CMD_WAIT; 121 int sbic_data_wait = SBIC_DATA_WAIT; 122 int sbic_init_wait = SBIC_INIT_WAIT; 123 124 /* 125 * was broken before.. now if you want this you get it for all drives 126 * on sbic controllers. 127 */ 128 u_char sbic_inhibit_sync[8]; 129 int sbic_enable_reselect = 1; 130 int sbic_clock_override = 0; 131 int sbic_no_dma = 0; 132 int sbic_parallel_operations = 1; 133 134 #ifdef DEBUG 135 sbic_regmap_p debug_sbic_regs; 136 int sbicdma_ops = 0; /* total DMA operations */ 137 int sbicdma_bounces = 0; /* number operations using bounce buffer */ 138 int sbicdma_hits = 0; /* number of DMA chains that were contiguous */ 139 int sbicdma_misses = 0; /* number of DMA chains that were not contiguous */ 140 int sbicdma_saves = 0; 141 #define QPRINTF(a) if (sbic_debug > 1) printf a 142 int sbic_debug = 0; 143 int sync_debug = 0; 144 int sbic_dma_debug = 0; 145 int reselect_debug = 0; 146 int report_sense = 0; 147 int data_pointer_debug = 0; 148 u_char debug_asr, debug_csr, routine; 149 void sbictimeout __P((struct sbic_softc *dev)); 150 void sbic_dump __P((struct sbic_softc *dev)); 151 152 #define CSR_TRACE_SIZE 32 153 #if CSR_TRACE_SIZE 154 #define CSR_TRACE(w,c,a,x) do { \ 155 int s = splbio(); \ 156 csr_trace[csr_traceptr].whr = (w); csr_trace[csr_traceptr].csr = (c); \ 157 csr_trace[csr_traceptr].asr = (a); csr_trace[csr_traceptr].xtn = (x); \ 158 dma_cachectl(&csr_trace[csr_traceptr], sizeof(csr_trace[0])); \ 159 csr_traceptr = (csr_traceptr + 1) & (CSR_TRACE_SIZE - 1); \ 160 /* dma_cachectl(&csr_traceptr, sizeof(csr_traceptr));*/ \ 161 splx(s); \ 162 } while (0) 163 int csr_traceptr; 164 int csr_tracesize = CSR_TRACE_SIZE; 165 struct { 166 u_char whr; 167 u_char csr; 168 u_char asr; 169 u_char xtn; 170 } csr_trace[CSR_TRACE_SIZE]; 171 #else 172 #define CSR_TRACE 173 #endif 174 175 #define SBIC_TRACE_SIZE 0 176 #if SBIC_TRACE_SIZE 177 #define SBIC_TRACE(dev) do { \ 178 int s = splbio(); \ 179 sbic_trace[sbic_traceptr].sp = &s; \ 180 sbic_trace[sbic_traceptr].line = __LINE__; \ 181 sbic_trace[sbic_traceptr].sr = s; \ 182 sbic_trace[sbic_traceptr].csr = csr_traceptr; \ 183 dma_cachectl(&sbic_trace[sbic_traceptr], sizeof(sbic_trace[0])); \ 184 sbic_traceptr = (sbic_traceptr + 1) & (SBIC_TRACE_SIZE - 1); \ 185 dma_cachectl(&sbic_traceptr, sizeof(sbic_traceptr)); \ 186 if (dev) dma_cachectl(dev, sizeof(*dev)); \ 187 splx(s); \ 188 } while (0) 189 int sbic_traceptr; 190 int sbic_tracesize = SBIC_TRACE_SIZE; 191 struct { 192 void *sp; 193 u_short line; 194 u_short sr; 195 int csr; 196 } sbic_trace[SBIC_TRACE_SIZE]; 197 #else 198 #define SBIC_TRACE 199 #endif 200 201 #else 202 #define QPRINTF 203 #define CSR_TRACE 204 #define SBIC_TRACE 205 #endif 206 207 /* 208 * default minphys routine for sbic based controllers 209 */ 210 void 211 sbic_minphys(bp) 212 struct buf *bp; 213 { 214 215 /* 216 * No max transfer at this level. 217 */ 218 minphys(bp); 219 } 220 221 /* 222 * Save DMA pointers. Take into account partial transfer. Shut down DMA. 223 */ 224 void 225 sbic_save_ptrs(dev, regs, target, lun) 226 struct sbic_softc *dev; 227 sbic_regmap_p regs; 228 int target, lun; 229 { 230 int count, asr, csr, s; 231 unsigned long ptr; 232 char *vptr; 233 struct sbic_acb* acb; 234 235 extern vm_offset_t vm_first_phys; 236 237 SBIC_TRACE(dev); 238 if( !dev->sc_cur ) return; 239 if( !(dev->sc_flags & SBICF_INDMA) ) return; /* DMA not active */ 240 241 s = splbio(); 242 243 acb = dev->sc_nexus; 244 count = -1; 245 do { 246 GET_SBIC_asr(regs, asr); 247 if( asr & SBIC_ASR_DBR ) { 248 printf("sbic_save_ptrs: asr %02x canceled!\n", asr); 249 splx(s); 250 SBIC_TRACE(dev); 251 return; 252 } 253 } while( asr & (SBIC_ASR_BSY|SBIC_ASR_CIP) ); 254 255 /* Save important state */ 256 /* must be done before dmastop */ 257 acb->sc_dmacmd = dev->sc_dmacmd; 258 SBIC_TC_GET(regs, count); 259 260 /* Shut down DMA ====CAREFUL==== */ 261 dev->sc_dmastop(dev); 262 dev->sc_flags &= ~SBICF_INDMA; 263 SBIC_TC_PUT(regs, 0); 264 265 #ifdef DEBUG 266 if(!count && sbic_debug) printf("%dcount0",target); 267 if(data_pointer_debug == -1) 268 printf("SBIC saving target %d data pointers from (%x,%x)%xASR:%02x", 269 target, dev->sc_cur->dc_addr, dev->sc_cur->dc_count, 270 acb->sc_dmacmd, asr); 271 #endif 272 273 /* Fixup partial xfers */ 274 acb->sc_kv.dc_addr += (dev->sc_tcnt - count); 275 acb->sc_kv.dc_count -= (dev->sc_tcnt - count); 276 acb->sc_pa.dc_addr += (dev->sc_tcnt - count); 277 acb->sc_pa.dc_count -= ((dev->sc_tcnt - count)>>1); 278 279 acb->sc_tcnt = dev->sc_tcnt = count; 280 #ifdef DEBUG 281 if(data_pointer_debug) 282 printf(" at (%x,%x):%x\n", 283 dev->sc_cur->dc_addr, dev->sc_cur->dc_count,count); 284 sbicdma_saves++; 285 #endif 286 splx(s); 287 SBIC_TRACE(dev); 288 } 289 290 291 /* 292 * DOES NOT RESTART DMA!!! 293 */ 294 void sbic_load_ptrs(dev, regs, target, lun) 295 struct sbic_softc *dev; 296 sbic_regmap_p regs; 297 int target, lun; 298 { 299 int i, s, asr, count; 300 char* vaddr, * paddr; 301 struct sbic_acb *acb; 302 303 SBIC_TRACE(dev); 304 acb = dev->sc_nexus; 305 if( !acb->sc_kv.dc_count ) { 306 /* No data to xfer */ 307 SBIC_TRACE(dev); 308 return; 309 } 310 311 s = splbio(); 312 313 dev->sc_last = dev->sc_cur = &acb->sc_pa; 314 dev->sc_tcnt = acb->sc_tcnt; 315 dev->sc_dmacmd = acb->sc_dmacmd; 316 317 #ifdef DEBUG 318 sbicdma_ops++; 319 #endif 320 if( !dev->sc_tcnt ) { 321 /* sc_tcnt == 0 implies end of segment */ 322 323 /* do kvm to pa mappings */ 324 paddr = acb->sc_pa.dc_addr = 325 (char *) kvtop(acb->sc_kv.dc_addr); 326 327 vaddr = acb->sc_kv.dc_addr; 328 count = acb->sc_kv.dc_count; 329 for(count = (NBPG - ((int)vaddr & PGOFSET)); 330 count < acb->sc_kv.dc_count 331 && (char*)kvtop(vaddr + count + 4) == paddr + count + 4; 332 count += NBPG); 333 /* If it's all contiguous... */ 334 if(count > acb->sc_kv.dc_count ) { 335 count = acb->sc_kv.dc_count; 336 #ifdef DEBUG 337 sbicdma_hits++; 338 #endif 339 } else { 340 #ifdef DEBUG 341 sbicdma_misses++; 342 #endif 343 } 344 acb->sc_tcnt = count; 345 acb->sc_pa.dc_count = count >> 1; 346 347 #ifdef DEBUG 348 if(data_pointer_debug) 349 printf("DMA recalc:kv(%x,%x)pa(%x,%x)\n", 350 acb->sc_kv.dc_addr, 351 acb->sc_kv.dc_count, 352 acb->sc_pa.dc_addr, 353 acb->sc_tcnt); 354 #endif 355 } 356 splx(s); 357 #ifdef DEBUG 358 if(data_pointer_debug) 359 printf("SBIC restoring target %d data pointers at (%x,%x)%x\n", 360 target, dev->sc_cur->dc_addr, dev->sc_cur->dc_count, 361 dev->sc_dmacmd); 362 #endif 363 SBIC_TRACE(dev); 364 } 365 366 /* 367 * used by specific sbic controller 368 * 369 * it appears that the higher level code does nothing with LUN's 370 * so I will too. I could plug it in, however so could they 371 * in scsi_scsi_cmd(). 372 */ 373 int 374 sbic_scsicmd(xs) 375 struct scsi_xfer *xs; 376 { 377 struct sbic_acb *acb; 378 struct sbic_softc *dev; 379 struct scsi_link *slp; 380 int flags, s, stat; 381 382 slp = xs->sc_link; 383 dev = slp->adapter_softc; 384 SBIC_TRACE(dev); 385 flags = xs->flags; 386 387 if (flags & SCSI_DATA_UIO) 388 panic("sbic: scsi data uio requested"); 389 390 if (dev->sc_nexus && flags & SCSI_POLL) 391 panic("sbic_scsicmd: busy"); 392 393 if (slp->target == slp->adapter_target) 394 return ESCAPE_NOT_SUPPORTED; 395 396 s = splbio(); 397 acb = dev->free_list.tqh_first; 398 if (acb) 399 TAILQ_REMOVE(&dev->free_list, acb, chain); 400 splx(s); 401 402 if (acb == NULL) { 403 #ifdef DEBUG 404 printf("sbic_scsicmd: unable to queue request for target %d\n", 405 slp->target); 406 #ifdef DDB 407 Debugger(); 408 #endif 409 #endif 410 xs->error = XS_DRIVER_STUFFUP; 411 SBIC_TRACE(dev); 412 return(TRY_AGAIN_LATER); 413 } 414 415 acb->flags = ACB_ACTIVE; 416 if (flags & SCSI_DATA_IN) 417 acb->flags |= ACB_DATAIN; 418 acb->xs = xs; 419 bcopy(xs->cmd, &acb->cmd, xs->cmdlen); 420 acb->clen = xs->cmdlen; 421 acb->sc_kv.dc_addr = xs->data; 422 acb->sc_kv.dc_count = xs->datalen; 423 acb->pa_addr = xs->data ? (char *)kvtop(xs->data) : 0; /* XXXX check */ 424 425 if (flags & SCSI_POLL) { 426 s = splbio(); 427 /* 428 * This has major side effects -- it locks up the machine 429 */ 430 431 dev->sc_flags |= SBICF_ICMD; 432 do { 433 while(dev->sc_nexus) 434 sbicpoll(dev); 435 dev->sc_nexus = acb; 436 dev->sc_stat[0] = -1; 437 dev->sc_xs = xs; 438 dev->target = slp->target; 439 dev->lun = slp->lun; 440 stat = sbicicmd(dev, slp->target, slp->lun, 441 &acb->cmd, acb->clen, 442 acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 443 } while (dev->sc_nexus != acb); 444 sbic_scsidone(acb, stat); 445 446 splx(s); 447 SBIC_TRACE(dev); 448 return(COMPLETE); 449 } 450 451 s = splbio(); 452 TAILQ_INSERT_TAIL(&dev->ready_list, acb, chain); 453 454 if (dev->sc_nexus) { 455 splx(s); 456 SBIC_TRACE(dev); 457 return(SUCCESSFULLY_QUEUED); 458 } 459 460 /* 461 * nothing is active, try to start it now. 462 */ 463 sbic_sched(dev); 464 splx(s); 465 466 SBIC_TRACE(dev); 467 /* TODO: add sbic_poll to do SCSI_POLL operations */ 468 #if 0 469 if (flags & SCSI_POLL) 470 return(COMPLETE); 471 #endif 472 return(SUCCESSFULLY_QUEUED); 473 } 474 475 /* 476 * attempt to start the next available command 477 */ 478 void 479 sbic_sched(dev) 480 struct sbic_softc *dev; 481 { 482 struct scsi_xfer *xs; 483 struct scsi_link *slp; 484 struct sbic_acb *acb; 485 int flags, /*phase,*/ stat, i; 486 487 SBIC_TRACE(dev); 488 if (dev->sc_nexus) 489 return; /* a command is current active */ 490 491 SBIC_TRACE(dev); 492 for (acb = dev->ready_list.tqh_first; acb; acb = acb->chain.tqe_next) { 493 slp = acb->xs->sc_link; 494 i = slp->target; 495 if (!(dev->sc_tinfo[i].lubusy & (1 << slp->lun))) { 496 struct sbic_tinfo *ti = &dev->sc_tinfo[i]; 497 498 TAILQ_REMOVE(&dev->ready_list, acb, chain); 499 dev->sc_nexus = acb; 500 slp = acb->xs->sc_link; 501 ti = &dev->sc_tinfo[slp->target]; 502 ti->lubusy |= (1 << slp->lun); 503 acb->sc_pa.dc_addr = acb->pa_addr; /* XXXX check */ 504 break; 505 } 506 } 507 508 SBIC_TRACE(dev); 509 if (acb == NULL) 510 return; /* did not find an available command */ 511 512 dev->sc_xs = xs = acb->xs; 513 slp = xs->sc_link; 514 flags = xs->flags; 515 516 if (flags & SCSI_RESET) 517 sbicreset(dev); 518 519 #ifdef DEBUG 520 if( data_pointer_debug > 1 ) 521 printf("sbic_sched(%d,%d)\n",slp->target,slp->lun); 522 #endif 523 dev->sc_stat[0] = -1; 524 dev->target = slp->target; 525 dev->lun = slp->lun; 526 if ( flags & SCSI_POLL || ( !sbic_parallel_operations 527 && (/*phase == STATUS_PHASE ||*/ 528 sbicdmaok(dev, xs) == 0) ) ) 529 stat = sbicicmd(dev, slp->target, slp->lun, &acb->cmd, 530 acb->clen, acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 531 else if (sbicgo(dev, xs) == 0) { 532 SBIC_TRACE(dev); 533 return; 534 } else 535 stat = dev->sc_stat[0]; 536 537 sbic_scsidone(acb, stat); 538 SBIC_TRACE(dev); 539 } 540 541 void 542 sbic_scsidone(acb, stat) 543 struct sbic_acb *acb; 544 int stat; 545 { 546 struct scsi_xfer *xs; 547 struct scsi_link *slp; 548 struct sbic_softc *dev; 549 int s, dosched = 0; 550 551 xs = acb->xs; 552 slp = xs->sc_link; 553 dev = slp->adapter_softc; 554 SBIC_TRACE(dev); 555 #ifdef DIAGNOSTIC 556 if (acb == NULL || xs == NULL) { 557 printf("sbic_scsidone -- (%d,%d) no scsi_xfer\n", 558 dev->target, dev->lun); 559 #ifdef DDB 560 Debugger(); 561 #endif 562 return; 563 } 564 #endif 565 /* 566 * XXX Support old-style instrumentation for now. 567 * IS THIS REALLY THE RIGHT PLACE FOR THIS? --thorpej 568 */ 569 if (slp->device_softc && 570 ((struct device *)(slp->device_softc))->dv_unit < dk_ndrive) 571 ++dk_xfer[((struct device *)(slp->device_softc))->dv_unit]; 572 /* 573 * is this right? 574 */ 575 xs->status = stat; 576 577 #ifdef DEBUG 578 if( data_pointer_debug > 1 ) 579 printf("scsidone: (%d,%d)->(%d,%d)%02x\n", 580 slp->target, slp->lun, 581 dev->target, dev->lun, stat); 582 if( xs->sc_link->target == dev->sc_link.adapter_target ) 583 panic("target == hostid"); 584 #endif 585 586 if (xs->error == XS_NOERROR && !(acb->flags & ACB_CHKSENSE)) { 587 if (stat == SCSI_CHECK) { 588 /* Schedule a REQUEST SENSE */ 589 struct scsi_sense *ss = (void *)&acb->cmd; 590 #ifdef DEBUG 591 if (report_sense) 592 printf("sbic_scsidone: autosense %02x targ %d lun %d", 593 acb->cmd.opcode, slp->target, slp->lun); 594 #endif 595 bzero(ss, sizeof(*ss)); 596 ss->opcode = REQUEST_SENSE; 597 ss->byte2 = slp->lun << 5; 598 ss->length = sizeof(struct scsi_sense_data); 599 acb->clen = sizeof(*ss); 600 acb->sc_kv.dc_addr = (char *)&xs->sense; 601 acb->sc_kv.dc_count = sizeof(struct scsi_sense_data); 602 acb->pa_addr = (char *)kvtop(&xs->sense); /* XXX check */ 603 acb->flags = ACB_ACTIVE | ACB_CHKSENSE | ACB_DATAIN; 604 TAILQ_INSERT_HEAD(&dev->ready_list, acb, chain); 605 dev->sc_tinfo[slp->target].lubusy &= 606 ~(1 << slp->lun); 607 dev->sc_tinfo[slp->target].senses++; 608 if (dev->sc_nexus == acb) { 609 dev->sc_nexus = NULL; 610 dev->sc_xs = NULL; 611 sbic_sched(dev); 612 } 613 SBIC_TRACE(dev); 614 return; 615 } 616 } 617 if (xs->error == XS_NOERROR && (acb->flags & ACB_CHKSENSE)) { 618 xs->error = XS_SENSE; 619 #ifdef DEBUG 620 if (report_sense) 621 printf(" => %02x %02x\n", xs->sense.flags, 622 xs->sense.extra_bytes[3]); 623 #endif 624 } else { 625 xs->resid = 0; /* XXXX */ 626 } 627 #if whataboutthisone 628 case SCSI_BUSY: 629 xs->error = XS_BUSY; 630 break; 631 #endif 632 xs->flags |= ITSDONE; 633 634 /* 635 * Remove the ACB from whatever queue it's on. We have to do a bit of 636 * a hack to figure out which queue it's on. Note that it is *not* 637 * necessary to cdr down the ready queue, but we must cdr down the 638 * nexus queue and see if it's there, so we can mark the unit as no 639 * longer busy. This code is sickening, but it works. 640 */ 641 if (acb == dev->sc_nexus) { 642 dev->sc_nexus = NULL; 643 dev->sc_xs = NULL; 644 dev->sc_tinfo[slp->target].lubusy &= ~(1<<slp->lun); 645 if (dev->ready_list.tqh_first) 646 dosched = 1; /* start next command */ 647 } else if (dev->ready_list.tqh_last == &acb->chain.tqe_next) { 648 TAILQ_REMOVE(&dev->ready_list, acb, chain); 649 } else { 650 register struct sbic_acb *acb2; 651 for (acb2 = dev->nexus_list.tqh_first; acb2; 652 acb2 = acb2->chain.tqe_next) { 653 if (acb2 == acb) { 654 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 655 dev->sc_tinfo[slp->target].lubusy 656 &= ~(1<<slp->lun); 657 break; 658 } 659 } 660 if (acb2) 661 ; 662 else if (acb->chain.tqe_next) { 663 TAILQ_REMOVE(&dev->ready_list, acb, chain); 664 } else { 665 printf("%s: can't find matching acb\n", 666 dev->sc_dev.dv_xname); 667 #ifdef DDB 668 Debugger(); 669 #endif 670 } 671 } 672 /* Put it on the free list. */ 673 acb->flags = ACB_FREE; 674 TAILQ_INSERT_HEAD(&dev->free_list, acb, chain); 675 676 dev->sc_tinfo[slp->target].cmds++; 677 678 scsi_done(xs); 679 680 if (dosched) 681 sbic_sched(dev); 682 SBIC_TRACE(dev); 683 } 684 685 int 686 sbicdmaok(dev, xs) 687 struct sbic_softc *dev; 688 struct scsi_xfer *xs; 689 { 690 if (sbic_no_dma || xs->datalen & 0x1 || (u_int)xs->data & 0x3) 691 return(0); 692 /* 693 * controller supports dma to any addresses? 694 */ 695 else if ((dev->sc_flags & SBICF_BADDMA) == 0) 696 return(1); 697 /* 698 * this address is ok for dma? 699 */ 700 else if (sbiccheckdmap(xs->data, xs->datalen, dev->sc_dmamask) == 0) 701 return(1); 702 /* 703 * we have a bounce buffer? 704 */ 705 else if (dev->sc_tinfo[xs->sc_link->target].bounce) 706 return(1); 707 /* 708 * try to get one 709 */ 710 else if (dev->sc_tinfo[xs->sc_link->target].bounce 711 = (char *)alloc_z2mem(MAXPHYS)) { 712 if (isztwomem(dev->sc_tinfo[xs->sc_link->target].bounce)) 713 printf("alloc ZII target %d bounce pa 0x%x\n", 714 xs->sc_link->target, 715 kvtop(dev->sc_tinfo[xs->sc_link->target].bounce)); 716 else if (dev->sc_tinfo[xs->sc_link->target].bounce) 717 printf("alloc CHIP target %d bounce pa 0x%x\n", 718 xs->sc_link->target, 719 PREP_DMA_MEM(dev->sc_tinfo[xs->sc_link->target].bounce)); 720 return(1); 721 } 722 723 return(0); 724 } 725 726 727 int 728 sbicwait(regs, until, timeo, line) 729 sbic_regmap_p regs; 730 char until; 731 int timeo; 732 int line; 733 { 734 u_char val; 735 int csr; 736 737 SBIC_TRACE((struct sbic_softc *)0); 738 if (timeo == 0) 739 timeo = 1000000; /* some large value.. */ 740 741 GET_SBIC_asr(regs,val); 742 while ((val & until) == 0) { 743 if (timeo-- == 0) { 744 GET_SBIC_csr(regs, csr); 745 printf("sbicwait TIMEO @%d with asr=x%x csr=x%x\n", 746 line, val, csr); 747 #if defined(DDB) && defined(DEBUG) 748 Debugger(); 749 #endif 750 return(val); /* Maybe I should abort */ 751 break; 752 } 753 DELAY(1); 754 GET_SBIC_asr(regs,val); 755 } 756 SBIC_TRACE((struct sbic_softc *)0); 757 return(val); 758 } 759 760 int 761 sbicabort(dev, regs, where) 762 struct sbic_softc *dev; 763 sbic_regmap_p regs; 764 char *where; 765 { 766 u_char csr, asr; 767 768 GET_SBIC_asr(regs, asr); 769 GET_SBIC_csr(regs, csr); 770 771 printf ("%s: abort %s: csr = 0x%02x, asr = 0x%02x\n", 772 dev->sc_dev.dv_xname, where, csr, asr); 773 774 775 #if 0 776 /* Clean up running command */ 777 if (dev->sc_nexus != NULL) { 778 dev->sc_nexus->xs->error = XS_DRIVER_STUFFUP; 779 sbic_scsidone(dev->sc_nexus, dev->sc_stat[0]); 780 } 781 while (acb = dev->nexus_list.tqh_first) { 782 acb->xs->error = XS_DRIVER_STUFFUP; 783 sbic_scsidone(acb, -1 /*acb->stat[0]*/); 784 } 785 #endif 786 787 /* Clean up chip itself */ 788 if (dev->sc_flags & SBICF_SELECTED) { 789 while( asr & SBIC_ASR_DBR ) { 790 /* sbic is jammed w/data. need to clear it */ 791 /* But we don't know what direction it needs to go */ 792 GET_SBIC_data(regs, asr); 793 printf("%s: abort %s: clearing data buffer 0x%02x\n", 794 dev->sc_dev.dv_xname, where, asr); 795 GET_SBIC_asr(regs, asr); 796 if( asr & SBIC_ASR_DBR ) /* Not the read direction, then */ 797 SET_SBIC_data(regs, asr); 798 GET_SBIC_asr(regs, asr); 799 } 800 WAIT_CIP(regs); 801 printf("%s: sbicabort - sending ABORT command\n", dev->sc_dev.dv_xname); 802 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 803 WAIT_CIP(regs); 804 805 GET_SBIC_asr(regs, asr); 806 if (asr & (SBIC_ASR_BSY|SBIC_ASR_LCI)) { 807 /* ok, get more drastic.. */ 808 809 printf("%s: sbicabort - asr %x, trying to reset\n", dev->sc_dev.dv_xname, asr); 810 sbicreset(dev); 811 dev->sc_flags &= ~SBICF_SELECTED; 812 return -1; 813 } 814 printf("%s: sbicabort - sending DISC command\n", dev->sc_dev.dv_xname); 815 SET_SBIC_cmd(regs, SBIC_CMD_DISC); 816 817 do { 818 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0); 819 GET_SBIC_csr (regs, csr); 820 CSR_TRACE('a',csr,asr,0); 821 } while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) 822 && (csr != SBIC_CSR_CMD_INVALID)); 823 824 /* lets just hope it worked.. */ 825 dev->sc_flags &= ~SBICF_SELECTED; 826 } 827 return -1; 828 } 829 830 831 /* 832 * Initialize driver-private structures 833 */ 834 835 void 836 sbicinit(dev) 837 struct sbic_softc *dev; 838 { 839 sbic_regmap_p regs; 840 u_int my_id, i, s; 841 u_char csr; 842 struct sbic_acb *acb; 843 u_int inhibit_sync; 844 845 extern u_long scsi_nosync; 846 extern int shift_nosync; 847 848 regs = dev->sc_sbicp; 849 850 if ((dev->sc_flags & SBICF_ALIVE) == 0) { 851 TAILQ_INIT(&dev->ready_list); 852 TAILQ_INIT(&dev->nexus_list); 853 TAILQ_INIT(&dev->free_list); 854 dev->sc_nexus = NULL; 855 dev->sc_xs = NULL; 856 acb = dev->sc_acb; 857 bzero(acb, sizeof(dev->sc_acb)); 858 for (i = 0; i < sizeof(dev->sc_acb) / sizeof(*acb); i++) { 859 TAILQ_INSERT_TAIL(&dev->free_list, acb, chain); 860 acb++; 861 } 862 bzero(dev->sc_tinfo, sizeof(dev->sc_tinfo)); 863 #ifdef DEBUG 864 /* make sure timeout is really not needed */ 865 timeout((void *)sbictimeout, dev, 30 * hz); 866 #endif 867 868 } else panic("sbic: reinitializing driver!"); 869 870 dev->sc_flags |= SBICF_ALIVE; 871 dev->sc_flags &= ~SBICF_SELECTED; 872 873 /* initialize inhibit array */ 874 if (scsi_nosync) { 875 inhibit_sync = (scsi_nosync >> shift_nosync) & 0xff; 876 shift_nosync += 8; 877 #ifdef DEBUG 878 if (inhibit_sync) 879 printf("%s: Inhibiting synchronous transfer %02x\n", 880 dev->sc_dev.dv_xname, inhibit_sync); 881 #endif 882 for (i = 0; i < 8; ++i) 883 if (inhibit_sync & (1 << i)) 884 sbic_inhibit_sync[i] = 1; 885 } 886 887 sbicreset(dev); 888 } 889 890 void 891 sbicreset(dev) 892 struct sbic_softc *dev; 893 { 894 sbic_regmap_p regs; 895 u_int my_id, i, s; 896 u_char csr; 897 struct sbic_acb *acb; 898 899 regs = dev->sc_sbicp; 900 #if 0 901 if (dev->sc_flags & SBICF_ALIVE) { 902 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 903 WAIT_CIP(regs); 904 } 905 #else 906 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 907 WAIT_CIP(regs); 908 #endif 909 s = splbio(); 910 my_id = dev->sc_link.adapter_target & SBIC_ID_MASK; 911 912 /* Enable advanced mode */ 913 my_id |= SBIC_ID_EAF /*| SBIC_ID_EHP*/ ; 914 SET_SBIC_myid(regs, my_id); 915 916 /* 917 * Disable interrupts (in dmainit) then reset the chip 918 */ 919 SET_SBIC_cmd(regs, SBIC_CMD_RESET); 920 DELAY(25); 921 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 922 GET_SBIC_csr(regs, csr); /* clears interrupt also */ 923 924 if (dev->sc_clkfreq < 110) 925 my_id |= SBIC_ID_FS_8_10; 926 else if (dev->sc_clkfreq < 160) 927 my_id |= SBIC_ID_FS_12_15; 928 else if (dev->sc_clkfreq < 210) 929 my_id |= SBIC_ID_FS_16_20; 930 931 SET_SBIC_myid(regs, my_id); 932 933 /* 934 * Set up various chip parameters 935 */ 936 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI /* | SBIC_CTL_HSP */ 937 | SBIC_MACHINE_DMA_MODE); 938 /* 939 * don't allow (re)selection (SBIC_RID_ES) 940 * until we can handle target mode!! 941 */ 942 SET_SBIC_rselid(regs, SBIC_RID_ER); 943 SET_SBIC_syn(regs, 0); /* asynch for now */ 944 945 /* 946 * anything else was zeroed by reset 947 */ 948 splx(s); 949 950 #if 0 951 if ((dev->sc_flags & SBICF_ALIVE) == 0) { 952 TAILQ_INIT(&dev->ready_list); 953 TAILQ_INIT(&dev->nexus_list); 954 TAILQ_INIT(&dev->free_list); 955 dev->sc_nexus = NULL; 956 dev->sc_xs = NULL; 957 acb = dev->sc_acb; 958 bzero(acb, sizeof(dev->sc_acb)); 959 for (i = 0; i < sizeof(dev->sc_acb) / sizeof(*acb); i++) { 960 TAILQ_INSERT_TAIL(&dev->free_list, acb, chain); 961 acb++; 962 } 963 bzero(dev->sc_tinfo, sizeof(dev->sc_tinfo)); 964 } else { 965 if (dev->sc_nexus != NULL) { 966 dev->sc_nexus->xs->error = XS_DRIVER_STUFFUP; 967 sbic_scsidone(dev->sc_nexus, dev->sc_stat[0]); 968 } 969 while (acb = dev->nexus_list.tqh_first) { 970 acb->xs->error = XS_DRIVER_STUFFUP; 971 sbic_scsidone(acb, -1 /*acb->stat[0]*/); 972 } 973 } 974 975 dev->sc_flags |= SBICF_ALIVE; 976 #endif 977 dev->sc_flags &= ~SBICF_SELECTED; 978 } 979 980 void 981 sbicerror(dev, regs, csr) 982 struct sbic_softc *dev; 983 sbic_regmap_p regs; 984 u_char csr; 985 { 986 struct scsi_xfer *xs; 987 988 xs = dev->sc_xs; 989 990 #ifdef DIAGNOSTIC 991 if (xs == NULL) 992 panic("sbicerror"); 993 #endif 994 if (xs->flags & SCSI_SILENT) 995 return; 996 997 printf("%s: ", dev->sc_dev.dv_xname); 998 printf("csr == 0x%02x\n", csr); /* XXX */ 999 } 1000 1001 /* 1002 * select the bus, return when selected or error. 1003 */ 1004 int 1005 sbicselectbus(dev, regs, target, lun, our_addr) 1006 struct sbic_softc *dev; 1007 sbic_regmap_p regs; 1008 u_char target, lun, our_addr; 1009 { 1010 u_char asr, csr, id; 1011 1012 SBIC_TRACE(dev); 1013 QPRINTF(("sbicselectbus %d\n", target)); 1014 1015 /* 1016 * if we're already selected, return (XXXX panic maybe?) 1017 */ 1018 if (dev->sc_flags & SBICF_SELECTED) { 1019 SBIC_TRACE(dev); 1020 return(1); 1021 } 1022 1023 /* 1024 * issue select 1025 */ 1026 SBIC_TC_PUT(regs, 0); 1027 SET_SBIC_selid(regs, target); 1028 SET_SBIC_timeo(regs, SBIC_TIMEOUT(250,dev->sc_clkfreq)); 1029 1030 /* 1031 * set sync or async 1032 */ 1033 if (dev->sc_sync[target].state == SYNC_DONE) 1034 SET_SBIC_syn(regs, SBIC_SYN (dev->sc_sync[target].offset, 1035 dev->sc_sync[target].period)); 1036 else 1037 SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period)); 1038 1039 GET_SBIC_asr(regs, asr); 1040 if( asr & (SBIC_ASR_INT|SBIC_ASR_BSY) ) { 1041 /* This means we got ourselves reselected upon */ 1042 /* printf("sbicselectbus: INT/BSY asr %02x\n", asr);*/ 1043 #ifdef DDB 1044 /* Debugger();*/ 1045 #endif 1046 SBIC_TRACE(dev); 1047 return 1; 1048 } 1049 1050 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN); 1051 1052 /* 1053 * wait for select (merged from seperate function may need 1054 * cleanup) 1055 */ 1056 WAIT_CIP(regs); 1057 do { 1058 asr = SBIC_WAIT(regs, SBIC_ASR_INT | SBIC_ASR_LCI, 0); 1059 if (asr & SBIC_ASR_LCI) { 1060 #ifdef DEBUG 1061 if (reselect_debug) 1062 printf("sbicselectbus: late LCI asr %02x\n", asr); 1063 #endif 1064 SBIC_TRACE(dev); 1065 return 1; 1066 } 1067 GET_SBIC_csr (regs, csr); 1068 CSR_TRACE('s',csr,asr,target); 1069 QPRINTF(("%02x ", csr)); 1070 if( csr == SBIC_CSR_RSLT_NI || csr == SBIC_CSR_RSLT_IFY) { 1071 #ifdef DEBUG 1072 if(reselect_debug) 1073 printf("sbicselectbus: reselected asr %02x\n", asr); 1074 #endif 1075 /* We need to handle this now so we don't lock up later */ 1076 sbicnextstate(dev, csr, asr); 1077 SBIC_TRACE(dev); 1078 return 1; 1079 } 1080 if( csr == SBIC_CSR_SLT || csr == SBIC_CSR_SLT_ATN) { 1081 panic("sbicselectbus: target issued select!"); 1082 return 1; 1083 } 1084 } while (csr != (SBIC_CSR_MIS_2|MESG_OUT_PHASE) 1085 && csr != (SBIC_CSR_MIS_2|CMD_PHASE) && csr != SBIC_CSR_SEL_TIMEO); 1086 1087 /* Enable (or not) reselection */ 1088 if(!sbic_enable_reselect && dev->nexus_list.tqh_first == NULL) 1089 SET_SBIC_rselid (regs, 0); 1090 else 1091 SET_SBIC_rselid (regs, SBIC_RID_ER); 1092 1093 if (csr == (SBIC_CSR_MIS_2|CMD_PHASE)) { 1094 dev->sc_flags |= SBICF_SELECTED; /* device ignored ATN */ 1095 GET_SBIC_selid(regs, id); 1096 dev->target = id; 1097 GET_SBIC_tlun(regs,dev->lun); 1098 if( dev->lun & SBIC_TLUN_VALID ) 1099 dev->lun &= SBIC_TLUN_MASK; 1100 else 1101 dev->lun = lun; 1102 } else if (csr == (SBIC_CSR_MIS_2|MESG_OUT_PHASE)) { 1103 /* 1104 * Send identify message 1105 * (SCSI-2 requires an identify msg (?)) 1106 */ 1107 GET_SBIC_selid(regs, id); 1108 dev->target = id; 1109 GET_SBIC_tlun(regs,dev->lun); 1110 if( dev->lun & SBIC_TLUN_VALID ) 1111 dev->lun &= SBIC_TLUN_MASK; 1112 else 1113 dev->lun = lun; 1114 /* 1115 * handle drives that don't want to be asked 1116 * whether to go sync at all. 1117 */ 1118 if (sbic_inhibit_sync[id] 1119 && dev->sc_sync[id].state == SYNC_START) { 1120 #ifdef DEBUG 1121 if (sync_debug) 1122 printf("Forcing target %d asynchronous.\n", id); 1123 #endif 1124 dev->sc_sync[id].offset = 0; 1125 dev->sc_sync[id].period = sbic_min_period; 1126 dev->sc_sync[id].state = SYNC_DONE; 1127 } 1128 1129 1130 if (dev->sc_sync[id].state != SYNC_START){ 1131 if( dev->sc_xs->flags & SCSI_POLL 1132 || (dev->sc_flags & SBICF_ICMD) 1133 || !sbic_enable_reselect ) 1134 SEND_BYTE (regs, MSG_IDENTIFY | lun); 1135 else 1136 SEND_BYTE (regs, MSG_IDENTIFY_DR | lun); 1137 } else { 1138 /* 1139 * try to initiate a sync transfer. 1140 * So compose the sync message we're going 1141 * to send to the target 1142 */ 1143 1144 #ifdef DEBUG 1145 if (sync_debug) 1146 printf("Sending sync request to target %d ... ", 1147 id); 1148 #endif 1149 /* 1150 * setup scsi message sync message request 1151 */ 1152 dev->sc_msg[0] = MSG_IDENTIFY | lun; 1153 dev->sc_msg[1] = MSG_EXT_MESSAGE; 1154 dev->sc_msg[2] = 3; 1155 dev->sc_msg[3] = MSG_SYNC_REQ; 1156 dev->sc_msg[4] = sbictoscsiperiod(dev, regs, 1157 sbic_min_period); 1158 dev->sc_msg[5] = sbic_max_offset; 1159 1160 if (sbicxfstart(regs, 6, MESG_OUT_PHASE, sbic_cmd_wait)) 1161 sbicxfout(regs, 6, dev->sc_msg, MESG_OUT_PHASE); 1162 1163 dev->sc_sync[id].state = SYNC_SENT; 1164 #ifdef DEBUG 1165 if (sync_debug) 1166 printf ("sent\n"); 1167 #endif 1168 } 1169 1170 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0); 1171 GET_SBIC_csr (regs, csr); 1172 CSR_TRACE('y',csr,asr,target); 1173 QPRINTF(("[%02x]", csr)); 1174 #ifdef DEBUG 1175 if (sync_debug && dev->sc_sync[id].state == SYNC_SENT) 1176 printf("csr-result of last msgout: 0x%x\n", csr); 1177 #endif 1178 1179 if (csr != SBIC_CSR_SEL_TIMEO) 1180 dev->sc_flags |= SBICF_SELECTED; 1181 } 1182 if (csr == SBIC_CSR_SEL_TIMEO) 1183 dev->sc_xs->error = XS_SELTIMEOUT; 1184 1185 QPRINTF(("\n")); 1186 1187 SBIC_TRACE(dev); 1188 return(csr == SBIC_CSR_SEL_TIMEO); 1189 } 1190 1191 int 1192 sbicxfstart(regs, len, phase, wait) 1193 sbic_regmap_p regs; 1194 int len, wait; 1195 u_char phase; 1196 { 1197 u_char id; 1198 1199 switch (phase) { 1200 case DATA_IN_PHASE: 1201 case MESG_IN_PHASE: 1202 GET_SBIC_selid (regs, id); 1203 id |= SBIC_SID_FROM_SCSI; 1204 SET_SBIC_selid (regs, id); 1205 SBIC_TC_PUT (regs, (unsigned)len); 1206 break; 1207 case DATA_OUT_PHASE: 1208 case MESG_OUT_PHASE: 1209 case CMD_PHASE: 1210 GET_SBIC_selid (regs, id); 1211 id &= ~SBIC_SID_FROM_SCSI; 1212 SET_SBIC_selid (regs, id); 1213 SBIC_TC_PUT (regs, (unsigned)len); 1214 break; 1215 default: 1216 SBIC_TC_PUT (regs, 0); 1217 } 1218 QPRINTF(("sbicxfstart %d, %d, %d\n", len, phase, wait)); 1219 1220 return(1); 1221 } 1222 1223 int 1224 sbicxfout(regs, len, bp, phase) 1225 sbic_regmap_p regs; 1226 int len; 1227 void *bp; 1228 int phase; 1229 { 1230 u_char orig_csr, csr, asr, *buf; 1231 int wait; 1232 1233 buf = bp; 1234 wait = sbic_data_wait; 1235 1236 QPRINTF(("sbicxfout {%d} %02x %02x %02x %02x %02x " 1237 "%02x %02x %02x %02x %02x\n", len, buf[0], buf[1], buf[2], 1238 buf[3], buf[4], buf[5], buf[6], buf[7], buf[8], buf[9])); 1239 1240 GET_SBIC_csr (regs, orig_csr); 1241 CSR_TRACE('>',orig_csr,0,0); 1242 1243 /* 1244 * sigh.. WD-PROTO strikes again.. sending the command in one go 1245 * causes the chip to lock up if talking to certain (misbehaving?) 1246 * targets. Anyway, this procedure should work for all targets, but 1247 * it's slightly slower due to the overhead 1248 */ 1249 WAIT_CIP (regs); 1250 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1251 for (;len > 0; len--) { 1252 GET_SBIC_asr (regs, asr); 1253 while ((asr & SBIC_ASR_DBR) == 0) { 1254 if ((asr & SBIC_ASR_INT) || --wait < 0) { 1255 #ifdef DEBUG 1256 if (sbic_debug) 1257 printf("sbicxfout fail: l%d i%x w%d\n", 1258 len, asr, wait); 1259 #endif 1260 return (len); 1261 } 1262 /* DELAY(1);*/ 1263 GET_SBIC_asr (regs, asr); 1264 } 1265 1266 SET_SBIC_data (regs, *buf); 1267 buf++; 1268 } 1269 SBIC_TC_GET(regs, len); 1270 QPRINTF(("sbicxfout done %d bytes\n", len)); 1271 /* 1272 * this leaves with one csr to be read 1273 */ 1274 return(0); 1275 } 1276 1277 /* returns # bytes left to read */ 1278 int 1279 sbicxfin(regs, len, bp) 1280 sbic_regmap_p regs; 1281 int len; 1282 void *bp; 1283 { 1284 int wait, read; 1285 u_char *obp, *buf; 1286 u_char orig_csr, csr, asr; 1287 1288 wait = sbic_data_wait; 1289 obp = bp; 1290 buf = bp; 1291 1292 GET_SBIC_csr (regs, orig_csr); 1293 CSR_TRACE('<',orig_csr,0,0); 1294 1295 QPRINTF(("sbicxfin %d, csr=%02x\n", len, orig_csr)); 1296 1297 WAIT_CIP (regs); 1298 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1299 for (;len > 0; len--) { 1300 GET_SBIC_asr (regs, asr); 1301 if((asr & SBIC_ASR_PE)) { 1302 #ifdef DEBUG 1303 printf("sbicxfin parity error: l%d i%x w%d\n", 1304 len, asr, wait); 1305 /* return ((unsigned long)buf - (unsigned long)bp); */ 1306 #ifdef DDB 1307 Debugger(); 1308 #endif 1309 #endif 1310 } 1311 while ((asr & SBIC_ASR_DBR) == 0) { 1312 if ((asr & SBIC_ASR_INT) || --wait < 0) { 1313 #ifdef DEBUG 1314 if (sbic_debug) { 1315 QPRINTF(("sbicxfin fail:{%d} %02x %02x %02x %02x %02x %02x " 1316 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1317 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1318 printf("sbicxfin fail: l%d i%x w%d\n", 1319 len, asr, wait); 1320 } 1321 #endif 1322 return len; 1323 } 1324 1325 if( ! asr & SBIC_ASR_BSY ) { 1326 GET_SBIC_csr(regs, csr); 1327 CSR_TRACE('<',csr,asr,len); 1328 QPRINTF(("[CSR%02xASR%02x]", csr, asr)); 1329 } 1330 1331 /* DELAY(1);*/ 1332 GET_SBIC_asr (regs, asr); 1333 } 1334 1335 GET_SBIC_data (regs, *buf); 1336 /* QPRINTF(("asr=%02x, csr=%02x, data=%02x\n", asr, csr, *buf));*/ 1337 buf++; 1338 } 1339 1340 QPRINTF(("sbicxfin {%d} %02x %02x %02x %02x %02x %02x " 1341 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1342 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1343 1344 /* this leaves with one csr to be read */ 1345 return len; 1346 } 1347 1348 /* 1349 * SCSI 'immediate' command: issue a command to some SCSI device 1350 * and get back an 'immediate' response (i.e., do programmed xfer 1351 * to get the response data). 'cbuf' is a buffer containing a scsi 1352 * command of length clen bytes. 'buf' is a buffer of length 'len' 1353 * bytes for data. The transfer direction is determined by the device 1354 * (i.e., by the scsi bus data xfer phase). If 'len' is zero, the 1355 * command must supply no data. 1356 */ 1357 int 1358 sbicicmd(dev, target, lun, cbuf, clen, buf, len) 1359 struct sbic_softc *dev; 1360 void *cbuf, *buf; 1361 int clen, len; 1362 { 1363 sbic_regmap_p regs; 1364 u_char phase, csr, asr; 1365 int wait, newtarget, cmd_sent, parity_err; 1366 struct sbic_acb *acb; 1367 1368 int discon; 1369 int i; 1370 1371 #define CSR_LOG_BUF_SIZE 0 1372 #if CSR_LOG_BUF_SIZE 1373 int bufptr; 1374 int csrbuf[CSR_LOG_BUF_SIZE]; 1375 bufptr=0; 1376 #endif 1377 1378 SBIC_TRACE(dev); 1379 regs = dev->sc_sbicp; 1380 acb = dev->sc_nexus; 1381 1382 /* Make sure pointers are OK */ 1383 dev->sc_last = dev->sc_cur = &acb->sc_pa; 1384 dev->sc_tcnt = acb->sc_tcnt = 0; 1385 acb->sc_pa.dc_count = 0; /* No DMA */ 1386 acb->sc_kv.dc_addr = buf; 1387 acb->sc_kv.dc_count = len; 1388 1389 #ifdef DEBUG 1390 routine = 3; 1391 debug_sbic_regs = regs; /* store this to allow debug calls */ 1392 if( data_pointer_debug > 1 ) 1393 printf("sbicicmd(%d,%d):%d\n", target, lun, 1394 acb->sc_kv.dc_count); 1395 #endif 1396 1397 /* 1398 * set the sbic into non-DMA mode 1399 */ 1400 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI /*| SBIC_CTL_HSP*/); 1401 1402 dev->sc_stat[0] = 0xff; 1403 dev->sc_msg[0] = 0xff; 1404 i = 1; /* pre-load */ 1405 1406 /* We're stealing the SCSI bus */ 1407 dev->sc_flags |= SBICF_ICMD; 1408 1409 do { 1410 /* 1411 * select the SCSI bus (it's an error if bus isn't free) 1412 */ 1413 if (!( dev->sc_flags & SBICF_SELECTED ) 1414 && sbicselectbus(dev, regs, target, lun, dev->sc_scsiaddr)) { 1415 /*printf("sbicicmd trying to select busy bus!\n");*/ 1416 dev->sc_flags &= ~SBICF_ICMD; 1417 return(-1); 1418 } 1419 1420 /* 1421 * Wait for a phase change (or error) then let the device sequence 1422 * us through the various SCSI phases. 1423 */ 1424 1425 wait = sbic_cmd_wait; 1426 1427 asr = GET_SBIC_asr (regs, asr); 1428 GET_SBIC_csr (regs, csr); 1429 CSR_TRACE('I',csr,asr,target); 1430 QPRINTF((">ASR:%02xCSR:%02x<", asr, csr)); 1431 1432 #if CSR_LOG_BUF_SIZE 1433 csrbuf[bufptr++] = csr; 1434 #endif 1435 1436 1437 switch (csr) { 1438 case SBIC_CSR_S_XFERRED: 1439 case SBIC_CSR_DISC: 1440 case SBIC_CSR_DISC_1: 1441 dev->sc_flags &= ~SBICF_SELECTED; 1442 GET_SBIC_cmd_phase (regs, phase); 1443 if (phase == 0x60) { 1444 GET_SBIC_tlun (regs, dev->sc_stat[0]); 1445 i = 0; /* done */ 1446 /* break; /* Bypass all the state gobldygook */ 1447 } else { 1448 #ifdef DEBUG 1449 if(reselect_debug>1) 1450 printf("sbicicmd: handling disconnect\n"); 1451 #endif 1452 i = SBIC_STATE_DISCONNECT; 1453 } 1454 break; 1455 1456 case SBIC_CSR_XFERRED|CMD_PHASE: 1457 case SBIC_CSR_MIS|CMD_PHASE: 1458 case SBIC_CSR_MIS_1|CMD_PHASE: 1459 case SBIC_CSR_MIS_2|CMD_PHASE: 1460 if (sbicxfstart(regs, clen, CMD_PHASE, sbic_cmd_wait)) 1461 if (sbicxfout(regs, clen, 1462 cbuf, CMD_PHASE)) 1463 i = sbicabort(dev, regs,"icmd sending cmd"); 1464 #if 0 1465 GET_SBIC_csr(regs, csr); /* Lets us reload tcount */ 1466 WAIT_CIP(regs); 1467 GET_SBIC_asr(regs, asr); 1468 CSR_TRACE('I',csr,asr,target); 1469 if( asr & (SBIC_ASR_BSY|SBIC_ASR_LCI|SBIC_ASR_CIP) ) 1470 printf("next: cmd sent asr %02x, csr %02x\n", 1471 asr, csr); 1472 #endif 1473 break; 1474 1475 #if 0 1476 case SBIC_CSR_XFERRED|DATA_OUT_PHASE: 1477 case SBIC_CSR_XFERRED|DATA_IN_PHASE: 1478 case SBIC_CSR_MIS|DATA_OUT_PHASE: 1479 case SBIC_CSR_MIS|DATA_IN_PHASE: 1480 case SBIC_CSR_MIS_1|DATA_OUT_PHASE: 1481 case SBIC_CSR_MIS_1|DATA_IN_PHASE: 1482 case SBIC_CSR_MIS_2|DATA_OUT_PHASE: 1483 case SBIC_CSR_MIS_2|DATA_IN_PHASE: 1484 if (acb->sc_kv.dc_count <= 0) 1485 i = sbicabort(dev, regs, "icmd out of data"); 1486 else { 1487 wait = sbic_data_wait; 1488 if (sbicxfstart(regs, 1489 acb->sc_kv.dc_count, 1490 SBIC_PHASE(csr), wait)) 1491 if (csr & 0x01) 1492 /* data in? */ 1493 i=sbicxfin(regs, 1494 acb->sc_kv.dc_count, 1495 acb->sc_kv.dc_addr); 1496 else 1497 i=sbicxfout(regs, 1498 acb->sc_kv.dc_count, 1499 acb->sc_kv.dc_addr, 1500 SBIC_PHASE(csr)); 1501 acb->sc_kv.dc_addr += 1502 (acb->sc_kv.dc_count - i); 1503 acb->sc_kv.dc_count = i; 1504 i = 1; 1505 } 1506 break; 1507 1508 #endif 1509 case SBIC_CSR_XFERRED|STATUS_PHASE: 1510 case SBIC_CSR_MIS|STATUS_PHASE: 1511 case SBIC_CSR_MIS_1|STATUS_PHASE: 1512 case SBIC_CSR_MIS_2|STATUS_PHASE: 1513 /* 1514 * the sbic does the status/cmd-complete reading ok, 1515 * so do this with its hi-level commands. 1516 */ 1517 #ifdef DEBUG 1518 if(sbic_debug) 1519 printf("SBICICMD status phase\n"); 1520 #endif 1521 SBIC_TC_PUT(regs, 0); 1522 SET_SBIC_cmd_phase(regs, 0x46); 1523 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1524 break; 1525 1526 #if THIS_IS_A_RESERVED_STATE 1527 case BUS_FREE_PHASE: /* This is not legal */ 1528 if( dev->sc_stat[0] != 0xff ) 1529 goto out; 1530 break; 1531 #endif 1532 1533 default: 1534 i = sbicnextstate(dev, csr, asr); 1535 } 1536 1537 /* 1538 * make sure the last command was taken, 1539 * ie. we're not hunting after an ignored command.. 1540 */ 1541 GET_SBIC_asr(regs, asr); 1542 1543 /* tapes may take a loooong time.. */ 1544 while (asr & SBIC_ASR_BSY){ 1545 if(asr & SBIC_ASR_DBR) { 1546 printf("sbicicmd: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", 1547 csr,asr); 1548 #ifdef DDB 1549 Debugger(); 1550 #endif 1551 /* SBIC is jammed */ 1552 /* DUNNO which direction */ 1553 /* Try old direction */ 1554 GET_SBIC_data(regs,i); 1555 GET_SBIC_asr(regs, asr); 1556 if( asr & SBIC_ASR_DBR) /* Wants us to write */ 1557 SET_SBIC_data(regs,i); 1558 } 1559 GET_SBIC_asr(regs, asr); 1560 } 1561 1562 /* 1563 * wait for last command to complete 1564 */ 1565 if (asr & SBIC_ASR_LCI) { 1566 printf("sbicicmd: last command ignored\n"); 1567 } 1568 else if( i == 1 ) /* Bsy */ 1569 SBIC_WAIT (regs, SBIC_ASR_INT, wait); 1570 1571 /* 1572 * do it again 1573 */ 1574 } while ( i > 0 && dev->sc_stat[0] == 0xff); 1575 1576 /* Sometimes we need to do an extra read of the CSR */ 1577 GET_SBIC_csr(regs, csr); 1578 CSR_TRACE('I',csr,asr,0xff); 1579 1580 #if CSR_LOG_BUF_SIZE 1581 if(reselect_debug>1) 1582 for(i=0; i<bufptr; i++) 1583 printf("CSR:%02x", csrbuf[i]); 1584 #endif 1585 1586 #ifdef DEBUG 1587 if(data_pointer_debug > 1) 1588 printf("sbicicmd done(%d,%d):%d =%d=\n", 1589 dev->target, lun, 1590 acb->sc_kv.dc_count, 1591 dev->sc_stat[0]); 1592 #endif 1593 1594 QPRINTF(("=STS:%02x=", dev->sc_stat[0])); 1595 dev->sc_flags &= ~SBICF_ICMD; 1596 1597 SBIC_TRACE(dev); 1598 return(dev->sc_stat[0]); 1599 } 1600 1601 /* 1602 * Finish SCSI xfer command: After the completion interrupt from 1603 * a read/write operation, sequence through the final phases in 1604 * programmed i/o. This routine is a lot like sbicicmd except we 1605 * skip (and don't allow) the select, cmd out and data in/out phases. 1606 */ 1607 void 1608 sbicxfdone(dev, regs, target) 1609 struct sbic_softc *dev; 1610 sbic_regmap_p regs; 1611 int target; 1612 { 1613 u_char phase, asr, csr; 1614 int s; 1615 1616 SBIC_TRACE(dev); 1617 QPRINTF(("{")); 1618 s = splbio(); 1619 1620 /* 1621 * have the sbic complete on its own 1622 */ 1623 SBIC_TC_PUT(regs, 0); 1624 SET_SBIC_cmd_phase(regs, 0x46); 1625 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1626 1627 do { 1628 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0); 1629 GET_SBIC_csr (regs, csr); 1630 CSR_TRACE('f',csr,asr,target); 1631 QPRINTF(("%02x:", csr)); 1632 } while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) 1633 && (csr != SBIC_CSR_S_XFERRED)); 1634 1635 dev->sc_flags &= ~SBICF_SELECTED; 1636 1637 GET_SBIC_cmd_phase (regs, phase); 1638 QPRINTF(("}%02x", phase)); 1639 if (phase == 0x60) 1640 GET_SBIC_tlun(regs, dev->sc_stat[0]); 1641 else 1642 sbicerror(dev, regs, csr); 1643 1644 QPRINTF(("=STS:%02x=\n", dev->sc_stat[0])); 1645 splx(s); 1646 SBIC_TRACE(dev); 1647 } 1648 1649 /* 1650 * No DMA chains 1651 */ 1652 1653 int 1654 sbicgo(dev, xs) 1655 struct sbic_softc *dev; 1656 struct scsi_xfer *xs; 1657 { 1658 int i, dmaflags, count, wait, usedma; 1659 u_char csr, asr, cmd, *addr; 1660 sbic_regmap_p regs; 1661 struct sbic_acb *acb; 1662 1663 SBIC_TRACE(dev); 1664 dev->target = xs->sc_link->target; 1665 dev->lun = xs->sc_link->lun; 1666 acb = dev->sc_nexus; 1667 regs = dev->sc_sbicp; 1668 1669 usedma = sbicdmaok(dev, xs); 1670 #ifdef DEBUG 1671 routine = 1; 1672 debug_sbic_regs = regs; /* store this to allow debug calls */ 1673 if( data_pointer_debug > 1 ) 1674 printf("sbicgo(%d,%d)\n", dev->target, dev->lun); 1675 #endif 1676 1677 /* 1678 * set the sbic into DMA mode 1679 */ 1680 if( usedma ) 1681 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI | 1682 SBIC_MACHINE_DMA_MODE); 1683 else 1684 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1685 1686 1687 /* 1688 * select the SCSI bus (it's an error if bus isn't free) 1689 */ 1690 if (sbicselectbus(dev, regs, dev->target, dev->lun, 1691 dev->sc_scsiaddr)) { 1692 /* printf("sbicgo: Trying to select busy bus!\n"); */ 1693 SBIC_TRACE(dev); 1694 return(0); /* Not done: needs to be rescheduled */ 1695 } 1696 dev->sc_stat[0] = 0xff; 1697 1698 /* 1699 * Calculate DMA chains now 1700 */ 1701 1702 dmaflags = 0; 1703 if (acb->flags & ACB_DATAIN) 1704 dmaflags |= DMAGO_READ; 1705 1706 1707 /* 1708 * Deal w/bounce buffers. 1709 */ 1710 1711 addr = acb->sc_kv.dc_addr; 1712 count = acb->sc_kv.dc_count; 1713 if (count && (char *)kvtop(addr) != acb->sc_pa.dc_addr) { /* XXXX check */ 1714 printf("sbic: DMA buffer mapping changed %x->%x\n", 1715 acb->sc_pa.dc_addr, kvtop(addr)); 1716 #ifdef DDB 1717 Debugger(); 1718 #endif 1719 } 1720 1721 #ifdef DEBUG 1722 ++sbicdma_ops; /* count total DMA operations */ 1723 #endif 1724 if (count && usedma && dev->sc_flags & SBICF_BADDMA && 1725 sbiccheckdmap(addr, count, dev->sc_dmamask)) { 1726 /* 1727 * need to bounce the dma. 1728 */ 1729 if (dmaflags & DMAGO_READ) { 1730 acb->flags |= ACB_BBUF; 1731 acb->sc_dmausrbuf = addr; 1732 acb->sc_dmausrlen = count; 1733 acb->sc_usrbufpa = (u_char *)kvtop(addr); 1734 if(!dev->sc_tinfo[dev->target].bounce) { 1735 printf("sbicgo: HELP! no bounce allocated for %d\n", 1736 dev->target); 1737 printf("xfer: (%x->%x,%x)\n", acb->sc_dmausrbuf, 1738 acb->sc_usrbufpa, acb->sc_dmausrlen); 1739 dev->sc_tinfo[xs->sc_link->target].bounce 1740 = (char *)alloc_z2mem(MAXPHYS); 1741 if (isztwomem(dev->sc_tinfo[xs->sc_link->target].bounce)) 1742 printf("alloc ZII target %d bounce pa 0x%x\n", 1743 xs->sc_link->target, 1744 kvtop(dev->sc_tinfo[xs->sc_link->target].bounce)); 1745 else if (dev->sc_tinfo[xs->sc_link->target].bounce) 1746 printf("alloc CHIP target %d bounce pa 0x%x\n", 1747 xs->sc_link->target, 1748 PREP_DMA_MEM(dev->sc_tinfo[xs->sc_link->target].bounce)); 1749 1750 printf("Allocating %d bounce at %x\n", 1751 dev->target, 1752 kvtop(dev->sc_tinfo[dev->target].bounce)); 1753 } 1754 } else { /* write: copy to dma buffer */ 1755 #ifdef DEBUG 1756 if(data_pointer_debug) 1757 printf("sbicgo: copying %x bytes to target %d bounce %x\n", 1758 count, dev->target, 1759 kvtop(dev->sc_tinfo[dev->target].bounce)); 1760 #endif 1761 bcopy (addr, dev->sc_tinfo[dev->target].bounce, count); 1762 } 1763 addr = dev->sc_tinfo[dev->target].bounce;/* and use dma buffer */ 1764 acb->sc_kv.dc_addr = addr; 1765 #ifdef DEBUG 1766 ++sbicdma_bounces; /* count number of bounced */ 1767 #endif 1768 } 1769 1770 /* 1771 * Allocate the DMA chain 1772 */ 1773 1774 /* Set start KVM addresses */ 1775 #if 0 1776 acb->sc_kv.dc_addr = addr; 1777 acb->sc_kv.dc_count = count; 1778 #endif 1779 1780 /* Mark end of segment */ 1781 acb->sc_tcnt = dev->sc_tcnt = 0; 1782 acb->sc_pa.dc_count = 0; 1783 1784 sbic_load_ptrs(dev, regs, dev->target, dev->lun); 1785 SBIC_TRACE(dev); 1786 /* Enable interrupts but don't do any DMA */ 1787 dev->sc_enintr(dev); 1788 if (usedma) { 1789 dev->sc_tcnt = dev->sc_dmago(dev, acb->sc_pa.dc_addr, 1790 acb->sc_pa.dc_count, 1791 dmaflags); 1792 #ifdef DEBUG 1793 dev->sc_dmatimo = dev->sc_tcnt ? 1 : 0; 1794 #endif 1795 } else 1796 dev->sc_dmacmd = 0; /* Don't use DMA */ 1797 dev->sc_flags |= SBICF_INDMA; 1798 /* SBIC_TC_PUT(regs, dev->sc_tcnt); /* XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX */ 1799 SBIC_TRACE(dev); 1800 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 1801 1802 /* 1803 * push the data cache ( I think this won't work (EH)) 1804 */ 1805 #if defined(M68040) 1806 if (mmutype == MMU_68040 && usedma && count) { 1807 dma_cachectl(addr, count); 1808 if (((u_int)addr & 0xF) || (((u_int)addr + count) & 0xF)) 1809 dev->sc_flags |= SBICF_DCFLUSH; 1810 } 1811 #endif 1812 1813 /* 1814 * enintr() also enables interrupts for the sbic 1815 */ 1816 #ifdef DEBUG 1817 if( data_pointer_debug > 1 ) 1818 printf("sbicgo dmago:%d(%x:%x)\n", 1819 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 1820 debug_asr = asr; 1821 debug_csr = csr; 1822 #endif 1823 1824 /* 1825 * Lets cycle a while then let the interrupt handler take over 1826 */ 1827 1828 asr = GET_SBIC_asr(regs, asr); 1829 do { 1830 GET_SBIC_csr(regs, csr); 1831 CSR_TRACE('g',csr,asr,dev->target); 1832 #ifdef DEBUG 1833 debug_csr = csr; 1834 routine = 1; 1835 #endif 1836 QPRINTF(("go[0x%x]", csr)); 1837 1838 i = sbicnextstate(dev, csr, asr); 1839 1840 WAIT_CIP(regs); 1841 GET_SBIC_asr(regs, asr); 1842 #ifdef DEBUG 1843 debug_asr = asr; 1844 #endif 1845 if(asr & SBIC_ASR_LCI) printf("sbicgo: LCI asr:%02x csr:%02x\n", 1846 asr,csr); 1847 } while( i == SBIC_STATE_RUNNING 1848 && asr & (SBIC_ASR_INT|SBIC_ASR_LCI) ); 1849 1850 CSR_TRACE('g',csr,asr,i<<4); 1851 SBIC_TRACE(dev); 1852 if (i == SBIC_STATE_DONE && dev->sc_stat[0] == 0xff) printf("sbicgo: done & stat = 0xff\n"); 1853 if (i == SBIC_STATE_DONE && dev->sc_stat[0] != 0xff) { 1854 /* if( i == SBIC_STATE_DONE && dev->sc_stat[0] ) { */ 1855 /* Did we really finish that fast? */ 1856 return 1; 1857 } 1858 return 0; 1859 } 1860 1861 1862 int 1863 sbicintr(dev) 1864 struct sbic_softc *dev; 1865 { 1866 sbic_regmap_p regs; 1867 struct dma_chain *df, *dl; 1868 u_char asr, csr, *tmpaddr; 1869 struct sbic_acb *acb; 1870 int i, newtarget, newlun; 1871 unsigned tcnt; 1872 1873 regs = dev->sc_sbicp; 1874 1875 /* 1876 * pending interrupt? 1877 */ 1878 GET_SBIC_asr (regs, asr); 1879 if ((asr & SBIC_ASR_INT) == 0) 1880 return(0); 1881 1882 SBIC_TRACE(dev); 1883 do { 1884 GET_SBIC_csr(regs, csr); 1885 CSR_TRACE('i',csr,asr,dev->target); 1886 #ifdef DEBUG 1887 debug_csr = csr; 1888 routine = 2; 1889 #endif 1890 QPRINTF(("intr[0x%x]", csr)); 1891 1892 i = sbicnextstate(dev, csr, asr); 1893 1894 WAIT_CIP(regs); 1895 GET_SBIC_asr(regs, asr); 1896 #ifdef DEBUG 1897 debug_asr = asr; 1898 #endif 1899 #if 0 1900 if(asr & SBIC_ASR_LCI) printf("sbicintr: LCI asr:%02x csr:%02x\n", 1901 asr,csr); 1902 #endif 1903 } while(i == SBIC_STATE_RUNNING && 1904 asr & (SBIC_ASR_INT|SBIC_ASR_LCI)); 1905 CSR_TRACE('i',csr,asr,i<<4); 1906 SBIC_TRACE(dev); 1907 return(1); 1908 } 1909 1910 /* 1911 * Run commands and wait for disconnect 1912 */ 1913 int 1914 sbicpoll(dev) 1915 struct sbic_softc *dev; 1916 { 1917 sbic_regmap_p regs; 1918 u_char asr, csr; 1919 struct sbic_pending* pendp; 1920 int i; 1921 unsigned tcnt; 1922 1923 SBIC_TRACE(dev); 1924 regs = dev->sc_sbicp; 1925 1926 do { 1927 GET_SBIC_asr (regs, asr); 1928 #ifdef DEBUG 1929 debug_asr = asr; 1930 #endif 1931 GET_SBIC_csr(regs, csr); 1932 CSR_TRACE('p',csr,asr,dev->target); 1933 #ifdef DEBUG 1934 debug_csr = csr; 1935 routine = 2; 1936 #endif 1937 QPRINTF(("poll[0x%x]", csr)); 1938 1939 i = sbicnextstate(dev, csr, asr); 1940 1941 WAIT_CIP(regs); 1942 GET_SBIC_asr(regs, asr); 1943 /* tapes may take a loooong time.. */ 1944 while (asr & SBIC_ASR_BSY){ 1945 if(asr & SBIC_ASR_DBR) { 1946 printf("sbipoll: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", 1947 csr,asr); 1948 #ifdef DDB 1949 Debugger(); 1950 #endif 1951 /* SBIC is jammed */ 1952 /* DUNNO which direction */ 1953 /* Try old direction */ 1954 GET_SBIC_data(regs,i); 1955 GET_SBIC_asr(regs, asr); 1956 if( asr & SBIC_ASR_DBR) /* Wants us to write */ 1957 SET_SBIC_data(regs,i); 1958 } 1959 GET_SBIC_asr(regs, asr); 1960 } 1961 1962 if(asr & SBIC_ASR_LCI) printf("sbicpoll: LCI asr:%02x csr:%02x\n", 1963 asr,csr); 1964 else if( i == 1 ) /* BSY */ 1965 SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait); 1966 } while(i == SBIC_STATE_RUNNING); 1967 CSR_TRACE('p',csr,asr,i<<4); 1968 SBIC_TRACE(dev); 1969 return(1); 1970 } 1971 1972 /* 1973 * Handle a single msgin 1974 */ 1975 1976 int 1977 sbicmsgin(dev) 1978 struct sbic_softc *dev; 1979 { 1980 sbic_regmap_p regs; 1981 int recvlen; 1982 u_char asr, csr, *tmpaddr; 1983 1984 regs = dev->sc_sbicp; 1985 1986 dev->sc_msg[0] = 0xff; 1987 dev->sc_msg[1] = 0xff; 1988 1989 GET_SBIC_asr(regs, asr); 1990 #ifdef DEBUG 1991 if(reselect_debug>1) 1992 printf("sbicmsgin asr=%02x\n", asr); 1993 #endif 1994 1995 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 1996 1997 GET_SBIC_selid (regs, csr); 1998 SET_SBIC_selid (regs, csr | SBIC_SID_FROM_SCSI); 1999 2000 SBIC_TC_PUT(regs, 0); 2001 tmpaddr = dev->sc_msg; 2002 recvlen = 1; 2003 do { 2004 while( recvlen-- ) { 2005 asr = GET_SBIC_asr(regs, asr); 2006 GET_SBIC_csr(regs, csr); 2007 QPRINTF(("sbicmsgin ready to go (csr,asr)=(%02x,%02x)\n", 2008 csr, asr)); 2009 2010 RECV_BYTE(regs, *tmpaddr); 2011 CSR_TRACE('m',csr,asr,*tmpaddr); 2012 #if 1 2013 /* 2014 * get the command completion interrupt, or we 2015 * can't send a new command (LCI) 2016 */ 2017 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2018 GET_SBIC_csr(regs, csr); 2019 CSR_TRACE('X',csr,asr,dev->target); 2020 #else 2021 WAIT_CIP(regs); 2022 do { 2023 GET_SBIC_asr(regs, asr); 2024 csr = 0xff; 2025 GET_SBIC_csr(regs, csr); 2026 CSR_TRACE('X',csr,asr,dev->target); 2027 if( csr == 0xff ) 2028 printf("sbicmsgin waiting: csr %02x asr %02x\n", csr, asr); 2029 } while( csr == 0xff ); 2030 #endif 2031 #ifdef DEBUG 2032 if(reselect_debug>1) 2033 printf("sbicmsgin: got %02x csr %02x asr %02x\n", 2034 *tmpaddr, csr, asr); 2035 #endif 2036 #if do_parity_check 2037 if( asr & SBIC_ASR_PE ) { 2038 printf ("Parity error"); 2039 /* This code simply does not work. */ 2040 WAIT_CIP(regs); 2041 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2042 WAIT_CIP(regs); 2043 GET_SBIC_asr(regs, asr); 2044 WAIT_CIP(regs); 2045 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2046 WAIT_CIP(regs); 2047 if( !(asr & SBIC_ASR_LCI) ) 2048 /* Target wants to send garbled msg*/ 2049 continue; 2050 printf("--fixing\n"); 2051 /* loop until a msgout phase occurs on target */ 2052 while(csr & 0x07 != MESG_OUT_PHASE) { 2053 while( asr & SBIC_ASR_BSY && 2054 !(asr & SBIC_ASR_DBR|SBIC_ASR_INT) ) 2055 GET_SBIC_asr(regs, asr); 2056 if( asr & SBIC_ASR_DBR ) 2057 panic("msgin: jammed again!\n"); 2058 GET_SBIC_csr(regs, csr); 2059 CSR_TRACE('e',csr,asr,dev->target); 2060 if( csr & 0x07 != MESG_OUT_PHASE ) { 2061 sbicnextstate(dev, csr, asr); 2062 sbic_save_ptrs(dev, regs, 2063 dev->target, 2064 dev->lun); 2065 } 2066 } 2067 /* Should be msg out by now */ 2068 SEND_BYTE(regs, MSG_PARITY_ERROR); 2069 } 2070 else 2071 #endif 2072 tmpaddr++; 2073 2074 if(recvlen) { 2075 /* Clear ACK */ 2076 WAIT_CIP(regs); 2077 GET_SBIC_asr(regs, asr); 2078 GET_SBIC_csr(regs, csr); 2079 CSR_TRACE('X',csr,asr,dev->target); 2080 QPRINTF(("sbicmsgin pre byte CLR_ACK (csr,asr)=(%02x,%02x)\n", 2081 csr, asr)); 2082 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2083 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2084 } 2085 2086 }; 2087 2088 if(dev->sc_msg[0] == 0xff) { 2089 printf("sbicmsgin: sbic swallowed our message\n"); 2090 break; 2091 } 2092 #ifdef DEBUG 2093 if (sync_debug) 2094 printf("msgin done csr 0x%x asr 0x%x msg 0x%x\n", 2095 csr, asr, dev->sc_msg[0]); 2096 #endif 2097 /* 2098 * test whether this is a reply to our sync 2099 * request 2100 */ 2101 if (MSG_ISIDENTIFY(dev->sc_msg[0])) { 2102 QPRINTF(("IFFY")); 2103 #if 0 2104 /* There is an implied load-ptrs here */ 2105 sbic_load_ptrs(dev, regs, dev->target, dev->lun); 2106 #endif 2107 /* Got IFFY msg -- ack it */ 2108 } else if (dev->sc_msg[0] == MSG_REJECT 2109 && dev->sc_sync[dev->target].state == SYNC_SENT) { 2110 QPRINTF(("REJECT of SYN")); 2111 #ifdef DEBUG 2112 if (sync_debug) 2113 printf("target %d rejected sync, going async\n", 2114 dev->target); 2115 #endif 2116 dev->sc_sync[dev->target].period = sbic_min_period; 2117 dev->sc_sync[dev->target].offset = 0; 2118 dev->sc_sync[dev->target].state = SYNC_DONE; 2119 SET_SBIC_syn(regs, 2120 SBIC_SYN(dev->sc_sync[dev->target].offset, 2121 dev->sc_sync[dev->target].period)); 2122 } else if ((dev->sc_msg[0] == MSG_REJECT)) { 2123 QPRINTF(("REJECT")); 2124 /* 2125 * we'll never REJECt a REJECT message.. 2126 */ 2127 } else if ((dev->sc_msg[0] == MSG_SAVE_DATA_PTR)) { 2128 QPRINTF(("MSG_SAVE_DATA_PTR")); 2129 /* 2130 * don't reject this either. 2131 */ 2132 } else if ((dev->sc_msg[0] == MSG_DISCONNECT)) { 2133 QPRINTF(("DISCONNECT")); 2134 #ifdef DEBUG 2135 if( reselect_debug>1 && dev->sc_msg[0] == MSG_DISCONNECT ) 2136 printf("sbicmsgin: got disconnect msg %s\n", 2137 (dev->sc_flags & SBICF_ICMD)?"rejecting":""); 2138 #endif 2139 if( dev->sc_flags & SBICF_ICMD ) { 2140 /* We're in immediate mode. Prevent disconnects. */ 2141 /* prepare to reject the message, NACK */ 2142 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2143 WAIT_CIP(regs); 2144 } 2145 } else if (dev->sc_msg[0] == MSG_CMD_COMPLETE ) { 2146 QPRINTF(("CMD_COMPLETE")); 2147 /* !! KLUDGE ALERT !! quite a few drives don't seem to 2148 * really like the current way of sending the 2149 * sync-handshake together with the ident-message, and 2150 * they react by sending command-complete and 2151 * disconnecting right after returning the valid sync 2152 * handshake. So, all I can do is reselect the drive, 2153 * and hope it won't disconnect again. I don't think 2154 * this is valid behavior, but I can't help fixing a 2155 * problem that apparently exists. 2156 * 2157 * Note: we should not get here on `normal' command 2158 * completion, as that condition is handled by the 2159 * high-level sel&xfer resume command used to walk 2160 * thru status/cc-phase. 2161 */ 2162 2163 #ifdef DEBUG 2164 if (sync_debug) 2165 printf ("GOT MSG %d! target %d acting weird.." 2166 " waiting for disconnect...\n", 2167 dev->sc_msg[0], dev->target); 2168 #endif 2169 /* Check to see if sbic is handling this */ 2170 GET_SBIC_asr(regs, asr); 2171 if(asr & SBIC_ASR_BSY) 2172 return SBIC_STATE_RUNNING; 2173 2174 /* Let's try this: Assume it works and set status to 00 */ 2175 dev->sc_stat[0] = 0; 2176 } else if (dev->sc_msg[0] == MSG_EXT_MESSAGE 2177 && tmpaddr == &dev->sc_msg[1]) { 2178 QPRINTF(("ExtMSG\n")); 2179 /* Read in whole extended message */ 2180 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2181 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2182 GET_SBIC_asr(regs, asr); 2183 GET_SBIC_csr(regs, csr); 2184 QPRINTF(("CLR ACK asr %02x, csr %02x\n", asr, csr)); 2185 RECV_BYTE(regs, *tmpaddr); 2186 CSR_TRACE('x',csr,asr,*tmpaddr); 2187 /* Wait for command completion IRQ */ 2188 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2189 recvlen = *tmpaddr++; 2190 QPRINTF(("Recving ext msg, asr %02x csr %02x len %02x\n", 2191 asr, csr, recvlen)); 2192 } else if (dev->sc_msg[0] == MSG_EXT_MESSAGE && dev->sc_msg[1] == 3 2193 && dev->sc_msg[2] == MSG_SYNC_REQ) { 2194 QPRINTF(("SYN")); 2195 dev->sc_sync[dev->target].period = 2196 sbicfromscsiperiod(dev, 2197 regs, dev->sc_msg[3]); 2198 dev->sc_sync[dev->target].offset = dev->sc_msg[4]; 2199 dev->sc_sync[dev->target].state = SYNC_DONE; 2200 SET_SBIC_syn(regs, 2201 SBIC_SYN(dev->sc_sync[dev->target].offset, 2202 dev->sc_sync[dev->target].period)); 2203 printf("%s: target %d now synchronous," 2204 " period=%dns, offset=%d.\n", 2205 dev->sc_dev.dv_xname, dev->target, 2206 dev->sc_msg[3] * 4, dev->sc_msg[4]); 2207 } else { 2208 #ifdef DEBUG 2209 if (sbic_debug || sync_debug) 2210 printf ("sbicmsgin: Rejecting message 0x%02x\n", 2211 dev->sc_msg[0]); 2212 #endif 2213 /* prepare to reject the message, NACK */ 2214 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2215 WAIT_CIP(regs); 2216 } 2217 /* Clear ACK */ 2218 WAIT_CIP(regs); 2219 GET_SBIC_asr(regs, asr); 2220 GET_SBIC_csr(regs, csr); 2221 CSR_TRACE('X',csr,asr,dev->target); 2222 QPRINTF(("sbicmsgin pre CLR_ACK (csr,asr)=(%02x,%02x)%d\n", 2223 csr, asr, recvlen)); 2224 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2225 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2226 } 2227 #if 0 2228 while((csr == SBIC_CSR_MSGIN_W_ACK) 2229 || (SBIC_PHASE(csr) == MESG_IN_PHASE)); 2230 #else 2231 while (recvlen>0); 2232 #endif 2233 2234 QPRINTF(("sbicmsgin finished: csr %02x, asr %02x\n",csr, asr)); 2235 2236 /* Should still have one CSR to read */ 2237 return SBIC_STATE_RUNNING; 2238 } 2239 2240 2241 /* 2242 * sbicnextstate() 2243 * return: 2244 * 0 == done 2245 * 1 == working 2246 * 2 == disconnected 2247 * -1 == error 2248 */ 2249 int 2250 sbicnextstate(dev, csr, asr) 2251 struct sbic_softc *dev; 2252 u_char csr, asr; 2253 { 2254 sbic_regmap_p regs; 2255 struct dma_chain *df, *dl; 2256 struct sbic_acb *acb; 2257 int i, newtarget, newlun, wait; 2258 unsigned tcnt; 2259 2260 SBIC_TRACE(dev); 2261 regs = dev->sc_sbicp; 2262 acb = dev->sc_nexus; 2263 2264 QPRINTF(("next[%02x,%02x]",asr,csr)); 2265 2266 switch (csr) { 2267 case SBIC_CSR_XFERRED|CMD_PHASE: 2268 case SBIC_CSR_MIS|CMD_PHASE: 2269 case SBIC_CSR_MIS_1|CMD_PHASE: 2270 case SBIC_CSR_MIS_2|CMD_PHASE: 2271 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 2272 if (sbicxfstart(regs, acb->clen, CMD_PHASE, sbic_cmd_wait)) 2273 if (sbicxfout(regs, acb->clen, 2274 &acb->cmd, CMD_PHASE)) 2275 goto abort; 2276 break; 2277 2278 case SBIC_CSR_XFERRED|STATUS_PHASE: 2279 case SBIC_CSR_MIS|STATUS_PHASE: 2280 case SBIC_CSR_MIS_1|STATUS_PHASE: 2281 case SBIC_CSR_MIS_2|STATUS_PHASE: 2282 /* 2283 * this should be the normal i/o completion case. 2284 * get the status & cmd complete msg then let the 2285 * device driver look at what happened. 2286 */ 2287 sbicxfdone(dev,regs,dev->target); 2288 /* 2289 * check for overlapping cache line, flush if so 2290 */ 2291 #ifdef M68040 2292 if (dev->sc_flags & SBICF_DCFLUSH) { 2293 #if 0 2294 printf("sbic: 68040 DMA cache flush needs fixing? %x:%x\n", 2295 dev->sc_xs->data, dev->sc_xs->datalen); 2296 #endif 2297 } 2298 #endif 2299 #ifdef DEBUG 2300 if( data_pointer_debug > 1 ) 2301 printf("next dmastop: %d(%x:%x)\n", 2302 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 2303 dev->sc_dmatimo = 0; 2304 #endif 2305 dev->sc_dmastop(dev); /* was dmafree */ 2306 if (acb->flags & ACB_BBUF) { 2307 if ((u_char *)kvtop(acb->sc_dmausrbuf) != acb->sc_usrbufpa) 2308 printf("%s: WARNING - buffer mapping changed %x->%x\n", 2309 dev->sc_dev.dv_xname, acb->sc_usrbufpa, 2310 kvtop(acb->sc_dmausrbuf)); 2311 #ifdef DEBUG 2312 if(data_pointer_debug) 2313 printf("sbicgo:copying %x bytes from target %d bounce %x\n", 2314 acb->sc_dmausrlen, 2315 dev->target, 2316 kvtop(dev->sc_tinfo[dev->target].bounce)); 2317 #endif 2318 bcopy(dev->sc_tinfo[dev->target].bounce, 2319 acb->sc_dmausrbuf, 2320 acb->sc_dmausrlen); 2321 } 2322 dev->sc_flags &= ~(SBICF_INDMA | SBICF_DCFLUSH); 2323 sbic_scsidone(acb, dev->sc_stat[0]); 2324 SBIC_TRACE(dev); 2325 return SBIC_STATE_DONE; 2326 2327 case SBIC_CSR_XFERRED|DATA_OUT_PHASE: 2328 case SBIC_CSR_XFERRED|DATA_IN_PHASE: 2329 case SBIC_CSR_MIS|DATA_OUT_PHASE: 2330 case SBIC_CSR_MIS|DATA_IN_PHASE: 2331 case SBIC_CSR_MIS_1|DATA_OUT_PHASE: 2332 case SBIC_CSR_MIS_1|DATA_IN_PHASE: 2333 case SBIC_CSR_MIS_2|DATA_OUT_PHASE: 2334 case SBIC_CSR_MIS_2|DATA_IN_PHASE: 2335 if( dev->sc_xs->flags & SCSI_POLL || dev->sc_flags & SBICF_ICMD 2336 || acb->sc_dmacmd == 0 ) { 2337 /* Do PIO */ 2338 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2339 if (acb->sc_kv.dc_count <= 0) { 2340 printf("sbicnextstate:xfer count %d asr%x csr%x\n", 2341 acb->sc_kv.dc_count, asr, csr); 2342 goto abort; 2343 } 2344 wait = sbic_data_wait; 2345 if( sbicxfstart(regs, 2346 acb->sc_kv.dc_count, 2347 SBIC_PHASE(csr), wait)) 2348 if( SBIC_PHASE(csr) == DATA_IN_PHASE ) 2349 /* data in? */ 2350 i=sbicxfin(regs, 2351 acb->sc_kv.dc_count, 2352 acb->sc_kv.dc_addr); 2353 else 2354 i=sbicxfout(regs, 2355 acb->sc_kv.dc_count, 2356 acb->sc_kv.dc_addr, 2357 SBIC_PHASE(csr)); 2358 acb->sc_kv.dc_addr += 2359 (acb->sc_kv.dc_count - i); 2360 acb->sc_kv.dc_count = i; 2361 } else { 2362 if (acb->sc_kv.dc_count <= 0) { 2363 printf("sbicnextstate:xfer count %d asr%x csr%x\n", 2364 acb->sc_kv.dc_count, asr, csr); 2365 goto abort; 2366 } 2367 /* 2368 * do scatter-gather dma 2369 * hacking the controller chip, ouch.. 2370 */ 2371 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI | 2372 SBIC_MACHINE_DMA_MODE); 2373 /* 2374 * set next dma addr and dec count 2375 */ 2376 #if 0 2377 SBIC_TC_GET(regs, tcnt); 2378 dev->sc_cur->dc_count -= ((dev->sc_tcnt - tcnt) >> 1); 2379 dev->sc_cur->dc_addr += (dev->sc_tcnt - tcnt); 2380 dev->sc_tcnt = acb->sc_tcnt = tcnt; 2381 #else 2382 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 2383 sbic_load_ptrs(dev, regs, dev->target, dev->lun); 2384 #endif 2385 #ifdef DEBUG 2386 if( data_pointer_debug > 1 ) 2387 printf("next dmanext: %d(%x:%x)\n", 2388 dev->target,dev->sc_cur->dc_addr, 2389 dev->sc_tcnt); 2390 dev->sc_dmatimo = 1; 2391 #endif 2392 dev->sc_tcnt = dev->sc_dmanext(dev); 2393 SBIC_TC_PUT(regs, (unsigned)dev->sc_tcnt); 2394 SET_SBIC_cmd(regs, SBIC_CMD_XFER_INFO); 2395 dev->sc_flags |= SBICF_INDMA; 2396 } 2397 break; 2398 2399 case SBIC_CSR_XFERRED|MESG_IN_PHASE: 2400 case SBIC_CSR_MIS|MESG_IN_PHASE: 2401 case SBIC_CSR_MIS_1|MESG_IN_PHASE: 2402 case SBIC_CSR_MIS_2|MESG_IN_PHASE: 2403 SBIC_TRACE(dev); 2404 return sbicmsgin(dev); 2405 2406 case SBIC_CSR_MSGIN_W_ACK: 2407 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); /* Dunno what I'm ACKing */ 2408 printf("Acking unknown msgin CSR:%02x",csr); 2409 break; 2410 2411 case SBIC_CSR_XFERRED|MESG_OUT_PHASE: 2412 case SBIC_CSR_MIS|MESG_OUT_PHASE: 2413 case SBIC_CSR_MIS_1|MESG_OUT_PHASE: 2414 case SBIC_CSR_MIS_2|MESG_OUT_PHASE: 2415 #ifdef DEBUG 2416 if (sync_debug) 2417 printf ("sending REJECT msg to last msg.\n"); 2418 #endif 2419 2420 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 2421 /* 2422 * should only get here on reject, 2423 * since it's always US that 2424 * initiate a sync transfer 2425 */ 2426 SEND_BYTE(regs, MSG_REJECT); 2427 WAIT_CIP(regs); 2428 if( asr & (SBIC_ASR_BSY|SBIC_ASR_LCI|SBIC_ASR_CIP) ) 2429 printf("next: REJECT sent asr %02x\n", asr); 2430 SBIC_TRACE(dev); 2431 return SBIC_STATE_RUNNING; 2432 2433 case SBIC_CSR_DISC: 2434 case SBIC_CSR_DISC_1: 2435 dev->sc_flags &= ~(SBICF_INDMA|SBICF_SELECTED); 2436 2437 /* Try to schedule another target */ 2438 #ifdef DEBUG 2439 if(reselect_debug>1) 2440 printf("sbicnext target %d disconnected\n", dev->target); 2441 #endif 2442 TAILQ_INSERT_HEAD(&dev->nexus_list, acb, chain); 2443 ++dev->sc_tinfo[dev->target].dconns; 2444 dev->sc_nexus = NULL; 2445 dev->sc_xs = NULL; 2446 2447 if( acb->xs->flags & SCSI_POLL 2448 || (dev->sc_flags & SBICF_ICMD) 2449 || !sbic_parallel_operations ) { 2450 SBIC_TRACE(dev); 2451 return SBIC_STATE_DISCONNECT; 2452 } 2453 sbic_sched(dev); 2454 SBIC_TRACE(dev); 2455 return SBIC_STATE_DISCONNECT; 2456 2457 case SBIC_CSR_RSLT_NI: 2458 case SBIC_CSR_RSLT_IFY: 2459 GET_SBIC_rselid(regs, newtarget); 2460 /* check SBIC_RID_SIV? */ 2461 newtarget &= SBIC_RID_MASK; 2462 if (csr == SBIC_CSR_RSLT_IFY) { 2463 /* Read IFY msg to avoid lockup */ 2464 GET_SBIC_data(regs, newlun); 2465 WAIT_CIP(regs); 2466 newlun &= SBIC_TLUN_MASK; 2467 CSR_TRACE('r',csr,asr,newtarget); 2468 } else { 2469 /* Need to get IFY message */ 2470 for (newlun = 256; newlun; --newlun) { 2471 GET_SBIC_asr(regs, asr); 2472 if (asr & SBIC_ASR_INT) 2473 break; 2474 delay(1); 2475 } 2476 newlun = 0; /* XXXX */ 2477 if ((asr & SBIC_ASR_INT) == 0) { 2478 #ifdef DEBUG 2479 if (reselect_debug) 2480 printf("RSLT_NI - no IFFY message? asr %x\n", asr); 2481 #endif 2482 } else { 2483 GET_SBIC_csr(regs,csr); 2484 CSR_TRACE('n',csr,asr,newtarget); 2485 if (csr == SBIC_CSR_MIS|MESG_IN_PHASE || 2486 csr == SBIC_CSR_MIS_1|MESG_IN_PHASE || 2487 csr == SBIC_CSR_MIS_2|MESG_IN_PHASE) { 2488 sbicmsgin(dev); 2489 newlun = dev->sc_msg[0] & 7; 2490 } else { 2491 printf("RSLT_NI - not MESG_IN_PHASE %x\n", 2492 csr); 2493 } 2494 } 2495 } 2496 #ifdef DEBUG 2497 if(reselect_debug>1 || (reselect_debug && csr==SBIC_CSR_RSLT_NI)) 2498 printf("sbicnext: reselect %s from targ %d lun %d\n", 2499 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", 2500 newtarget, newlun); 2501 #endif 2502 if (dev->sc_nexus) { 2503 #ifdef DEBUG 2504 if (reselect_debug > 1) 2505 printf("%s: reselect %s with active command\n", 2506 dev->sc_dev.dv_xname, 2507 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY"); 2508 #ifdef DDB 2509 /* Debugger();*/ 2510 #endif 2511 #endif 2512 TAILQ_INSERT_HEAD(&dev->ready_list, dev->sc_nexus, chain); 2513 dev->sc_tinfo[dev->target].lubusy &= ~(1 << dev->lun); 2514 dev->sc_nexus = NULL; 2515 dev->sc_xs = NULL; 2516 } 2517 /* Reload sync values for this target */ 2518 if (dev->sc_sync[newtarget].state == SYNC_DONE) 2519 SET_SBIC_syn(regs, SBIC_SYN (dev->sc_sync[newtarget].offset, 2520 dev->sc_sync[newtarget].period)); 2521 else 2522 SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period)); 2523 for (acb = dev->nexus_list.tqh_first; acb; 2524 acb = acb->chain.tqe_next) { 2525 if (acb->xs->sc_link->target != newtarget || 2526 acb->xs->sc_link->lun != newlun) 2527 continue; 2528 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 2529 dev->sc_nexus = acb; 2530 dev->sc_xs = acb->xs; 2531 dev->sc_flags |= SBICF_SELECTED; 2532 dev->target = newtarget; 2533 dev->lun = newlun; 2534 break; 2535 } 2536 if (acb == NULL) { 2537 printf("%s: reselect %s targ %d not in nexus_list %x\n", 2538 dev->sc_dev.dv_xname, 2539 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", newtarget, 2540 &dev->nexus_list.tqh_first); 2541 panic("bad reselect in sbic"); 2542 } 2543 if (csr == SBIC_CSR_RSLT_IFY) 2544 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2545 break; 2546 2547 default: 2548 abort: 2549 /* 2550 * Something unexpected happened -- deal with it. 2551 */ 2552 printf("sbicnextstate: aborting csr %02x asr %02x\n", csr, asr); 2553 #ifdef DDB 2554 Debugger(); 2555 #endif 2556 #ifdef DEBUG 2557 if( data_pointer_debug > 1 ) 2558 printf("next dmastop: %d(%x:%x)\n", 2559 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 2560 dev->sc_dmatimo = 0; 2561 #endif 2562 dev->sc_dmastop(dev); 2563 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2564 sbicerror(dev, regs, csr); 2565 sbicabort(dev, regs, "next"); 2566 if (dev->sc_flags & SBICF_INDMA) { 2567 /* 2568 * check for overlapping cache line, flush if so 2569 */ 2570 #ifdef M68040 2571 if (dev->sc_flags & SBICF_DCFLUSH) { 2572 #if 0 2573 printf("sibc: 68040 DMA cache flush needs fixing? %x:%x\n", 2574 dev->sc_xs->data, dev->sc_xs->datalen); 2575 #endif 2576 } 2577 #endif 2578 dev->sc_flags &= 2579 ~(SBICF_INDMA | SBICF_DCFLUSH); 2580 #ifdef DEBUG 2581 if( data_pointer_debug > 1 ) 2582 printf("next dmastop: %d(%x:%x)\n", 2583 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 2584 dev->sc_dmatimo = 0; 2585 #endif 2586 dev->sc_dmastop(dev); 2587 sbic_scsidone(acb, -1); 2588 } 2589 SBIC_TRACE(dev); 2590 return SBIC_STATE_ERROR; 2591 } 2592 2593 SBIC_TRACE(dev); 2594 return(SBIC_STATE_RUNNING); 2595 } 2596 2597 2598 /* 2599 * Check if DMA can not be used with specified buffer 2600 */ 2601 2602 int 2603 sbiccheckdmap(bp, len, mask) 2604 void *bp; 2605 u_long len, mask; 2606 { 2607 u_char *buffer; 2608 u_long phy_buf; 2609 u_long phy_len; 2610 2611 buffer = bp; 2612 2613 if (len == 0) 2614 return(0); 2615 2616 while (len) { 2617 phy_buf = kvtop(buffer); 2618 if (len < (phy_len = NBPG - ((int) buffer & PGOFSET))) 2619 phy_len = len; 2620 if (phy_buf & mask) 2621 return(1); 2622 buffer += phy_len; 2623 len -= phy_len; 2624 } 2625 return(0); 2626 } 2627 2628 int 2629 sbictoscsiperiod(dev, regs, a) 2630 struct sbic_softc *dev; 2631 sbic_regmap_p regs; 2632 int a; 2633 { 2634 unsigned int fs; 2635 2636 /* 2637 * cycle = DIV / (2*CLK) 2638 * DIV = FS+2 2639 * best we can do is 200ns at 20Mhz, 2 cycles 2640 */ 2641 2642 GET_SBIC_myid(regs,fs); 2643 fs = (fs >>6) + 2; /* DIV */ 2644 fs = (fs * 10000) / (dev->sc_clkfreq<<1); /* Cycle, in ns */ 2645 if (a < 2) a = 8; /* map to Cycles */ 2646 return ((fs*a)>>2); /* in 4 ns units */ 2647 } 2648 2649 int 2650 sbicfromscsiperiod(dev, regs, p) 2651 struct sbic_softc *dev; 2652 sbic_regmap_p regs; 2653 int p; 2654 { 2655 register unsigned int fs, ret; 2656 2657 /* Just the inverse of the above */ 2658 2659 GET_SBIC_myid(regs,fs); 2660 fs = (fs >>6) + 2; /* DIV */ 2661 fs = (fs * 10000) / (dev->sc_clkfreq<<1); /* Cycle, in ns */ 2662 2663 ret = p << 2; /* in ns units */ 2664 ret = ret / fs; /* in Cycles */ 2665 if (ret < sbic_min_period) 2666 return(sbic_min_period); 2667 2668 /* verify rounding */ 2669 if (sbictoscsiperiod(dev, regs, ret) < p) 2670 ret++; 2671 return (ret >= 8) ? 0 : ret; 2672 } 2673 2674 #ifdef DEBUG 2675 2676 void sbicdumpstate() 2677 { 2678 u_char csr, asr; 2679 2680 GET_SBIC_asr(debug_sbic_regs,asr); 2681 GET_SBIC_csr(debug_sbic_regs,csr); 2682 printf("%s: asr:csr(%02x:%02x)->(%02x:%02x)\n", 2683 (routine==1)?"sbicgo": 2684 (routine==2)?"sbicintr": 2685 (routine==3)?"sbicicmd": 2686 (routine==4)?"sbicnext":"unknown", 2687 debug_asr, debug_csr, asr, csr); 2688 2689 } 2690 2691 void sbictimeout(dev) 2692 struct sbic_softc *dev; 2693 { 2694 int s, asr; 2695 2696 s = splbio(); 2697 if (dev->sc_dmatimo) { 2698 if (dev->sc_dmatimo > 1) { 2699 printf("%s: dma timeout #%d\n", 2700 dev->sc_dev.dv_xname, dev->sc_dmatimo - 1); 2701 GET_SBIC_asr(dev->sc_sbicp, asr); 2702 if( asr & SBIC_ASR_INT ) { 2703 /* We need to service a missed IRQ */ 2704 printf("Servicing a missed int:(%02x,%02x)->(%02x,??)\n", 2705 debug_asr, debug_csr, asr); 2706 sbicintr(dev); 2707 } 2708 sbicdumpstate(); 2709 } 2710 dev->sc_dmatimo++; 2711 } 2712 splx(s); 2713 timeout((void *)sbictimeout, dev, 30 * hz); 2714 } 2715 2716 void 2717 sbic_dump_acb(acb) 2718 struct sbic_acb *acb; 2719 { 2720 u_char *b = (u_char *) &acb->cmd; 2721 int i; 2722 2723 printf("acb@%x ", acb); 2724 if (acb->xs == NULL) { 2725 printf("<unused>\n"); 2726 return; 2727 } 2728 printf("(%d:%d) flags %2x clen %2d cmd ", acb->xs->sc_link->target, 2729 acb->xs->sc_link->lun, acb->flags, acb->clen); 2730 for (i = acb->clen; i; --i) 2731 printf(" %02x", *b++); 2732 printf("\n"); 2733 printf(" xs: %08x data %8x:%04x ", acb->xs, acb->xs->data, 2734 acb->xs->datalen); 2735 printf("va %8x:%04x ", acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 2736 printf("pa %8x:%04x tcnt %x\n", acb->sc_pa.dc_addr, acb->sc_pa.dc_count, 2737 acb->sc_tcnt); 2738 } 2739 2740 void 2741 sbic_dump(dev) 2742 struct sbic_softc *dev; 2743 { 2744 sbic_regmap_p regs; 2745 u_char csr, asr; 2746 struct sbic_acb *acb; 2747 int s; 2748 int i; 2749 2750 s = splbio(); 2751 regs = dev->sc_sbicp; 2752 #if CSR_TRACE_SIZE 2753 printf("csr trace: "); 2754 i = csr_traceptr; 2755 do { 2756 printf("%c%02x%02x%02x ", csr_trace[i].whr, 2757 csr_trace[i].csr, csr_trace[i].asr, csr_trace[i].xtn); 2758 switch(csr_trace[i].whr) { 2759 case 'g': 2760 printf("go "); break; 2761 case 's': 2762 printf("select "); break; 2763 case 'y': 2764 printf("select+ "); break; 2765 case 'i': 2766 printf("intr "); break; 2767 case 'f': 2768 printf("finish "); break; 2769 case '>': 2770 printf("out "); break; 2771 case '<': 2772 printf("in "); break; 2773 case 'm': 2774 printf("msgin "); break; 2775 case 'x': 2776 printf("msginx "); break; 2777 case 'X': 2778 printf("msginX "); break; 2779 case 'r': 2780 printf("reselect "); break; 2781 case 'I': 2782 printf("icmd "); break; 2783 case 'a': 2784 printf("abort "); break; 2785 default: 2786 printf("? "); 2787 } 2788 switch(csr_trace[i].csr) { 2789 case 0x11: 2790 printf("INITIATOR"); break; 2791 case 0x16: 2792 printf("S_XFERRED"); break; 2793 case 0x20: 2794 printf("MSGIN_ACK"); break; 2795 case 0x41: 2796 printf("DISC"); break; 2797 case 0x42: 2798 printf("SEL_TIMEO"); break; 2799 case 0x80: 2800 printf("RSLT_NI"); break; 2801 case 0x81: 2802 printf("RSLT_IFY"); break; 2803 case 0x85: 2804 printf("DISC_1"); break; 2805 case 0x18: case 0x19: case 0x1a: 2806 case 0x1b: case 0x1e: case 0x1f: 2807 case 0x28: case 0x29: case 0x2a: 2808 case 0x2b: case 0x2e: case 0x2f: 2809 case 0x48: case 0x49: case 0x4a: 2810 case 0x4b: case 0x4e: case 0x4f: 2811 case 0x88: case 0x89: case 0x8a: 2812 case 0x8b: case 0x8e: case 0x8f: 2813 switch(csr_trace[i].csr & 0xf0) { 2814 case 0x10: 2815 printf("DONE_"); break; 2816 case 0x20: 2817 printf("STOP_"); break; 2818 case 0x40: 2819 printf("ERR_"); break; 2820 case 0x80: 2821 printf("REQ_"); break; 2822 } 2823 switch(csr_trace[i].csr & 7) { 2824 case 0: 2825 printf("DATA_OUT"); break; 2826 case 1: 2827 printf("DATA_IN"); break; 2828 case 2: 2829 printf("CMD"); break; 2830 case 3: 2831 printf("STATUS"); break; 2832 case 6: 2833 printf("MSG_OUT"); break; 2834 case 7: 2835 printf("MSG_IN"); break; 2836 default: 2837 printf("invld phs"); 2838 } 2839 break; 2840 default: printf("****"); break; 2841 } 2842 if (csr_trace[i].asr & SBIC_ASR_INT) 2843 printf(" ASR_INT"); 2844 if (csr_trace[i].asr & SBIC_ASR_LCI) 2845 printf(" ASR_LCI"); 2846 if (csr_trace[i].asr & SBIC_ASR_BSY) 2847 printf(" ASR_BSY"); 2848 if (csr_trace[i].asr & SBIC_ASR_CIP) 2849 printf(" ASR_CIP"); 2850 printf("\n"); 2851 i = (i + 1) & (CSR_TRACE_SIZE - 1); 2852 } while (i != csr_traceptr); 2853 #endif 2854 GET_SBIC_asr(regs, asr); 2855 if ((asr & SBIC_ASR_INT) == 0) 2856 GET_SBIC_csr(regs, csr); 2857 else 2858 csr = 0; 2859 printf("%s@%x regs %x asr %x csr %x\n", dev->sc_dev.dv_xname, 2860 dev, regs, asr, csr); 2861 if (acb = dev->free_list.tqh_first) { 2862 printf("Free list:\n"); 2863 while (acb) { 2864 sbic_dump_acb(acb); 2865 acb = acb->chain.tqe_next; 2866 } 2867 } 2868 if (acb = dev->ready_list.tqh_first) { 2869 printf("Ready list:\n"); 2870 while (acb) { 2871 sbic_dump_acb(acb); 2872 acb = acb->chain.tqe_next; 2873 } 2874 } 2875 if (acb = dev->nexus_list.tqh_first) { 2876 printf("Nexus list:\n"); 2877 while (acb) { 2878 sbic_dump_acb(acb); 2879 acb = acb->chain.tqe_next; 2880 } 2881 } 2882 if (dev->sc_nexus) { 2883 printf("nexus:\n"); 2884 sbic_dump_acb(dev->sc_nexus); 2885 } 2886 printf("sc_xs %x targ %d lun %d flags %x tcnt %x dmacmd %x mask %x\n", 2887 dev->sc_xs, dev->target, dev->lun, dev->sc_flags, dev->sc_tcnt, 2888 dev->sc_dmacmd, dev->sc_dmamask); 2889 for (i = 0; i < 8; ++i) { 2890 if (dev->sc_tinfo[i].cmds > 2) { 2891 printf("tgt %d: cmds %d disc %d senses %d lubusy %x\n", 2892 i, dev->sc_tinfo[i].cmds, 2893 dev->sc_tinfo[i].dconns, 2894 dev->sc_tinfo[i].senses, 2895 dev->sc_tinfo[i].lubusy); 2896 } 2897 } 2898 splx(s); 2899 } 2900 2901 #endif 2902
Indexes created Thu Oct 02 14:10:14 GMT 2025