sbic.c revision 1.23
1 /* $NetBSD: sbic.c,v 1.23 1996/04/21 21:12:21 veego Exp $ */ 2 3 /* 4 * Copyright (c) 1994 Christian E. Hopps 5 * Copyright (c) 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * Van Jacobson of Lawrence Berkeley Laboratory. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the University of 22 * California, Berkeley and its contributors. 23 * 4. Neither the name of the University nor the names of its contributors 24 * may be used to endorse or promote products derived from this software 25 * without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 37 * SUCH DAMAGE. 38 * 39 * @(#)scsi.c 7.5 (Berkeley) 5/4/91 40 */ 41 42 /* 43 * AMIGA AMD 33C93 scsi adaptor driver 44 */ 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/device.h> 49 #include <sys/kernel.h> /* For hz */ 50 #include <sys/disklabel.h> 51 #include <sys/dkstat.h> 52 #include <sys/buf.h> 53 #include <scsi/scsi_all.h> 54 #include <scsi/scsiconf.h> 55 #include <vm/vm.h> 56 #include <vm/vm_kern.h> 57 #include <vm/vm_page.h> 58 #include <machine/pmap.h> 59 #include <machine/cpu.h> 60 #include <amiga/amiga/device.h> 61 #include <amiga/amiga/custom.h> 62 #include <amiga/amiga/isr.h> 63 #include <amiga/dev/dmavar.h> 64 #include <amiga/dev/sbicreg.h> 65 #include <amiga/dev/sbicvar.h> 66 67 /* These are for bounce buffers */ 68 #include <amiga/amiga/cc.h> 69 #include <amiga/dev/zbusvar.h> 70 71 #include <vm/pmap.h> 72 73 /* Since I can't find this in any other header files */ 74 #define SCSI_PHASE(reg) (reg&0x07) 75 76 /* 77 * SCSI delays 78 * In u-seconds, primarily for state changes on the SPC. 79 */ 80 #define SBIC_CMD_WAIT 50000 /* wait per step of 'immediate' cmds */ 81 #define SBIC_DATA_WAIT 50000 /* wait per data in/out step */ 82 #define SBIC_INIT_WAIT 50000 /* wait per step (both) during init */ 83 84 #define b_cylin b_resid 85 #define SBIC_WAIT(regs, until, timeo) sbicwait(regs, until, timeo, __LINE__) 86 87 int sbicicmd __P((struct sbic_softc *, int, int, void *, int, void *, int)); 88 int sbicgo __P((struct sbic_softc *, struct scsi_xfer *)); 89 int sbicdmaok __P((struct sbic_softc *, struct scsi_xfer *)); 90 int sbicwait __P((sbic_regmap_p, char, int , int)); 91 int sbiccheckdmap __P((void *, u_long, u_long)); 92 int sbicselectbus __P((struct sbic_softc *, sbic_regmap_p, u_char, u_char, u_char)); 93 int sbicxfstart __P((sbic_regmap_p, int, u_char, int)); 94 int sbicxfout __P((sbic_regmap_p regs, int, void *, int)); 95 int sbicfromscsiperiod __P((struct sbic_softc *, sbic_regmap_p, int)); 96 int sbictoscsiperiod __P((struct sbic_softc *, sbic_regmap_p, int)); 97 int sbicpoll __P((struct sbic_softc *)); 98 int sbicnextstate __P((struct sbic_softc *, u_char, u_char)); 99 int sbicmsgin __P((struct sbic_softc *)); 100 int sbicxfin __P((sbic_regmap_p regs, int, void *)); 101 int sbicabort __P((struct sbic_softc *, sbic_regmap_p, char *)); 102 void sbicxfdone __P((struct sbic_softc *, sbic_regmap_p, int)); 103 void sbicerror __P((struct sbic_softc *, sbic_regmap_p, u_char)); 104 void sbicstart __P((struct sbic_softc *)); 105 void sbicreset __P((struct sbic_softc *)); 106 void sbic_scsidone __P((struct sbic_acb *, int)); 107 void sbic_sched __P((struct sbic_softc *)); 108 void sbic_save_ptrs __P((struct sbic_softc *, sbic_regmap_p,int,int)); 109 void sbic_load_ptrs __P((struct sbic_softc *, sbic_regmap_p,int,int)); 110 #ifdef DEBUG 111 void sbicdumpstate __P((void)); 112 void sbic_dump_acb __P((struct sbic_acb *)); 113 #endif 114 115 /* 116 * Synch xfer parameters, and timing conversions 117 */ 118 int sbic_min_period = SBIC_SYN_MIN_PERIOD; /* in cycles = f(ICLK,FSn) */ 119 int sbic_max_offset = SBIC_SYN_MAX_OFFSET; /* pure number */ 120 121 int sbic_cmd_wait = SBIC_CMD_WAIT; 122 int sbic_data_wait = SBIC_DATA_WAIT; 123 int sbic_init_wait = SBIC_INIT_WAIT; 124 125 /* 126 * was broken before.. now if you want this you get it for all drives 127 * on sbic controllers. 128 */ 129 u_char sbic_inhibit_sync[8]; 130 int sbic_enable_reselect = 1; 131 int sbic_clock_override = 0; 132 int sbic_no_dma = 0; 133 int sbic_parallel_operations = 1; 134 135 #ifdef DEBUG 136 sbic_regmap_p debug_sbic_regs; 137 int sbicdma_ops = 0; /* total DMA operations */ 138 int sbicdma_bounces = 0; /* number operations using bounce buffer */ 139 int sbicdma_hits = 0; /* number of DMA chains that were contiguous */ 140 int sbicdma_misses = 0; /* number of DMA chains that were not contiguous */ 141 int sbicdma_saves = 0; 142 #define QPRINTF(a) if (sbic_debug > 1) printf a 143 int sbic_debug = 0; 144 int sync_debug = 0; 145 int sbic_dma_debug = 0; 146 int reselect_debug = 0; 147 int report_sense = 0; 148 int data_pointer_debug = 0; 149 u_char debug_asr, debug_csr, routine; 150 void sbictimeout __P((struct sbic_softc *dev)); 151 152 #define CSR_TRACE_SIZE 32 153 #if CSR_TRACE_SIZE 154 #define CSR_TRACE(w,c,a,x) do { \ 155 int s = splbio(); \ 156 csr_trace[csr_traceptr].whr = (w); csr_trace[csr_traceptr].csr = (c); \ 157 csr_trace[csr_traceptr].asr = (a); csr_trace[csr_traceptr].xtn = (x); \ 158 dma_cachectl((caddr_t)&csr_trace[csr_traceptr], sizeof(csr_trace[0])); \ 159 csr_traceptr = (csr_traceptr + 1) & (CSR_TRACE_SIZE - 1); \ 160 /* dma_cachectl((caddr_t)&csr_traceptr, sizeof(csr_traceptr));*/ \ 161 splx(s); \ 162 } while (0) 163 int csr_traceptr; 164 int csr_tracesize = CSR_TRACE_SIZE; 165 struct { 166 u_char whr; 167 u_char csr; 168 u_char asr; 169 u_char xtn; 170 } csr_trace[CSR_TRACE_SIZE]; 171 #else 172 #define CSR_TRACE(w,c,a,x) 173 #endif 174 175 #define SBIC_TRACE_SIZE 0 176 #if SBIC_TRACE_SIZE 177 #define SBIC_TRACE(dev) do { \ 178 int s = splbio(); \ 179 sbic_trace[sbic_traceptr].sp = &s; \ 180 sbic_trace[sbic_traceptr].line = __LINE__; \ 181 sbic_trace[sbic_traceptr].sr = s; \ 182 sbic_trace[sbic_traceptr].csr = csr_traceptr; \ 183 dma_cachectl(&sbic_trace[sbic_traceptr], sizeof(sbic_trace[0])); \ 184 sbic_traceptr = (sbic_traceptr + 1) & (SBIC_TRACE_SIZE - 1); \ 185 dma_cachectl(&sbic_traceptr, sizeof(sbic_traceptr)); \ 186 if (dev) dma_cachectl(dev, sizeof(*dev)); \ 187 splx(s); \ 188 } while (0) 189 int sbic_traceptr; 190 int sbic_tracesize = SBIC_TRACE_SIZE; 191 struct { 192 void *sp; 193 u_short line; 194 u_short sr; 195 int csr; 196 } sbic_trace[SBIC_TRACE_SIZE]; 197 #else 198 #define SBIC_TRACE(dev) 199 #endif 200 201 #else /* DEBUG */ 202 #define QPRINTF(a) 203 #define CSR_TRACE(w,c,a,x) 204 #define SBIC_TRACE(dev) 205 #endif /* DEBUG */ 206 207 /* 208 * default minphys routine for sbic based controllers 209 */ 210 void 211 sbic_minphys(bp) 212 struct buf *bp; 213 { 214 215 /* 216 * No max transfer at this level. 217 */ 218 minphys(bp); 219 } 220 221 /* 222 * Save DMA pointers. Take into account partial transfer. Shut down DMA. 223 */ 224 void 225 sbic_save_ptrs(dev, regs, target, lun) 226 struct sbic_softc *dev; 227 sbic_regmap_p regs; 228 int target, lun; 229 { 230 int count, asr, s; 231 struct sbic_acb* acb; 232 233 SBIC_TRACE(dev); 234 if( !dev->sc_cur ) return; 235 if( !(dev->sc_flags & SBICF_INDMA) ) return; /* DMA not active */ 236 237 s = splbio(); 238 239 acb = dev->sc_nexus; 240 count = -1; 241 do { 242 GET_SBIC_asr(regs, asr); 243 if( asr & SBIC_ASR_DBR ) { 244 printf("sbic_save_ptrs: asr %02x canceled!\n", asr); 245 splx(s); 246 SBIC_TRACE(dev); 247 return; 248 } 249 } while( asr & (SBIC_ASR_BSY|SBIC_ASR_CIP) ); 250 251 /* Save important state */ 252 /* must be done before dmastop */ 253 acb->sc_dmacmd = dev->sc_dmacmd; 254 SBIC_TC_GET(regs, count); 255 256 /* Shut down DMA ====CAREFUL==== */ 257 dev->sc_dmastop(dev); 258 dev->sc_flags &= ~SBICF_INDMA; 259 SBIC_TC_PUT(regs, 0); 260 261 #ifdef DEBUG 262 if(!count && sbic_debug) printf("%dcount0",target); 263 if(data_pointer_debug == -1) 264 printf("SBIC saving target %d data pointers from (%p,%x)%xASR:%02x", 265 target, dev->sc_cur->dc_addr, dev->sc_cur->dc_count, 266 acb->sc_dmacmd, asr); 267 #endif 268 269 /* Fixup partial xfers */ 270 acb->sc_kv.dc_addr += (dev->sc_tcnt - count); 271 acb->sc_kv.dc_count -= (dev->sc_tcnt - count); 272 acb->sc_pa.dc_addr += (dev->sc_tcnt - count); 273 acb->sc_pa.dc_count -= ((dev->sc_tcnt - count)>>1); 274 275 acb->sc_tcnt = dev->sc_tcnt = count; 276 #ifdef DEBUG 277 if(data_pointer_debug) 278 printf(" at (%p,%x):%x\n", 279 dev->sc_cur->dc_addr, dev->sc_cur->dc_count,count); 280 sbicdma_saves++; 281 #endif 282 splx(s); 283 SBIC_TRACE(dev); 284 } 285 286 287 /* 288 * DOES NOT RESTART DMA!!! 289 */ 290 void sbic_load_ptrs(dev, regs, target, lun) 291 struct sbic_softc *dev; 292 sbic_regmap_p regs; 293 int target, lun; 294 { 295 int s, count; 296 char* vaddr, * paddr; 297 struct sbic_acb *acb; 298 299 SBIC_TRACE(dev); 300 acb = dev->sc_nexus; 301 if( !acb->sc_kv.dc_count ) { 302 /* No data to xfer */ 303 SBIC_TRACE(dev); 304 return; 305 } 306 307 s = splbio(); 308 309 dev->sc_last = dev->sc_cur = &acb->sc_pa; 310 dev->sc_tcnt = acb->sc_tcnt; 311 dev->sc_dmacmd = acb->sc_dmacmd; 312 313 #ifdef DEBUG 314 sbicdma_ops++; 315 #endif 316 if( !dev->sc_tcnt ) { 317 /* sc_tcnt == 0 implies end of segment */ 318 319 /* do kvm to pa mappings */ 320 paddr = acb->sc_pa.dc_addr = 321 (char *) kvtop(acb->sc_kv.dc_addr); 322 323 vaddr = acb->sc_kv.dc_addr; 324 count = acb->sc_kv.dc_count; 325 for(count = (NBPG - ((int)vaddr & PGOFSET)); 326 count < acb->sc_kv.dc_count 327 && (char*)kvtop(vaddr + count + 4) == paddr + count + 4; 328 count += NBPG); 329 /* If it's all contiguous... */ 330 if(count > acb->sc_kv.dc_count ) { 331 count = acb->sc_kv.dc_count; 332 #ifdef DEBUG 333 sbicdma_hits++; 334 #endif 335 } else { 336 #ifdef DEBUG 337 sbicdma_misses++; 338 #endif 339 } 340 acb->sc_tcnt = count; 341 acb->sc_pa.dc_count = count >> 1; 342 343 #ifdef DEBUG 344 if(data_pointer_debug) 345 printf("DMA recalc:kv(%p,%x)pa(%p,%lx)\n", 346 acb->sc_kv.dc_addr, 347 acb->sc_kv.dc_count, 348 acb->sc_pa.dc_addr, 349 acb->sc_tcnt); 350 #endif 351 } 352 splx(s); 353 #ifdef DEBUG 354 if(data_pointer_debug) 355 printf("SBIC restoring target %d data pointers at (%p,%x)%x\n", 356 target, dev->sc_cur->dc_addr, dev->sc_cur->dc_count, 357 dev->sc_dmacmd); 358 #endif 359 SBIC_TRACE(dev); 360 } 361 362 /* 363 * used by specific sbic controller 364 * 365 * it appears that the higher level code does nothing with LUN's 366 * so I will too. I could plug it in, however so could they 367 * in scsi_scsi_cmd(). 368 */ 369 int 370 sbic_scsicmd(xs) 371 struct scsi_xfer *xs; 372 { 373 struct sbic_acb *acb; 374 struct sbic_softc *dev; 375 struct scsi_link *slp; 376 int flags, s, stat; 377 378 slp = xs->sc_link; 379 dev = slp->adapter_softc; 380 SBIC_TRACE(dev); 381 flags = xs->flags; 382 383 if (flags & SCSI_DATA_UIO) 384 panic("sbic: scsi data uio requested"); 385 386 if (dev->sc_nexus && flags & SCSI_POLL) 387 panic("sbic_scsicmd: busy"); 388 389 if (slp->target == slp->adapter_target) 390 return ESCAPE_NOT_SUPPORTED; 391 392 s = splbio(); 393 acb = dev->free_list.tqh_first; 394 if (acb) 395 TAILQ_REMOVE(&dev->free_list, acb, chain); 396 splx(s); 397 398 if (acb == NULL) { 399 #ifdef DEBUG 400 printf("sbic_scsicmd: unable to queue request for target %d\n", 401 slp->target); 402 #ifdef DDB 403 Debugger(); 404 #endif 405 #endif 406 xs->error = XS_DRIVER_STUFFUP; 407 SBIC_TRACE(dev); 408 return(TRY_AGAIN_LATER); 409 } 410 411 acb->flags = ACB_ACTIVE; 412 if (flags & SCSI_DATA_IN) 413 acb->flags |= ACB_DATAIN; 414 acb->xs = xs; 415 bcopy(xs->cmd, &acb->cmd, xs->cmdlen); 416 acb->clen = xs->cmdlen; 417 acb->sc_kv.dc_addr = xs->data; 418 acb->sc_kv.dc_count = xs->datalen; 419 acb->pa_addr = xs->data ? (char *)kvtop(xs->data) : 0; /* XXXX check */ 420 421 if (flags & SCSI_POLL) { 422 s = splbio(); 423 /* 424 * This has major side effects -- it locks up the machine 425 */ 426 427 dev->sc_flags |= SBICF_ICMD; 428 do { 429 while(dev->sc_nexus) 430 sbicpoll(dev); 431 dev->sc_nexus = acb; 432 dev->sc_stat[0] = -1; 433 dev->sc_xs = xs; 434 dev->target = slp->target; 435 dev->lun = slp->lun; 436 stat = sbicicmd(dev, slp->target, slp->lun, 437 &acb->cmd, acb->clen, 438 acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 439 } while (dev->sc_nexus != acb); 440 sbic_scsidone(acb, stat); 441 442 splx(s); 443 SBIC_TRACE(dev); 444 return(COMPLETE); 445 } 446 447 s = splbio(); 448 TAILQ_INSERT_TAIL(&dev->ready_list, acb, chain); 449 450 if (dev->sc_nexus) { 451 splx(s); 452 SBIC_TRACE(dev); 453 return(SUCCESSFULLY_QUEUED); 454 } 455 456 /* 457 * nothing is active, try to start it now. 458 */ 459 sbic_sched(dev); 460 splx(s); 461 462 SBIC_TRACE(dev); 463 /* TODO: add sbic_poll to do SCSI_POLL operations */ 464 #if 0 465 if (flags & SCSI_POLL) 466 return(COMPLETE); 467 #endif 468 return(SUCCESSFULLY_QUEUED); 469 } 470 471 /* 472 * attempt to start the next available command 473 */ 474 void 475 sbic_sched(dev) 476 struct sbic_softc *dev; 477 { 478 struct scsi_xfer *xs; 479 struct scsi_link *slp; 480 struct sbic_acb *acb; 481 int flags, /*phase,*/ stat, i; 482 483 SBIC_TRACE(dev); 484 if (dev->sc_nexus) 485 return; /* a command is current active */ 486 487 SBIC_TRACE(dev); 488 for (acb = dev->ready_list.tqh_first; acb; acb = acb->chain.tqe_next) { 489 slp = acb->xs->sc_link; 490 i = slp->target; 491 if (!(dev->sc_tinfo[i].lubusy & (1 << slp->lun))) { 492 struct sbic_tinfo *ti = &dev->sc_tinfo[i]; 493 494 TAILQ_REMOVE(&dev->ready_list, acb, chain); 495 dev->sc_nexus = acb; 496 slp = acb->xs->sc_link; 497 ti = &dev->sc_tinfo[slp->target]; 498 ti->lubusy |= (1 << slp->lun); 499 acb->sc_pa.dc_addr = acb->pa_addr; /* XXXX check */ 500 break; 501 } 502 } 503 504 SBIC_TRACE(dev); 505 if (acb == NULL) 506 return; /* did not find an available command */ 507 508 dev->sc_xs = xs = acb->xs; 509 slp = xs->sc_link; 510 flags = xs->flags; 511 512 if (flags & SCSI_RESET) 513 sbicreset(dev); 514 515 #ifdef DEBUG 516 if( data_pointer_debug > 1 ) 517 printf("sbic_sched(%d,%d)\n",slp->target,slp->lun); 518 #endif 519 dev->sc_stat[0] = -1; 520 dev->target = slp->target; 521 dev->lun = slp->lun; 522 if ( flags & SCSI_POLL || ( !sbic_parallel_operations 523 && (/*phase == STATUS_PHASE ||*/ 524 sbicdmaok(dev, xs) == 0) ) ) 525 stat = sbicicmd(dev, slp->target, slp->lun, &acb->cmd, 526 acb->clen, acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 527 else if (sbicgo(dev, xs) == 0) { 528 SBIC_TRACE(dev); 529 return; 530 } else 531 stat = dev->sc_stat[0]; 532 533 sbic_scsidone(acb, stat); 534 SBIC_TRACE(dev); 535 } 536 537 void 538 sbic_scsidone(acb, stat) 539 struct sbic_acb *acb; 540 int stat; 541 { 542 struct scsi_xfer *xs; 543 struct scsi_link *slp; 544 struct sbic_softc *dev; 545 int dosched = 0; 546 547 xs = acb->xs; 548 slp = xs->sc_link; 549 dev = slp->adapter_softc; 550 SBIC_TRACE(dev); 551 #ifdef DIAGNOSTIC 552 if (acb == NULL || xs == NULL) { 553 printf("sbic_scsidone -- (%d,%d) no scsi_xfer\n", 554 dev->target, dev->lun); 555 #ifdef DDB 556 Debugger(); 557 #endif 558 return; 559 } 560 #endif 561 /* 562 * XXX Support old-style instrumentation for now. 563 * IS THIS REALLY THE RIGHT PLACE FOR THIS? --thorpej 564 */ 565 if (slp->device_softc && 566 ((struct device *)(slp->device_softc))->dv_unit < dk_ndrive) 567 ++dk_xfer[((struct device *)(slp->device_softc))->dv_unit]; 568 /* 569 * is this right? 570 */ 571 xs->status = stat; 572 573 #ifdef DEBUG 574 if( data_pointer_debug > 1 ) 575 printf("scsidone: (%d,%d)->(%d,%d)%02x\n", 576 slp->target, slp->lun, 577 dev->target, dev->lun, stat); 578 if( xs->sc_link->target == dev->sc_link.adapter_target ) 579 panic("target == hostid"); 580 #endif 581 582 if (xs->error == XS_NOERROR && !(acb->flags & ACB_CHKSENSE)) { 583 if (stat == SCSI_CHECK) { 584 /* Schedule a REQUEST SENSE */ 585 struct scsi_sense *ss = (void *)&acb->cmd; 586 #ifdef DEBUG 587 if (report_sense) 588 printf("sbic_scsidone: autosense %02x targ %d lun %d", 589 acb->cmd.opcode, slp->target, slp->lun); 590 #endif 591 bzero(ss, sizeof(*ss)); 592 ss->opcode = REQUEST_SENSE; 593 ss->byte2 = slp->lun << 5; 594 ss->length = sizeof(struct scsi_sense_data); 595 acb->clen = sizeof(*ss); 596 acb->sc_kv.dc_addr = (char *)&xs->sense; 597 acb->sc_kv.dc_count = sizeof(struct scsi_sense_data); 598 acb->pa_addr = (char *)kvtop((u_char *)&xs->sense); /* XXX check */ 599 acb->flags = ACB_ACTIVE | ACB_CHKSENSE | ACB_DATAIN; 600 TAILQ_INSERT_HEAD(&dev->ready_list, acb, chain); 601 dev->sc_tinfo[slp->target].lubusy &= 602 ~(1 << slp->lun); 603 dev->sc_tinfo[slp->target].senses++; 604 if (dev->sc_nexus == acb) { 605 dev->sc_nexus = NULL; 606 dev->sc_xs = NULL; 607 sbic_sched(dev); 608 } 609 SBIC_TRACE(dev); 610 return; 611 } 612 } 613 if (xs->error == XS_NOERROR && (acb->flags & ACB_CHKSENSE)) { 614 xs->error = XS_SENSE; 615 #ifdef DEBUG 616 if (report_sense) 617 printf(" => %02x %02x\n", xs->sense.flags, 618 xs->sense.extra_bytes[3]); 619 #endif 620 } else { 621 xs->resid = 0; /* XXXX */ 622 } 623 #if whataboutthisone 624 case SCSI_BUSY: 625 xs->error = XS_BUSY; 626 break; 627 #endif 628 xs->flags |= ITSDONE; 629 630 /* 631 * Remove the ACB from whatever queue it's on. We have to do a bit of 632 * a hack to figure out which queue it's on. Note that it is *not* 633 * necessary to cdr down the ready queue, but we must cdr down the 634 * nexus queue and see if it's there, so we can mark the unit as no 635 * longer busy. This code is sickening, but it works. 636 */ 637 if (acb == dev->sc_nexus) { 638 dev->sc_nexus = NULL; 639 dev->sc_xs = NULL; 640 dev->sc_tinfo[slp->target].lubusy &= ~(1<<slp->lun); 641 if (dev->ready_list.tqh_first) 642 dosched = 1; /* start next command */ 643 } else if (dev->ready_list.tqh_last == &acb->chain.tqe_next) { 644 TAILQ_REMOVE(&dev->ready_list, acb, chain); 645 } else { 646 register struct sbic_acb *acb2; 647 for (acb2 = dev->nexus_list.tqh_first; acb2; 648 acb2 = acb2->chain.tqe_next) { 649 if (acb2 == acb) { 650 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 651 dev->sc_tinfo[slp->target].lubusy 652 &= ~(1<<slp->lun); 653 break; 654 } 655 } 656 if (acb2) 657 ; 658 else if (acb->chain.tqe_next) { 659 TAILQ_REMOVE(&dev->ready_list, acb, chain); 660 } else { 661 printf("%s: can't find matching acb\n", 662 dev->sc_dev.dv_xname); 663 #ifdef DDB 664 Debugger(); 665 #endif 666 } 667 } 668 /* Put it on the free list. */ 669 acb->flags = ACB_FREE; 670 TAILQ_INSERT_HEAD(&dev->free_list, acb, chain); 671 672 dev->sc_tinfo[slp->target].cmds++; 673 674 scsi_done(xs); 675 676 if (dosched) 677 sbic_sched(dev); 678 SBIC_TRACE(dev); 679 } 680 681 int 682 sbicdmaok(dev, xs) 683 struct sbic_softc *dev; 684 struct scsi_xfer *xs; 685 { 686 if (sbic_no_dma || xs->datalen & 0x1 || (u_int)xs->data & 0x3) 687 return(0); 688 /* 689 * controller supports dma to any addresses? 690 */ 691 else if ((dev->sc_flags & SBICF_BADDMA) == 0) 692 return(1); 693 /* 694 * this address is ok for dma? 695 */ 696 else if (sbiccheckdmap(xs->data, xs->datalen, dev->sc_dmamask) == 0) 697 return(1); 698 /* 699 * we have a bounce buffer? 700 */ 701 else if (dev->sc_tinfo[xs->sc_link->target].bounce) 702 return(1); 703 /* 704 * try to get one 705 */ 706 else if ((dev->sc_tinfo[xs->sc_link->target].bounce 707 = (char *)alloc_z2mem(MAXPHYS))) { 708 if (isztwomem(dev->sc_tinfo[xs->sc_link->target].bounce)) 709 printf("alloc ZII target %d bounce pa 0x%x\n", 710 xs->sc_link->target, 711 kvtop(dev->sc_tinfo[xs->sc_link->target].bounce)); 712 else if (dev->sc_tinfo[xs->sc_link->target].bounce) 713 printf("alloc CHIP target %d bounce pa 0x%p\n", 714 xs->sc_link->target, 715 PREP_DMA_MEM(dev->sc_tinfo[xs->sc_link->target].bounce)); 716 return(1); 717 } 718 719 return(0); 720 } 721 722 723 int 724 sbicwait(regs, until, timeo, line) 725 sbic_regmap_p regs; 726 char until; 727 int timeo; 728 int line; 729 { 730 u_char val; 731 int csr; 732 733 SBIC_TRACE((struct sbic_softc *)0); 734 if (timeo == 0) 735 timeo = 1000000; /* some large value.. */ 736 737 GET_SBIC_asr(regs,val); 738 while ((val & until) == 0) { 739 if (timeo-- == 0) { 740 GET_SBIC_csr(regs, csr); 741 printf("sbicwait TIMEO @%d with asr=x%x csr=x%x\n", 742 line, val, csr); 743 #if defined(DDB) && defined(DEBUG) 744 Debugger(); 745 #endif 746 return(val); /* Maybe I should abort */ 747 break; 748 } 749 DELAY(1); 750 GET_SBIC_asr(regs,val); 751 } 752 SBIC_TRACE((struct sbic_softc *)0); 753 return(val); 754 } 755 756 int 757 sbicabort(dev, regs, where) 758 struct sbic_softc *dev; 759 sbic_regmap_p regs; 760 char *where; 761 { 762 u_char csr, asr; 763 764 GET_SBIC_asr(regs, asr); 765 GET_SBIC_csr(regs, csr); 766 767 printf ("%s: abort %s: csr = 0x%02x, asr = 0x%02x\n", 768 dev->sc_dev.dv_xname, where, csr, asr); 769 770 771 #if 0 772 /* Clean up running command */ 773 if (dev->sc_nexus != NULL) { 774 dev->sc_nexus->xs->error = XS_DRIVER_STUFFUP; 775 sbic_scsidone(dev->sc_nexus, dev->sc_stat[0]); 776 } 777 while (acb = dev->nexus_list.tqh_first) { 778 acb->xs->error = XS_DRIVER_STUFFUP; 779 sbic_scsidone(acb, -1 /*acb->stat[0]*/); 780 } 781 #endif 782 783 /* Clean up chip itself */ 784 if (dev->sc_flags & SBICF_SELECTED) { 785 while( asr & SBIC_ASR_DBR ) { 786 /* sbic is jammed w/data. need to clear it */ 787 /* But we don't know what direction it needs to go */ 788 GET_SBIC_data(regs, asr); 789 printf("%s: abort %s: clearing data buffer 0x%02x\n", 790 dev->sc_dev.dv_xname, where, asr); 791 GET_SBIC_asr(regs, asr); 792 if( asr & SBIC_ASR_DBR ) /* Not the read direction, then */ 793 SET_SBIC_data(regs, asr); 794 GET_SBIC_asr(regs, asr); 795 } 796 WAIT_CIP(regs); 797 printf("%s: sbicabort - sending ABORT command\n", dev->sc_dev.dv_xname); 798 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 799 WAIT_CIP(regs); 800 801 GET_SBIC_asr(regs, asr); 802 if (asr & (SBIC_ASR_BSY|SBIC_ASR_LCI)) { 803 /* ok, get more drastic.. */ 804 805 printf("%s: sbicabort - asr %x, trying to reset\n", dev->sc_dev.dv_xname, asr); 806 sbicreset(dev); 807 dev->sc_flags &= ~SBICF_SELECTED; 808 return -1; 809 } 810 printf("%s: sbicabort - sending DISC command\n", dev->sc_dev.dv_xname); 811 SET_SBIC_cmd(regs, SBIC_CMD_DISC); 812 813 do { 814 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0); 815 GET_SBIC_csr (regs, csr); 816 CSR_TRACE('a',csr,asr,0); 817 } while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) 818 && (csr != SBIC_CSR_CMD_INVALID)); 819 820 /* lets just hope it worked.. */ 821 dev->sc_flags &= ~SBICF_SELECTED; 822 } 823 return -1; 824 } 825 826 827 /* 828 * Initialize driver-private structures 829 */ 830 831 void 832 sbicinit(dev) 833 struct sbic_softc *dev; 834 { 835 sbic_regmap_p regs; 836 u_int i; 837 struct sbic_acb *acb; 838 u_int inhibit_sync; 839 840 extern u_long scsi_nosync; 841 extern int shift_nosync; 842 843 regs = dev->sc_sbicp; 844 845 if ((dev->sc_flags & SBICF_ALIVE) == 0) { 846 TAILQ_INIT(&dev->ready_list); 847 TAILQ_INIT(&dev->nexus_list); 848 TAILQ_INIT(&dev->free_list); 849 dev->sc_nexus = NULL; 850 dev->sc_xs = NULL; 851 acb = dev->sc_acb; 852 bzero(acb, sizeof(dev->sc_acb)); 853 for (i = 0; i < sizeof(dev->sc_acb) / sizeof(*acb); i++) { 854 TAILQ_INSERT_TAIL(&dev->free_list, acb, chain); 855 acb++; 856 } 857 bzero(dev->sc_tinfo, sizeof(dev->sc_tinfo)); 858 #ifdef DEBUG 859 /* make sure timeout is really not needed */ 860 timeout((void *)sbictimeout, dev, 30 * hz); 861 #endif 862 863 } else panic("sbic: reinitializing driver!"); 864 865 dev->sc_flags |= SBICF_ALIVE; 866 dev->sc_flags &= ~SBICF_SELECTED; 867 868 /* initialize inhibit array */ 869 if (scsi_nosync) { 870 inhibit_sync = (scsi_nosync >> shift_nosync) & 0xff; 871 shift_nosync += 8; 872 #ifdef DEBUG 873 if (inhibit_sync) 874 printf("%s: Inhibiting synchronous transfer %02x\n", 875 dev->sc_dev.dv_xname, inhibit_sync); 876 #endif 877 for (i = 0; i < 8; ++i) 878 if (inhibit_sync & (1 << i)) 879 sbic_inhibit_sync[i] = 1; 880 } 881 882 sbicreset(dev); 883 } 884 885 void 886 sbicreset(dev) 887 struct sbic_softc *dev; 888 { 889 sbic_regmap_p regs; 890 u_int my_id, s; 891 u_char csr; 892 #if 0 893 u_int i; 894 struct sbic_acb *acb; 895 #endif 896 897 regs = dev->sc_sbicp; 898 #if 0 899 if (dev->sc_flags & SBICF_ALIVE) { 900 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 901 WAIT_CIP(regs); 902 } 903 #else 904 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 905 WAIT_CIP(regs); 906 #endif 907 s = splbio(); 908 my_id = dev->sc_link.adapter_target & SBIC_ID_MASK; 909 910 /* Enable advanced mode */ 911 my_id |= SBIC_ID_EAF /*| SBIC_ID_EHP*/ ; 912 SET_SBIC_myid(regs, my_id); 913 914 /* 915 * Disable interrupts (in dmainit) then reset the chip 916 */ 917 SET_SBIC_cmd(regs, SBIC_CMD_RESET); 918 DELAY(25); 919 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 920 GET_SBIC_csr(regs, csr); /* clears interrupt also */ 921 922 if (dev->sc_clkfreq < 110) 923 my_id |= SBIC_ID_FS_8_10; 924 else if (dev->sc_clkfreq < 160) 925 my_id |= SBIC_ID_FS_12_15; 926 else if (dev->sc_clkfreq < 210) 927 my_id |= SBIC_ID_FS_16_20; 928 929 SET_SBIC_myid(regs, my_id); 930 931 /* 932 * Set up various chip parameters 933 */ 934 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI /* | SBIC_CTL_HSP */ 935 | SBIC_MACHINE_DMA_MODE); 936 /* 937 * don't allow (re)selection (SBIC_RID_ES) 938 * until we can handle target mode!! 939 */ 940 SET_SBIC_rselid(regs, SBIC_RID_ER); 941 SET_SBIC_syn(regs, 0); /* asynch for now */ 942 943 /* 944 * anything else was zeroed by reset 945 */ 946 splx(s); 947 948 #if 0 949 if ((dev->sc_flags & SBICF_ALIVE) == 0) { 950 TAILQ_INIT(&dev->ready_list); 951 TAILQ_INIT(&dev->nexus_list); 952 TAILQ_INIT(&dev->free_list); 953 dev->sc_nexus = NULL; 954 dev->sc_xs = NULL; 955 acb = dev->sc_acb; 956 bzero(acb, sizeof(dev->sc_acb)); 957 for (i = 0; i < sizeof(dev->sc_acb) / sizeof(*acb); i++) { 958 TAILQ_INSERT_TAIL(&dev->free_list, acb, chain); 959 acb++; 960 } 961 bzero(dev->sc_tinfo, sizeof(dev->sc_tinfo)); 962 } else { 963 if (dev->sc_nexus != NULL) { 964 dev->sc_nexus->xs->error = XS_DRIVER_STUFFUP; 965 sbic_scsidone(dev->sc_nexus, dev->sc_stat[0]); 966 } 967 while (acb = dev->nexus_list.tqh_first) { 968 acb->xs->error = XS_DRIVER_STUFFUP; 969 sbic_scsidone(acb, -1 /*acb->stat[0]*/); 970 } 971 } 972 973 dev->sc_flags |= SBICF_ALIVE; 974 #endif 975 dev->sc_flags &= ~SBICF_SELECTED; 976 } 977 978 void 979 sbicerror(dev, regs, csr) 980 struct sbic_softc *dev; 981 sbic_regmap_p regs; 982 u_char csr; 983 { 984 struct scsi_xfer *xs; 985 986 xs = dev->sc_xs; 987 988 #ifdef DIAGNOSTIC 989 if (xs == NULL) 990 panic("sbicerror"); 991 #endif 992 if (xs->flags & SCSI_SILENT) 993 return; 994 995 printf("%s: ", dev->sc_dev.dv_xname); 996 printf("csr == 0x%02x\n", csr); /* XXX */ 997 } 998 999 /* 1000 * select the bus, return when selected or error. 1001 */ 1002 int 1003 sbicselectbus(dev, regs, target, lun, our_addr) 1004 struct sbic_softc *dev; 1005 sbic_regmap_p regs; 1006 u_char target, lun, our_addr; 1007 { 1008 u_char asr, csr, id; 1009 1010 SBIC_TRACE(dev); 1011 QPRINTF(("sbicselectbus %d\n", target)); 1012 1013 /* 1014 * if we're already selected, return (XXXX panic maybe?) 1015 */ 1016 if (dev->sc_flags & SBICF_SELECTED) { 1017 SBIC_TRACE(dev); 1018 return(1); 1019 } 1020 1021 /* 1022 * issue select 1023 */ 1024 SBIC_TC_PUT(regs, 0); 1025 SET_SBIC_selid(regs, target); 1026 SET_SBIC_timeo(regs, SBIC_TIMEOUT(250,dev->sc_clkfreq)); 1027 1028 /* 1029 * set sync or async 1030 */ 1031 if (dev->sc_sync[target].state == SYNC_DONE) 1032 SET_SBIC_syn(regs, SBIC_SYN (dev->sc_sync[target].offset, 1033 dev->sc_sync[target].period)); 1034 else 1035 SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period)); 1036 1037 GET_SBIC_asr(regs, asr); 1038 if( asr & (SBIC_ASR_INT|SBIC_ASR_BSY) ) { 1039 /* This means we got ourselves reselected upon */ 1040 /* printf("sbicselectbus: INT/BSY asr %02x\n", asr);*/ 1041 #ifdef DDB 1042 /* Debugger();*/ 1043 #endif 1044 SBIC_TRACE(dev); 1045 return 1; 1046 } 1047 1048 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN); 1049 1050 /* 1051 * wait for select (merged from seperate function may need 1052 * cleanup) 1053 */ 1054 WAIT_CIP(regs); 1055 do { 1056 asr = SBIC_WAIT(regs, SBIC_ASR_INT | SBIC_ASR_LCI, 0); 1057 if (asr & SBIC_ASR_LCI) { 1058 #ifdef DEBUG 1059 if (reselect_debug) 1060 printf("sbicselectbus: late LCI asr %02x\n", asr); 1061 #endif 1062 SBIC_TRACE(dev); 1063 return 1; 1064 } 1065 GET_SBIC_csr (regs, csr); 1066 CSR_TRACE('s',csr,asr,target); 1067 QPRINTF(("%02x ", csr)); 1068 if( csr == SBIC_CSR_RSLT_NI || csr == SBIC_CSR_RSLT_IFY) { 1069 #ifdef DEBUG 1070 if(reselect_debug) 1071 printf("sbicselectbus: reselected asr %02x\n", asr); 1072 #endif 1073 /* We need to handle this now so we don't lock up later */ 1074 sbicnextstate(dev, csr, asr); 1075 SBIC_TRACE(dev); 1076 return 1; 1077 } 1078 if( csr == SBIC_CSR_SLT || csr == SBIC_CSR_SLT_ATN) { 1079 panic("sbicselectbus: target issued select!"); 1080 return 1; 1081 } 1082 } while (csr != (SBIC_CSR_MIS_2|MESG_OUT_PHASE) 1083 && csr != (SBIC_CSR_MIS_2|CMD_PHASE) && csr != SBIC_CSR_SEL_TIMEO); 1084 1085 /* Enable (or not) reselection */ 1086 if(!sbic_enable_reselect && dev->nexus_list.tqh_first == NULL) 1087 SET_SBIC_rselid (regs, 0); 1088 else 1089 SET_SBIC_rselid (regs, SBIC_RID_ER); 1090 1091 if (csr == (SBIC_CSR_MIS_2|CMD_PHASE)) { 1092 dev->sc_flags |= SBICF_SELECTED; /* device ignored ATN */ 1093 GET_SBIC_selid(regs, id); 1094 dev->target = id; 1095 GET_SBIC_tlun(regs,dev->lun); 1096 if( dev->lun & SBIC_TLUN_VALID ) 1097 dev->lun &= SBIC_TLUN_MASK; 1098 else 1099 dev->lun = lun; 1100 } else if (csr == (SBIC_CSR_MIS_2|MESG_OUT_PHASE)) { 1101 /* 1102 * Send identify message 1103 * (SCSI-2 requires an identify msg (?)) 1104 */ 1105 GET_SBIC_selid(regs, id); 1106 dev->target = id; 1107 GET_SBIC_tlun(regs,dev->lun); 1108 if( dev->lun & SBIC_TLUN_VALID ) 1109 dev->lun &= SBIC_TLUN_MASK; 1110 else 1111 dev->lun = lun; 1112 /* 1113 * handle drives that don't want to be asked 1114 * whether to go sync at all. 1115 */ 1116 if (sbic_inhibit_sync[id] 1117 && dev->sc_sync[id].state == SYNC_START) { 1118 #ifdef DEBUG 1119 if (sync_debug) 1120 printf("Forcing target %d asynchronous.\n", id); 1121 #endif 1122 dev->sc_sync[id].offset = 0; 1123 dev->sc_sync[id].period = sbic_min_period; 1124 dev->sc_sync[id].state = SYNC_DONE; 1125 } 1126 1127 1128 if (dev->sc_sync[id].state != SYNC_START){ 1129 if( dev->sc_xs->flags & SCSI_POLL 1130 || (dev->sc_flags & SBICF_ICMD) 1131 || !sbic_enable_reselect ) 1132 SEND_BYTE (regs, MSG_IDENTIFY | lun); 1133 else 1134 SEND_BYTE (regs, MSG_IDENTIFY_DR | lun); 1135 } else { 1136 /* 1137 * try to initiate a sync transfer. 1138 * So compose the sync message we're going 1139 * to send to the target 1140 */ 1141 1142 #ifdef DEBUG 1143 if (sync_debug) 1144 printf("Sending sync request to target %d ... ", 1145 id); 1146 #endif 1147 /* 1148 * setup scsi message sync message request 1149 */ 1150 dev->sc_msg[0] = MSG_IDENTIFY | lun; 1151 dev->sc_msg[1] = MSG_EXT_MESSAGE; 1152 dev->sc_msg[2] = 3; 1153 dev->sc_msg[3] = MSG_SYNC_REQ; 1154 dev->sc_msg[4] = sbictoscsiperiod(dev, regs, 1155 sbic_min_period); 1156 dev->sc_msg[5] = sbic_max_offset; 1157 1158 if (sbicxfstart(regs, 6, MESG_OUT_PHASE, sbic_cmd_wait)) 1159 sbicxfout(regs, 6, dev->sc_msg, MESG_OUT_PHASE); 1160 1161 dev->sc_sync[id].state = SYNC_SENT; 1162 #ifdef DEBUG 1163 if (sync_debug) 1164 printf ("sent\n"); 1165 #endif 1166 } 1167 1168 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0); 1169 GET_SBIC_csr (regs, csr); 1170 CSR_TRACE('y',csr,asr,target); 1171 QPRINTF(("[%02x]", csr)); 1172 #ifdef DEBUG 1173 if (sync_debug && dev->sc_sync[id].state == SYNC_SENT) 1174 printf("csr-result of last msgout: 0x%x\n", csr); 1175 #endif 1176 1177 if (csr != SBIC_CSR_SEL_TIMEO) 1178 dev->sc_flags |= SBICF_SELECTED; 1179 } 1180 if (csr == SBIC_CSR_SEL_TIMEO) 1181 dev->sc_xs->error = XS_SELTIMEOUT; 1182 1183 QPRINTF(("\n")); 1184 1185 SBIC_TRACE(dev); 1186 return(csr == SBIC_CSR_SEL_TIMEO); 1187 } 1188 1189 int 1190 sbicxfstart(regs, len, phase, wait) 1191 sbic_regmap_p regs; 1192 int len, wait; 1193 u_char phase; 1194 { 1195 u_char id; 1196 1197 switch (phase) { 1198 case DATA_IN_PHASE: 1199 case MESG_IN_PHASE: 1200 GET_SBIC_selid (regs, id); 1201 id |= SBIC_SID_FROM_SCSI; 1202 SET_SBIC_selid (regs, id); 1203 SBIC_TC_PUT (regs, (unsigned)len); 1204 break; 1205 case DATA_OUT_PHASE: 1206 case MESG_OUT_PHASE: 1207 case CMD_PHASE: 1208 GET_SBIC_selid (regs, id); 1209 id &= ~SBIC_SID_FROM_SCSI; 1210 SET_SBIC_selid (regs, id); 1211 SBIC_TC_PUT (regs, (unsigned)len); 1212 break; 1213 default: 1214 SBIC_TC_PUT (regs, 0); 1215 } 1216 QPRINTF(("sbicxfstart %d, %d, %d\n", len, phase, wait)); 1217 1218 return(1); 1219 } 1220 1221 int 1222 sbicxfout(regs, len, bp, phase) 1223 sbic_regmap_p regs; 1224 int len; 1225 void *bp; 1226 int phase; 1227 { 1228 u_char orig_csr, asr, *buf; 1229 int wait; 1230 1231 buf = bp; 1232 wait = sbic_data_wait; 1233 1234 QPRINTF(("sbicxfout {%d} %02x %02x %02x %02x %02x " 1235 "%02x %02x %02x %02x %02x\n", len, buf[0], buf[1], buf[2], 1236 buf[3], buf[4], buf[5], buf[6], buf[7], buf[8], buf[9])); 1237 1238 GET_SBIC_csr (regs, orig_csr); 1239 CSR_TRACE('>',orig_csr,0,0); 1240 1241 /* 1242 * sigh.. WD-PROTO strikes again.. sending the command in one go 1243 * causes the chip to lock up if talking to certain (misbehaving?) 1244 * targets. Anyway, this procedure should work for all targets, but 1245 * it's slightly slower due to the overhead 1246 */ 1247 WAIT_CIP (regs); 1248 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1249 for (;len > 0; len--) { 1250 GET_SBIC_asr (regs, asr); 1251 while ((asr & SBIC_ASR_DBR) == 0) { 1252 if ((asr & SBIC_ASR_INT) || --wait < 0) { 1253 #ifdef DEBUG 1254 if (sbic_debug) 1255 printf("sbicxfout fail: l%d i%x w%d\n", 1256 len, asr, wait); 1257 #endif 1258 return (len); 1259 } 1260 /* DELAY(1);*/ 1261 GET_SBIC_asr (regs, asr); 1262 } 1263 1264 SET_SBIC_data (regs, *buf); 1265 buf++; 1266 } 1267 SBIC_TC_GET(regs, len); 1268 QPRINTF(("sbicxfout done %d bytes\n", len)); 1269 /* 1270 * this leaves with one csr to be read 1271 */ 1272 return(0); 1273 } 1274 1275 /* returns # bytes left to read */ 1276 int 1277 sbicxfin(regs, len, bp) 1278 sbic_regmap_p regs; 1279 int len; 1280 void *bp; 1281 { 1282 int wait; 1283 u_char *obp, *buf; 1284 u_char orig_csr, csr, asr; 1285 1286 wait = sbic_data_wait; 1287 obp = bp; 1288 buf = bp; 1289 1290 GET_SBIC_csr (regs, orig_csr); 1291 CSR_TRACE('<',orig_csr,0,0); 1292 1293 QPRINTF(("sbicxfin %d, csr=%02x\n", len, orig_csr)); 1294 1295 WAIT_CIP (regs); 1296 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1297 for (;len > 0; len--) { 1298 GET_SBIC_asr (regs, asr); 1299 if((asr & SBIC_ASR_PE)) { 1300 #ifdef DEBUG 1301 printf("sbicxfin parity error: l%d i%x w%d\n", 1302 len, asr, wait); 1303 /* return ((unsigned long)buf - (unsigned long)bp); */ 1304 #ifdef DDB 1305 Debugger(); 1306 #endif 1307 #endif 1308 } 1309 while ((asr & SBIC_ASR_DBR) == 0) { 1310 if ((asr & SBIC_ASR_INT) || --wait < 0) { 1311 #ifdef DEBUG 1312 if (sbic_debug) { 1313 QPRINTF(("sbicxfin fail:{%d} %02x %02x %02x %02x %02x %02x " 1314 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1315 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1316 printf("sbicxfin fail: l%d i%x w%d\n", 1317 len, asr, wait); 1318 } 1319 #endif 1320 return len; 1321 } 1322 1323 if( ! asr & SBIC_ASR_BSY ) { 1324 GET_SBIC_csr(regs, csr); 1325 CSR_TRACE('<',csr,asr,len); 1326 QPRINTF(("[CSR%02xASR%02x]", csr, asr)); 1327 } 1328 1329 /* DELAY(1);*/ 1330 GET_SBIC_asr (regs, asr); 1331 } 1332 1333 GET_SBIC_data (regs, *buf); 1334 /* QPRINTF(("asr=%02x, csr=%02x, data=%02x\n", asr, csr, *buf));*/ 1335 buf++; 1336 } 1337 1338 QPRINTF(("sbicxfin {%d} %02x %02x %02x %02x %02x %02x " 1339 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1340 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1341 1342 /* this leaves with one csr to be read */ 1343 return len; 1344 } 1345 1346 /* 1347 * SCSI 'immediate' command: issue a command to some SCSI device 1348 * and get back an 'immediate' response (i.e., do programmed xfer 1349 * to get the response data). 'cbuf' is a buffer containing a scsi 1350 * command of length clen bytes. 'buf' is a buffer of length 'len' 1351 * bytes for data. The transfer direction is determined by the device 1352 * (i.e., by the scsi bus data xfer phase). If 'len' is zero, the 1353 * command must supply no data. 1354 */ 1355 int 1356 sbicicmd(dev, target, lun, cbuf, clen, buf, len) 1357 struct sbic_softc *dev; 1358 void *cbuf, *buf; 1359 int clen, len; 1360 { 1361 sbic_regmap_p regs; 1362 u_char phase, csr, asr; 1363 int wait, i; 1364 struct sbic_acb *acb; 1365 1366 #define CSR_LOG_BUF_SIZE 0 1367 #if CSR_LOG_BUF_SIZE 1368 int bufptr; 1369 int csrbuf[CSR_LOG_BUF_SIZE]; 1370 bufptr=0; 1371 #endif 1372 1373 SBIC_TRACE(dev); 1374 regs = dev->sc_sbicp; 1375 acb = dev->sc_nexus; 1376 1377 /* Make sure pointers are OK */ 1378 dev->sc_last = dev->sc_cur = &acb->sc_pa; 1379 dev->sc_tcnt = acb->sc_tcnt = 0; 1380 acb->sc_pa.dc_count = 0; /* No DMA */ 1381 acb->sc_kv.dc_addr = buf; 1382 acb->sc_kv.dc_count = len; 1383 1384 #ifdef DEBUG 1385 routine = 3; 1386 debug_sbic_regs = regs; /* store this to allow debug calls */ 1387 if( data_pointer_debug > 1 ) 1388 printf("sbicicmd(%d,%d):%d\n", target, lun, 1389 acb->sc_kv.dc_count); 1390 #endif 1391 1392 /* 1393 * set the sbic into non-DMA mode 1394 */ 1395 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI /*| SBIC_CTL_HSP*/); 1396 1397 dev->sc_stat[0] = 0xff; 1398 dev->sc_msg[0] = 0xff; 1399 i = 1; /* pre-load */ 1400 1401 /* We're stealing the SCSI bus */ 1402 dev->sc_flags |= SBICF_ICMD; 1403 1404 do { 1405 /* 1406 * select the SCSI bus (it's an error if bus isn't free) 1407 */ 1408 if (!( dev->sc_flags & SBICF_SELECTED ) 1409 && sbicselectbus(dev, regs, target, lun, dev->sc_scsiaddr)) { 1410 /*printf("sbicicmd trying to select busy bus!\n");*/ 1411 dev->sc_flags &= ~SBICF_ICMD; 1412 return(-1); 1413 } 1414 1415 /* 1416 * Wait for a phase change (or error) then let the device sequence 1417 * us through the various SCSI phases. 1418 */ 1419 1420 wait = sbic_cmd_wait; 1421 1422 asr = GET_SBIC_asr (regs, asr); 1423 GET_SBIC_csr (regs, csr); 1424 CSR_TRACE('I',csr,asr,target); 1425 QPRINTF((">ASR:%02xCSR:%02x<", asr, csr)); 1426 1427 #if CSR_LOG_BUF_SIZE 1428 csrbuf[bufptr++] = csr; 1429 #endif 1430 1431 1432 switch (csr) { 1433 case SBIC_CSR_S_XFERRED: 1434 case SBIC_CSR_DISC: 1435 case SBIC_CSR_DISC_1: 1436 dev->sc_flags &= ~SBICF_SELECTED; 1437 GET_SBIC_cmd_phase (regs, phase); 1438 if (phase == 0x60) { 1439 GET_SBIC_tlun (regs, dev->sc_stat[0]); 1440 i = 0; /* done */ 1441 /* break; */ /* Bypass all the state gobldygook */ 1442 } else { 1443 #ifdef DEBUG 1444 if(reselect_debug>1) 1445 printf("sbicicmd: handling disconnect\n"); 1446 #endif 1447 i = SBIC_STATE_DISCONNECT; 1448 } 1449 break; 1450 1451 case SBIC_CSR_XFERRED|CMD_PHASE: 1452 case SBIC_CSR_MIS|CMD_PHASE: 1453 case SBIC_CSR_MIS_1|CMD_PHASE: 1454 case SBIC_CSR_MIS_2|CMD_PHASE: 1455 if (sbicxfstart(regs, clen, CMD_PHASE, sbic_cmd_wait)) 1456 if (sbicxfout(regs, clen, 1457 cbuf, CMD_PHASE)) 1458 i = sbicabort(dev, regs,"icmd sending cmd"); 1459 #if 0 1460 GET_SBIC_csr(regs, csr); /* Lets us reload tcount */ 1461 WAIT_CIP(regs); 1462 GET_SBIC_asr(regs, asr); 1463 CSR_TRACE('I',csr,asr,target); 1464 if( asr & (SBIC_ASR_BSY|SBIC_ASR_LCI|SBIC_ASR_CIP) ) 1465 printf("next: cmd sent asr %02x, csr %02x\n", 1466 asr, csr); 1467 #endif 1468 break; 1469 1470 #if 0 1471 case SBIC_CSR_XFERRED|DATA_OUT_PHASE: 1472 case SBIC_CSR_XFERRED|DATA_IN_PHASE: 1473 case SBIC_CSR_MIS|DATA_OUT_PHASE: 1474 case SBIC_CSR_MIS|DATA_IN_PHASE: 1475 case SBIC_CSR_MIS_1|DATA_OUT_PHASE: 1476 case SBIC_CSR_MIS_1|DATA_IN_PHASE: 1477 case SBIC_CSR_MIS_2|DATA_OUT_PHASE: 1478 case SBIC_CSR_MIS_2|DATA_IN_PHASE: 1479 if (acb->sc_kv.dc_count <= 0) 1480 i = sbicabort(dev, regs, "icmd out of data"); 1481 else { 1482 wait = sbic_data_wait; 1483 if (sbicxfstart(regs, 1484 acb->sc_kv.dc_count, 1485 SBIC_PHASE(csr), wait)) 1486 if (csr & 0x01) 1487 /* data in? */ 1488 i=sbicxfin(regs, 1489 acb->sc_kv.dc_count, 1490 acb->sc_kv.dc_addr); 1491 else 1492 i=sbicxfout(regs, 1493 acb->sc_kv.dc_count, 1494 acb->sc_kv.dc_addr, 1495 SBIC_PHASE(csr)); 1496 acb->sc_kv.dc_addr += 1497 (acb->sc_kv.dc_count - i); 1498 acb->sc_kv.dc_count = i; 1499 i = 1; 1500 } 1501 break; 1502 1503 #endif 1504 case SBIC_CSR_XFERRED|STATUS_PHASE: 1505 case SBIC_CSR_MIS|STATUS_PHASE: 1506 case SBIC_CSR_MIS_1|STATUS_PHASE: 1507 case SBIC_CSR_MIS_2|STATUS_PHASE: 1508 /* 1509 * the sbic does the status/cmd-complete reading ok, 1510 * so do this with its hi-level commands. 1511 */ 1512 #ifdef DEBUG 1513 if(sbic_debug) 1514 printf("SBICICMD status phase\n"); 1515 #endif 1516 SBIC_TC_PUT(regs, 0); 1517 SET_SBIC_cmd_phase(regs, 0x46); 1518 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1519 break; 1520 1521 #if THIS_IS_A_RESERVED_STATE 1522 case BUS_FREE_PHASE: /* This is not legal */ 1523 if( dev->sc_stat[0] != 0xff ) 1524 goto out; 1525 break; 1526 #endif 1527 1528 default: 1529 i = sbicnextstate(dev, csr, asr); 1530 } 1531 1532 /* 1533 * make sure the last command was taken, 1534 * ie. we're not hunting after an ignored command.. 1535 */ 1536 GET_SBIC_asr(regs, asr); 1537 1538 /* tapes may take a loooong time.. */ 1539 while (asr & SBIC_ASR_BSY){ 1540 if(asr & SBIC_ASR_DBR) { 1541 printf("sbicicmd: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", 1542 csr,asr); 1543 #ifdef DDB 1544 Debugger(); 1545 #endif 1546 /* SBIC is jammed */ 1547 /* DUNNO which direction */ 1548 /* Try old direction */ 1549 GET_SBIC_data(regs,i); 1550 GET_SBIC_asr(regs, asr); 1551 if( asr & SBIC_ASR_DBR) /* Wants us to write */ 1552 SET_SBIC_data(regs,i); 1553 } 1554 GET_SBIC_asr(regs, asr); 1555 } 1556 1557 /* 1558 * wait for last command to complete 1559 */ 1560 if (asr & SBIC_ASR_LCI) { 1561 printf("sbicicmd: last command ignored\n"); 1562 } 1563 else if( i == 1 ) /* Bsy */ 1564 SBIC_WAIT (regs, SBIC_ASR_INT, wait); 1565 1566 /* 1567 * do it again 1568 */ 1569 } while ( i > 0 && dev->sc_stat[0] == 0xff); 1570 1571 /* Sometimes we need to do an extra read of the CSR */ 1572 GET_SBIC_csr(regs, csr); 1573 CSR_TRACE('I',csr,asr,0xff); 1574 1575 #if CSR_LOG_BUF_SIZE 1576 if(reselect_debug>1) 1577 for(i=0; i<bufptr; i++) 1578 printf("CSR:%02x", csrbuf[i]); 1579 #endif 1580 1581 #ifdef DEBUG 1582 if(data_pointer_debug > 1) 1583 printf("sbicicmd done(%d,%d):%d =%d=\n", 1584 dev->target, lun, 1585 acb->sc_kv.dc_count, 1586 dev->sc_stat[0]); 1587 #endif 1588 1589 QPRINTF(("=STS:%02x=", dev->sc_stat[0])); 1590 dev->sc_flags &= ~SBICF_ICMD; 1591 1592 SBIC_TRACE(dev); 1593 return(dev->sc_stat[0]); 1594 } 1595 1596 /* 1597 * Finish SCSI xfer command: After the completion interrupt from 1598 * a read/write operation, sequence through the final phases in 1599 * programmed i/o. This routine is a lot like sbicicmd except we 1600 * skip (and don't allow) the select, cmd out and data in/out phases. 1601 */ 1602 void 1603 sbicxfdone(dev, regs, target) 1604 struct sbic_softc *dev; 1605 sbic_regmap_p regs; 1606 int target; 1607 { 1608 u_char phase, asr, csr; 1609 int s; 1610 1611 SBIC_TRACE(dev); 1612 QPRINTF(("{")); 1613 s = splbio(); 1614 1615 /* 1616 * have the sbic complete on its own 1617 */ 1618 SBIC_TC_PUT(regs, 0); 1619 SET_SBIC_cmd_phase(regs, 0x46); 1620 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1621 1622 do { 1623 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0); 1624 GET_SBIC_csr (regs, csr); 1625 CSR_TRACE('f',csr,asr,target); 1626 QPRINTF(("%02x:", csr)); 1627 } while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) 1628 && (csr != SBIC_CSR_S_XFERRED)); 1629 1630 dev->sc_flags &= ~SBICF_SELECTED; 1631 1632 GET_SBIC_cmd_phase (regs, phase); 1633 QPRINTF(("}%02x", phase)); 1634 if (phase == 0x60) 1635 GET_SBIC_tlun(regs, dev->sc_stat[0]); 1636 else 1637 sbicerror(dev, regs, csr); 1638 1639 QPRINTF(("=STS:%02x=\n", dev->sc_stat[0])); 1640 splx(s); 1641 SBIC_TRACE(dev); 1642 } 1643 1644 /* 1645 * No DMA chains 1646 */ 1647 1648 int 1649 sbicgo(dev, xs) 1650 struct sbic_softc *dev; 1651 struct scsi_xfer *xs; 1652 { 1653 int i, dmaflags, count, usedma; 1654 u_char csr, asr, *addr; 1655 sbic_regmap_p regs; 1656 struct sbic_acb *acb; 1657 1658 SBIC_TRACE(dev); 1659 dev->target = xs->sc_link->target; 1660 dev->lun = xs->sc_link->lun; 1661 acb = dev->sc_nexus; 1662 regs = dev->sc_sbicp; 1663 1664 usedma = sbicdmaok(dev, xs); 1665 #ifdef DEBUG 1666 routine = 1; 1667 debug_sbic_regs = regs; /* store this to allow debug calls */ 1668 if( data_pointer_debug > 1 ) 1669 printf("sbicgo(%d,%d)\n", dev->target, dev->lun); 1670 #endif 1671 1672 /* 1673 * set the sbic into DMA mode 1674 */ 1675 if( usedma ) 1676 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI | 1677 SBIC_MACHINE_DMA_MODE); 1678 else 1679 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1680 1681 1682 /* 1683 * select the SCSI bus (it's an error if bus isn't free) 1684 */ 1685 if (sbicselectbus(dev, regs, dev->target, dev->lun, 1686 dev->sc_scsiaddr)) { 1687 /* printf("sbicgo: Trying to select busy bus!\n"); */ 1688 SBIC_TRACE(dev); 1689 return(0); /* Not done: needs to be rescheduled */ 1690 } 1691 dev->sc_stat[0] = 0xff; 1692 1693 /* 1694 * Calculate DMA chains now 1695 */ 1696 1697 dmaflags = 0; 1698 if (acb->flags & ACB_DATAIN) 1699 dmaflags |= DMAGO_READ; 1700 1701 1702 /* 1703 * Deal w/bounce buffers. 1704 */ 1705 1706 addr = acb->sc_kv.dc_addr; 1707 count = acb->sc_kv.dc_count; 1708 if (count && (char *)kvtop(addr) != acb->sc_pa.dc_addr) { /* XXXX check */ 1709 printf("sbic: DMA buffer mapping changed %p->%x\n", 1710 acb->sc_pa.dc_addr, kvtop(addr)); 1711 #ifdef DDB 1712 Debugger(); 1713 #endif 1714 } 1715 1716 #ifdef DEBUG 1717 ++sbicdma_ops; /* count total DMA operations */ 1718 #endif 1719 if (count && usedma && dev->sc_flags & SBICF_BADDMA && 1720 sbiccheckdmap(addr, count, dev->sc_dmamask)) { 1721 /* 1722 * need to bounce the dma. 1723 */ 1724 if (dmaflags & DMAGO_READ) { 1725 acb->flags |= ACB_BBUF; 1726 acb->sc_dmausrbuf = addr; 1727 acb->sc_dmausrlen = count; 1728 acb->sc_usrbufpa = (u_char *)kvtop(addr); 1729 if(!dev->sc_tinfo[dev->target].bounce) { 1730 printf("sbicgo: HELP! no bounce allocated for %d\n", 1731 dev->target); 1732 printf("xfer: (%p->%p,%lx)\n", acb->sc_dmausrbuf, 1733 acb->sc_usrbufpa, acb->sc_dmausrlen); 1734 dev->sc_tinfo[xs->sc_link->target].bounce 1735 = (char *)alloc_z2mem(MAXPHYS); 1736 if (isztwomem(dev->sc_tinfo[xs->sc_link->target].bounce)) 1737 printf("alloc ZII target %d bounce pa 0x%x\n", 1738 xs->sc_link->target, 1739 kvtop(dev->sc_tinfo[xs->sc_link->target].bounce)); 1740 else if (dev->sc_tinfo[xs->sc_link->target].bounce) 1741 printf("alloc CHIP target %d bounce pa 0x%p\n", 1742 xs->sc_link->target, 1743 PREP_DMA_MEM(dev->sc_tinfo[xs->sc_link->target].bounce)); 1744 1745 printf("Allocating %d bounce at %x\n", 1746 dev->target, 1747 kvtop(dev->sc_tinfo[dev->target].bounce)); 1748 } 1749 } else { /* write: copy to dma buffer */ 1750 #ifdef DEBUG 1751 if(data_pointer_debug) 1752 printf("sbicgo: copying %x bytes to target %d bounce %x\n", 1753 count, dev->target, 1754 kvtop(dev->sc_tinfo[dev->target].bounce)); 1755 #endif 1756 bcopy (addr, dev->sc_tinfo[dev->target].bounce, count); 1757 } 1758 addr = dev->sc_tinfo[dev->target].bounce;/* and use dma buffer */ 1759 acb->sc_kv.dc_addr = addr; 1760 #ifdef DEBUG 1761 ++sbicdma_bounces; /* count number of bounced */ 1762 #endif 1763 } 1764 1765 /* 1766 * Allocate the DMA chain 1767 */ 1768 1769 /* Set start KVM addresses */ 1770 #if 0 1771 acb->sc_kv.dc_addr = addr; 1772 acb->sc_kv.dc_count = count; 1773 #endif 1774 1775 /* Mark end of segment */ 1776 acb->sc_tcnt = dev->sc_tcnt = 0; 1777 acb->sc_pa.dc_count = 0; 1778 1779 sbic_load_ptrs(dev, regs, dev->target, dev->lun); 1780 SBIC_TRACE(dev); 1781 /* Enable interrupts but don't do any DMA */ 1782 dev->sc_enintr(dev); 1783 if (usedma) { 1784 dev->sc_tcnt = dev->sc_dmago(dev, acb->sc_pa.dc_addr, 1785 acb->sc_pa.dc_count, 1786 dmaflags); 1787 #ifdef DEBUG 1788 dev->sc_dmatimo = dev->sc_tcnt ? 1 : 0; 1789 #endif 1790 } else 1791 dev->sc_dmacmd = 0; /* Don't use DMA */ 1792 dev->sc_flags |= SBICF_INDMA; 1793 /* SBIC_TC_PUT(regs, dev->sc_tcnt); */ /* XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX */ 1794 SBIC_TRACE(dev); 1795 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 1796 1797 /* 1798 * push the data cache ( I think this won't work (EH)) 1799 */ 1800 #if defined(M68040) 1801 if (mmutype == MMU_68040 && usedma && count) { 1802 dma_cachectl(addr, count); 1803 if (((u_int)addr & 0xF) || (((u_int)addr + count) & 0xF)) 1804 dev->sc_flags |= SBICF_DCFLUSH; 1805 } 1806 #endif 1807 1808 /* 1809 * enintr() also enables interrupts for the sbic 1810 */ 1811 #ifdef DEBUG 1812 if( data_pointer_debug > 1 ) 1813 printf("sbicgo dmago:%d(%p:%lx)\n", 1814 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 1815 debug_asr = asr; 1816 debug_csr = csr; 1817 #endif 1818 1819 /* 1820 * Lets cycle a while then let the interrupt handler take over 1821 */ 1822 1823 asr = GET_SBIC_asr(regs, asr); 1824 do { 1825 GET_SBIC_csr(regs, csr); 1826 CSR_TRACE('g',csr,asr,dev->target); 1827 #ifdef DEBUG 1828 debug_csr = csr; 1829 routine = 1; 1830 #endif 1831 QPRINTF(("go[0x%x]", csr)); 1832 1833 i = sbicnextstate(dev, csr, asr); 1834 1835 WAIT_CIP(regs); 1836 GET_SBIC_asr(regs, asr); 1837 #ifdef DEBUG 1838 debug_asr = asr; 1839 #endif 1840 if(asr & SBIC_ASR_LCI) printf("sbicgo: LCI asr:%02x csr:%02x\n", 1841 asr,csr); 1842 } while( i == SBIC_STATE_RUNNING 1843 && asr & (SBIC_ASR_INT|SBIC_ASR_LCI) ); 1844 1845 CSR_TRACE('g',csr,asr,i<<4); 1846 SBIC_TRACE(dev); 1847 if (i == SBIC_STATE_DONE && dev->sc_stat[0] == 0xff) printf("sbicgo: done & stat = 0xff\n"); 1848 if (i == SBIC_STATE_DONE && dev->sc_stat[0] != 0xff) { 1849 /* if( i == SBIC_STATE_DONE && dev->sc_stat[0] ) { */ 1850 /* Did we really finish that fast? */ 1851 return 1; 1852 } 1853 return 0; 1854 } 1855 1856 1857 int 1858 sbicintr(dev) 1859 struct sbic_softc *dev; 1860 { 1861 sbic_regmap_p regs; 1862 u_char asr, csr; 1863 int i; 1864 1865 regs = dev->sc_sbicp; 1866 1867 /* 1868 * pending interrupt? 1869 */ 1870 GET_SBIC_asr (regs, asr); 1871 if ((asr & SBIC_ASR_INT) == 0) 1872 return(0); 1873 1874 SBIC_TRACE(dev); 1875 do { 1876 GET_SBIC_csr(regs, csr); 1877 CSR_TRACE('i',csr,asr,dev->target); 1878 #ifdef DEBUG 1879 debug_csr = csr; 1880 routine = 2; 1881 #endif 1882 QPRINTF(("intr[0x%x]", csr)); 1883 1884 i = sbicnextstate(dev, csr, asr); 1885 1886 WAIT_CIP(regs); 1887 GET_SBIC_asr(regs, asr); 1888 #ifdef DEBUG 1889 debug_asr = asr; 1890 #endif 1891 #if 0 1892 if(asr & SBIC_ASR_LCI) printf("sbicintr: LCI asr:%02x csr:%02x\n", 1893 asr,csr); 1894 #endif 1895 } while(i == SBIC_STATE_RUNNING && 1896 asr & (SBIC_ASR_INT|SBIC_ASR_LCI)); 1897 CSR_TRACE('i',csr,asr,i<<4); 1898 SBIC_TRACE(dev); 1899 return(1); 1900 } 1901 1902 /* 1903 * Run commands and wait for disconnect 1904 */ 1905 int 1906 sbicpoll(dev) 1907 struct sbic_softc *dev; 1908 { 1909 sbic_regmap_p regs; 1910 u_char asr, csr; 1911 int i; 1912 1913 SBIC_TRACE(dev); 1914 regs = dev->sc_sbicp; 1915 1916 do { 1917 GET_SBIC_asr (regs, asr); 1918 #ifdef DEBUG 1919 debug_asr = asr; 1920 #endif 1921 GET_SBIC_csr(regs, csr); 1922 CSR_TRACE('p',csr,asr,dev->target); 1923 #ifdef DEBUG 1924 debug_csr = csr; 1925 routine = 2; 1926 #endif 1927 QPRINTF(("poll[0x%x]", csr)); 1928 1929 i = sbicnextstate(dev, csr, asr); 1930 1931 WAIT_CIP(regs); 1932 GET_SBIC_asr(regs, asr); 1933 /* tapes may take a loooong time.. */ 1934 while (asr & SBIC_ASR_BSY){ 1935 if(asr & SBIC_ASR_DBR) { 1936 printf("sbipoll: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", 1937 csr,asr); 1938 #ifdef DDB 1939 Debugger(); 1940 #endif 1941 /* SBIC is jammed */ 1942 /* DUNNO which direction */ 1943 /* Try old direction */ 1944 GET_SBIC_data(regs,i); 1945 GET_SBIC_asr(regs, asr); 1946 if( asr & SBIC_ASR_DBR) /* Wants us to write */ 1947 SET_SBIC_data(regs,i); 1948 } 1949 GET_SBIC_asr(regs, asr); 1950 } 1951 1952 if(asr & SBIC_ASR_LCI) printf("sbicpoll: LCI asr:%02x csr:%02x\n", 1953 asr,csr); 1954 else if( i == 1 ) /* BSY */ 1955 SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait); 1956 } while(i == SBIC_STATE_RUNNING); 1957 CSR_TRACE('p',csr,asr,i<<4); 1958 SBIC_TRACE(dev); 1959 return(1); 1960 } 1961 1962 /* 1963 * Handle a single msgin 1964 */ 1965 1966 int 1967 sbicmsgin(dev) 1968 struct sbic_softc *dev; 1969 { 1970 sbic_regmap_p regs; 1971 int recvlen; 1972 u_char asr, csr, *tmpaddr; 1973 1974 regs = dev->sc_sbicp; 1975 1976 dev->sc_msg[0] = 0xff; 1977 dev->sc_msg[1] = 0xff; 1978 1979 GET_SBIC_asr(regs, asr); 1980 #ifdef DEBUG 1981 if(reselect_debug>1) 1982 printf("sbicmsgin asr=%02x\n", asr); 1983 #endif 1984 1985 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 1986 1987 GET_SBIC_selid (regs, csr); 1988 SET_SBIC_selid (regs, csr | SBIC_SID_FROM_SCSI); 1989 1990 SBIC_TC_PUT(regs, 0); 1991 tmpaddr = dev->sc_msg; 1992 recvlen = 1; 1993 do { 1994 while( recvlen-- ) { 1995 asr = GET_SBIC_asr(regs, asr); 1996 GET_SBIC_csr(regs, csr); 1997 QPRINTF(("sbicmsgin ready to go (csr,asr)=(%02x,%02x)\n", 1998 csr, asr)); 1999 2000 RECV_BYTE(regs, *tmpaddr); 2001 CSR_TRACE('m',csr,asr,*tmpaddr); 2002 #if 1 2003 /* 2004 * get the command completion interrupt, or we 2005 * can't send a new command (LCI) 2006 */ 2007 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2008 GET_SBIC_csr(regs, csr); 2009 CSR_TRACE('X',csr,asr,dev->target); 2010 #else 2011 WAIT_CIP(regs); 2012 do { 2013 GET_SBIC_asr(regs, asr); 2014 csr = 0xff; 2015 GET_SBIC_csr(regs, csr); 2016 CSR_TRACE('X',csr,asr,dev->target); 2017 if( csr == 0xff ) 2018 printf("sbicmsgin waiting: csr %02x asr %02x\n", csr, asr); 2019 } while( csr == 0xff ); 2020 #endif 2021 #ifdef DEBUG 2022 if(reselect_debug>1) 2023 printf("sbicmsgin: got %02x csr %02x asr %02x\n", 2024 *tmpaddr, csr, asr); 2025 #endif 2026 #if do_parity_check 2027 if( asr & SBIC_ASR_PE ) { 2028 printf ("Parity error"); 2029 /* This code simply does not work. */ 2030 WAIT_CIP(regs); 2031 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2032 WAIT_CIP(regs); 2033 GET_SBIC_asr(regs, asr); 2034 WAIT_CIP(regs); 2035 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2036 WAIT_CIP(regs); 2037 if( !(asr & SBIC_ASR_LCI) ) 2038 /* Target wants to send garbled msg*/ 2039 continue; 2040 printf("--fixing\n"); 2041 /* loop until a msgout phase occurs on target */ 2042 while(csr & 0x07 != MESG_OUT_PHASE) { 2043 while( asr & SBIC_ASR_BSY && 2044 !(asr & SBIC_ASR_DBR|SBIC_ASR_INT) ) 2045 GET_SBIC_asr(regs, asr); 2046 if( asr & SBIC_ASR_DBR ) 2047 panic("msgin: jammed again!\n"); 2048 GET_SBIC_csr(regs, csr); 2049 CSR_TRACE('e',csr,asr,dev->target); 2050 if( csr & 0x07 != MESG_OUT_PHASE ) { 2051 sbicnextstate(dev, csr, asr); 2052 sbic_save_ptrs(dev, regs, 2053 dev->target, 2054 dev->lun); 2055 } 2056 } 2057 /* Should be msg out by now */ 2058 SEND_BYTE(regs, MSG_PARITY_ERROR); 2059 } 2060 else 2061 #endif 2062 tmpaddr++; 2063 2064 if(recvlen) { 2065 /* Clear ACK */ 2066 WAIT_CIP(regs); 2067 GET_SBIC_asr(regs, asr); 2068 GET_SBIC_csr(regs, csr); 2069 CSR_TRACE('X',csr,asr,dev->target); 2070 QPRINTF(("sbicmsgin pre byte CLR_ACK (csr,asr)=(%02x,%02x)\n", 2071 csr, asr)); 2072 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2073 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2074 } 2075 2076 }; 2077 2078 if(dev->sc_msg[0] == 0xff) { 2079 printf("sbicmsgin: sbic swallowed our message\n"); 2080 break; 2081 } 2082 #ifdef DEBUG 2083 if (sync_debug) 2084 printf("msgin done csr 0x%x asr 0x%x msg 0x%x\n", 2085 csr, asr, dev->sc_msg[0]); 2086 #endif 2087 /* 2088 * test whether this is a reply to our sync 2089 * request 2090 */ 2091 if (MSG_ISIDENTIFY(dev->sc_msg[0])) { 2092 QPRINTF(("IFFY")); 2093 #if 0 2094 /* There is an implied load-ptrs here */ 2095 sbic_load_ptrs(dev, regs, dev->target, dev->lun); 2096 #endif 2097 /* Got IFFY msg -- ack it */ 2098 } else if (dev->sc_msg[0] == MSG_REJECT 2099 && dev->sc_sync[dev->target].state == SYNC_SENT) { 2100 QPRINTF(("REJECT of SYN")); 2101 #ifdef DEBUG 2102 if (sync_debug) 2103 printf("target %d rejected sync, going async\n", 2104 dev->target); 2105 #endif 2106 dev->sc_sync[dev->target].period = sbic_min_period; 2107 dev->sc_sync[dev->target].offset = 0; 2108 dev->sc_sync[dev->target].state = SYNC_DONE; 2109 SET_SBIC_syn(regs, 2110 SBIC_SYN(dev->sc_sync[dev->target].offset, 2111 dev->sc_sync[dev->target].period)); 2112 } else if ((dev->sc_msg[0] == MSG_REJECT)) { 2113 QPRINTF(("REJECT")); 2114 /* 2115 * we'll never REJECt a REJECT message.. 2116 */ 2117 } else if ((dev->sc_msg[0] == MSG_SAVE_DATA_PTR)) { 2118 QPRINTF(("MSG_SAVE_DATA_PTR")); 2119 /* 2120 * don't reject this either. 2121 */ 2122 } else if ((dev->sc_msg[0] == MSG_DISCONNECT)) { 2123 QPRINTF(("DISCONNECT")); 2124 #ifdef DEBUG 2125 if( reselect_debug>1 && dev->sc_msg[0] == MSG_DISCONNECT ) 2126 printf("sbicmsgin: got disconnect msg %s\n", 2127 (dev->sc_flags & SBICF_ICMD)?"rejecting":""); 2128 #endif 2129 if( dev->sc_flags & SBICF_ICMD ) { 2130 /* We're in immediate mode. Prevent disconnects. */ 2131 /* prepare to reject the message, NACK */ 2132 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2133 WAIT_CIP(regs); 2134 } 2135 } else if (dev->sc_msg[0] == MSG_CMD_COMPLETE ) { 2136 QPRINTF(("CMD_COMPLETE")); 2137 /* !! KLUDGE ALERT !! quite a few drives don't seem to 2138 * really like the current way of sending the 2139 * sync-handshake together with the ident-message, and 2140 * they react by sending command-complete and 2141 * disconnecting right after returning the valid sync 2142 * handshake. So, all I can do is reselect the drive, 2143 * and hope it won't disconnect again. I don't think 2144 * this is valid behavior, but I can't help fixing a 2145 * problem that apparently exists. 2146 * 2147 * Note: we should not get here on `normal' command 2148 * completion, as that condition is handled by the 2149 * high-level sel&xfer resume command used to walk 2150 * thru status/cc-phase. 2151 */ 2152 2153 #ifdef DEBUG 2154 if (sync_debug) 2155 printf ("GOT MSG %d! target %d acting weird.." 2156 " waiting for disconnect...\n", 2157 dev->sc_msg[0], dev->target); 2158 #endif 2159 /* Check to see if sbic is handling this */ 2160 GET_SBIC_asr(regs, asr); 2161 if(asr & SBIC_ASR_BSY) 2162 return SBIC_STATE_RUNNING; 2163 2164 /* Let's try this: Assume it works and set status to 00 */ 2165 dev->sc_stat[0] = 0; 2166 } else if (dev->sc_msg[0] == MSG_EXT_MESSAGE 2167 && tmpaddr == &dev->sc_msg[1]) { 2168 QPRINTF(("ExtMSG\n")); 2169 /* Read in whole extended message */ 2170 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2171 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2172 GET_SBIC_asr(regs, asr); 2173 GET_SBIC_csr(regs, csr); 2174 QPRINTF(("CLR ACK asr %02x, csr %02x\n", asr, csr)); 2175 RECV_BYTE(regs, *tmpaddr); 2176 CSR_TRACE('x',csr,asr,*tmpaddr); 2177 /* Wait for command completion IRQ */ 2178 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2179 recvlen = *tmpaddr++; 2180 QPRINTF(("Recving ext msg, asr %02x csr %02x len %02x\n", 2181 asr, csr, recvlen)); 2182 } else if (dev->sc_msg[0] == MSG_EXT_MESSAGE && dev->sc_msg[1] == 3 2183 && dev->sc_msg[2] == MSG_SYNC_REQ) { 2184 QPRINTF(("SYN")); 2185 dev->sc_sync[dev->target].period = 2186 sbicfromscsiperiod(dev, 2187 regs, dev->sc_msg[3]); 2188 dev->sc_sync[dev->target].offset = dev->sc_msg[4]; 2189 dev->sc_sync[dev->target].state = SYNC_DONE; 2190 SET_SBIC_syn(regs, 2191 SBIC_SYN(dev->sc_sync[dev->target].offset, 2192 dev->sc_sync[dev->target].period)); 2193 printf("%s: target %d now synchronous," 2194 " period=%dns, offset=%d.\n", 2195 dev->sc_dev.dv_xname, dev->target, 2196 dev->sc_msg[3] * 4, dev->sc_msg[4]); 2197 } else { 2198 #ifdef DEBUG 2199 if (sbic_debug || sync_debug) 2200 printf ("sbicmsgin: Rejecting message 0x%02x\n", 2201 dev->sc_msg[0]); 2202 #endif 2203 /* prepare to reject the message, NACK */ 2204 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2205 WAIT_CIP(regs); 2206 } 2207 /* Clear ACK */ 2208 WAIT_CIP(regs); 2209 GET_SBIC_asr(regs, asr); 2210 GET_SBIC_csr(regs, csr); 2211 CSR_TRACE('X',csr,asr,dev->target); 2212 QPRINTF(("sbicmsgin pre CLR_ACK (csr,asr)=(%02x,%02x)%d\n", 2213 csr, asr, recvlen)); 2214 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2215 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2216 } 2217 #if 0 2218 while((csr == SBIC_CSR_MSGIN_W_ACK) 2219 || (SBIC_PHASE(csr) == MESG_IN_PHASE)); 2220 #else 2221 while (recvlen>0); 2222 #endif 2223 2224 QPRINTF(("sbicmsgin finished: csr %02x, asr %02x\n",csr, asr)); 2225 2226 /* Should still have one CSR to read */ 2227 return SBIC_STATE_RUNNING; 2228 } 2229 2230 2231 /* 2232 * sbicnextstate() 2233 * return: 2234 * 0 == done 2235 * 1 == working 2236 * 2 == disconnected 2237 * -1 == error 2238 */ 2239 int 2240 sbicnextstate(dev, csr, asr) 2241 struct sbic_softc *dev; 2242 u_char csr, asr; 2243 { 2244 sbic_regmap_p regs; 2245 struct sbic_acb *acb; 2246 int i, newtarget, newlun, wait; 2247 #if 0 2248 unsigned tcnt; 2249 #endif 2250 2251 i = 0; 2252 SBIC_TRACE(dev); 2253 regs = dev->sc_sbicp; 2254 acb = dev->sc_nexus; 2255 2256 QPRINTF(("next[%02x,%02x]",asr,csr)); 2257 2258 switch (csr) { 2259 case SBIC_CSR_XFERRED|CMD_PHASE: 2260 case SBIC_CSR_MIS|CMD_PHASE: 2261 case SBIC_CSR_MIS_1|CMD_PHASE: 2262 case SBIC_CSR_MIS_2|CMD_PHASE: 2263 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 2264 if (sbicxfstart(regs, acb->clen, CMD_PHASE, sbic_cmd_wait)) 2265 if (sbicxfout(regs, acb->clen, 2266 &acb->cmd, CMD_PHASE)) 2267 goto abort; 2268 break; 2269 2270 case SBIC_CSR_XFERRED|STATUS_PHASE: 2271 case SBIC_CSR_MIS|STATUS_PHASE: 2272 case SBIC_CSR_MIS_1|STATUS_PHASE: 2273 case SBIC_CSR_MIS_2|STATUS_PHASE: 2274 /* 2275 * this should be the normal i/o completion case. 2276 * get the status & cmd complete msg then let the 2277 * device driver look at what happened. 2278 */ 2279 sbicxfdone(dev,regs,dev->target); 2280 /* 2281 * check for overlapping cache line, flush if so 2282 */ 2283 #ifdef M68040 2284 if (dev->sc_flags & SBICF_DCFLUSH) { 2285 #if 0 2286 printf("sbic: 68040 DMA cache flush needs fixing? %x:%x\n", 2287 dev->sc_xs->data, dev->sc_xs->datalen); 2288 #endif 2289 } 2290 #endif 2291 #ifdef DEBUG 2292 if( data_pointer_debug > 1 ) 2293 printf("next dmastop: %d(%p:%lx)\n", 2294 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 2295 dev->sc_dmatimo = 0; 2296 #endif 2297 dev->sc_dmastop(dev); /* was dmafree */ 2298 if (acb->flags & ACB_BBUF) { 2299 if ((u_char *)kvtop(acb->sc_dmausrbuf) != acb->sc_usrbufpa) 2300 printf("%s: WARNING - buffer mapping changed %p->%x\n", 2301 dev->sc_dev.dv_xname, acb->sc_usrbufpa, 2302 kvtop(acb->sc_dmausrbuf)); 2303 #ifdef DEBUG 2304 if(data_pointer_debug) 2305 printf("sbicgo:copying %lx bytes from target %d bounce %x\n", 2306 acb->sc_dmausrlen, 2307 dev->target, 2308 kvtop(dev->sc_tinfo[dev->target].bounce)); 2309 #endif 2310 bcopy(dev->sc_tinfo[dev->target].bounce, 2311 acb->sc_dmausrbuf, 2312 acb->sc_dmausrlen); 2313 } 2314 dev->sc_flags &= ~(SBICF_INDMA | SBICF_DCFLUSH); 2315 sbic_scsidone(acb, dev->sc_stat[0]); 2316 SBIC_TRACE(dev); 2317 return SBIC_STATE_DONE; 2318 2319 case SBIC_CSR_XFERRED|DATA_OUT_PHASE: 2320 case SBIC_CSR_XFERRED|DATA_IN_PHASE: 2321 case SBIC_CSR_MIS|DATA_OUT_PHASE: 2322 case SBIC_CSR_MIS|DATA_IN_PHASE: 2323 case SBIC_CSR_MIS_1|DATA_OUT_PHASE: 2324 case SBIC_CSR_MIS_1|DATA_IN_PHASE: 2325 case SBIC_CSR_MIS_2|DATA_OUT_PHASE: 2326 case SBIC_CSR_MIS_2|DATA_IN_PHASE: 2327 if( dev->sc_xs->flags & SCSI_POLL || dev->sc_flags & SBICF_ICMD 2328 || acb->sc_dmacmd == 0 ) { 2329 /* Do PIO */ 2330 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2331 if (acb->sc_kv.dc_count <= 0) { 2332 printf("sbicnextstate:xfer count %d asr%x csr%x\n", 2333 acb->sc_kv.dc_count, asr, csr); 2334 goto abort; 2335 } 2336 wait = sbic_data_wait; 2337 if( sbicxfstart(regs, 2338 acb->sc_kv.dc_count, 2339 SBIC_PHASE(csr), wait)) 2340 if( SBIC_PHASE(csr) == DATA_IN_PHASE ) 2341 /* data in? */ 2342 i=sbicxfin(regs, 2343 acb->sc_kv.dc_count, 2344 acb->sc_kv.dc_addr); 2345 else 2346 i=sbicxfout(regs, 2347 acb->sc_kv.dc_count, 2348 acb->sc_kv.dc_addr, 2349 SBIC_PHASE(csr)); 2350 acb->sc_kv.dc_addr += 2351 (acb->sc_kv.dc_count - i); 2352 acb->sc_kv.dc_count = i; 2353 } else { 2354 if (acb->sc_kv.dc_count <= 0) { 2355 printf("sbicnextstate:xfer count %d asr%x csr%x\n", 2356 acb->sc_kv.dc_count, asr, csr); 2357 goto abort; 2358 } 2359 /* 2360 * do scatter-gather dma 2361 * hacking the controller chip, ouch.. 2362 */ 2363 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI | 2364 SBIC_MACHINE_DMA_MODE); 2365 /* 2366 * set next dma addr and dec count 2367 */ 2368 #if 0 2369 SBIC_TC_GET(regs, tcnt); 2370 dev->sc_cur->dc_count -= ((dev->sc_tcnt - tcnt) >> 1); 2371 dev->sc_cur->dc_addr += (dev->sc_tcnt - tcnt); 2372 dev->sc_tcnt = acb->sc_tcnt = tcnt; 2373 #else 2374 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 2375 sbic_load_ptrs(dev, regs, dev->target, dev->lun); 2376 #endif 2377 #ifdef DEBUG 2378 if( data_pointer_debug > 1 ) 2379 printf("next dmanext: %d(%p:%lx)\n", 2380 dev->target,dev->sc_cur->dc_addr, 2381 dev->sc_tcnt); 2382 dev->sc_dmatimo = 1; 2383 #endif 2384 dev->sc_tcnt = dev->sc_dmanext(dev); 2385 SBIC_TC_PUT(regs, (unsigned)dev->sc_tcnt); 2386 SET_SBIC_cmd(regs, SBIC_CMD_XFER_INFO); 2387 dev->sc_flags |= SBICF_INDMA; 2388 } 2389 break; 2390 2391 case SBIC_CSR_XFERRED|MESG_IN_PHASE: 2392 case SBIC_CSR_MIS|MESG_IN_PHASE: 2393 case SBIC_CSR_MIS_1|MESG_IN_PHASE: 2394 case SBIC_CSR_MIS_2|MESG_IN_PHASE: 2395 SBIC_TRACE(dev); 2396 return sbicmsgin(dev); 2397 2398 case SBIC_CSR_MSGIN_W_ACK: 2399 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); /* Dunno what I'm ACKing */ 2400 printf("Acking unknown msgin CSR:%02x",csr); 2401 break; 2402 2403 case SBIC_CSR_XFERRED|MESG_OUT_PHASE: 2404 case SBIC_CSR_MIS|MESG_OUT_PHASE: 2405 case SBIC_CSR_MIS_1|MESG_OUT_PHASE: 2406 case SBIC_CSR_MIS_2|MESG_OUT_PHASE: 2407 #ifdef DEBUG 2408 if (sync_debug) 2409 printf ("sending REJECT msg to last msg.\n"); 2410 #endif 2411 2412 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 2413 /* 2414 * should only get here on reject, 2415 * since it's always US that 2416 * initiate a sync transfer 2417 */ 2418 SEND_BYTE(regs, MSG_REJECT); 2419 WAIT_CIP(regs); 2420 if( asr & (SBIC_ASR_BSY|SBIC_ASR_LCI|SBIC_ASR_CIP) ) 2421 printf("next: REJECT sent asr %02x\n", asr); 2422 SBIC_TRACE(dev); 2423 return SBIC_STATE_RUNNING; 2424 2425 case SBIC_CSR_DISC: 2426 case SBIC_CSR_DISC_1: 2427 dev->sc_flags &= ~(SBICF_INDMA|SBICF_SELECTED); 2428 2429 /* Try to schedule another target */ 2430 #ifdef DEBUG 2431 if(reselect_debug>1) 2432 printf("sbicnext target %d disconnected\n", dev->target); 2433 #endif 2434 TAILQ_INSERT_HEAD(&dev->nexus_list, acb, chain); 2435 ++dev->sc_tinfo[dev->target].dconns; 2436 dev->sc_nexus = NULL; 2437 dev->sc_xs = NULL; 2438 2439 if( acb->xs->flags & SCSI_POLL 2440 || (dev->sc_flags & SBICF_ICMD) 2441 || !sbic_parallel_operations ) { 2442 SBIC_TRACE(dev); 2443 return SBIC_STATE_DISCONNECT; 2444 } 2445 sbic_sched(dev); 2446 SBIC_TRACE(dev); 2447 return SBIC_STATE_DISCONNECT; 2448 2449 case SBIC_CSR_RSLT_NI: 2450 case SBIC_CSR_RSLT_IFY: 2451 GET_SBIC_rselid(regs, newtarget); 2452 /* check SBIC_RID_SIV? */ 2453 newtarget &= SBIC_RID_MASK; 2454 if (csr == SBIC_CSR_RSLT_IFY) { 2455 /* Read IFY msg to avoid lockup */ 2456 GET_SBIC_data(regs, newlun); 2457 WAIT_CIP(regs); 2458 newlun &= SBIC_TLUN_MASK; 2459 CSR_TRACE('r',csr,asr,newtarget); 2460 } else { 2461 /* Need to get IFY message */ 2462 for (newlun = 256; newlun; --newlun) { 2463 GET_SBIC_asr(regs, asr); 2464 if (asr & SBIC_ASR_INT) 2465 break; 2466 delay(1); 2467 } 2468 newlun = 0; /* XXXX */ 2469 if ((asr & SBIC_ASR_INT) == 0) { 2470 #ifdef DEBUG 2471 if (reselect_debug) 2472 printf("RSLT_NI - no IFFY message? asr %x\n", asr); 2473 #endif 2474 } else { 2475 GET_SBIC_csr(regs,csr); 2476 CSR_TRACE('n',csr,asr,newtarget); 2477 if (csr == (SBIC_CSR_MIS | MESG_IN_PHASE) || 2478 csr == (SBIC_CSR_MIS_1 | MESG_IN_PHASE) || 2479 csr == (SBIC_CSR_MIS_2 | MESG_IN_PHASE)) { 2480 sbicmsgin(dev); 2481 newlun = dev->sc_msg[0] & 7; 2482 } else { 2483 printf("RSLT_NI - not MESG_IN_PHASE %x\n", 2484 csr); 2485 } 2486 } 2487 } 2488 #ifdef DEBUG 2489 if(reselect_debug>1 || (reselect_debug && csr==SBIC_CSR_RSLT_NI)) 2490 printf("sbicnext: reselect %s from targ %d lun %d\n", 2491 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", 2492 newtarget, newlun); 2493 #endif 2494 if (dev->sc_nexus) { 2495 #ifdef DEBUG 2496 if (reselect_debug > 1) 2497 printf("%s: reselect %s with active command\n", 2498 dev->sc_dev.dv_xname, 2499 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY"); 2500 #ifdef DDB 2501 /* Debugger();*/ 2502 #endif 2503 #endif 2504 TAILQ_INSERT_HEAD(&dev->ready_list, dev->sc_nexus, chain); 2505 dev->sc_tinfo[dev->target].lubusy &= ~(1 << dev->lun); 2506 dev->sc_nexus = NULL; 2507 dev->sc_xs = NULL; 2508 } 2509 /* Reload sync values for this target */ 2510 if (dev->sc_sync[newtarget].state == SYNC_DONE) 2511 SET_SBIC_syn(regs, SBIC_SYN (dev->sc_sync[newtarget].offset, 2512 dev->sc_sync[newtarget].period)); 2513 else 2514 SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period)); 2515 for (acb = dev->nexus_list.tqh_first; acb; 2516 acb = acb->chain.tqe_next) { 2517 if (acb->xs->sc_link->target != newtarget || 2518 acb->xs->sc_link->lun != newlun) 2519 continue; 2520 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 2521 dev->sc_nexus = acb; 2522 dev->sc_xs = acb->xs; 2523 dev->sc_flags |= SBICF_SELECTED; 2524 dev->target = newtarget; 2525 dev->lun = newlun; 2526 break; 2527 } 2528 if (acb == NULL) { 2529 printf("%s: reselect %s targ %d not in nexus_list %p\n", 2530 dev->sc_dev.dv_xname, 2531 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", newtarget, 2532 &dev->nexus_list.tqh_first); 2533 panic("bad reselect in sbic"); 2534 } 2535 if (csr == SBIC_CSR_RSLT_IFY) 2536 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2537 break; 2538 2539 default: 2540 abort: 2541 /* 2542 * Something unexpected happened -- deal with it. 2543 */ 2544 printf("sbicnextstate: aborting csr %02x asr %02x\n", csr, asr); 2545 #ifdef DDB 2546 Debugger(); 2547 #endif 2548 #ifdef DEBUG 2549 if( data_pointer_debug > 1 ) 2550 printf("next dmastop: %d(%p:%lx)\n", 2551 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 2552 dev->sc_dmatimo = 0; 2553 #endif 2554 dev->sc_dmastop(dev); 2555 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2556 sbicerror(dev, regs, csr); 2557 sbicabort(dev, regs, "next"); 2558 if (dev->sc_flags & SBICF_INDMA) { 2559 /* 2560 * check for overlapping cache line, flush if so 2561 */ 2562 #ifdef M68040 2563 if (dev->sc_flags & SBICF_DCFLUSH) { 2564 #if 0 2565 printf("sibc: 68040 DMA cache flush needs fixing? %x:%x\n", 2566 dev->sc_xs->data, dev->sc_xs->datalen); 2567 #endif 2568 } 2569 #endif 2570 dev->sc_flags &= 2571 ~(SBICF_INDMA | SBICF_DCFLUSH); 2572 #ifdef DEBUG 2573 if( data_pointer_debug > 1 ) 2574 printf("next dmastop: %d(%p:%lx)\n", 2575 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 2576 dev->sc_dmatimo = 0; 2577 #endif 2578 dev->sc_dmastop(dev); 2579 sbic_scsidone(acb, -1); 2580 } 2581 SBIC_TRACE(dev); 2582 return SBIC_STATE_ERROR; 2583 } 2584 2585 SBIC_TRACE(dev); 2586 return(SBIC_STATE_RUNNING); 2587 } 2588 2589 2590 /* 2591 * Check if DMA can not be used with specified buffer 2592 */ 2593 2594 int 2595 sbiccheckdmap(bp, len, mask) 2596 void *bp; 2597 u_long len, mask; 2598 { 2599 u_char *buffer; 2600 u_long phy_buf; 2601 u_long phy_len; 2602 2603 buffer = bp; 2604 2605 if (len == 0) 2606 return(0); 2607 2608 while (len) { 2609 phy_buf = kvtop(buffer); 2610 if (len < (phy_len = NBPG - ((int) buffer & PGOFSET))) 2611 phy_len = len; 2612 if (phy_buf & mask) 2613 return(1); 2614 buffer += phy_len; 2615 len -= phy_len; 2616 } 2617 return(0); 2618 } 2619 2620 int 2621 sbictoscsiperiod(dev, regs, a) 2622 struct sbic_softc *dev; 2623 sbic_regmap_p regs; 2624 int a; 2625 { 2626 unsigned int fs; 2627 2628 /* 2629 * cycle = DIV / (2*CLK) 2630 * DIV = FS+2 2631 * best we can do is 200ns at 20Mhz, 2 cycles 2632 */ 2633 2634 GET_SBIC_myid(regs,fs); 2635 fs = (fs >>6) + 2; /* DIV */ 2636 fs = (fs * 10000) / (dev->sc_clkfreq<<1); /* Cycle, in ns */ 2637 if (a < 2) a = 8; /* map to Cycles */ 2638 return ((fs*a)>>2); /* in 4 ns units */ 2639 } 2640 2641 int 2642 sbicfromscsiperiod(dev, regs, p) 2643 struct sbic_softc *dev; 2644 sbic_regmap_p regs; 2645 int p; 2646 { 2647 register unsigned int fs, ret; 2648 2649 /* Just the inverse of the above */ 2650 2651 GET_SBIC_myid(regs,fs); 2652 fs = (fs >>6) + 2; /* DIV */ 2653 fs = (fs * 10000) / (dev->sc_clkfreq<<1); /* Cycle, in ns */ 2654 2655 ret = p << 2; /* in ns units */ 2656 ret = ret / fs; /* in Cycles */ 2657 if (ret < sbic_min_period) 2658 return(sbic_min_period); 2659 2660 /* verify rounding */ 2661 if (sbictoscsiperiod(dev, regs, ret) < p) 2662 ret++; 2663 return (ret >= 8) ? 0 : ret; 2664 } 2665 2666 #ifdef DEBUG 2667 2668 void 2669 sbicdumpstate() 2670 { 2671 u_char csr, asr; 2672 2673 GET_SBIC_asr(debug_sbic_regs,asr); 2674 GET_SBIC_csr(debug_sbic_regs,csr); 2675 printf("%s: asr:csr(%02x:%02x)->(%02x:%02x)\n", 2676 (routine==1)?"sbicgo": 2677 (routine==2)?"sbicintr": 2678 (routine==3)?"sbicicmd": 2679 (routine==4)?"sbicnext":"unknown", 2680 debug_asr, debug_csr, asr, csr); 2681 2682 } 2683 2684 void 2685 sbictimeout(dev) 2686 struct sbic_softc *dev; 2687 { 2688 int s, asr; 2689 2690 s = splbio(); 2691 if (dev->sc_dmatimo) { 2692 if (dev->sc_dmatimo > 1) { 2693 printf("%s: dma timeout #%d\n", 2694 dev->sc_dev.dv_xname, dev->sc_dmatimo - 1); 2695 GET_SBIC_asr(dev->sc_sbicp, asr); 2696 if( asr & SBIC_ASR_INT ) { 2697 /* We need to service a missed IRQ */ 2698 printf("Servicing a missed int:(%02x,%02x)->(%02x,??)\n", 2699 debug_asr, debug_csr, asr); 2700 sbicintr(dev); 2701 } 2702 sbicdumpstate(); 2703 } 2704 dev->sc_dmatimo++; 2705 } 2706 splx(s); 2707 timeout((void *)sbictimeout, dev, 30 * hz); 2708 } 2709 2710 void 2711 sbic_dump_acb(acb) 2712 struct sbic_acb *acb; 2713 { 2714 u_char *b = (u_char *) &acb->cmd; 2715 int i; 2716 2717 printf("acb@%p ", acb); 2718 if (acb->xs == NULL) { 2719 printf("<unused>\n"); 2720 return; 2721 } 2722 printf("(%d:%d) flags %2x clen %2d cmd ", acb->xs->sc_link->target, 2723 acb->xs->sc_link->lun, acb->flags, acb->clen); 2724 for (i = acb->clen; i; --i) 2725 printf(" %02x", *b++); 2726 printf("\n"); 2727 printf(" xs: %8p data %8p:%04x ", acb->xs, acb->xs->data, 2728 acb->xs->datalen); 2729 printf("va %8p:%04x ", acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 2730 printf("pa %8p:%04x tcnt %lx\n", acb->sc_pa.dc_addr, acb->sc_pa.dc_count, 2731 acb->sc_tcnt); 2732 } 2733 2734 void 2735 sbic_dump(dev) 2736 struct sbic_softc *dev; 2737 { 2738 sbic_regmap_p regs; 2739 u_char csr, asr; 2740 struct sbic_acb *acb; 2741 int s; 2742 int i; 2743 2744 s = splbio(); 2745 regs = dev->sc_sbicp; 2746 #if CSR_TRACE_SIZE 2747 printf("csr trace: "); 2748 i = csr_traceptr; 2749 do { 2750 printf("%c%02x%02x%02x ", csr_trace[i].whr, 2751 csr_trace[i].csr, csr_trace[i].asr, csr_trace[i].xtn); 2752 switch(csr_trace[i].whr) { 2753 case 'g': 2754 printf("go "); break; 2755 case 's': 2756 printf("select "); break; 2757 case 'y': 2758 printf("select+ "); break; 2759 case 'i': 2760 printf("intr "); break; 2761 case 'f': 2762 printf("finish "); break; 2763 case '>': 2764 printf("out "); break; 2765 case '<': 2766 printf("in "); break; 2767 case 'm': 2768 printf("msgin "); break; 2769 case 'x': 2770 printf("msginx "); break; 2771 case 'X': 2772 printf("msginX "); break; 2773 case 'r': 2774 printf("reselect "); break; 2775 case 'I': 2776 printf("icmd "); break; 2777 case 'a': 2778 printf("abort "); break; 2779 default: 2780 printf("? "); 2781 } 2782 switch(csr_trace[i].csr) { 2783 case 0x11: 2784 printf("INITIATOR"); break; 2785 case 0x16: 2786 printf("S_XFERRED"); break; 2787 case 0x20: 2788 printf("MSGIN_ACK"); break; 2789 case 0x41: 2790 printf("DISC"); break; 2791 case 0x42: 2792 printf("SEL_TIMEO"); break; 2793 case 0x80: 2794 printf("RSLT_NI"); break; 2795 case 0x81: 2796 printf("RSLT_IFY"); break; 2797 case 0x85: 2798 printf("DISC_1"); break; 2799 case 0x18: case 0x19: case 0x1a: 2800 case 0x1b: case 0x1e: case 0x1f: 2801 case 0x28: case 0x29: case 0x2a: 2802 case 0x2b: case 0x2e: case 0x2f: 2803 case 0x48: case 0x49: case 0x4a: 2804 case 0x4b: case 0x4e: case 0x4f: 2805 case 0x88: case 0x89: case 0x8a: 2806 case 0x8b: case 0x8e: case 0x8f: 2807 switch(csr_trace[i].csr & 0xf0) { 2808 case 0x10: 2809 printf("DONE_"); break; 2810 case 0x20: 2811 printf("STOP_"); break; 2812 case 0x40: 2813 printf("ERR_"); break; 2814 case 0x80: 2815 printf("REQ_"); break; 2816 } 2817 switch(csr_trace[i].csr & 7) { 2818 case 0: 2819 printf("DATA_OUT"); break; 2820 case 1: 2821 printf("DATA_IN"); break; 2822 case 2: 2823 printf("CMD"); break; 2824 case 3: 2825 printf("STATUS"); break; 2826 case 6: 2827 printf("MSG_OUT"); break; 2828 case 7: 2829 printf("MSG_IN"); break; 2830 default: 2831 printf("invld phs"); 2832 } 2833 break; 2834 default: printf("****"); break; 2835 } 2836 if (csr_trace[i].asr & SBIC_ASR_INT) 2837 printf(" ASR_INT"); 2838 if (csr_trace[i].asr & SBIC_ASR_LCI) 2839 printf(" ASR_LCI"); 2840 if (csr_trace[i].asr & SBIC_ASR_BSY) 2841 printf(" ASR_BSY"); 2842 if (csr_trace[i].asr & SBIC_ASR_CIP) 2843 printf(" ASR_CIP"); 2844 printf("\n"); 2845 i = (i + 1) & (CSR_TRACE_SIZE - 1); 2846 } while (i != csr_traceptr); 2847 #endif 2848 GET_SBIC_asr(regs, asr); 2849 if ((asr & SBIC_ASR_INT) == 0) 2850 GET_SBIC_csr(regs, csr); 2851 else 2852 csr = 0; 2853 printf("%s@%p regs %x asr %x csr %x\n", dev->sc_dev.dv_xname, 2854 dev, regs, asr, csr); 2855 if ((acb = dev->free_list.tqh_first)) { 2856 printf("Free list:\n"); 2857 while (acb) { 2858 sbic_dump_acb(acb); 2859 acb = acb->chain.tqe_next; 2860 } 2861 } 2862 if ((acb = dev->ready_list.tqh_first)) { 2863 printf("Ready list:\n"); 2864 while (acb) { 2865 sbic_dump_acb(acb); 2866 acb = acb->chain.tqe_next; 2867 } 2868 } 2869 if ((acb = dev->nexus_list.tqh_first)) { 2870 printf("Nexus list:\n"); 2871 while (acb) { 2872 sbic_dump_acb(acb); 2873 acb = acb->chain.tqe_next; 2874 } 2875 } 2876 if (dev->sc_nexus) { 2877 printf("nexus:\n"); 2878 sbic_dump_acb(dev->sc_nexus); 2879 } 2880 printf("sc_xs %p targ %d lun %d flags %x tcnt %lx dmacmd %x mask %lx\n", 2881 dev->sc_xs, dev->target, dev->lun, dev->sc_flags, dev->sc_tcnt, 2882 dev->sc_dmacmd, dev->sc_dmamask); 2883 for (i = 0; i < 8; ++i) { 2884 if (dev->sc_tinfo[i].cmds > 2) { 2885 printf("tgt %d: cmds %d disc %d senses %d lubusy %x\n", 2886 i, dev->sc_tinfo[i].cmds, 2887 dev->sc_tinfo[i].dconns, 2888 dev->sc_tinfo[i].senses, 2889 dev->sc_tinfo[i].lubusy); 2890 } 2891 } 2892 splx(s); 2893 } 2894 2895 #endif 2896
Indexes created Thu Oct 02 14:10:14 GMT 2025