sbic.c revision 1.28
1 /* $NetBSD: sbic.c,v 1.28 1996/10/13 03:07:29 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1994 Christian E. Hopps 5 * Copyright (c) 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * Van Jacobson of Lawrence Berkeley Laboratory. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the University of 22 * California, Berkeley and its contributors. 23 * 4. Neither the name of the University nor the names of its contributors 24 * may be used to endorse or promote products derived from this software 25 * without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 37 * SUCH DAMAGE. 38 * 39 * @(#)scsi.c 7.5 (Berkeley) 5/4/91 40 */ 41 42 /* 43 * AMIGA AMD 33C93 scsi adaptor driver 44 */ 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/device.h> 49 #include <sys/kernel.h> /* For hz */ 50 #include <sys/disklabel.h> 51 #include <sys/dkstat.h> 52 #include <sys/buf.h> 53 #include <scsi/scsi_all.h> 54 #include <scsi/scsiconf.h> 55 #include <vm/vm.h> 56 #include <vm/vm_kern.h> 57 #include <vm/vm_page.h> 58 #include <machine/pmap.h> 59 #include <machine/cpu.h> 60 #include <amiga/amiga/device.h> 61 #include <amiga/amiga/custom.h> 62 #include <amiga/amiga/isr.h> 63 #include <amiga/dev/dmavar.h> 64 #include <amiga/dev/sbicreg.h> 65 #include <amiga/dev/sbicvar.h> 66 67 /* These are for bounce buffers */ 68 #include <amiga/amiga/cc.h> 69 #include <amiga/dev/zbusvar.h> 70 71 #include <vm/pmap.h> 72 73 /* Since I can't find this in any other header files */ 74 #define SCSI_PHASE(reg) (reg&0x07) 75 76 /* 77 * SCSI delays 78 * In u-seconds, primarily for state changes on the SPC. 79 */ 80 #define SBIC_CMD_WAIT 50000 /* wait per step of 'immediate' cmds */ 81 #define SBIC_DATA_WAIT 50000 /* wait per data in/out step */ 82 #define SBIC_INIT_WAIT 50000 /* wait per step (both) during init */ 83 84 #define b_cylin b_resid 85 #define SBIC_WAIT(regs, until, timeo) sbicwait(regs, until, timeo, __LINE__) 86 87 int sbicicmd __P((struct sbic_softc *, int, int, void *, int, void *, int)); 88 int sbicgo __P((struct sbic_softc *, struct scsi_xfer *)); 89 int sbicdmaok __P((struct sbic_softc *, struct scsi_xfer *)); 90 int sbicwait __P((sbic_regmap_p, char, int , int)); 91 int sbiccheckdmap __P((void *, u_long, u_long)); 92 int sbicselectbus __P((struct sbic_softc *, sbic_regmap_p, u_char, u_char, u_char)); 93 int sbicxfstart __P((sbic_regmap_p, int, u_char, int)); 94 int sbicxfout __P((sbic_regmap_p regs, int, void *, int)); 95 int sbicfromscsiperiod __P((struct sbic_softc *, sbic_regmap_p, int)); 96 int sbictoscsiperiod __P((struct sbic_softc *, sbic_regmap_p, int)); 97 int sbicpoll __P((struct sbic_softc *)); 98 int sbicnextstate __P((struct sbic_softc *, u_char, u_char)); 99 int sbicmsgin __P((struct sbic_softc *)); 100 int sbicxfin __P((sbic_regmap_p regs, int, void *)); 101 int sbicabort __P((struct sbic_softc *, sbic_regmap_p, char *)); 102 void sbicxfdone __P((struct sbic_softc *, sbic_regmap_p, int)); 103 void sbicerror __P((struct sbic_softc *, sbic_regmap_p, u_char)); 104 void sbicstart __P((struct sbic_softc *)); 105 void sbicreset __P((struct sbic_softc *)); 106 void sbic_scsidone __P((struct sbic_acb *, int)); 107 void sbic_sched __P((struct sbic_softc *)); 108 void sbic_save_ptrs __P((struct sbic_softc *, sbic_regmap_p,int,int)); 109 void sbic_load_ptrs __P((struct sbic_softc *, sbic_regmap_p,int,int)); 110 #ifdef DEBUG 111 void sbicdumpstate __P((void)); 112 void sbic_dump_acb __P((struct sbic_acb *)); 113 #endif 114 115 /* 116 * Synch xfer parameters, and timing conversions 117 */ 118 int sbic_min_period = SBIC_SYN_MIN_PERIOD; /* in cycles = f(ICLK,FSn) */ 119 int sbic_max_offset = SBIC_SYN_MAX_OFFSET; /* pure number */ 120 121 int sbic_cmd_wait = SBIC_CMD_WAIT; 122 int sbic_data_wait = SBIC_DATA_WAIT; 123 int sbic_init_wait = SBIC_INIT_WAIT; 124 125 /* 126 * was broken before.. now if you want this you get it for all drives 127 * on sbic controllers. 128 */ 129 u_char sbic_inhibit_sync[8]; 130 int sbic_enable_reselect = 1; 131 int sbic_clock_override = 0; 132 int sbic_no_dma = 0; 133 int sbic_parallel_operations = 1; 134 135 #ifdef DEBUG 136 sbic_regmap_p debug_sbic_regs; 137 int sbicdma_ops = 0; /* total DMA operations */ 138 int sbicdma_bounces = 0; /* number operations using bounce buffer */ 139 int sbicdma_hits = 0; /* number of DMA chains that were contiguous */ 140 int sbicdma_misses = 0; /* number of DMA chains that were not contiguous */ 141 int sbicdma_saves = 0; 142 #define QPRINTF(a) if (sbic_debug > 1) printf a 143 int sbic_debug = 0; 144 int sync_debug = 0; 145 int sbic_dma_debug = 0; 146 int reselect_debug = 0; 147 int report_sense = 0; 148 int data_pointer_debug = 0; 149 u_char debug_asr, debug_csr, routine; 150 void sbictimeout __P((struct sbic_softc *dev)); 151 152 #define CSR_TRACE_SIZE 32 153 #if CSR_TRACE_SIZE 154 #define CSR_TRACE(w,c,a,x) do { \ 155 int s = splbio(); \ 156 csr_trace[csr_traceptr].whr = (w); csr_trace[csr_traceptr].csr = (c); \ 157 csr_trace[csr_traceptr].asr = (a); csr_trace[csr_traceptr].xtn = (x); \ 158 dma_cachectl((caddr_t)&csr_trace[csr_traceptr], sizeof(csr_trace[0])); \ 159 csr_traceptr = (csr_traceptr + 1) & (CSR_TRACE_SIZE - 1); \ 160 /* dma_cachectl((caddr_t)&csr_traceptr, sizeof(csr_traceptr));*/ \ 161 splx(s); \ 162 } while (0) 163 int csr_traceptr; 164 int csr_tracesize = CSR_TRACE_SIZE; 165 struct { 166 u_char whr; 167 u_char csr; 168 u_char asr; 169 u_char xtn; 170 } csr_trace[CSR_TRACE_SIZE]; 171 #else 172 #define CSR_TRACE(w,c,a,x) 173 #endif 174 175 #define SBIC_TRACE_SIZE 0 176 #if SBIC_TRACE_SIZE 177 #define SBIC_TRACE(dev) do { \ 178 int s = splbio(); \ 179 sbic_trace[sbic_traceptr].sp = &s; \ 180 sbic_trace[sbic_traceptr].line = __LINE__; \ 181 sbic_trace[sbic_traceptr].sr = s; \ 182 sbic_trace[sbic_traceptr].csr = csr_traceptr; \ 183 dma_cachectl(&sbic_trace[sbic_traceptr], sizeof(sbic_trace[0])); \ 184 sbic_traceptr = (sbic_traceptr + 1) & (SBIC_TRACE_SIZE - 1); \ 185 dma_cachectl(&sbic_traceptr, sizeof(sbic_traceptr)); \ 186 if (dev) dma_cachectl(dev, sizeof(*dev)); \ 187 splx(s); \ 188 } while (0) 189 int sbic_traceptr; 190 int sbic_tracesize = SBIC_TRACE_SIZE; 191 struct { 192 void *sp; 193 u_short line; 194 u_short sr; 195 int csr; 196 } sbic_trace[SBIC_TRACE_SIZE]; 197 #else 198 #define SBIC_TRACE(dev) 199 #endif 200 201 #else /* DEBUG */ 202 #define QPRINTF(a) 203 #define CSR_TRACE(w,c,a,x) 204 #define SBIC_TRACE(dev) 205 #endif /* DEBUG */ 206 207 /* 208 * default minphys routine for sbic based controllers 209 */ 210 void 211 sbic_minphys(bp) 212 struct buf *bp; 213 { 214 215 /* 216 * No max transfer at this level. 217 */ 218 minphys(bp); 219 } 220 221 /* 222 * Save DMA pointers. Take into account partial transfer. Shut down DMA. 223 */ 224 void 225 sbic_save_ptrs(dev, regs, target, lun) 226 struct sbic_softc *dev; 227 sbic_regmap_p regs; 228 int target, lun; 229 { 230 int count, asr, s; 231 struct sbic_acb* acb; 232 233 SBIC_TRACE(dev); 234 if( !dev->sc_cur ) return; 235 if( !(dev->sc_flags & SBICF_INDMA) ) return; /* DMA not active */ 236 237 s = splbio(); 238 239 acb = dev->sc_nexus; 240 count = -1; 241 do { 242 GET_SBIC_asr(regs, asr); 243 if( asr & SBIC_ASR_DBR ) { 244 printf("sbic_save_ptrs: asr %02x canceled!\n", asr); 245 splx(s); 246 SBIC_TRACE(dev); 247 return; 248 } 249 } while( asr & (SBIC_ASR_BSY|SBIC_ASR_CIP) ); 250 251 /* Save important state */ 252 /* must be done before dmastop */ 253 acb->sc_dmacmd = dev->sc_dmacmd; 254 SBIC_TC_GET(regs, count); 255 256 /* Shut down DMA ====CAREFUL==== */ 257 dev->sc_dmastop(dev); 258 dev->sc_flags &= ~SBICF_INDMA; 259 SBIC_TC_PUT(regs, 0); 260 261 #ifdef DEBUG 262 if(!count && sbic_debug) printf("%dcount0",target); 263 if(data_pointer_debug == -1) 264 printf("SBIC saving target %d data pointers from (%p,%x)%xASR:%02x", 265 target, dev->sc_cur->dc_addr, dev->sc_cur->dc_count, 266 acb->sc_dmacmd, asr); 267 #endif 268 269 /* Fixup partial xfers */ 270 acb->sc_kv.dc_addr += (dev->sc_tcnt - count); 271 acb->sc_kv.dc_count -= (dev->sc_tcnt - count); 272 acb->sc_pa.dc_addr += (dev->sc_tcnt - count); 273 acb->sc_pa.dc_count -= ((dev->sc_tcnt - count)>>1); 274 275 acb->sc_tcnt = dev->sc_tcnt = count; 276 #ifdef DEBUG 277 if(data_pointer_debug) 278 printf(" at (%p,%x):%x\n", 279 dev->sc_cur->dc_addr, dev->sc_cur->dc_count,count); 280 sbicdma_saves++; 281 #endif 282 splx(s); 283 SBIC_TRACE(dev); 284 } 285 286 287 /* 288 * DOES NOT RESTART DMA!!! 289 */ 290 void sbic_load_ptrs(dev, regs, target, lun) 291 struct sbic_softc *dev; 292 sbic_regmap_p regs; 293 int target, lun; 294 { 295 int s, count; 296 char* vaddr, * paddr; 297 struct sbic_acb *acb; 298 299 SBIC_TRACE(dev); 300 acb = dev->sc_nexus; 301 if( !acb->sc_kv.dc_count ) { 302 /* No data to xfer */ 303 SBIC_TRACE(dev); 304 return; 305 } 306 307 s = splbio(); 308 309 dev->sc_last = dev->sc_cur = &acb->sc_pa; 310 dev->sc_tcnt = acb->sc_tcnt; 311 dev->sc_dmacmd = acb->sc_dmacmd; 312 313 #ifdef DEBUG 314 sbicdma_ops++; 315 #endif 316 if( !dev->sc_tcnt ) { 317 /* sc_tcnt == 0 implies end of segment */ 318 319 /* do kvm to pa mappings */ 320 paddr = acb->sc_pa.dc_addr = 321 (char *) kvtop(acb->sc_kv.dc_addr); 322 323 vaddr = acb->sc_kv.dc_addr; 324 count = acb->sc_kv.dc_count; 325 for(count = (NBPG - ((int)vaddr & PGOFSET)); 326 count < acb->sc_kv.dc_count 327 && (char*)kvtop(vaddr + count + 4) == paddr + count + 4; 328 count += NBPG); 329 /* If it's all contiguous... */ 330 if(count > acb->sc_kv.dc_count ) { 331 count = acb->sc_kv.dc_count; 332 #ifdef DEBUG 333 sbicdma_hits++; 334 #endif 335 } else { 336 #ifdef DEBUG 337 sbicdma_misses++; 338 #endif 339 } 340 acb->sc_tcnt = count; 341 acb->sc_pa.dc_count = count >> 1; 342 343 #ifdef DEBUG 344 if(data_pointer_debug) 345 printf("DMA recalc:kv(%p,%x)pa(%p,%lx)\n", 346 acb->sc_kv.dc_addr, 347 acb->sc_kv.dc_count, 348 acb->sc_pa.dc_addr, 349 acb->sc_tcnt); 350 #endif 351 } 352 splx(s); 353 #ifdef DEBUG 354 if(data_pointer_debug) 355 printf("SBIC restoring target %d data pointers at (%p,%x)%x\n", 356 target, dev->sc_cur->dc_addr, dev->sc_cur->dc_count, 357 dev->sc_dmacmd); 358 #endif 359 SBIC_TRACE(dev); 360 } 361 362 /* 363 * used by specific sbic controller 364 * 365 * it appears that the higher level code does nothing with LUN's 366 * so I will too. I could plug it in, however so could they 367 * in scsi_scsi_cmd(). 368 */ 369 int 370 sbic_scsicmd(xs) 371 struct scsi_xfer *xs; 372 { 373 struct sbic_acb *acb; 374 struct sbic_softc *dev; 375 struct scsi_link *slp; 376 int flags, s, stat; 377 378 slp = xs->sc_link; 379 dev = slp->adapter_softc; 380 SBIC_TRACE(dev); 381 flags = xs->flags; 382 383 if (flags & SCSI_DATA_UIO) 384 panic("sbic: scsi data uio requested"); 385 386 if (dev->sc_nexus && flags & SCSI_POLL) 387 panic("sbic_scsicmd: busy"); 388 389 if (slp->target == slp->adapter_target) 390 return ESCAPE_NOT_SUPPORTED; 391 392 s = splbio(); 393 acb = dev->free_list.tqh_first; 394 if (acb) 395 TAILQ_REMOVE(&dev->free_list, acb, chain); 396 splx(s); 397 398 if (acb == NULL) { 399 #ifdef DEBUG 400 printf("sbic_scsicmd: unable to queue request for target %d\n", 401 slp->target); 402 #ifdef DDB 403 Debugger(); 404 #endif 405 #endif 406 xs->error = XS_DRIVER_STUFFUP; 407 SBIC_TRACE(dev); 408 return(TRY_AGAIN_LATER); 409 } 410 411 acb->flags = ACB_ACTIVE; 412 if (flags & SCSI_DATA_IN) 413 acb->flags |= ACB_DATAIN; 414 acb->xs = xs; 415 bcopy(xs->cmd, &acb->cmd, xs->cmdlen); 416 acb->clen = xs->cmdlen; 417 acb->sc_kv.dc_addr = xs->data; 418 acb->sc_kv.dc_count = xs->datalen; 419 acb->pa_addr = xs->data ? (char *)kvtop(xs->data) : 0; /* XXXX check */ 420 421 if (flags & SCSI_POLL) { 422 s = splbio(); 423 /* 424 * This has major side effects -- it locks up the machine 425 */ 426 427 dev->sc_flags |= SBICF_ICMD; 428 do { 429 while(dev->sc_nexus) 430 sbicpoll(dev); 431 dev->sc_nexus = acb; 432 dev->sc_stat[0] = -1; 433 dev->sc_xs = xs; 434 dev->target = slp->target; 435 dev->lun = slp->lun; 436 stat = sbicicmd(dev, slp->target, slp->lun, 437 &acb->cmd, acb->clen, 438 acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 439 } while (dev->sc_nexus != acb); 440 sbic_scsidone(acb, stat); 441 442 splx(s); 443 SBIC_TRACE(dev); 444 return(COMPLETE); 445 } 446 447 s = splbio(); 448 TAILQ_INSERT_TAIL(&dev->ready_list, acb, chain); 449 450 if (dev->sc_nexus) { 451 splx(s); 452 SBIC_TRACE(dev); 453 return(SUCCESSFULLY_QUEUED); 454 } 455 456 /* 457 * nothing is active, try to start it now. 458 */ 459 sbic_sched(dev); 460 splx(s); 461 462 SBIC_TRACE(dev); 463 /* TODO: add sbic_poll to do SCSI_POLL operations */ 464 #if 0 465 if (flags & SCSI_POLL) 466 return(COMPLETE); 467 #endif 468 return(SUCCESSFULLY_QUEUED); 469 } 470 471 /* 472 * attempt to start the next available command 473 */ 474 void 475 sbic_sched(dev) 476 struct sbic_softc *dev; 477 { 478 struct scsi_xfer *xs; 479 struct scsi_link *slp; 480 struct sbic_acb *acb; 481 int flags, /*phase,*/ stat, i; 482 483 SBIC_TRACE(dev); 484 if (dev->sc_nexus) 485 return; /* a command is current active */ 486 487 SBIC_TRACE(dev); 488 for (acb = dev->ready_list.tqh_first; acb; acb = acb->chain.tqe_next) { 489 slp = acb->xs->sc_link; 490 i = slp->target; 491 if (!(dev->sc_tinfo[i].lubusy & (1 << slp->lun))) { 492 struct sbic_tinfo *ti = &dev->sc_tinfo[i]; 493 494 TAILQ_REMOVE(&dev->ready_list, acb, chain); 495 dev->sc_nexus = acb; 496 slp = acb->xs->sc_link; 497 ti = &dev->sc_tinfo[slp->target]; 498 ti->lubusy |= (1 << slp->lun); 499 acb->sc_pa.dc_addr = acb->pa_addr; /* XXXX check */ 500 break; 501 } 502 } 503 504 SBIC_TRACE(dev); 505 if (acb == NULL) 506 return; /* did not find an available command */ 507 508 dev->sc_xs = xs = acb->xs; 509 slp = xs->sc_link; 510 flags = xs->flags; 511 512 if (flags & SCSI_RESET) 513 sbicreset(dev); 514 515 #ifdef DEBUG 516 if( data_pointer_debug > 1 ) 517 printf("sbic_sched(%d,%d)\n",slp->target,slp->lun); 518 #endif 519 dev->sc_stat[0] = -1; 520 dev->target = slp->target; 521 dev->lun = slp->lun; 522 if ( flags & SCSI_POLL || ( !sbic_parallel_operations 523 && (/*phase == STATUS_PHASE ||*/ 524 sbicdmaok(dev, xs) == 0) ) ) 525 stat = sbicicmd(dev, slp->target, slp->lun, &acb->cmd, 526 acb->clen, acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 527 else if (sbicgo(dev, xs) == 0) { 528 SBIC_TRACE(dev); 529 return; 530 } else 531 stat = dev->sc_stat[0]; 532 533 sbic_scsidone(acb, stat); 534 SBIC_TRACE(dev); 535 } 536 537 void 538 sbic_scsidone(acb, stat) 539 struct sbic_acb *acb; 540 int stat; 541 { 542 struct scsi_xfer *xs; 543 struct scsi_link *slp; 544 struct sbic_softc *dev; 545 int dosched = 0; 546 547 xs = acb->xs; 548 slp = xs->sc_link; 549 dev = slp->adapter_softc; 550 SBIC_TRACE(dev); 551 #ifdef DIAGNOSTIC 552 if (acb == NULL || xs == NULL) { 553 printf("sbic_scsidone -- (%d,%d) no scsi_xfer\n", 554 dev->target, dev->lun); 555 #ifdef DDB 556 Debugger(); 557 #endif 558 return; 559 } 560 #endif 561 /* 562 * is this right? 563 */ 564 xs->status = stat; 565 566 #ifdef DEBUG 567 if( data_pointer_debug > 1 ) 568 printf("scsidone: (%d,%d)->(%d,%d)%02x\n", 569 slp->target, slp->lun, 570 dev->target, dev->lun, stat); 571 if( xs->sc_link->target == dev->sc_link.adapter_target ) 572 panic("target == hostid"); 573 #endif 574 575 if (xs->error == XS_NOERROR && !(acb->flags & ACB_CHKSENSE)) { 576 if (stat == SCSI_CHECK) { 577 /* Schedule a REQUEST SENSE */ 578 struct scsi_sense *ss = (void *)&acb->cmd; 579 #ifdef DEBUG 580 if (report_sense) 581 printf("sbic_scsidone: autosense %02x targ %d lun %d", 582 acb->cmd.opcode, slp->target, slp->lun); 583 #endif 584 bzero(ss, sizeof(*ss)); 585 ss->opcode = REQUEST_SENSE; 586 ss->byte2 = slp->lun << 5; 587 ss->length = sizeof(struct scsi_sense_data); 588 acb->clen = sizeof(*ss); 589 acb->sc_kv.dc_addr = (char *)&xs->sense; 590 acb->sc_kv.dc_count = sizeof(struct scsi_sense_data); 591 acb->pa_addr = (char *)kvtop((u_char *)&xs->sense); /* XXX check */ 592 acb->flags = ACB_ACTIVE | ACB_CHKSENSE | ACB_DATAIN; 593 TAILQ_INSERT_HEAD(&dev->ready_list, acb, chain); 594 dev->sc_tinfo[slp->target].lubusy &= 595 ~(1 << slp->lun); 596 dev->sc_tinfo[slp->target].senses++; 597 if (dev->sc_nexus == acb) { 598 dev->sc_nexus = NULL; 599 dev->sc_xs = NULL; 600 sbic_sched(dev); 601 } 602 SBIC_TRACE(dev); 603 return; 604 } 605 } 606 if (xs->error == XS_NOERROR && (acb->flags & ACB_CHKSENSE)) { 607 xs->error = XS_SENSE; 608 #ifdef DEBUG 609 if (report_sense) 610 printf(" => %02x %02x\n", xs->sense.flags, 611 xs->sense.extra_bytes[3]); 612 #endif 613 } else { 614 xs->resid = 0; /* XXXX */ 615 } 616 #if whataboutthisone 617 case SCSI_BUSY: 618 xs->error = XS_BUSY; 619 break; 620 #endif 621 xs->flags |= ITSDONE; 622 623 /* 624 * Remove the ACB from whatever queue it's on. We have to do a bit of 625 * a hack to figure out which queue it's on. Note that it is *not* 626 * necessary to cdr down the ready queue, but we must cdr down the 627 * nexus queue and see if it's there, so we can mark the unit as no 628 * longer busy. This code is sickening, but it works. 629 */ 630 if (acb == dev->sc_nexus) { 631 dev->sc_nexus = NULL; 632 dev->sc_xs = NULL; 633 dev->sc_tinfo[slp->target].lubusy &= ~(1<<slp->lun); 634 if (dev->ready_list.tqh_first) 635 dosched = 1; /* start next command */ 636 } else if (dev->ready_list.tqh_last == &acb->chain.tqe_next) { 637 TAILQ_REMOVE(&dev->ready_list, acb, chain); 638 } else { 639 register struct sbic_acb *acb2; 640 for (acb2 = dev->nexus_list.tqh_first; acb2; 641 acb2 = acb2->chain.tqe_next) { 642 if (acb2 == acb) { 643 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 644 dev->sc_tinfo[slp->target].lubusy 645 &= ~(1<<slp->lun); 646 break; 647 } 648 } 649 if (acb2) 650 ; 651 else if (acb->chain.tqe_next) { 652 TAILQ_REMOVE(&dev->ready_list, acb, chain); 653 } else { 654 printf("%s: can't find matching acb\n", 655 dev->sc_dev.dv_xname); 656 #ifdef DDB 657 Debugger(); 658 #endif 659 } 660 } 661 /* Put it on the free list. */ 662 acb->flags = ACB_FREE; 663 TAILQ_INSERT_HEAD(&dev->free_list, acb, chain); 664 665 dev->sc_tinfo[slp->target].cmds++; 666 667 scsi_done(xs); 668 669 if (dosched) 670 sbic_sched(dev); 671 SBIC_TRACE(dev); 672 } 673 674 int 675 sbicdmaok(dev, xs) 676 struct sbic_softc *dev; 677 struct scsi_xfer *xs; 678 { 679 if (sbic_no_dma || xs->datalen & 0x1 || (u_int)xs->data & 0x3) 680 return(0); 681 /* 682 * controller supports dma to any addresses? 683 */ 684 else if ((dev->sc_flags & SBICF_BADDMA) == 0) 685 return(1); 686 /* 687 * this address is ok for dma? 688 */ 689 else if (sbiccheckdmap(xs->data, xs->datalen, dev->sc_dmamask) == 0) 690 return(1); 691 /* 692 * we have a bounce buffer? 693 */ 694 else if (dev->sc_tinfo[xs->sc_link->target].bounce) 695 return(1); 696 /* 697 * try to get one 698 */ 699 else if ((dev->sc_tinfo[xs->sc_link->target].bounce 700 = (char *)alloc_z2mem(MAXPHYS))) { 701 if (isztwomem(dev->sc_tinfo[xs->sc_link->target].bounce)) 702 printf("alloc ZII target %d bounce pa 0x%x\n", 703 xs->sc_link->target, 704 kvtop(dev->sc_tinfo[xs->sc_link->target].bounce)); 705 else if (dev->sc_tinfo[xs->sc_link->target].bounce) 706 printf("alloc CHIP target %d bounce pa 0x%p\n", 707 xs->sc_link->target, 708 PREP_DMA_MEM(dev->sc_tinfo[xs->sc_link->target].bounce)); 709 return(1); 710 } 711 712 return(0); 713 } 714 715 716 int 717 sbicwait(regs, until, timeo, line) 718 sbic_regmap_p regs; 719 char until; 720 int timeo; 721 int line; 722 { 723 u_char val; 724 int csr; 725 726 SBIC_TRACE((struct sbic_softc *)0); 727 if (timeo == 0) 728 timeo = 1000000; /* some large value.. */ 729 730 GET_SBIC_asr(regs,val); 731 while ((val & until) == 0) { 732 if (timeo-- == 0) { 733 GET_SBIC_csr(regs, csr); 734 printf("sbicwait TIMEO @%d with asr=x%x csr=x%x\n", 735 line, val, csr); 736 #if defined(DDB) && defined(DEBUG) 737 Debugger(); 738 #endif 739 return(val); /* Maybe I should abort */ 740 break; 741 } 742 DELAY(1); 743 GET_SBIC_asr(regs,val); 744 } 745 SBIC_TRACE((struct sbic_softc *)0); 746 return(val); 747 } 748 749 int 750 sbicabort(dev, regs, where) 751 struct sbic_softc *dev; 752 sbic_regmap_p regs; 753 char *where; 754 { 755 u_char csr, asr; 756 757 GET_SBIC_asr(regs, asr); 758 GET_SBIC_csr(regs, csr); 759 760 printf ("%s: abort %s: csr = 0x%02x, asr = 0x%02x\n", 761 dev->sc_dev.dv_xname, where, csr, asr); 762 763 764 #if 0 765 /* Clean up running command */ 766 if (dev->sc_nexus != NULL) { 767 dev->sc_nexus->xs->error = XS_DRIVER_STUFFUP; 768 sbic_scsidone(dev->sc_nexus, dev->sc_stat[0]); 769 } 770 while (acb = dev->nexus_list.tqh_first) { 771 acb->xs->error = XS_DRIVER_STUFFUP; 772 sbic_scsidone(acb, -1 /*acb->stat[0]*/); 773 } 774 #endif 775 776 /* Clean up chip itself */ 777 if (dev->sc_flags & SBICF_SELECTED) { 778 while( asr & SBIC_ASR_DBR ) { 779 /* sbic is jammed w/data. need to clear it */ 780 /* But we don't know what direction it needs to go */ 781 GET_SBIC_data(regs, asr); 782 printf("%s: abort %s: clearing data buffer 0x%02x\n", 783 dev->sc_dev.dv_xname, where, asr); 784 GET_SBIC_asr(regs, asr); 785 if( asr & SBIC_ASR_DBR ) /* Not the read direction, then */ 786 SET_SBIC_data(regs, asr); 787 GET_SBIC_asr(regs, asr); 788 } 789 WAIT_CIP(regs); 790 printf("%s: sbicabort - sending ABORT command\n", dev->sc_dev.dv_xname); 791 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 792 WAIT_CIP(regs); 793 794 GET_SBIC_asr(regs, asr); 795 if (asr & (SBIC_ASR_BSY|SBIC_ASR_LCI)) { 796 /* ok, get more drastic.. */ 797 798 printf("%s: sbicabort - asr %x, trying to reset\n", dev->sc_dev.dv_xname, asr); 799 sbicreset(dev); 800 dev->sc_flags &= ~SBICF_SELECTED; 801 return -1; 802 } 803 printf("%s: sbicabort - sending DISC command\n", dev->sc_dev.dv_xname); 804 SET_SBIC_cmd(regs, SBIC_CMD_DISC); 805 806 do { 807 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0); 808 GET_SBIC_csr (regs, csr); 809 CSR_TRACE('a',csr,asr,0); 810 } while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) 811 && (csr != SBIC_CSR_CMD_INVALID)); 812 813 /* lets just hope it worked.. */ 814 dev->sc_flags &= ~SBICF_SELECTED; 815 } 816 return -1; 817 } 818 819 820 /* 821 * Initialize driver-private structures 822 */ 823 824 void 825 sbicinit(dev) 826 struct sbic_softc *dev; 827 { 828 sbic_regmap_p regs; 829 u_int i; 830 struct sbic_acb *acb; 831 u_int inhibit_sync; 832 833 extern u_long scsi_nosync; 834 extern int shift_nosync; 835 836 regs = dev->sc_sbicp; 837 838 if ((dev->sc_flags & SBICF_ALIVE) == 0) { 839 TAILQ_INIT(&dev->ready_list); 840 TAILQ_INIT(&dev->nexus_list); 841 TAILQ_INIT(&dev->free_list); 842 dev->sc_nexus = NULL; 843 dev->sc_xs = NULL; 844 acb = dev->sc_acb; 845 bzero(acb, sizeof(dev->sc_acb)); 846 for (i = 0; i < sizeof(dev->sc_acb) / sizeof(*acb); i++) { 847 TAILQ_INSERT_TAIL(&dev->free_list, acb, chain); 848 acb++; 849 } 850 bzero(dev->sc_tinfo, sizeof(dev->sc_tinfo)); 851 #ifdef DEBUG 852 /* make sure timeout is really not needed */ 853 timeout((void *)sbictimeout, dev, 30 * hz); 854 #endif 855 856 } else panic("sbic: reinitializing driver!"); 857 858 dev->sc_flags |= SBICF_ALIVE; 859 dev->sc_flags &= ~SBICF_SELECTED; 860 861 /* initialize inhibit array */ 862 if (scsi_nosync) { 863 inhibit_sync = (scsi_nosync >> shift_nosync) & 0xff; 864 shift_nosync += 8; 865 #ifdef DEBUG 866 if (inhibit_sync) 867 printf("%s: Inhibiting synchronous transfer %02x\n", 868 dev->sc_dev.dv_xname, inhibit_sync); 869 #endif 870 for (i = 0; i < 8; ++i) 871 if (inhibit_sync & (1 << i)) 872 sbic_inhibit_sync[i] = 1; 873 } 874 875 sbicreset(dev); 876 } 877 878 void 879 sbicreset(dev) 880 struct sbic_softc *dev; 881 { 882 sbic_regmap_p regs; 883 u_int my_id, s; 884 u_char csr; 885 #if 0 886 u_int i; 887 struct sbic_acb *acb; 888 #endif 889 890 regs = dev->sc_sbicp; 891 #if 0 892 if (dev->sc_flags & SBICF_ALIVE) { 893 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 894 WAIT_CIP(regs); 895 } 896 #else 897 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 898 WAIT_CIP(regs); 899 #endif 900 s = splbio(); 901 my_id = dev->sc_link.adapter_target & SBIC_ID_MASK; 902 903 /* Enable advanced mode */ 904 my_id |= SBIC_ID_EAF /*| SBIC_ID_EHP*/ ; 905 SET_SBIC_myid(regs, my_id); 906 907 /* 908 * Disable interrupts (in dmainit) then reset the chip 909 */ 910 SET_SBIC_cmd(regs, SBIC_CMD_RESET); 911 DELAY(25); 912 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 913 GET_SBIC_csr(regs, csr); /* clears interrupt also */ 914 915 if (dev->sc_clkfreq < 110) 916 my_id |= SBIC_ID_FS_8_10; 917 else if (dev->sc_clkfreq < 160) 918 my_id |= SBIC_ID_FS_12_15; 919 else if (dev->sc_clkfreq < 210) 920 my_id |= SBIC_ID_FS_16_20; 921 922 SET_SBIC_myid(regs, my_id); 923 924 /* 925 * Set up various chip parameters 926 */ 927 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI /* | SBIC_CTL_HSP */ 928 | SBIC_MACHINE_DMA_MODE); 929 /* 930 * don't allow (re)selection (SBIC_RID_ES) 931 * until we can handle target mode!! 932 */ 933 SET_SBIC_rselid(regs, SBIC_RID_ER); 934 SET_SBIC_syn(regs, 0); /* asynch for now */ 935 936 /* 937 * anything else was zeroed by reset 938 */ 939 splx(s); 940 941 #if 0 942 if ((dev->sc_flags & SBICF_ALIVE) == 0) { 943 TAILQ_INIT(&dev->ready_list); 944 TAILQ_INIT(&dev->nexus_list); 945 TAILQ_INIT(&dev->free_list); 946 dev->sc_nexus = NULL; 947 dev->sc_xs = NULL; 948 acb = dev->sc_acb; 949 bzero(acb, sizeof(dev->sc_acb)); 950 for (i = 0; i < sizeof(dev->sc_acb) / sizeof(*acb); i++) { 951 TAILQ_INSERT_TAIL(&dev->free_list, acb, chain); 952 acb++; 953 } 954 bzero(dev->sc_tinfo, sizeof(dev->sc_tinfo)); 955 } else { 956 if (dev->sc_nexus != NULL) { 957 dev->sc_nexus->xs->error = XS_DRIVER_STUFFUP; 958 sbic_scsidone(dev->sc_nexus, dev->sc_stat[0]); 959 } 960 while (acb = dev->nexus_list.tqh_first) { 961 acb->xs->error = XS_DRIVER_STUFFUP; 962 sbic_scsidone(acb, -1 /*acb->stat[0]*/); 963 } 964 } 965 966 dev->sc_flags |= SBICF_ALIVE; 967 #endif 968 dev->sc_flags &= ~SBICF_SELECTED; 969 } 970 971 void 972 sbicerror(dev, regs, csr) 973 struct sbic_softc *dev; 974 sbic_regmap_p regs; 975 u_char csr; 976 { 977 struct scsi_xfer *xs; 978 979 xs = dev->sc_xs; 980 981 #ifdef DIAGNOSTIC 982 if (xs == NULL) 983 panic("sbicerror"); 984 #endif 985 if (xs->flags & SCSI_SILENT) 986 return; 987 988 printf("%s: ", dev->sc_dev.dv_xname); 989 printf("csr == 0x%02x\n", csr); /* XXX */ 990 } 991 992 /* 993 * select the bus, return when selected or error. 994 */ 995 int 996 sbicselectbus(dev, regs, target, lun, our_addr) 997 struct sbic_softc *dev; 998 sbic_regmap_p regs; 999 u_char target, lun, our_addr; 1000 { 1001 u_char asr, csr, id; 1002 1003 SBIC_TRACE(dev); 1004 QPRINTF(("sbicselectbus %d\n", target)); 1005 1006 /* 1007 * if we're already selected, return (XXXX panic maybe?) 1008 */ 1009 if (dev->sc_flags & SBICF_SELECTED) { 1010 SBIC_TRACE(dev); 1011 return(1); 1012 } 1013 1014 /* 1015 * issue select 1016 */ 1017 SBIC_TC_PUT(regs, 0); 1018 SET_SBIC_selid(regs, target); 1019 SET_SBIC_timeo(regs, SBIC_TIMEOUT(250,dev->sc_clkfreq)); 1020 1021 /* 1022 * set sync or async 1023 */ 1024 if (dev->sc_sync[target].state == SYNC_DONE) 1025 SET_SBIC_syn(regs, SBIC_SYN (dev->sc_sync[target].offset, 1026 dev->sc_sync[target].period)); 1027 else 1028 SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period)); 1029 1030 GET_SBIC_asr(regs, asr); 1031 if( asr & (SBIC_ASR_INT|SBIC_ASR_BSY) ) { 1032 /* This means we got ourselves reselected upon */ 1033 /* printf("sbicselectbus: INT/BSY asr %02x\n", asr);*/ 1034 #ifdef DDB 1035 /* Debugger();*/ 1036 #endif 1037 SBIC_TRACE(dev); 1038 return 1; 1039 } 1040 1041 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN); 1042 1043 /* 1044 * wait for select (merged from seperate function may need 1045 * cleanup) 1046 */ 1047 WAIT_CIP(regs); 1048 do { 1049 asr = SBIC_WAIT(regs, SBIC_ASR_INT | SBIC_ASR_LCI, 0); 1050 if (asr & SBIC_ASR_LCI) { 1051 #ifdef DEBUG 1052 if (reselect_debug) 1053 printf("sbicselectbus: late LCI asr %02x\n", asr); 1054 #endif 1055 SBIC_TRACE(dev); 1056 return 1; 1057 } 1058 GET_SBIC_csr (regs, csr); 1059 CSR_TRACE('s',csr,asr,target); 1060 QPRINTF(("%02x ", csr)); 1061 if( csr == SBIC_CSR_RSLT_NI || csr == SBIC_CSR_RSLT_IFY) { 1062 #ifdef DEBUG 1063 if(reselect_debug) 1064 printf("sbicselectbus: reselected asr %02x\n", asr); 1065 #endif 1066 /* We need to handle this now so we don't lock up later */ 1067 sbicnextstate(dev, csr, asr); 1068 SBIC_TRACE(dev); 1069 return 1; 1070 } 1071 if( csr == SBIC_CSR_SLT || csr == SBIC_CSR_SLT_ATN) { 1072 panic("sbicselectbus: target issued select!"); 1073 return 1; 1074 } 1075 } while (csr != (SBIC_CSR_MIS_2|MESG_OUT_PHASE) 1076 && csr != (SBIC_CSR_MIS_2|CMD_PHASE) && csr != SBIC_CSR_SEL_TIMEO); 1077 1078 /* Enable (or not) reselection */ 1079 if(!sbic_enable_reselect && dev->nexus_list.tqh_first == NULL) 1080 SET_SBIC_rselid (regs, 0); 1081 else 1082 SET_SBIC_rselid (regs, SBIC_RID_ER); 1083 1084 if (csr == (SBIC_CSR_MIS_2|CMD_PHASE)) { 1085 dev->sc_flags |= SBICF_SELECTED; /* device ignored ATN */ 1086 GET_SBIC_selid(regs, id); 1087 dev->target = id; 1088 GET_SBIC_tlun(regs,dev->lun); 1089 if( dev->lun & SBIC_TLUN_VALID ) 1090 dev->lun &= SBIC_TLUN_MASK; 1091 else 1092 dev->lun = lun; 1093 } else if (csr == (SBIC_CSR_MIS_2|MESG_OUT_PHASE)) { 1094 /* 1095 * Send identify message 1096 * (SCSI-2 requires an identify msg (?)) 1097 */ 1098 GET_SBIC_selid(regs, id); 1099 dev->target = id; 1100 GET_SBIC_tlun(regs,dev->lun); 1101 if( dev->lun & SBIC_TLUN_VALID ) 1102 dev->lun &= SBIC_TLUN_MASK; 1103 else 1104 dev->lun = lun; 1105 /* 1106 * handle drives that don't want to be asked 1107 * whether to go sync at all. 1108 */ 1109 if (sbic_inhibit_sync[id] 1110 && dev->sc_sync[id].state == SYNC_START) { 1111 #ifdef DEBUG 1112 if (sync_debug) 1113 printf("Forcing target %d asynchronous.\n", id); 1114 #endif 1115 dev->sc_sync[id].offset = 0; 1116 dev->sc_sync[id].period = sbic_min_period; 1117 dev->sc_sync[id].state = SYNC_DONE; 1118 } 1119 1120 1121 if (dev->sc_sync[id].state != SYNC_START){ 1122 if( dev->sc_xs->flags & SCSI_POLL 1123 || (dev->sc_flags & SBICF_ICMD) 1124 || !sbic_enable_reselect ) 1125 SEND_BYTE (regs, MSG_IDENTIFY | lun); 1126 else 1127 SEND_BYTE (regs, MSG_IDENTIFY_DR | lun); 1128 } else { 1129 /* 1130 * try to initiate a sync transfer. 1131 * So compose the sync message we're going 1132 * to send to the target 1133 */ 1134 1135 #ifdef DEBUG 1136 if (sync_debug) 1137 printf("Sending sync request to target %d ... ", 1138 id); 1139 #endif 1140 /* 1141 * setup scsi message sync message request 1142 */ 1143 dev->sc_msg[0] = MSG_IDENTIFY | lun; 1144 dev->sc_msg[1] = MSG_EXT_MESSAGE; 1145 dev->sc_msg[2] = 3; 1146 dev->sc_msg[3] = MSG_SYNC_REQ; 1147 dev->sc_msg[4] = sbictoscsiperiod(dev, regs, 1148 sbic_min_period); 1149 dev->sc_msg[5] = sbic_max_offset; 1150 1151 if (sbicxfstart(regs, 6, MESG_OUT_PHASE, sbic_cmd_wait)) 1152 sbicxfout(regs, 6, dev->sc_msg, MESG_OUT_PHASE); 1153 1154 dev->sc_sync[id].state = SYNC_SENT; 1155 #ifdef DEBUG 1156 if (sync_debug) 1157 printf ("sent\n"); 1158 #endif 1159 } 1160 1161 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0); 1162 GET_SBIC_csr (regs, csr); 1163 CSR_TRACE('y',csr,asr,target); 1164 QPRINTF(("[%02x]", csr)); 1165 #ifdef DEBUG 1166 if (sync_debug && dev->sc_sync[id].state == SYNC_SENT) 1167 printf("csr-result of last msgout: 0x%x\n", csr); 1168 #endif 1169 1170 if (csr != SBIC_CSR_SEL_TIMEO) 1171 dev->sc_flags |= SBICF_SELECTED; 1172 } 1173 if (csr == SBIC_CSR_SEL_TIMEO) 1174 dev->sc_xs->error = XS_SELTIMEOUT; 1175 1176 QPRINTF(("\n")); 1177 1178 SBIC_TRACE(dev); 1179 return(csr == SBIC_CSR_SEL_TIMEO); 1180 } 1181 1182 int 1183 sbicxfstart(regs, len, phase, wait) 1184 sbic_regmap_p regs; 1185 int len, wait; 1186 u_char phase; 1187 { 1188 u_char id; 1189 1190 switch (phase) { 1191 case DATA_IN_PHASE: 1192 case MESG_IN_PHASE: 1193 GET_SBIC_selid (regs, id); 1194 id |= SBIC_SID_FROM_SCSI; 1195 SET_SBIC_selid (regs, id); 1196 SBIC_TC_PUT (regs, (unsigned)len); 1197 break; 1198 case DATA_OUT_PHASE: 1199 case MESG_OUT_PHASE: 1200 case CMD_PHASE: 1201 GET_SBIC_selid (regs, id); 1202 id &= ~SBIC_SID_FROM_SCSI; 1203 SET_SBIC_selid (regs, id); 1204 SBIC_TC_PUT (regs, (unsigned)len); 1205 break; 1206 default: 1207 SBIC_TC_PUT (regs, 0); 1208 } 1209 QPRINTF(("sbicxfstart %d, %d, %d\n", len, phase, wait)); 1210 1211 return(1); 1212 } 1213 1214 int 1215 sbicxfout(regs, len, bp, phase) 1216 sbic_regmap_p regs; 1217 int len; 1218 void *bp; 1219 int phase; 1220 { 1221 u_char orig_csr, asr, *buf; 1222 int wait; 1223 1224 buf = bp; 1225 wait = sbic_data_wait; 1226 1227 QPRINTF(("sbicxfout {%d} %02x %02x %02x %02x %02x " 1228 "%02x %02x %02x %02x %02x\n", len, buf[0], buf[1], buf[2], 1229 buf[3], buf[4], buf[5], buf[6], buf[7], buf[8], buf[9])); 1230 1231 GET_SBIC_csr (regs, orig_csr); 1232 CSR_TRACE('>',orig_csr,0,0); 1233 1234 /* 1235 * sigh.. WD-PROTO strikes again.. sending the command in one go 1236 * causes the chip to lock up if talking to certain (misbehaving?) 1237 * targets. Anyway, this procedure should work for all targets, but 1238 * it's slightly slower due to the overhead 1239 */ 1240 WAIT_CIP (regs); 1241 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1242 for (;len > 0; len--) { 1243 GET_SBIC_asr (regs, asr); 1244 while ((asr & SBIC_ASR_DBR) == 0) { 1245 if ((asr & SBIC_ASR_INT) || --wait < 0) { 1246 #ifdef DEBUG 1247 if (sbic_debug) 1248 printf("sbicxfout fail: l%d i%x w%d\n", 1249 len, asr, wait); 1250 #endif 1251 return (len); 1252 } 1253 /* DELAY(1);*/ 1254 GET_SBIC_asr (regs, asr); 1255 } 1256 1257 SET_SBIC_data (regs, *buf); 1258 buf++; 1259 } 1260 SBIC_TC_GET(regs, len); 1261 QPRINTF(("sbicxfout done %d bytes\n", len)); 1262 /* 1263 * this leaves with one csr to be read 1264 */ 1265 return(0); 1266 } 1267 1268 /* returns # bytes left to read */ 1269 int 1270 sbicxfin(regs, len, bp) 1271 sbic_regmap_p regs; 1272 int len; 1273 void *bp; 1274 { 1275 int wait; 1276 u_char *obp, *buf; 1277 u_char orig_csr, csr, asr; 1278 1279 wait = sbic_data_wait; 1280 obp = bp; 1281 buf = bp; 1282 1283 GET_SBIC_csr (regs, orig_csr); 1284 CSR_TRACE('<',orig_csr,0,0); 1285 1286 QPRINTF(("sbicxfin %d, csr=%02x\n", len, orig_csr)); 1287 1288 WAIT_CIP (regs); 1289 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1290 for (;len > 0; len--) { 1291 GET_SBIC_asr (regs, asr); 1292 if((asr & SBIC_ASR_PE)) { 1293 #ifdef DEBUG 1294 printf("sbicxfin parity error: l%d i%x w%d\n", 1295 len, asr, wait); 1296 /* return ((unsigned long)buf - (unsigned long)bp); */ 1297 #ifdef DDB 1298 Debugger(); 1299 #endif 1300 #endif 1301 } 1302 while ((asr & SBIC_ASR_DBR) == 0) { 1303 if ((asr & SBIC_ASR_INT) || --wait < 0) { 1304 #ifdef DEBUG 1305 if (sbic_debug) { 1306 QPRINTF(("sbicxfin fail:{%d} %02x %02x %02x %02x %02x %02x " 1307 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1308 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1309 printf("sbicxfin fail: l%d i%x w%d\n", 1310 len, asr, wait); 1311 } 1312 #endif 1313 return len; 1314 } 1315 1316 if( ! asr & SBIC_ASR_BSY ) { 1317 GET_SBIC_csr(regs, csr); 1318 CSR_TRACE('<',csr,asr,len); 1319 QPRINTF(("[CSR%02xASR%02x]", csr, asr)); 1320 } 1321 1322 /* DELAY(1);*/ 1323 GET_SBIC_asr (regs, asr); 1324 } 1325 1326 GET_SBIC_data (regs, *buf); 1327 /* QPRINTF(("asr=%02x, csr=%02x, data=%02x\n", asr, csr, *buf));*/ 1328 buf++; 1329 } 1330 1331 QPRINTF(("sbicxfin {%d} %02x %02x %02x %02x %02x %02x " 1332 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1333 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1334 1335 /* this leaves with one csr to be read */ 1336 return len; 1337 } 1338 1339 /* 1340 * SCSI 'immediate' command: issue a command to some SCSI device 1341 * and get back an 'immediate' response (i.e., do programmed xfer 1342 * to get the response data). 'cbuf' is a buffer containing a scsi 1343 * command of length clen bytes. 'buf' is a buffer of length 'len' 1344 * bytes for data. The transfer direction is determined by the device 1345 * (i.e., by the scsi bus data xfer phase). If 'len' is zero, the 1346 * command must supply no data. 1347 */ 1348 int 1349 sbicicmd(dev, target, lun, cbuf, clen, buf, len) 1350 struct sbic_softc *dev; 1351 void *cbuf, *buf; 1352 int clen, len; 1353 { 1354 sbic_regmap_p regs; 1355 u_char phase, csr, asr; 1356 int wait, i; 1357 struct sbic_acb *acb; 1358 1359 #define CSR_LOG_BUF_SIZE 0 1360 #if CSR_LOG_BUF_SIZE 1361 int bufptr; 1362 int csrbuf[CSR_LOG_BUF_SIZE]; 1363 bufptr=0; 1364 #endif 1365 1366 SBIC_TRACE(dev); 1367 regs = dev->sc_sbicp; 1368 acb = dev->sc_nexus; 1369 1370 /* Make sure pointers are OK */ 1371 dev->sc_last = dev->sc_cur = &acb->sc_pa; 1372 dev->sc_tcnt = acb->sc_tcnt = 0; 1373 acb->sc_pa.dc_count = 0; /* No DMA */ 1374 acb->sc_kv.dc_addr = buf; 1375 acb->sc_kv.dc_count = len; 1376 1377 #ifdef DEBUG 1378 routine = 3; 1379 debug_sbic_regs = regs; /* store this to allow debug calls */ 1380 if( data_pointer_debug > 1 ) 1381 printf("sbicicmd(%d,%d):%d\n", target, lun, 1382 acb->sc_kv.dc_count); 1383 #endif 1384 1385 /* 1386 * set the sbic into non-DMA mode 1387 */ 1388 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI /*| SBIC_CTL_HSP*/); 1389 1390 dev->sc_stat[0] = 0xff; 1391 dev->sc_msg[0] = 0xff; 1392 i = 1; /* pre-load */ 1393 1394 /* We're stealing the SCSI bus */ 1395 dev->sc_flags |= SBICF_ICMD; 1396 1397 do { 1398 /* 1399 * select the SCSI bus (it's an error if bus isn't free) 1400 */ 1401 if (!( dev->sc_flags & SBICF_SELECTED ) 1402 && sbicselectbus(dev, regs, target, lun, dev->sc_scsiaddr)) { 1403 /*printf("sbicicmd trying to select busy bus!\n");*/ 1404 dev->sc_flags &= ~SBICF_ICMD; 1405 return(-1); 1406 } 1407 1408 /* 1409 * Wait for a phase change (or error) then let the device sequence 1410 * us through the various SCSI phases. 1411 */ 1412 1413 wait = sbic_cmd_wait; 1414 1415 asr = GET_SBIC_asr (regs, asr); 1416 GET_SBIC_csr (regs, csr); 1417 CSR_TRACE('I',csr,asr,target); 1418 QPRINTF((">ASR:%02xCSR:%02x<", asr, csr)); 1419 1420 #if CSR_LOG_BUF_SIZE 1421 csrbuf[bufptr++] = csr; 1422 #endif 1423 1424 1425 switch (csr) { 1426 case SBIC_CSR_S_XFERRED: 1427 case SBIC_CSR_DISC: 1428 case SBIC_CSR_DISC_1: 1429 dev->sc_flags &= ~SBICF_SELECTED; 1430 GET_SBIC_cmd_phase (regs, phase); 1431 if (phase == 0x60) { 1432 GET_SBIC_tlun (regs, dev->sc_stat[0]); 1433 i = 0; /* done */ 1434 /* break; */ /* Bypass all the state gobldygook */ 1435 } else { 1436 #ifdef DEBUG 1437 if(reselect_debug>1) 1438 printf("sbicicmd: handling disconnect\n"); 1439 #endif 1440 i = SBIC_STATE_DISCONNECT; 1441 } 1442 break; 1443 1444 case SBIC_CSR_XFERRED|CMD_PHASE: 1445 case SBIC_CSR_MIS|CMD_PHASE: 1446 case SBIC_CSR_MIS_1|CMD_PHASE: 1447 case SBIC_CSR_MIS_2|CMD_PHASE: 1448 if (sbicxfstart(regs, clen, CMD_PHASE, sbic_cmd_wait)) 1449 if (sbicxfout(regs, clen, 1450 cbuf, CMD_PHASE)) 1451 i = sbicabort(dev, regs,"icmd sending cmd"); 1452 #if 0 1453 GET_SBIC_csr(regs, csr); /* Lets us reload tcount */ 1454 WAIT_CIP(regs); 1455 GET_SBIC_asr(regs, asr); 1456 CSR_TRACE('I',csr,asr,target); 1457 if( asr & (SBIC_ASR_BSY|SBIC_ASR_LCI|SBIC_ASR_CIP) ) 1458 printf("next: cmd sent asr %02x, csr %02x\n", 1459 asr, csr); 1460 #endif 1461 break; 1462 1463 #if 0 1464 case SBIC_CSR_XFERRED|DATA_OUT_PHASE: 1465 case SBIC_CSR_XFERRED|DATA_IN_PHASE: 1466 case SBIC_CSR_MIS|DATA_OUT_PHASE: 1467 case SBIC_CSR_MIS|DATA_IN_PHASE: 1468 case SBIC_CSR_MIS_1|DATA_OUT_PHASE: 1469 case SBIC_CSR_MIS_1|DATA_IN_PHASE: 1470 case SBIC_CSR_MIS_2|DATA_OUT_PHASE: 1471 case SBIC_CSR_MIS_2|DATA_IN_PHASE: 1472 if (acb->sc_kv.dc_count <= 0) 1473 i = sbicabort(dev, regs, "icmd out of data"); 1474 else { 1475 wait = sbic_data_wait; 1476 if (sbicxfstart(regs, 1477 acb->sc_kv.dc_count, 1478 SBIC_PHASE(csr), wait)) 1479 if (csr & 0x01) 1480 /* data in? */ 1481 i=sbicxfin(regs, 1482 acb->sc_kv.dc_count, 1483 acb->sc_kv.dc_addr); 1484 else 1485 i=sbicxfout(regs, 1486 acb->sc_kv.dc_count, 1487 acb->sc_kv.dc_addr, 1488 SBIC_PHASE(csr)); 1489 acb->sc_kv.dc_addr += 1490 (acb->sc_kv.dc_count - i); 1491 acb->sc_kv.dc_count = i; 1492 i = 1; 1493 } 1494 break; 1495 1496 #endif 1497 case SBIC_CSR_XFERRED|STATUS_PHASE: 1498 case SBIC_CSR_MIS|STATUS_PHASE: 1499 case SBIC_CSR_MIS_1|STATUS_PHASE: 1500 case SBIC_CSR_MIS_2|STATUS_PHASE: 1501 /* 1502 * the sbic does the status/cmd-complete reading ok, 1503 * so do this with its hi-level commands. 1504 */ 1505 #ifdef DEBUG 1506 if(sbic_debug) 1507 printf("SBICICMD status phase\n"); 1508 #endif 1509 SBIC_TC_PUT(regs, 0); 1510 SET_SBIC_cmd_phase(regs, 0x46); 1511 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1512 break; 1513 1514 #if THIS_IS_A_RESERVED_STATE 1515 case BUS_FREE_PHASE: /* This is not legal */ 1516 if( dev->sc_stat[0] != 0xff ) 1517 goto out; 1518 break; 1519 #endif 1520 1521 default: 1522 i = sbicnextstate(dev, csr, asr); 1523 } 1524 1525 /* 1526 * make sure the last command was taken, 1527 * ie. we're not hunting after an ignored command.. 1528 */ 1529 GET_SBIC_asr(regs, asr); 1530 1531 /* tapes may take a loooong time.. */ 1532 while (asr & SBIC_ASR_BSY){ 1533 if(asr & SBIC_ASR_DBR) { 1534 printf("sbicicmd: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", 1535 csr,asr); 1536 #ifdef DDB 1537 Debugger(); 1538 #endif 1539 /* SBIC is jammed */ 1540 /* DUNNO which direction */ 1541 /* Try old direction */ 1542 GET_SBIC_data(regs,i); 1543 GET_SBIC_asr(regs, asr); 1544 if( asr & SBIC_ASR_DBR) /* Wants us to write */ 1545 SET_SBIC_data(regs,i); 1546 } 1547 GET_SBIC_asr(regs, asr); 1548 } 1549 1550 /* 1551 * wait for last command to complete 1552 */ 1553 if (asr & SBIC_ASR_LCI) { 1554 printf("sbicicmd: last command ignored\n"); 1555 } 1556 else if( i == 1 ) /* Bsy */ 1557 SBIC_WAIT (regs, SBIC_ASR_INT, wait); 1558 1559 /* 1560 * do it again 1561 */ 1562 } while ( i > 0 && dev->sc_stat[0] == 0xff); 1563 1564 /* Sometimes we need to do an extra read of the CSR */ 1565 GET_SBIC_csr(regs, csr); 1566 CSR_TRACE('I',csr,asr,0xff); 1567 1568 #if CSR_LOG_BUF_SIZE 1569 if(reselect_debug>1) 1570 for(i=0; i<bufptr; i++) 1571 printf("CSR:%02x", csrbuf[i]); 1572 #endif 1573 1574 #ifdef DEBUG 1575 if(data_pointer_debug > 1) 1576 printf("sbicicmd done(%d,%d):%d =%d=\n", 1577 dev->target, lun, 1578 acb->sc_kv.dc_count, 1579 dev->sc_stat[0]); 1580 #endif 1581 1582 QPRINTF(("=STS:%02x=", dev->sc_stat[0])); 1583 dev->sc_flags &= ~SBICF_ICMD; 1584 1585 SBIC_TRACE(dev); 1586 return(dev->sc_stat[0]); 1587 } 1588 1589 /* 1590 * Finish SCSI xfer command: After the completion interrupt from 1591 * a read/write operation, sequence through the final phases in 1592 * programmed i/o. This routine is a lot like sbicicmd except we 1593 * skip (and don't allow) the select, cmd out and data in/out phases. 1594 */ 1595 void 1596 sbicxfdone(dev, regs, target) 1597 struct sbic_softc *dev; 1598 sbic_regmap_p regs; 1599 int target; 1600 { 1601 u_char phase, asr, csr; 1602 int s; 1603 1604 SBIC_TRACE(dev); 1605 QPRINTF(("{")); 1606 s = splbio(); 1607 1608 /* 1609 * have the sbic complete on its own 1610 */ 1611 SBIC_TC_PUT(regs, 0); 1612 SET_SBIC_cmd_phase(regs, 0x46); 1613 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1614 1615 do { 1616 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0); 1617 GET_SBIC_csr (regs, csr); 1618 CSR_TRACE('f',csr,asr,target); 1619 QPRINTF(("%02x:", csr)); 1620 } while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) 1621 && (csr != SBIC_CSR_S_XFERRED)); 1622 1623 dev->sc_flags &= ~SBICF_SELECTED; 1624 1625 GET_SBIC_cmd_phase (regs, phase); 1626 QPRINTF(("}%02x", phase)); 1627 if (phase == 0x60) 1628 GET_SBIC_tlun(regs, dev->sc_stat[0]); 1629 else 1630 sbicerror(dev, regs, csr); 1631 1632 QPRINTF(("=STS:%02x=\n", dev->sc_stat[0])); 1633 splx(s); 1634 SBIC_TRACE(dev); 1635 } 1636 1637 /* 1638 * No DMA chains 1639 */ 1640 1641 int 1642 sbicgo(dev, xs) 1643 struct sbic_softc *dev; 1644 struct scsi_xfer *xs; 1645 { 1646 int i, dmaflags, count, usedma; 1647 u_char csr, asr, *addr; 1648 sbic_regmap_p regs; 1649 struct sbic_acb *acb; 1650 1651 SBIC_TRACE(dev); 1652 dev->target = xs->sc_link->target; 1653 dev->lun = xs->sc_link->lun; 1654 acb = dev->sc_nexus; 1655 regs = dev->sc_sbicp; 1656 1657 usedma = sbicdmaok(dev, xs); 1658 #ifdef DEBUG 1659 routine = 1; 1660 debug_sbic_regs = regs; /* store this to allow debug calls */ 1661 if( data_pointer_debug > 1 ) 1662 printf("sbicgo(%d,%d)\n", dev->target, dev->lun); 1663 #endif 1664 1665 /* 1666 * set the sbic into DMA mode 1667 */ 1668 if( usedma ) 1669 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI | 1670 SBIC_MACHINE_DMA_MODE); 1671 else 1672 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1673 1674 1675 /* 1676 * select the SCSI bus (it's an error if bus isn't free) 1677 */ 1678 if (sbicselectbus(dev, regs, dev->target, dev->lun, 1679 dev->sc_scsiaddr)) { 1680 /* printf("sbicgo: Trying to select busy bus!\n"); */ 1681 SBIC_TRACE(dev); 1682 return(0); /* Not done: needs to be rescheduled */ 1683 } 1684 dev->sc_stat[0] = 0xff; 1685 1686 /* 1687 * Calculate DMA chains now 1688 */ 1689 1690 dmaflags = 0; 1691 if (acb->flags & ACB_DATAIN) 1692 dmaflags |= DMAGO_READ; 1693 1694 1695 /* 1696 * Deal w/bounce buffers. 1697 */ 1698 1699 addr = acb->sc_kv.dc_addr; 1700 count = acb->sc_kv.dc_count; 1701 if (count && (char *)kvtop(addr) != acb->sc_pa.dc_addr) { /* XXXX check */ 1702 printf("sbic: DMA buffer mapping changed %p->%x\n", 1703 acb->sc_pa.dc_addr, kvtop(addr)); 1704 #ifdef DDB 1705 Debugger(); 1706 #endif 1707 } 1708 1709 #ifdef DEBUG 1710 ++sbicdma_ops; /* count total DMA operations */ 1711 #endif 1712 if (count && usedma && dev->sc_flags & SBICF_BADDMA && 1713 sbiccheckdmap(addr, count, dev->sc_dmamask)) { 1714 /* 1715 * need to bounce the dma. 1716 */ 1717 if (dmaflags & DMAGO_READ) { 1718 acb->flags |= ACB_BBUF; 1719 acb->sc_dmausrbuf = addr; 1720 acb->sc_dmausrlen = count; 1721 acb->sc_usrbufpa = (u_char *)kvtop(addr); 1722 if(!dev->sc_tinfo[dev->target].bounce) { 1723 printf("sbicgo: HELP! no bounce allocated for %d\n", 1724 dev->target); 1725 printf("xfer: (%p->%p,%lx)\n", acb->sc_dmausrbuf, 1726 acb->sc_usrbufpa, acb->sc_dmausrlen); 1727 dev->sc_tinfo[xs->sc_link->target].bounce 1728 = (char *)alloc_z2mem(MAXPHYS); 1729 if (isztwomem(dev->sc_tinfo[xs->sc_link->target].bounce)) 1730 printf("alloc ZII target %d bounce pa 0x%x\n", 1731 xs->sc_link->target, 1732 kvtop(dev->sc_tinfo[xs->sc_link->target].bounce)); 1733 else if (dev->sc_tinfo[xs->sc_link->target].bounce) 1734 printf("alloc CHIP target %d bounce pa 0x%p\n", 1735 xs->sc_link->target, 1736 PREP_DMA_MEM(dev->sc_tinfo[xs->sc_link->target].bounce)); 1737 1738 printf("Allocating %d bounce at %x\n", 1739 dev->target, 1740 kvtop(dev->sc_tinfo[dev->target].bounce)); 1741 } 1742 } else { /* write: copy to dma buffer */ 1743 #ifdef DEBUG 1744 if(data_pointer_debug) 1745 printf("sbicgo: copying %x bytes to target %d bounce %x\n", 1746 count, dev->target, 1747 kvtop(dev->sc_tinfo[dev->target].bounce)); 1748 #endif 1749 bcopy (addr, dev->sc_tinfo[dev->target].bounce, count); 1750 } 1751 addr = dev->sc_tinfo[dev->target].bounce;/* and use dma buffer */ 1752 acb->sc_kv.dc_addr = addr; 1753 #ifdef DEBUG 1754 ++sbicdma_bounces; /* count number of bounced */ 1755 #endif 1756 } 1757 1758 /* 1759 * Allocate the DMA chain 1760 */ 1761 1762 /* Set start KVM addresses */ 1763 #if 0 1764 acb->sc_kv.dc_addr = addr; 1765 acb->sc_kv.dc_count = count; 1766 #endif 1767 1768 /* Mark end of segment */ 1769 acb->sc_tcnt = dev->sc_tcnt = 0; 1770 acb->sc_pa.dc_count = 0; 1771 1772 sbic_load_ptrs(dev, regs, dev->target, dev->lun); 1773 SBIC_TRACE(dev); 1774 /* Enable interrupts but don't do any DMA */ 1775 dev->sc_enintr(dev); 1776 if (usedma) { 1777 dev->sc_tcnt = dev->sc_dmago(dev, acb->sc_pa.dc_addr, 1778 acb->sc_pa.dc_count, 1779 dmaflags); 1780 #ifdef DEBUG 1781 dev->sc_dmatimo = dev->sc_tcnt ? 1 : 0; 1782 #endif 1783 } else 1784 dev->sc_dmacmd = 0; /* Don't use DMA */ 1785 dev->sc_flags |= SBICF_INDMA; 1786 /* SBIC_TC_PUT(regs, dev->sc_tcnt); */ /* XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX */ 1787 SBIC_TRACE(dev); 1788 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 1789 1790 /* 1791 * push the data cache ( I think this won't work (EH)) 1792 */ 1793 #if defined(M68040) || defined(M68060) 1794 if (mmutype == MMU_68040 && usedma && count) { 1795 dma_cachectl(addr, count); 1796 if (((u_int)addr & 0xF) || (((u_int)addr + count) & 0xF)) 1797 dev->sc_flags |= SBICF_DCFLUSH; 1798 } 1799 #endif 1800 1801 /* 1802 * enintr() also enables interrupts for the sbic 1803 */ 1804 #ifdef DEBUG 1805 if( data_pointer_debug > 1 ) 1806 printf("sbicgo dmago:%d(%p:%lx)\n", 1807 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 1808 #if 0 1809 /* 1810 * Hmm - this isn't right: asr and csr haven't been set yet. 1811 */ 1812 debug_asr = asr; 1813 debug_csr = csr; 1814 #endif 1815 #endif 1816 1817 /* 1818 * Lets cycle a while then let the interrupt handler take over 1819 */ 1820 1821 asr = GET_SBIC_asr(regs, asr); 1822 do { 1823 GET_SBIC_csr(regs, csr); 1824 CSR_TRACE('g',csr,asr,dev->target); 1825 #ifdef DEBUG 1826 debug_csr = csr; 1827 routine = 1; 1828 #endif 1829 QPRINTF(("go[0x%x]", csr)); 1830 1831 i = sbicnextstate(dev, csr, asr); 1832 1833 WAIT_CIP(regs); 1834 GET_SBIC_asr(regs, asr); 1835 #ifdef DEBUG 1836 debug_asr = asr; 1837 #endif 1838 if(asr & SBIC_ASR_LCI) printf("sbicgo: LCI asr:%02x csr:%02x\n", 1839 asr,csr); 1840 } while( i == SBIC_STATE_RUNNING 1841 && asr & (SBIC_ASR_INT|SBIC_ASR_LCI) ); 1842 1843 CSR_TRACE('g',csr,asr,i<<4); 1844 SBIC_TRACE(dev); 1845 if (i == SBIC_STATE_DONE && dev->sc_stat[0] == 0xff) printf("sbicgo: done & stat = 0xff\n"); 1846 if (i == SBIC_STATE_DONE && dev->sc_stat[0] != 0xff) { 1847 /* if( i == SBIC_STATE_DONE && dev->sc_stat[0] ) { */ 1848 /* Did we really finish that fast? */ 1849 return 1; 1850 } 1851 return 0; 1852 } 1853 1854 1855 int 1856 sbicintr(dev) 1857 struct sbic_softc *dev; 1858 { 1859 sbic_regmap_p regs; 1860 u_char asr, csr; 1861 int i; 1862 1863 regs = dev->sc_sbicp; 1864 1865 /* 1866 * pending interrupt? 1867 */ 1868 GET_SBIC_asr (regs, asr); 1869 if ((asr & SBIC_ASR_INT) == 0) 1870 return(0); 1871 1872 SBIC_TRACE(dev); 1873 do { 1874 GET_SBIC_csr(regs, csr); 1875 CSR_TRACE('i',csr,asr,dev->target); 1876 #ifdef DEBUG 1877 debug_csr = csr; 1878 routine = 2; 1879 #endif 1880 QPRINTF(("intr[0x%x]", csr)); 1881 1882 i = sbicnextstate(dev, csr, asr); 1883 1884 WAIT_CIP(regs); 1885 GET_SBIC_asr(regs, asr); 1886 #ifdef DEBUG 1887 debug_asr = asr; 1888 #endif 1889 #if 0 1890 if(asr & SBIC_ASR_LCI) printf("sbicintr: LCI asr:%02x csr:%02x\n", 1891 asr,csr); 1892 #endif 1893 } while(i == SBIC_STATE_RUNNING && 1894 asr & (SBIC_ASR_INT|SBIC_ASR_LCI)); 1895 CSR_TRACE('i',csr,asr,i<<4); 1896 SBIC_TRACE(dev); 1897 return(1); 1898 } 1899 1900 /* 1901 * Run commands and wait for disconnect 1902 */ 1903 int 1904 sbicpoll(dev) 1905 struct sbic_softc *dev; 1906 { 1907 sbic_regmap_p regs; 1908 u_char asr, csr; 1909 int i; 1910 1911 SBIC_TRACE(dev); 1912 regs = dev->sc_sbicp; 1913 1914 do { 1915 GET_SBIC_asr (regs, asr); 1916 #ifdef DEBUG 1917 debug_asr = asr; 1918 #endif 1919 GET_SBIC_csr(regs, csr); 1920 CSR_TRACE('p',csr,asr,dev->target); 1921 #ifdef DEBUG 1922 debug_csr = csr; 1923 routine = 2; 1924 #endif 1925 QPRINTF(("poll[0x%x]", csr)); 1926 1927 i = sbicnextstate(dev, csr, asr); 1928 1929 WAIT_CIP(regs); 1930 GET_SBIC_asr(regs, asr); 1931 /* tapes may take a loooong time.. */ 1932 while (asr & SBIC_ASR_BSY){ 1933 if(asr & SBIC_ASR_DBR) { 1934 printf("sbipoll: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", 1935 csr,asr); 1936 #ifdef DDB 1937 Debugger(); 1938 #endif 1939 /* SBIC is jammed */ 1940 /* DUNNO which direction */ 1941 /* Try old direction */ 1942 GET_SBIC_data(regs,i); 1943 GET_SBIC_asr(regs, asr); 1944 if( asr & SBIC_ASR_DBR) /* Wants us to write */ 1945 SET_SBIC_data(regs,i); 1946 } 1947 GET_SBIC_asr(regs, asr); 1948 } 1949 1950 if(asr & SBIC_ASR_LCI) printf("sbicpoll: LCI asr:%02x csr:%02x\n", 1951 asr,csr); 1952 else if( i == 1 ) /* BSY */ 1953 SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait); 1954 } while(i == SBIC_STATE_RUNNING); 1955 CSR_TRACE('p',csr,asr,i<<4); 1956 SBIC_TRACE(dev); 1957 return(1); 1958 } 1959 1960 /* 1961 * Handle a single msgin 1962 */ 1963 1964 int 1965 sbicmsgin(dev) 1966 struct sbic_softc *dev; 1967 { 1968 sbic_regmap_p regs; 1969 int recvlen; 1970 u_char asr, csr, *tmpaddr; 1971 1972 regs = dev->sc_sbicp; 1973 1974 dev->sc_msg[0] = 0xff; 1975 dev->sc_msg[1] = 0xff; 1976 1977 GET_SBIC_asr(regs, asr); 1978 #ifdef DEBUG 1979 if(reselect_debug>1) 1980 printf("sbicmsgin asr=%02x\n", asr); 1981 #endif 1982 1983 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 1984 1985 GET_SBIC_selid (regs, csr); 1986 SET_SBIC_selid (regs, csr | SBIC_SID_FROM_SCSI); 1987 1988 SBIC_TC_PUT(regs, 0); 1989 tmpaddr = dev->sc_msg; 1990 recvlen = 1; 1991 do { 1992 while( recvlen-- ) { 1993 asr = GET_SBIC_asr(regs, asr); 1994 GET_SBIC_csr(regs, csr); 1995 QPRINTF(("sbicmsgin ready to go (csr,asr)=(%02x,%02x)\n", 1996 csr, asr)); 1997 1998 RECV_BYTE(regs, *tmpaddr); 1999 CSR_TRACE('m',csr,asr,*tmpaddr); 2000 #if 1 2001 /* 2002 * get the command completion interrupt, or we 2003 * can't send a new command (LCI) 2004 */ 2005 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2006 GET_SBIC_csr(regs, csr); 2007 CSR_TRACE('X',csr,asr,dev->target); 2008 #else 2009 WAIT_CIP(regs); 2010 do { 2011 GET_SBIC_asr(regs, asr); 2012 csr = 0xff; 2013 GET_SBIC_csr(regs, csr); 2014 CSR_TRACE('X',csr,asr,dev->target); 2015 if( csr == 0xff ) 2016 printf("sbicmsgin waiting: csr %02x asr %02x\n", csr, asr); 2017 } while( csr == 0xff ); 2018 #endif 2019 #ifdef DEBUG 2020 if(reselect_debug>1) 2021 printf("sbicmsgin: got %02x csr %02x asr %02x\n", 2022 *tmpaddr, csr, asr); 2023 #endif 2024 #if do_parity_check 2025 if( asr & SBIC_ASR_PE ) { 2026 printf ("Parity error"); 2027 /* This code simply does not work. */ 2028 WAIT_CIP(regs); 2029 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2030 WAIT_CIP(regs); 2031 GET_SBIC_asr(regs, asr); 2032 WAIT_CIP(regs); 2033 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2034 WAIT_CIP(regs); 2035 if( !(asr & SBIC_ASR_LCI) ) 2036 /* Target wants to send garbled msg*/ 2037 continue; 2038 printf("--fixing\n"); 2039 /* loop until a msgout phase occurs on target */ 2040 while(csr & 0x07 != MESG_OUT_PHASE) { 2041 while( asr & SBIC_ASR_BSY && 2042 !(asr & SBIC_ASR_DBR|SBIC_ASR_INT) ) 2043 GET_SBIC_asr(regs, asr); 2044 if( asr & SBIC_ASR_DBR ) 2045 panic("msgin: jammed again!\n"); 2046 GET_SBIC_csr(regs, csr); 2047 CSR_TRACE('e',csr,asr,dev->target); 2048 if( csr & 0x07 != MESG_OUT_PHASE ) { 2049 sbicnextstate(dev, csr, asr); 2050 sbic_save_ptrs(dev, regs, 2051 dev->target, 2052 dev->lun); 2053 } 2054 } 2055 /* Should be msg out by now */ 2056 SEND_BYTE(regs, MSG_PARITY_ERROR); 2057 } 2058 else 2059 #endif 2060 tmpaddr++; 2061 2062 if(recvlen) { 2063 /* Clear ACK */ 2064 WAIT_CIP(regs); 2065 GET_SBIC_asr(regs, asr); 2066 GET_SBIC_csr(regs, csr); 2067 CSR_TRACE('X',csr,asr,dev->target); 2068 QPRINTF(("sbicmsgin pre byte CLR_ACK (csr,asr)=(%02x,%02x)\n", 2069 csr, asr)); 2070 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2071 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2072 } 2073 2074 }; 2075 2076 if(dev->sc_msg[0] == 0xff) { 2077 printf("sbicmsgin: sbic swallowed our message\n"); 2078 break; 2079 } 2080 #ifdef DEBUG 2081 if (sync_debug) 2082 printf("msgin done csr 0x%x asr 0x%x msg 0x%x\n", 2083 csr, asr, dev->sc_msg[0]); 2084 #endif 2085 /* 2086 * test whether this is a reply to our sync 2087 * request 2088 */ 2089 if (MSG_ISIDENTIFY(dev->sc_msg[0])) { 2090 QPRINTF(("IFFY")); 2091 #if 0 2092 /* There is an implied load-ptrs here */ 2093 sbic_load_ptrs(dev, regs, dev->target, dev->lun); 2094 #endif 2095 /* Got IFFY msg -- ack it */ 2096 } else if (dev->sc_msg[0] == MSG_REJECT 2097 && dev->sc_sync[dev->target].state == SYNC_SENT) { 2098 QPRINTF(("REJECT of SYN")); 2099 #ifdef DEBUG 2100 if (sync_debug) 2101 printf("target %d rejected sync, going async\n", 2102 dev->target); 2103 #endif 2104 dev->sc_sync[dev->target].period = sbic_min_period; 2105 dev->sc_sync[dev->target].offset = 0; 2106 dev->sc_sync[dev->target].state = SYNC_DONE; 2107 SET_SBIC_syn(regs, 2108 SBIC_SYN(dev->sc_sync[dev->target].offset, 2109 dev->sc_sync[dev->target].period)); 2110 } else if ((dev->sc_msg[0] == MSG_REJECT)) { 2111 QPRINTF(("REJECT")); 2112 /* 2113 * we'll never REJECt a REJECT message.. 2114 */ 2115 } else if ((dev->sc_msg[0] == MSG_SAVE_DATA_PTR)) { 2116 QPRINTF(("MSG_SAVE_DATA_PTR")); 2117 /* 2118 * don't reject this either. 2119 */ 2120 } else if ((dev->sc_msg[0] == MSG_DISCONNECT)) { 2121 QPRINTF(("DISCONNECT")); 2122 #ifdef DEBUG 2123 if( reselect_debug>1 && dev->sc_msg[0] == MSG_DISCONNECT ) 2124 printf("sbicmsgin: got disconnect msg %s\n", 2125 (dev->sc_flags & SBICF_ICMD)?"rejecting":""); 2126 #endif 2127 if( dev->sc_flags & SBICF_ICMD ) { 2128 /* We're in immediate mode. Prevent disconnects. */ 2129 /* prepare to reject the message, NACK */ 2130 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2131 WAIT_CIP(regs); 2132 } 2133 } else if (dev->sc_msg[0] == MSG_CMD_COMPLETE ) { 2134 QPRINTF(("CMD_COMPLETE")); 2135 /* !! KLUDGE ALERT !! quite a few drives don't seem to 2136 * really like the current way of sending the 2137 * sync-handshake together with the ident-message, and 2138 * they react by sending command-complete and 2139 * disconnecting right after returning the valid sync 2140 * handshake. So, all I can do is reselect the drive, 2141 * and hope it won't disconnect again. I don't think 2142 * this is valid behavior, but I can't help fixing a 2143 * problem that apparently exists. 2144 * 2145 * Note: we should not get here on `normal' command 2146 * completion, as that condition is handled by the 2147 * high-level sel&xfer resume command used to walk 2148 * thru status/cc-phase. 2149 */ 2150 2151 #ifdef DEBUG 2152 if (sync_debug) 2153 printf ("GOT MSG %d! target %d acting weird.." 2154 " waiting for disconnect...\n", 2155 dev->sc_msg[0], dev->target); 2156 #endif 2157 /* Check to see if sbic is handling this */ 2158 GET_SBIC_asr(regs, asr); 2159 if(asr & SBIC_ASR_BSY) 2160 return SBIC_STATE_RUNNING; 2161 2162 /* Let's try this: Assume it works and set status to 00 */ 2163 dev->sc_stat[0] = 0; 2164 } else if (dev->sc_msg[0] == MSG_EXT_MESSAGE 2165 && tmpaddr == &dev->sc_msg[1]) { 2166 QPRINTF(("ExtMSG\n")); 2167 /* Read in whole extended message */ 2168 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2169 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2170 GET_SBIC_asr(regs, asr); 2171 GET_SBIC_csr(regs, csr); 2172 QPRINTF(("CLR ACK asr %02x, csr %02x\n", asr, csr)); 2173 RECV_BYTE(regs, *tmpaddr); 2174 CSR_TRACE('x',csr,asr,*tmpaddr); 2175 /* Wait for command completion IRQ */ 2176 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2177 recvlen = *tmpaddr++; 2178 QPRINTF(("Recving ext msg, asr %02x csr %02x len %02x\n", 2179 asr, csr, recvlen)); 2180 } else if (dev->sc_msg[0] == MSG_EXT_MESSAGE && dev->sc_msg[1] == 3 2181 && dev->sc_msg[2] == MSG_SYNC_REQ) { 2182 QPRINTF(("SYN")); 2183 dev->sc_sync[dev->target].period = 2184 sbicfromscsiperiod(dev, 2185 regs, dev->sc_msg[3]); 2186 dev->sc_sync[dev->target].offset = dev->sc_msg[4]; 2187 dev->sc_sync[dev->target].state = SYNC_DONE; 2188 SET_SBIC_syn(regs, 2189 SBIC_SYN(dev->sc_sync[dev->target].offset, 2190 dev->sc_sync[dev->target].period)); 2191 printf("%s: target %d now synchronous," 2192 " period=%dns, offset=%d.\n", 2193 dev->sc_dev.dv_xname, dev->target, 2194 dev->sc_msg[3] * 4, dev->sc_msg[4]); 2195 } else { 2196 #ifdef DEBUG 2197 if (sbic_debug || sync_debug) 2198 printf ("sbicmsgin: Rejecting message 0x%02x\n", 2199 dev->sc_msg[0]); 2200 #endif 2201 /* prepare to reject the message, NACK */ 2202 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2203 WAIT_CIP(regs); 2204 } 2205 /* Clear ACK */ 2206 WAIT_CIP(regs); 2207 GET_SBIC_asr(regs, asr); 2208 GET_SBIC_csr(regs, csr); 2209 CSR_TRACE('X',csr,asr,dev->target); 2210 QPRINTF(("sbicmsgin pre CLR_ACK (csr,asr)=(%02x,%02x)%d\n", 2211 csr, asr, recvlen)); 2212 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2213 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2214 } 2215 #if 0 2216 while((csr == SBIC_CSR_MSGIN_W_ACK) 2217 || (SBIC_PHASE(csr) == MESG_IN_PHASE)); 2218 #else 2219 while (recvlen>0); 2220 #endif 2221 2222 QPRINTF(("sbicmsgin finished: csr %02x, asr %02x\n",csr, asr)); 2223 2224 /* Should still have one CSR to read */ 2225 return SBIC_STATE_RUNNING; 2226 } 2227 2228 2229 /* 2230 * sbicnextstate() 2231 * return: 2232 * 0 == done 2233 * 1 == working 2234 * 2 == disconnected 2235 * -1 == error 2236 */ 2237 int 2238 sbicnextstate(dev, csr, asr) 2239 struct sbic_softc *dev; 2240 u_char csr, asr; 2241 { 2242 sbic_regmap_p regs; 2243 struct sbic_acb *acb; 2244 int i, newtarget, newlun, wait; 2245 #if 0 2246 unsigned tcnt; 2247 #endif 2248 2249 i = 0; 2250 SBIC_TRACE(dev); 2251 regs = dev->sc_sbicp; 2252 acb = dev->sc_nexus; 2253 2254 QPRINTF(("next[%02x,%02x]",asr,csr)); 2255 2256 switch (csr) { 2257 case SBIC_CSR_XFERRED|CMD_PHASE: 2258 case SBIC_CSR_MIS|CMD_PHASE: 2259 case SBIC_CSR_MIS_1|CMD_PHASE: 2260 case SBIC_CSR_MIS_2|CMD_PHASE: 2261 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 2262 if (sbicxfstart(regs, acb->clen, CMD_PHASE, sbic_cmd_wait)) 2263 if (sbicxfout(regs, acb->clen, 2264 &acb->cmd, CMD_PHASE)) 2265 goto abort; 2266 break; 2267 2268 case SBIC_CSR_XFERRED|STATUS_PHASE: 2269 case SBIC_CSR_MIS|STATUS_PHASE: 2270 case SBIC_CSR_MIS_1|STATUS_PHASE: 2271 case SBIC_CSR_MIS_2|STATUS_PHASE: 2272 /* 2273 * this should be the normal i/o completion case. 2274 * get the status & cmd complete msg then let the 2275 * device driver look at what happened. 2276 */ 2277 sbicxfdone(dev,regs,dev->target); 2278 /* 2279 * check for overlapping cache line, flush if so 2280 */ 2281 #if defined(M68040) || defined(M68060) 2282 if (dev->sc_flags & SBICF_DCFLUSH) { 2283 #if 0 2284 printf("sbic: 68040/68060 DMA cache flush needs" 2285 "fixing? %x:%x\n", 2286 dev->sc_xs->data, dev->sc_xs->datalen); 2287 #endif 2288 } 2289 #endif 2290 #ifdef DEBUG 2291 if( data_pointer_debug > 1 ) 2292 printf("next dmastop: %d(%p:%lx)\n", 2293 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 2294 dev->sc_dmatimo = 0; 2295 #endif 2296 dev->sc_dmastop(dev); /* was dmafree */ 2297 if (acb->flags & ACB_BBUF) { 2298 if ((u_char *)kvtop(acb->sc_dmausrbuf) != acb->sc_usrbufpa) 2299 printf("%s: WARNING - buffer mapping changed %p->%x\n", 2300 dev->sc_dev.dv_xname, acb->sc_usrbufpa, 2301 kvtop(acb->sc_dmausrbuf)); 2302 #ifdef DEBUG 2303 if(data_pointer_debug) 2304 printf("sbicgo:copying %lx bytes from target %d bounce %x\n", 2305 acb->sc_dmausrlen, 2306 dev->target, 2307 kvtop(dev->sc_tinfo[dev->target].bounce)); 2308 #endif 2309 bcopy(dev->sc_tinfo[dev->target].bounce, 2310 acb->sc_dmausrbuf, 2311 acb->sc_dmausrlen); 2312 } 2313 dev->sc_flags &= ~(SBICF_INDMA | SBICF_DCFLUSH); 2314 sbic_scsidone(acb, dev->sc_stat[0]); 2315 SBIC_TRACE(dev); 2316 return SBIC_STATE_DONE; 2317 2318 case SBIC_CSR_XFERRED|DATA_OUT_PHASE: 2319 case SBIC_CSR_XFERRED|DATA_IN_PHASE: 2320 case SBIC_CSR_MIS|DATA_OUT_PHASE: 2321 case SBIC_CSR_MIS|DATA_IN_PHASE: 2322 case SBIC_CSR_MIS_1|DATA_OUT_PHASE: 2323 case SBIC_CSR_MIS_1|DATA_IN_PHASE: 2324 case SBIC_CSR_MIS_2|DATA_OUT_PHASE: 2325 case SBIC_CSR_MIS_2|DATA_IN_PHASE: 2326 if( dev->sc_xs->flags & SCSI_POLL || dev->sc_flags & SBICF_ICMD 2327 || acb->sc_dmacmd == 0 ) { 2328 /* Do PIO */ 2329 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2330 if (acb->sc_kv.dc_count <= 0) { 2331 printf("sbicnextstate:xfer count %d asr%x csr%x\n", 2332 acb->sc_kv.dc_count, asr, csr); 2333 goto abort; 2334 } 2335 wait = sbic_data_wait; 2336 if( sbicxfstart(regs, 2337 acb->sc_kv.dc_count, 2338 SBIC_PHASE(csr), wait)) 2339 if( SBIC_PHASE(csr) == DATA_IN_PHASE ) 2340 /* data in? */ 2341 i=sbicxfin(regs, 2342 acb->sc_kv.dc_count, 2343 acb->sc_kv.dc_addr); 2344 else 2345 i=sbicxfout(regs, 2346 acb->sc_kv.dc_count, 2347 acb->sc_kv.dc_addr, 2348 SBIC_PHASE(csr)); 2349 acb->sc_kv.dc_addr += 2350 (acb->sc_kv.dc_count - i); 2351 acb->sc_kv.dc_count = i; 2352 } else { 2353 if (acb->sc_kv.dc_count <= 0) { 2354 printf("sbicnextstate:xfer count %d asr%x csr%x\n", 2355 acb->sc_kv.dc_count, asr, csr); 2356 goto abort; 2357 } 2358 /* 2359 * do scatter-gather dma 2360 * hacking the controller chip, ouch.. 2361 */ 2362 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI | 2363 SBIC_MACHINE_DMA_MODE); 2364 /* 2365 * set next dma addr and dec count 2366 */ 2367 #if 0 2368 SBIC_TC_GET(regs, tcnt); 2369 dev->sc_cur->dc_count -= ((dev->sc_tcnt - tcnt) >> 1); 2370 dev->sc_cur->dc_addr += (dev->sc_tcnt - tcnt); 2371 dev->sc_tcnt = acb->sc_tcnt = tcnt; 2372 #else 2373 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 2374 sbic_load_ptrs(dev, regs, dev->target, dev->lun); 2375 #endif 2376 #ifdef DEBUG 2377 if( data_pointer_debug > 1 ) 2378 printf("next dmanext: %d(%p:%lx)\n", 2379 dev->target,dev->sc_cur->dc_addr, 2380 dev->sc_tcnt); 2381 dev->sc_dmatimo = 1; 2382 #endif 2383 dev->sc_tcnt = dev->sc_dmanext(dev); 2384 SBIC_TC_PUT(regs, (unsigned)dev->sc_tcnt); 2385 SET_SBIC_cmd(regs, SBIC_CMD_XFER_INFO); 2386 dev->sc_flags |= SBICF_INDMA; 2387 } 2388 break; 2389 2390 case SBIC_CSR_XFERRED|MESG_IN_PHASE: 2391 case SBIC_CSR_MIS|MESG_IN_PHASE: 2392 case SBIC_CSR_MIS_1|MESG_IN_PHASE: 2393 case SBIC_CSR_MIS_2|MESG_IN_PHASE: 2394 SBIC_TRACE(dev); 2395 return sbicmsgin(dev); 2396 2397 case SBIC_CSR_MSGIN_W_ACK: 2398 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); /* Dunno what I'm ACKing */ 2399 printf("Acking unknown msgin CSR:%02x",csr); 2400 break; 2401 2402 case SBIC_CSR_XFERRED|MESG_OUT_PHASE: 2403 case SBIC_CSR_MIS|MESG_OUT_PHASE: 2404 case SBIC_CSR_MIS_1|MESG_OUT_PHASE: 2405 case SBIC_CSR_MIS_2|MESG_OUT_PHASE: 2406 #ifdef DEBUG 2407 if (sync_debug) 2408 printf ("sending REJECT msg to last msg.\n"); 2409 #endif 2410 2411 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 2412 /* 2413 * should only get here on reject, 2414 * since it's always US that 2415 * initiate a sync transfer 2416 */ 2417 SEND_BYTE(regs, MSG_REJECT); 2418 WAIT_CIP(regs); 2419 if( asr & (SBIC_ASR_BSY|SBIC_ASR_LCI|SBIC_ASR_CIP) ) 2420 printf("next: REJECT sent asr %02x\n", asr); 2421 SBIC_TRACE(dev); 2422 return SBIC_STATE_RUNNING; 2423 2424 case SBIC_CSR_DISC: 2425 case SBIC_CSR_DISC_1: 2426 dev->sc_flags &= ~(SBICF_INDMA|SBICF_SELECTED); 2427 2428 /* Try to schedule another target */ 2429 #ifdef DEBUG 2430 if(reselect_debug>1) 2431 printf("sbicnext target %d disconnected\n", dev->target); 2432 #endif 2433 TAILQ_INSERT_HEAD(&dev->nexus_list, acb, chain); 2434 ++dev->sc_tinfo[dev->target].dconns; 2435 dev->sc_nexus = NULL; 2436 dev->sc_xs = NULL; 2437 2438 if( acb->xs->flags & SCSI_POLL 2439 || (dev->sc_flags & SBICF_ICMD) 2440 || !sbic_parallel_operations ) { 2441 SBIC_TRACE(dev); 2442 return SBIC_STATE_DISCONNECT; 2443 } 2444 sbic_sched(dev); 2445 SBIC_TRACE(dev); 2446 return SBIC_STATE_DISCONNECT; 2447 2448 case SBIC_CSR_RSLT_NI: 2449 case SBIC_CSR_RSLT_IFY: 2450 GET_SBIC_rselid(regs, newtarget); 2451 /* check SBIC_RID_SIV? */ 2452 newtarget &= SBIC_RID_MASK; 2453 if (csr == SBIC_CSR_RSLT_IFY) { 2454 /* Read IFY msg to avoid lockup */ 2455 GET_SBIC_data(regs, newlun); 2456 WAIT_CIP(regs); 2457 newlun &= SBIC_TLUN_MASK; 2458 CSR_TRACE('r',csr,asr,newtarget); 2459 } else { 2460 /* Need to get IFY message */ 2461 for (newlun = 256; newlun; --newlun) { 2462 GET_SBIC_asr(regs, asr); 2463 if (asr & SBIC_ASR_INT) 2464 break; 2465 delay(1); 2466 } 2467 newlun = 0; /* XXXX */ 2468 if ((asr & SBIC_ASR_INT) == 0) { 2469 #ifdef DEBUG 2470 if (reselect_debug) 2471 printf("RSLT_NI - no IFFY message? asr %x\n", asr); 2472 #endif 2473 } else { 2474 GET_SBIC_csr(regs,csr); 2475 CSR_TRACE('n',csr,asr,newtarget); 2476 if (csr == (SBIC_CSR_MIS | MESG_IN_PHASE) || 2477 csr == (SBIC_CSR_MIS_1 | MESG_IN_PHASE) || 2478 csr == (SBIC_CSR_MIS_2 | MESG_IN_PHASE)) { 2479 sbicmsgin(dev); 2480 newlun = dev->sc_msg[0] & 7; 2481 } else { 2482 printf("RSLT_NI - not MESG_IN_PHASE %x\n", 2483 csr); 2484 } 2485 } 2486 } 2487 #ifdef DEBUG 2488 if(reselect_debug>1 || (reselect_debug && csr==SBIC_CSR_RSLT_NI)) 2489 printf("sbicnext: reselect %s from targ %d lun %d\n", 2490 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", 2491 newtarget, newlun); 2492 #endif 2493 if (dev->sc_nexus) { 2494 #ifdef DEBUG 2495 if (reselect_debug > 1) 2496 printf("%s: reselect %s with active command\n", 2497 dev->sc_dev.dv_xname, 2498 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY"); 2499 #ifdef DDB 2500 /* Debugger();*/ 2501 #endif 2502 #endif 2503 TAILQ_INSERT_HEAD(&dev->ready_list, dev->sc_nexus, chain); 2504 dev->sc_tinfo[dev->target].lubusy &= ~(1 << dev->lun); 2505 dev->sc_nexus = NULL; 2506 dev->sc_xs = NULL; 2507 } 2508 /* Reload sync values for this target */ 2509 if (dev->sc_sync[newtarget].state == SYNC_DONE) 2510 SET_SBIC_syn(regs, SBIC_SYN (dev->sc_sync[newtarget].offset, 2511 dev->sc_sync[newtarget].period)); 2512 else 2513 SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period)); 2514 for (acb = dev->nexus_list.tqh_first; acb; 2515 acb = acb->chain.tqe_next) { 2516 if (acb->xs->sc_link->target != newtarget || 2517 acb->xs->sc_link->lun != newlun) 2518 continue; 2519 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 2520 dev->sc_nexus = acb; 2521 dev->sc_xs = acb->xs; 2522 dev->sc_flags |= SBICF_SELECTED; 2523 dev->target = newtarget; 2524 dev->lun = newlun; 2525 break; 2526 } 2527 if (acb == NULL) { 2528 printf("%s: reselect %s targ %d not in nexus_list %p\n", 2529 dev->sc_dev.dv_xname, 2530 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", newtarget, 2531 &dev->nexus_list.tqh_first); 2532 panic("bad reselect in sbic"); 2533 } 2534 if (csr == SBIC_CSR_RSLT_IFY) 2535 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2536 break; 2537 2538 default: 2539 abort: 2540 /* 2541 * Something unexpected happened -- deal with it. 2542 */ 2543 printf("sbicnextstate: aborting csr %02x asr %02x\n", csr, asr); 2544 #ifdef DDB 2545 Debugger(); 2546 #endif 2547 #ifdef DEBUG 2548 if( data_pointer_debug > 1 ) 2549 printf("next dmastop: %d(%p:%lx)\n", 2550 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 2551 dev->sc_dmatimo = 0; 2552 #endif 2553 dev->sc_dmastop(dev); 2554 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2555 sbicerror(dev, regs, csr); 2556 sbicabort(dev, regs, "next"); 2557 if (dev->sc_flags & SBICF_INDMA) { 2558 /* 2559 * check for overlapping cache line, flush if so 2560 */ 2561 #if defined(M68040) || defined(M68060) 2562 if (dev->sc_flags & SBICF_DCFLUSH) { 2563 #if 0 2564 printf("sbic: 68040/060 DMA cache flush needs" 2565 "fixing? %x:%x\n", 2566 dev->sc_xs->data, dev->sc_xs->datalen); 2567 #endif 2568 } 2569 #endif 2570 dev->sc_flags &= 2571 ~(SBICF_INDMA | SBICF_DCFLUSH); 2572 #ifdef DEBUG 2573 if( data_pointer_debug > 1 ) 2574 printf("next dmastop: %d(%p:%lx)\n", 2575 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 2576 dev->sc_dmatimo = 0; 2577 #endif 2578 dev->sc_dmastop(dev); 2579 sbic_scsidone(acb, -1); 2580 } 2581 SBIC_TRACE(dev); 2582 return SBIC_STATE_ERROR; 2583 } 2584 2585 SBIC_TRACE(dev); 2586 return(SBIC_STATE_RUNNING); 2587 } 2588 2589 2590 /* 2591 * Check if DMA can not be used with specified buffer 2592 */ 2593 2594 int 2595 sbiccheckdmap(bp, len, mask) 2596 void *bp; 2597 u_long len, mask; 2598 { 2599 u_char *buffer; 2600 u_long phy_buf; 2601 u_long phy_len; 2602 2603 buffer = bp; 2604 2605 if (len == 0) 2606 return(0); 2607 2608 while (len) { 2609 phy_buf = kvtop(buffer); 2610 if (len < (phy_len = NBPG - ((int) buffer & PGOFSET))) 2611 phy_len = len; 2612 if (phy_buf & mask) 2613 return(1); 2614 buffer += phy_len; 2615 len -= phy_len; 2616 } 2617 return(0); 2618 } 2619 2620 int 2621 sbictoscsiperiod(dev, regs, a) 2622 struct sbic_softc *dev; 2623 sbic_regmap_p regs; 2624 int a; 2625 { 2626 unsigned int fs; 2627 2628 /* 2629 * cycle = DIV / (2*CLK) 2630 * DIV = FS+2 2631 * best we can do is 200ns at 20Mhz, 2 cycles 2632 */ 2633 2634 GET_SBIC_myid(regs,fs); 2635 fs = (fs >>6) + 2; /* DIV */ 2636 fs = (fs * 10000) / (dev->sc_clkfreq<<1); /* Cycle, in ns */ 2637 if (a < 2) a = 8; /* map to Cycles */ 2638 return ((fs*a)>>2); /* in 4 ns units */ 2639 } 2640 2641 int 2642 sbicfromscsiperiod(dev, regs, p) 2643 struct sbic_softc *dev; 2644 sbic_regmap_p regs; 2645 int p; 2646 { 2647 register unsigned int fs, ret; 2648 2649 /* Just the inverse of the above */ 2650 2651 GET_SBIC_myid(regs,fs); 2652 fs = (fs >>6) + 2; /* DIV */ 2653 fs = (fs * 10000) / (dev->sc_clkfreq<<1); /* Cycle, in ns */ 2654 2655 ret = p << 2; /* in ns units */ 2656 ret = ret / fs; /* in Cycles */ 2657 if (ret < sbic_min_period) 2658 return(sbic_min_period); 2659 2660 /* verify rounding */ 2661 if (sbictoscsiperiod(dev, regs, ret) < p) 2662 ret++; 2663 return (ret >= 8) ? 0 : ret; 2664 } 2665 2666 #ifdef DEBUG 2667 2668 void 2669 sbicdumpstate() 2670 { 2671 u_char csr, asr; 2672 2673 GET_SBIC_asr(debug_sbic_regs,asr); 2674 GET_SBIC_csr(debug_sbic_regs,csr); 2675 printf("%s: asr:csr(%02x:%02x)->(%02x:%02x)\n", 2676 (routine==1)?"sbicgo": 2677 (routine==2)?"sbicintr": 2678 (routine==3)?"sbicicmd": 2679 (routine==4)?"sbicnext":"unknown", 2680 debug_asr, debug_csr, asr, csr); 2681 2682 } 2683 2684 void 2685 sbictimeout(dev) 2686 struct sbic_softc *dev; 2687 { 2688 int s, asr; 2689 2690 s = splbio(); 2691 if (dev->sc_dmatimo) { 2692 if (dev->sc_dmatimo > 1) { 2693 printf("%s: dma timeout #%d\n", 2694 dev->sc_dev.dv_xname, dev->sc_dmatimo - 1); 2695 GET_SBIC_asr(dev->sc_sbicp, asr); 2696 if( asr & SBIC_ASR_INT ) { 2697 /* We need to service a missed IRQ */ 2698 printf("Servicing a missed int:(%02x,%02x)->(%02x,??)\n", 2699 debug_asr, debug_csr, asr); 2700 sbicintr(dev); 2701 } 2702 sbicdumpstate(); 2703 } 2704 dev->sc_dmatimo++; 2705 } 2706 splx(s); 2707 timeout((void *)sbictimeout, dev, 30 * hz); 2708 } 2709 2710 void 2711 sbic_dump_acb(acb) 2712 struct sbic_acb *acb; 2713 { 2714 u_char *b = (u_char *) &acb->cmd; 2715 int i; 2716 2717 printf("acb@%p ", acb); 2718 if (acb->xs == NULL) { 2719 printf("<unused>\n"); 2720 return; 2721 } 2722 printf("(%d:%d) flags %2x clen %2d cmd ", acb->xs->sc_link->target, 2723 acb->xs->sc_link->lun, acb->flags, acb->clen); 2724 for (i = acb->clen; i; --i) 2725 printf(" %02x", *b++); 2726 printf("\n"); 2727 printf(" xs: %8p data %8p:%04x ", acb->xs, acb->xs->data, 2728 acb->xs->datalen); 2729 printf("va %8p:%04x ", acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 2730 printf("pa %8p:%04x tcnt %lx\n", acb->sc_pa.dc_addr, acb->sc_pa.dc_count, 2731 acb->sc_tcnt); 2732 } 2733 2734 void 2735 sbic_dump(dev) 2736 struct sbic_softc *dev; 2737 { 2738 sbic_regmap_p regs; 2739 u_char csr, asr; 2740 struct sbic_acb *acb; 2741 int s; 2742 int i; 2743 2744 s = splbio(); 2745 regs = dev->sc_sbicp; 2746 #if CSR_TRACE_SIZE 2747 printf("csr trace: "); 2748 i = csr_traceptr; 2749 do { 2750 printf("%c%02x%02x%02x ", csr_trace[i].whr, 2751 csr_trace[i].csr, csr_trace[i].asr, csr_trace[i].xtn); 2752 switch(csr_trace[i].whr) { 2753 case 'g': 2754 printf("go "); break; 2755 case 's': 2756 printf("select "); break; 2757 case 'y': 2758 printf("select+ "); break; 2759 case 'i': 2760 printf("intr "); break; 2761 case 'f': 2762 printf("finish "); break; 2763 case '>': 2764 printf("out "); break; 2765 case '<': 2766 printf("in "); break; 2767 case 'm': 2768 printf("msgin "); break; 2769 case 'x': 2770 printf("msginx "); break; 2771 case 'X': 2772 printf("msginX "); break; 2773 case 'r': 2774 printf("reselect "); break; 2775 case 'I': 2776 printf("icmd "); break; 2777 case 'a': 2778 printf("abort "); break; 2779 default: 2780 printf("? "); 2781 } 2782 switch(csr_trace[i].csr) { 2783 case 0x11: 2784 printf("INITIATOR"); break; 2785 case 0x16: 2786 printf("S_XFERRED"); break; 2787 case 0x20: 2788 printf("MSGIN_ACK"); break; 2789 case 0x41: 2790 printf("DISC"); break; 2791 case 0x42: 2792 printf("SEL_TIMEO"); break; 2793 case 0x80: 2794 printf("RSLT_NI"); break; 2795 case 0x81: 2796 printf("RSLT_IFY"); break; 2797 case 0x85: 2798 printf("DISC_1"); break; 2799 case 0x18: case 0x19: case 0x1a: 2800 case 0x1b: case 0x1e: case 0x1f: 2801 case 0x28: case 0x29: case 0x2a: 2802 case 0x2b: case 0x2e: case 0x2f: 2803 case 0x48: case 0x49: case 0x4a: 2804 case 0x4b: case 0x4e: case 0x4f: 2805 case 0x88: case 0x89: case 0x8a: 2806 case 0x8b: case 0x8e: case 0x8f: 2807 switch(csr_trace[i].csr & 0xf0) { 2808 case 0x10: 2809 printf("DONE_"); break; 2810 case 0x20: 2811 printf("STOP_"); break; 2812 case 0x40: 2813 printf("ERR_"); break; 2814 case 0x80: 2815 printf("REQ_"); break; 2816 } 2817 switch(csr_trace[i].csr & 7) { 2818 case 0: 2819 printf("DATA_OUT"); break; 2820 case 1: 2821 printf("DATA_IN"); break; 2822 case 2: 2823 printf("CMD"); break; 2824 case 3: 2825 printf("STATUS"); break; 2826 case 6: 2827 printf("MSG_OUT"); break; 2828 case 7: 2829 printf("MSG_IN"); break; 2830 default: 2831 printf("invld phs"); 2832 } 2833 break; 2834 default: printf("****"); break; 2835 } 2836 if (csr_trace[i].asr & SBIC_ASR_INT) 2837 printf(" ASR_INT"); 2838 if (csr_trace[i].asr & SBIC_ASR_LCI) 2839 printf(" ASR_LCI"); 2840 if (csr_trace[i].asr & SBIC_ASR_BSY) 2841 printf(" ASR_BSY"); 2842 if (csr_trace[i].asr & SBIC_ASR_CIP) 2843 printf(" ASR_CIP"); 2844 printf("\n"); 2845 i = (i + 1) & (CSR_TRACE_SIZE - 1); 2846 } while (i != csr_traceptr); 2847 #endif 2848 GET_SBIC_asr(regs, asr); 2849 if ((asr & SBIC_ASR_INT) == 0) 2850 GET_SBIC_csr(regs, csr); 2851 else 2852 csr = 0; 2853 printf("%s@%p regs %p asr %x csr %x\n", dev->sc_dev.dv_xname, 2854 dev, regs, asr, csr); 2855 if ((acb = dev->free_list.tqh_first)) { 2856 printf("Free list:\n"); 2857 while (acb) { 2858 sbic_dump_acb(acb); 2859 acb = acb->chain.tqe_next; 2860 } 2861 } 2862 if ((acb = dev->ready_list.tqh_first)) { 2863 printf("Ready list:\n"); 2864 while (acb) { 2865 sbic_dump_acb(acb); 2866 acb = acb->chain.tqe_next; 2867 } 2868 } 2869 if ((acb = dev->nexus_list.tqh_first)) { 2870 printf("Nexus list:\n"); 2871 while (acb) { 2872 sbic_dump_acb(acb); 2873 acb = acb->chain.tqe_next; 2874 } 2875 } 2876 if (dev->sc_nexus) { 2877 printf("nexus:\n"); 2878 sbic_dump_acb(dev->sc_nexus); 2879 } 2880 printf("sc_xs %p targ %d lun %d flags %x tcnt %lx dmacmd %x mask %lx\n", 2881 dev->sc_xs, dev->target, dev->lun, dev->sc_flags, dev->sc_tcnt, 2882 dev->sc_dmacmd, dev->sc_dmamask); 2883 for (i = 0; i < 8; ++i) { 2884 if (dev->sc_tinfo[i].cmds > 2) { 2885 printf("tgt %d: cmds %d disc %d senses %d lubusy %x\n", 2886 i, dev->sc_tinfo[i].cmds, 2887 dev->sc_tinfo[i].dconns, 2888 dev->sc_tinfo[i].senses, 2889 dev->sc_tinfo[i].lubusy); 2890 } 2891 } 2892 splx(s); 2893 } 2894 2895 #endif 2896
Indexes created Fri Sep 26 20:09:58 GMT 2025