sbic.c revision 1.28.8.1
1 /* $NetBSD: sbic.c,v 1.28.8.1 1997/07/01 17:33:24 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1994 Christian E. Hopps 5 * Copyright (c) 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * Van Jacobson of Lawrence Berkeley Laboratory. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the University of 22 * California, Berkeley and its contributors. 23 * 4. Neither the name of the University nor the names of its contributors 24 * may be used to endorse or promote products derived from this software 25 * without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 37 * SUCH DAMAGE. 38 * 39 * @(#)scsi.c 7.5 (Berkeley) 5/4/91 40 */ 41 42 /* 43 * AMIGA AMD 33C93 scsi adaptor driver 44 */ 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/device.h> 49 #include <sys/kernel.h> /* For hz */ 50 #include <sys/disklabel.h> 51 #include <sys/dkstat.h> 52 #include <sys/buf.h> 53 #include <dev/scsipi/scsi_all.h> 54 #include <dev/scsipi/scsipi_all.h> 55 #include <dev/scsipi/scsiconf.h> 56 #include <vm/vm.h> 57 #include <vm/vm_kern.h> 58 #include <vm/vm_page.h> 59 #include <machine/pmap.h> 60 #include <machine/cpu.h> 61 #include <amiga/amiga/device.h> 62 #include <amiga/amiga/custom.h> 63 #include <amiga/amiga/isr.h> 64 #include <amiga/dev/dmavar.h> 65 #include <amiga/dev/sbicreg.h> 66 #include <amiga/dev/sbicvar.h> 67 68 /* These are for bounce buffers */ 69 #include <amiga/amiga/cc.h> 70 #include <amiga/dev/zbusvar.h> 71 72 #include <vm/pmap.h> 73 74 /* Since I can't find this in any other header files */ 75 #define SCSI_PHASE(reg) (reg&0x07) 76 77 /* 78 * SCSI delays 79 * In u-seconds, primarily for state changes on the SPC. 80 */ 81 #define SBIC_CMD_WAIT 50000 /* wait per step of 'immediate' cmds */ 82 #define SBIC_DATA_WAIT 50000 /* wait per data in/out step */ 83 #define SBIC_INIT_WAIT 50000 /* wait per step (both) during init */ 84 85 #define b_cylin b_resid 86 #define SBIC_WAIT(regs, until, timeo) sbicwait(regs, until, timeo, __LINE__) 87 88 int sbicicmd __P((struct sbic_softc *, int, int, void *, int, void *, int)); 89 int sbicgo __P((struct sbic_softc *, struct scsipi_xfer *)); 90 int sbicdmaok __P((struct sbic_softc *, struct scsipi_xfer *)); 91 int sbicwait __P((sbic_regmap_p, char, int , int)); 92 int sbiccheckdmap __P((void *, u_long, u_long)); 93 int sbicselectbus __P((struct sbic_softc *, sbic_regmap_p, u_char, u_char, u_char)); 94 int sbicxfstart __P((sbic_regmap_p, int, u_char, int)); 95 int sbicxfout __P((sbic_regmap_p regs, int, void *, int)); 96 int sbicfromscsiperiod __P((struct sbic_softc *, sbic_regmap_p, int)); 97 int sbictoscsiperiod __P((struct sbic_softc *, sbic_regmap_p, int)); 98 int sbicpoll __P((struct sbic_softc *)); 99 int sbicnextstate __P((struct sbic_softc *, u_char, u_char)); 100 int sbicmsgin __P((struct sbic_softc *)); 101 int sbicxfin __P((sbic_regmap_p regs, int, void *)); 102 int sbicabort __P((struct sbic_softc *, sbic_regmap_p, char *)); 103 void sbicxfdone __P((struct sbic_softc *, sbic_regmap_p, int)); 104 void sbicerror __P((struct sbic_softc *, sbic_regmap_p, u_char)); 105 void sbicstart __P((struct sbic_softc *)); 106 void sbicreset __P((struct sbic_softc *)); 107 void sbic_scsidone __P((struct sbic_acb *, int)); 108 void sbic_sched __P((struct sbic_softc *)); 109 void sbic_save_ptrs __P((struct sbic_softc *, sbic_regmap_p,int,int)); 110 void sbic_load_ptrs __P((struct sbic_softc *, sbic_regmap_p,int,int)); 111 #ifdef DEBUG 112 void sbicdumpstate __P((void)); 113 void sbic_dump_acb __P((struct sbic_acb *)); 114 #endif 115 116 /* 117 * Synch xfer parameters, and timing conversions 118 */ 119 int sbic_min_period = SBIC_SYN_MIN_PERIOD; /* in cycles = f(ICLK,FSn) */ 120 int sbic_max_offset = SBIC_SYN_MAX_OFFSET; /* pure number */ 121 122 int sbic_cmd_wait = SBIC_CMD_WAIT; 123 int sbic_data_wait = SBIC_DATA_WAIT; 124 int sbic_init_wait = SBIC_INIT_WAIT; 125 126 /* 127 * was broken before.. now if you want this you get it for all drives 128 * on sbic controllers. 129 */ 130 u_char sbic_inhibit_sync[8]; 131 int sbic_enable_reselect = 1; 132 int sbic_clock_override = 0; 133 int sbic_no_dma = 0; 134 int sbic_parallel_operations = 1; 135 136 #ifdef DEBUG 137 sbic_regmap_p debug_sbic_regs; 138 int sbicdma_ops = 0; /* total DMA operations */ 139 int sbicdma_bounces = 0; /* number operations using bounce buffer */ 140 int sbicdma_hits = 0; /* number of DMA chains that were contiguous */ 141 int sbicdma_misses = 0; /* number of DMA chains that were not contiguous */ 142 int sbicdma_saves = 0; 143 #define QPRINTF(a) if (sbic_debug > 1) printf a 144 int sbic_debug = 0; 145 int sync_debug = 0; 146 int sbic_dma_debug = 0; 147 int reselect_debug = 0; 148 int report_sense = 0; 149 int data_pointer_debug = 0; 150 u_char debug_asr, debug_csr, routine; 151 void sbictimeout __P((struct sbic_softc *dev)); 152 153 #define CSR_TRACE_SIZE 32 154 #if CSR_TRACE_SIZE 155 #define CSR_TRACE(w,c,a,x) do { \ 156 int s = splbio(); \ 157 csr_trace[csr_traceptr].whr = (w); csr_trace[csr_traceptr].csr = (c); \ 158 csr_trace[csr_traceptr].asr = (a); csr_trace[csr_traceptr].xtn = (x); \ 159 dma_cachectl((caddr_t)&csr_trace[csr_traceptr], sizeof(csr_trace[0])); \ 160 csr_traceptr = (csr_traceptr + 1) & (CSR_TRACE_SIZE - 1); \ 161 /* dma_cachectl((caddr_t)&csr_traceptr, sizeof(csr_traceptr));*/ \ 162 splx(s); \ 163 } while (0) 164 int csr_traceptr; 165 int csr_tracesize = CSR_TRACE_SIZE; 166 struct { 167 u_char whr; 168 u_char csr; 169 u_char asr; 170 u_char xtn; 171 } csr_trace[CSR_TRACE_SIZE]; 172 #else 173 #define CSR_TRACE(w,c,a,x) 174 #endif 175 176 #define SBIC_TRACE_SIZE 0 177 #if SBIC_TRACE_SIZE 178 #define SBIC_TRACE(dev) do { \ 179 int s = splbio(); \ 180 sbic_trace[sbic_traceptr].sp = &s; \ 181 sbic_trace[sbic_traceptr].line = __LINE__; \ 182 sbic_trace[sbic_traceptr].sr = s; \ 183 sbic_trace[sbic_traceptr].csr = csr_traceptr; \ 184 dma_cachectl(&sbic_trace[sbic_traceptr], sizeof(sbic_trace[0])); \ 185 sbic_traceptr = (sbic_traceptr + 1) & (SBIC_TRACE_SIZE - 1); \ 186 dma_cachectl(&sbic_traceptr, sizeof(sbic_traceptr)); \ 187 if (dev) dma_cachectl(dev, sizeof(*dev)); \ 188 splx(s); \ 189 } while (0) 190 int sbic_traceptr; 191 int sbic_tracesize = SBIC_TRACE_SIZE; 192 struct { 193 void *sp; 194 u_short line; 195 u_short sr; 196 int csr; 197 } sbic_trace[SBIC_TRACE_SIZE]; 198 #else 199 #define SBIC_TRACE(dev) 200 #endif 201 202 #else /* DEBUG */ 203 #define QPRINTF(a) 204 #define CSR_TRACE(w,c,a,x) 205 #define SBIC_TRACE(dev) 206 #endif /* DEBUG */ 207 208 /* 209 * default minphys routine for sbic based controllers 210 */ 211 void 212 sbic_minphys(bp) 213 struct buf *bp; 214 { 215 216 /* 217 * No max transfer at this level. 218 */ 219 minphys(bp); 220 } 221 222 /* 223 * Save DMA pointers. Take into account partial transfer. Shut down DMA. 224 */ 225 void 226 sbic_save_ptrs(dev, regs, target, lun) 227 struct sbic_softc *dev; 228 sbic_regmap_p regs; 229 int target, lun; 230 { 231 int count, asr, s; 232 struct sbic_acb* acb; 233 234 SBIC_TRACE(dev); 235 if( !dev->sc_cur ) return; 236 if( !(dev->sc_flags & SBICF_INDMA) ) return; /* DMA not active */ 237 238 s = splbio(); 239 240 acb = dev->sc_nexus; 241 count = -1; 242 do { 243 GET_SBIC_asr(regs, asr); 244 if( asr & SBIC_ASR_DBR ) { 245 printf("sbic_save_ptrs: asr %02x canceled!\n", asr); 246 splx(s); 247 SBIC_TRACE(dev); 248 return; 249 } 250 } while( asr & (SBIC_ASR_BSY|SBIC_ASR_CIP) ); 251 252 /* Save important state */ 253 /* must be done before dmastop */ 254 acb->sc_dmacmd = dev->sc_dmacmd; 255 SBIC_TC_GET(regs, count); 256 257 /* Shut down DMA ====CAREFUL==== */ 258 dev->sc_dmastop(dev); 259 dev->sc_flags &= ~SBICF_INDMA; 260 SBIC_TC_PUT(regs, 0); 261 262 #ifdef DEBUG 263 if(!count && sbic_debug) printf("%dcount0",target); 264 if(data_pointer_debug == -1) 265 printf("SBIC saving target %d data pointers from (%p,%x)%xASR:%02x", 266 target, dev->sc_cur->dc_addr, dev->sc_cur->dc_count, 267 acb->sc_dmacmd, asr); 268 #endif 269 270 /* Fixup partial xfers */ 271 acb->sc_kv.dc_addr += (dev->sc_tcnt - count); 272 acb->sc_kv.dc_count -= (dev->sc_tcnt - count); 273 acb->sc_pa.dc_addr += (dev->sc_tcnt - count); 274 acb->sc_pa.dc_count -= ((dev->sc_tcnt - count)>>1); 275 276 acb->sc_tcnt = dev->sc_tcnt = count; 277 #ifdef DEBUG 278 if(data_pointer_debug) 279 printf(" at (%p,%x):%x\n", 280 dev->sc_cur->dc_addr, dev->sc_cur->dc_count,count); 281 sbicdma_saves++; 282 #endif 283 splx(s); 284 SBIC_TRACE(dev); 285 } 286 287 288 /* 289 * DOES NOT RESTART DMA!!! 290 */ 291 void sbic_load_ptrs(dev, regs, target, lun) 292 struct sbic_softc *dev; 293 sbic_regmap_p regs; 294 int target, lun; 295 { 296 int s, count; 297 char* vaddr, * paddr; 298 struct sbic_acb *acb; 299 300 SBIC_TRACE(dev); 301 acb = dev->sc_nexus; 302 if( !acb->sc_kv.dc_count ) { 303 /* No data to xfer */ 304 SBIC_TRACE(dev); 305 return; 306 } 307 308 s = splbio(); 309 310 dev->sc_last = dev->sc_cur = &acb->sc_pa; 311 dev->sc_tcnt = acb->sc_tcnt; 312 dev->sc_dmacmd = acb->sc_dmacmd; 313 314 #ifdef DEBUG 315 sbicdma_ops++; 316 #endif 317 if( !dev->sc_tcnt ) { 318 /* sc_tcnt == 0 implies end of segment */ 319 320 /* do kvm to pa mappings */ 321 paddr = acb->sc_pa.dc_addr = 322 (char *) kvtop(acb->sc_kv.dc_addr); 323 324 vaddr = acb->sc_kv.dc_addr; 325 count = acb->sc_kv.dc_count; 326 for(count = (NBPG - ((int)vaddr & PGOFSET)); 327 count < acb->sc_kv.dc_count 328 && (char*)kvtop(vaddr + count + 4) == paddr + count + 4; 329 count += NBPG); 330 /* If it's all contiguous... */ 331 if(count > acb->sc_kv.dc_count ) { 332 count = acb->sc_kv.dc_count; 333 #ifdef DEBUG 334 sbicdma_hits++; 335 #endif 336 } else { 337 #ifdef DEBUG 338 sbicdma_misses++; 339 #endif 340 } 341 acb->sc_tcnt = count; 342 acb->sc_pa.dc_count = count >> 1; 343 344 #ifdef DEBUG 345 if(data_pointer_debug) 346 printf("DMA recalc:kv(%p,%x)pa(%p,%lx)\n", 347 acb->sc_kv.dc_addr, 348 acb->sc_kv.dc_count, 349 acb->sc_pa.dc_addr, 350 acb->sc_tcnt); 351 #endif 352 } 353 splx(s); 354 #ifdef DEBUG 355 if(data_pointer_debug) 356 printf("SBIC restoring target %d data pointers at (%p,%x)%x\n", 357 target, dev->sc_cur->dc_addr, dev->sc_cur->dc_count, 358 dev->sc_dmacmd); 359 #endif 360 SBIC_TRACE(dev); 361 } 362 363 /* 364 * used by specific sbic controller 365 * 366 * it appears that the higher level code does nothing with LUN's 367 * so I will too. I could plug it in, however so could they 368 * in scsi_scsipi_cmd(). 369 */ 370 int 371 sbic_scsicmd(xs) 372 struct scsipi_xfer *xs; 373 { 374 struct sbic_acb *acb; 375 struct sbic_softc *dev; 376 struct scsipi_link *slp; 377 int flags, s, stat; 378 379 slp = xs->sc_link; 380 dev = slp->adapter_softc; 381 SBIC_TRACE(dev); 382 flags = xs->flags; 383 384 if (flags & SCSI_DATA_UIO) 385 panic("sbic: scsi data uio requested"); 386 387 if (dev->sc_nexus && flags & SCSI_POLL) 388 panic("sbic_scsicmd: busy"); 389 390 if (slp->scsipi_scsi.target == slp->scsipi_scsi.adapter_target) 391 return ESCAPE_NOT_SUPPORTED; 392 393 s = splbio(); 394 acb = dev->free_list.tqh_first; 395 if (acb) 396 TAILQ_REMOVE(&dev->free_list, acb, chain); 397 splx(s); 398 399 if (acb == NULL) { 400 #ifdef DEBUG 401 printf("sbic_scsicmd: unable to queue request for target %d\n", 402 slp->scsipi_scsi.target); 403 #ifdef DDB 404 Debugger(); 405 #endif 406 #endif 407 xs->error = XS_DRIVER_STUFFUP; 408 SBIC_TRACE(dev); 409 return(TRY_AGAIN_LATER); 410 } 411 412 acb->flags = ACB_ACTIVE; 413 if (flags & SCSI_DATA_IN) 414 acb->flags |= ACB_DATAIN; 415 acb->xs = xs; 416 bcopy(xs->cmd, &acb->cmd, xs->cmdlen); 417 acb->clen = xs->cmdlen; 418 acb->sc_kv.dc_addr = xs->data; 419 acb->sc_kv.dc_count = xs->datalen; 420 acb->pa_addr = xs->data ? (char *)kvtop(xs->data) : 0; /* XXXX check */ 421 422 if (flags & SCSI_POLL) { 423 s = splbio(); 424 /* 425 * This has major side effects -- it locks up the machine 426 */ 427 428 dev->sc_flags |= SBICF_ICMD; 429 do { 430 while(dev->sc_nexus) 431 sbicpoll(dev); 432 dev->sc_nexus = acb; 433 dev->sc_stat[0] = -1; 434 dev->sc_xs = xs; 435 dev->target = slp->scsipi_scsi.target; 436 dev->lun = slp->scsipi_scsi.lun; 437 stat = sbicicmd(dev, slp->scsipi_scsi.target, slp->scsipi_scsi.lun, 438 &acb->cmd, acb->clen, 439 acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 440 } while (dev->sc_nexus != acb); 441 sbic_scsidone(acb, stat); 442 443 splx(s); 444 SBIC_TRACE(dev); 445 return(COMPLETE); 446 } 447 448 s = splbio(); 449 TAILQ_INSERT_TAIL(&dev->ready_list, acb, chain); 450 451 if (dev->sc_nexus) { 452 splx(s); 453 SBIC_TRACE(dev); 454 return(SUCCESSFULLY_QUEUED); 455 } 456 457 /* 458 * nothing is active, try to start it now. 459 */ 460 sbic_sched(dev); 461 splx(s); 462 463 SBIC_TRACE(dev); 464 /* TODO: add sbic_poll to do SCSI_POLL operations */ 465 #if 0 466 if (flags & SCSI_POLL) 467 return(COMPLETE); 468 #endif 469 return(SUCCESSFULLY_QUEUED); 470 } 471 472 /* 473 * attempt to start the next available command 474 */ 475 void 476 sbic_sched(dev) 477 struct sbic_softc *dev; 478 { 479 struct scsipi_xfer *xs; 480 struct scsipi_link *slp; 481 struct sbic_acb *acb; 482 int flags, /*phase,*/ stat, i; 483 484 SBIC_TRACE(dev); 485 if (dev->sc_nexus) 486 return; /* a command is current active */ 487 488 SBIC_TRACE(dev); 489 for (acb = dev->ready_list.tqh_first; acb; acb = acb->chain.tqe_next) { 490 slp = acb->xs->sc_link; 491 i = slp->scsipi_scsi.target; 492 if (!(dev->sc_tinfo[i].lubusy & (1 << slp->scsipi_scsi.lun))) { 493 struct sbic_tinfo *ti = &dev->sc_tinfo[i]; 494 495 TAILQ_REMOVE(&dev->ready_list, acb, chain); 496 dev->sc_nexus = acb; 497 slp = acb->xs->sc_link; 498 ti = &dev->sc_tinfo[slp->scsipi_scsi.target]; 499 ti->lubusy |= (1 << slp->scsipi_scsi.lun); 500 acb->sc_pa.dc_addr = acb->pa_addr; /* XXXX check */ 501 break; 502 } 503 } 504 505 SBIC_TRACE(dev); 506 if (acb == NULL) 507 return; /* did not find an available command */ 508 509 dev->sc_xs = xs = acb->xs; 510 slp = xs->sc_link; 511 flags = xs->flags; 512 513 if (flags & SCSI_RESET) 514 sbicreset(dev); 515 516 #ifdef DEBUG 517 if( data_pointer_debug > 1 ) 518 printf("sbic_sched(%d,%d)\n",slp->scsipi_scsi.target, 519 slp->scsipi_scsi.lun); 520 #endif 521 dev->sc_stat[0] = -1; 522 dev->target = slp->scsipi_scsi.target; 523 dev->lun = slp->scsipi_scsi.lun; 524 if ( flags & SCSI_POLL || ( !sbic_parallel_operations 525 && (/*phase == STATUS_PHASE ||*/ 526 sbicdmaok(dev, xs) == 0) ) ) 527 stat = sbicicmd(dev, slp->scsipi_scsi.target, 528 slp->scsipi_scsi.lun, &acb->cmd, 529 acb->clen, acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 530 else if (sbicgo(dev, xs) == 0) { 531 SBIC_TRACE(dev); 532 return; 533 } else 534 stat = dev->sc_stat[0]; 535 536 sbic_scsidone(acb, stat); 537 SBIC_TRACE(dev); 538 } 539 540 void 541 sbic_scsidone(acb, stat) 542 struct sbic_acb *acb; 543 int stat; 544 { 545 struct scsipi_xfer *xs; 546 struct scsipi_link *slp; 547 struct sbic_softc *dev; 548 int dosched = 0; 549 550 xs = acb->xs; 551 slp = xs->sc_link; 552 dev = slp->adapter_softc; 553 SBIC_TRACE(dev); 554 #ifdef DIAGNOSTIC 555 if (acb == NULL || xs == NULL) { 556 printf("sbic_scsidone -- (%d,%d) no scsi_xfer\n", 557 dev->target, dev->lun); 558 #ifdef DDB 559 Debugger(); 560 #endif 561 return; 562 } 563 #endif 564 /* 565 * is this right? 566 */ 567 xs->status = stat; 568 569 #ifdef DEBUG 570 if( data_pointer_debug > 1 ) 571 printf("scsidone: (%d,%d)->(%d,%d)%02x\n", 572 slp->scsipi_scsi.target, slp->scsipi_scsi.lun, 573 dev->target, dev->lun, stat); 574 if( xs->sc_link->scsipi_scsi.target == 575 dev->sc_link.scsipi_scsi.adapter_target ) 576 panic("target == hostid"); 577 #endif 578 579 if (xs->error == XS_NOERROR && !(acb->flags & ACB_CHKSENSE)) { 580 if (stat == SCSI_CHECK) { 581 /* Schedule a REQUEST SENSE */ 582 struct scsipi_sense *ss = (void *)&acb->cmd; 583 #ifdef DEBUG 584 if (report_sense) 585 printf("sbic_scsidone: autosense %02x targ %d lun %d", 586 acb->cmd.opcode, slp->scsipi_scsi.target, 587 slp->scsipi_scsi.lun); 588 #endif 589 bzero(ss, sizeof(*ss)); 590 ss->opcode = REQUEST_SENSE; 591 ss->byte2 = slp->scsipi_scsi.lun << 5; 592 ss->length = sizeof(struct scsipi_sense_data); 593 acb->clen = sizeof(*ss); 594 acb->sc_kv.dc_addr = (char *)&xs->sense.scsi_sense; 595 acb->sc_kv.dc_count = sizeof(struct scsipi_sense_data); 596 acb->pa_addr = (char *)kvtop((u_char *)&xs->sense.scsi_sense); /* XXX check */ 597 acb->flags = ACB_ACTIVE | ACB_CHKSENSE | ACB_DATAIN; 598 TAILQ_INSERT_HEAD(&dev->ready_list, acb, chain); 599 dev->sc_tinfo[slp->scsipi_scsi.target].lubusy &= 600 ~(1 << slp->scsipi_scsi.lun); 601 dev->sc_tinfo[slp->scsipi_scsi.target].senses++; 602 if (dev->sc_nexus == acb) { 603 dev->sc_nexus = NULL; 604 dev->sc_xs = NULL; 605 sbic_sched(dev); 606 } 607 SBIC_TRACE(dev); 608 return; 609 } 610 } 611 if (xs->error == XS_NOERROR && (acb->flags & ACB_CHKSENSE)) { 612 xs->error = XS_SENSE; 613 #ifdef DEBUG 614 if (report_sense) 615 printf(" => %02x %02x\n", xs->sense.scsi_sense.flags, 616 xs->sense.scsi_sense.extra_bytes[3]); 617 #endif 618 } else { 619 xs->resid = 0; /* XXXX */ 620 } 621 #if whataboutthisone 622 case SCSI_BUSY: 623 xs->error = XS_BUSY; 624 break; 625 #endif 626 xs->flags |= ITSDONE; 627 628 /* 629 * Remove the ACB from whatever queue it's on. We have to do a bit of 630 * a hack to figure out which queue it's on. Note that it is *not* 631 * necessary to cdr down the ready queue, but we must cdr down the 632 * nexus queue and see if it's there, so we can mark the unit as no 633 * longer busy. This code is sickening, but it works. 634 */ 635 if (acb == dev->sc_nexus) { 636 dev->sc_nexus = NULL; 637 dev->sc_xs = NULL; 638 dev->sc_tinfo[slp->scsipi_scsi.target].lubusy &= 639 ~(1<<slp->scsipi_scsi.lun); 640 if (dev->ready_list.tqh_first) 641 dosched = 1; /* start next command */ 642 } else if (dev->ready_list.tqh_last == &acb->chain.tqe_next) { 643 TAILQ_REMOVE(&dev->ready_list, acb, chain); 644 } else { 645 register struct sbic_acb *acb2; 646 for (acb2 = dev->nexus_list.tqh_first; acb2; 647 acb2 = acb2->chain.tqe_next) { 648 if (acb2 == acb) { 649 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 650 dev->sc_tinfo[slp->scsipi_scsi.target].lubusy 651 &= ~(1<<slp->scsipi_scsi.lun); 652 break; 653 } 654 } 655 if (acb2) 656 ; 657 else if (acb->chain.tqe_next) { 658 TAILQ_REMOVE(&dev->ready_list, acb, chain); 659 } else { 660 printf("%s: can't find matching acb\n", 661 dev->sc_dev.dv_xname); 662 #ifdef DDB 663 Debugger(); 664 #endif 665 } 666 } 667 /* Put it on the free list. */ 668 acb->flags = ACB_FREE; 669 TAILQ_INSERT_HEAD(&dev->free_list, acb, chain); 670 671 dev->sc_tinfo[slp->scsipi_scsi.target].cmds++; 672 673 scsipi_done(xs); 674 675 if (dosched) 676 sbic_sched(dev); 677 SBIC_TRACE(dev); 678 } 679 680 int 681 sbicdmaok(dev, xs) 682 struct sbic_softc *dev; 683 struct scsipi_xfer *xs; 684 { 685 if (sbic_no_dma || xs->datalen & 0x1 || (u_int)xs->data & 0x3) 686 return(0); 687 /* 688 * controller supports dma to any addresses? 689 */ 690 else if ((dev->sc_flags & SBICF_BADDMA) == 0) 691 return(1); 692 /* 693 * this address is ok for dma? 694 */ 695 else if (sbiccheckdmap(xs->data, xs->datalen, dev->sc_dmamask) == 0) 696 return(1); 697 /* 698 * we have a bounce buffer? 699 */ 700 else if (dev->sc_tinfo[xs->sc_link->scsipi_scsi.target].bounce) 701 return(1); 702 /* 703 * try to get one 704 */ 705 else if ((dev->sc_tinfo[xs->sc_link->scsipi_scsi.target].bounce 706 = (char *)alloc_z2mem(MAXPHYS))) { 707 if (isztwomem(dev->sc_tinfo[xs->sc_link->scsipi_scsi.target].bounce)) 708 printf("alloc ZII target %d bounce pa 0x%x\n", 709 xs->sc_link->scsipi_scsi.target, 710 kvtop(dev->sc_tinfo[xs->sc_link->scsipi_scsi.target].bounce)); 711 else if (dev->sc_tinfo[xs->sc_link->scsipi_scsi.target].bounce) 712 printf("alloc CHIP target %d bounce pa 0x%p\n", 713 xs->sc_link->scsipi_scsi.target, 714 PREP_DMA_MEM(dev->sc_tinfo[xs->sc_link->scsipi_scsi.target].bounce)); 715 return(1); 716 } 717 718 return(0); 719 } 720 721 722 int 723 sbicwait(regs, until, timeo, line) 724 sbic_regmap_p regs; 725 char until; 726 int timeo; 727 int line; 728 { 729 u_char val; 730 int csr; 731 732 SBIC_TRACE((struct sbic_softc *)0); 733 if (timeo == 0) 734 timeo = 1000000; /* some large value.. */ 735 736 GET_SBIC_asr(regs,val); 737 while ((val & until) == 0) { 738 if (timeo-- == 0) { 739 GET_SBIC_csr(regs, csr); 740 printf("sbicwait TIMEO @%d with asr=x%x csr=x%x\n", 741 line, val, csr); 742 #if defined(DDB) && defined(DEBUG) 743 Debugger(); 744 #endif 745 return(val); /* Maybe I should abort */ 746 break; 747 } 748 DELAY(1); 749 GET_SBIC_asr(regs,val); 750 } 751 SBIC_TRACE((struct sbic_softc *)0); 752 return(val); 753 } 754 755 int 756 sbicabort(dev, regs, where) 757 struct sbic_softc *dev; 758 sbic_regmap_p regs; 759 char *where; 760 { 761 u_char csr, asr; 762 763 GET_SBIC_asr(regs, asr); 764 GET_SBIC_csr(regs, csr); 765 766 printf ("%s: abort %s: csr = 0x%02x, asr = 0x%02x\n", 767 dev->sc_dev.dv_xname, where, csr, asr); 768 769 770 #if 0 771 /* Clean up running command */ 772 if (dev->sc_nexus != NULL) { 773 dev->sc_nexus->xs->error = XS_DRIVER_STUFFUP; 774 sbic_scsidone(dev->sc_nexus, dev->sc_stat[0]); 775 } 776 while (acb = dev->nexus_list.tqh_first) { 777 acb->xs->error = XS_DRIVER_STUFFUP; 778 sbic_scsidone(acb, -1 /*acb->stat[0]*/); 779 } 780 #endif 781 782 /* Clean up chip itself */ 783 if (dev->sc_flags & SBICF_SELECTED) { 784 while( asr & SBIC_ASR_DBR ) { 785 /* sbic is jammed w/data. need to clear it */ 786 /* But we don't know what direction it needs to go */ 787 GET_SBIC_data(regs, asr); 788 printf("%s: abort %s: clearing data buffer 0x%02x\n", 789 dev->sc_dev.dv_xname, where, asr); 790 GET_SBIC_asr(regs, asr); 791 if( asr & SBIC_ASR_DBR ) /* Not the read direction, then */ 792 SET_SBIC_data(regs, asr); 793 GET_SBIC_asr(regs, asr); 794 } 795 WAIT_CIP(regs); 796 printf("%s: sbicabort - sending ABORT command\n", dev->sc_dev.dv_xname); 797 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 798 WAIT_CIP(regs); 799 800 GET_SBIC_asr(regs, asr); 801 if (asr & (SBIC_ASR_BSY|SBIC_ASR_LCI)) { 802 /* ok, get more drastic.. */ 803 804 printf("%s: sbicabort - asr %x, trying to reset\n", dev->sc_dev.dv_xname, asr); 805 sbicreset(dev); 806 dev->sc_flags &= ~SBICF_SELECTED; 807 return -1; 808 } 809 printf("%s: sbicabort - sending DISC command\n", dev->sc_dev.dv_xname); 810 SET_SBIC_cmd(regs, SBIC_CMD_DISC); 811 812 do { 813 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0); 814 GET_SBIC_csr (regs, csr); 815 CSR_TRACE('a',csr,asr,0); 816 } while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) 817 && (csr != SBIC_CSR_CMD_INVALID)); 818 819 /* lets just hope it worked.. */ 820 dev->sc_flags &= ~SBICF_SELECTED; 821 } 822 return -1; 823 } 824 825 826 /* 827 * Initialize driver-private structures 828 */ 829 830 void 831 sbicinit(dev) 832 struct sbic_softc *dev; 833 { 834 sbic_regmap_p regs; 835 u_int i; 836 struct sbic_acb *acb; 837 u_int inhibit_sync; 838 839 extern u_long scsi_nosync; 840 extern int shift_nosync; 841 842 regs = dev->sc_sbicp; 843 844 if ((dev->sc_flags & SBICF_ALIVE) == 0) { 845 TAILQ_INIT(&dev->ready_list); 846 TAILQ_INIT(&dev->nexus_list); 847 TAILQ_INIT(&dev->free_list); 848 dev->sc_nexus = NULL; 849 dev->sc_xs = NULL; 850 acb = dev->sc_acb; 851 bzero(acb, sizeof(dev->sc_acb)); 852 for (i = 0; i < sizeof(dev->sc_acb) / sizeof(*acb); i++) { 853 TAILQ_INSERT_TAIL(&dev->free_list, acb, chain); 854 acb++; 855 } 856 bzero(dev->sc_tinfo, sizeof(dev->sc_tinfo)); 857 #ifdef DEBUG 858 /* make sure timeout is really not needed */ 859 timeout((void *)sbictimeout, dev, 30 * hz); 860 #endif 861 862 } else panic("sbic: reinitializing driver!"); 863 864 dev->sc_flags |= SBICF_ALIVE; 865 dev->sc_flags &= ~SBICF_SELECTED; 866 867 /* initialize inhibit array */ 868 if (scsi_nosync) { 869 inhibit_sync = (scsi_nosync >> shift_nosync) & 0xff; 870 shift_nosync += 8; 871 #ifdef DEBUG 872 if (inhibit_sync) 873 printf("%s: Inhibiting synchronous transfer %02x\n", 874 dev->sc_dev.dv_xname, inhibit_sync); 875 #endif 876 for (i = 0; i < 8; ++i) 877 if (inhibit_sync & (1 << i)) 878 sbic_inhibit_sync[i] = 1; 879 } 880 881 sbicreset(dev); 882 } 883 884 void 885 sbicreset(dev) 886 struct sbic_softc *dev; 887 { 888 sbic_regmap_p regs; 889 u_int my_id, s; 890 u_char csr; 891 #if 0 892 u_int i; 893 struct sbic_acb *acb; 894 #endif 895 896 regs = dev->sc_sbicp; 897 #if 0 898 if (dev->sc_flags & SBICF_ALIVE) { 899 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 900 WAIT_CIP(regs); 901 } 902 #else 903 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 904 WAIT_CIP(regs); 905 #endif 906 s = splbio(); 907 my_id = dev->sc_link.scsipi_scsi.adapter_target & SBIC_ID_MASK; 908 909 /* Enable advanced mode */ 910 my_id |= SBIC_ID_EAF /*| SBIC_ID_EHP*/ ; 911 SET_SBIC_myid(regs, my_id); 912 913 /* 914 * Disable interrupts (in dmainit) then reset the chip 915 */ 916 SET_SBIC_cmd(regs, SBIC_CMD_RESET); 917 DELAY(25); 918 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 919 GET_SBIC_csr(regs, csr); /* clears interrupt also */ 920 921 if (dev->sc_clkfreq < 110) 922 my_id |= SBIC_ID_FS_8_10; 923 else if (dev->sc_clkfreq < 160) 924 my_id |= SBIC_ID_FS_12_15; 925 else if (dev->sc_clkfreq < 210) 926 my_id |= SBIC_ID_FS_16_20; 927 928 SET_SBIC_myid(regs, my_id); 929 930 /* 931 * Set up various chip parameters 932 */ 933 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI /* | SBIC_CTL_HSP */ 934 | SBIC_MACHINE_DMA_MODE); 935 /* 936 * don't allow (re)selection (SBIC_RID_ES) 937 * until we can handle target mode!! 938 */ 939 SET_SBIC_rselid(regs, SBIC_RID_ER); 940 SET_SBIC_syn(regs, 0); /* asynch for now */ 941 942 /* 943 * anything else was zeroed by reset 944 */ 945 splx(s); 946 947 #if 0 948 if ((dev->sc_flags & SBICF_ALIVE) == 0) { 949 TAILQ_INIT(&dev->ready_list); 950 TAILQ_INIT(&dev->nexus_list); 951 TAILQ_INIT(&dev->free_list); 952 dev->sc_nexus = NULL; 953 dev->sc_xs = NULL; 954 acb = dev->sc_acb; 955 bzero(acb, sizeof(dev->sc_acb)); 956 for (i = 0; i < sizeof(dev->sc_acb) / sizeof(*acb); i++) { 957 TAILQ_INSERT_TAIL(&dev->free_list, acb, chain); 958 acb++; 959 } 960 bzero(dev->sc_tinfo, sizeof(dev->sc_tinfo)); 961 } else { 962 if (dev->sc_nexus != NULL) { 963 dev->sc_nexus->xs->error = XS_DRIVER_STUFFUP; 964 sbic_scsidone(dev->sc_nexus, dev->sc_stat[0]); 965 } 966 while (acb = dev->nexus_list.tqh_first) { 967 acb->xs->error = XS_DRIVER_STUFFUP; 968 sbic_scsidone(acb, -1 /*acb->stat[0]*/); 969 } 970 } 971 972 dev->sc_flags |= SBICF_ALIVE; 973 #endif 974 dev->sc_flags &= ~SBICF_SELECTED; 975 } 976 977 void 978 sbicerror(dev, regs, csr) 979 struct sbic_softc *dev; 980 sbic_regmap_p regs; 981 u_char csr; 982 { 983 struct scsipi_xfer *xs; 984 985 xs = dev->sc_xs; 986 987 #ifdef DIAGNOSTIC 988 if (xs == NULL) 989 panic("sbicerror"); 990 #endif 991 if (xs->flags & SCSI_SILENT) 992 return; 993 994 printf("%s: ", dev->sc_dev.dv_xname); 995 printf("csr == 0x%02x\n", csr); /* XXX */ 996 } 997 998 /* 999 * select the bus, return when selected or error. 1000 */ 1001 int 1002 sbicselectbus(dev, regs, target, lun, our_addr) 1003 struct sbic_softc *dev; 1004 sbic_regmap_p regs; 1005 u_char target, lun, our_addr; 1006 { 1007 u_char asr, csr, id; 1008 1009 SBIC_TRACE(dev); 1010 QPRINTF(("sbicselectbus %d\n", target)); 1011 1012 /* 1013 * if we're already selected, return (XXXX panic maybe?) 1014 */ 1015 if (dev->sc_flags & SBICF_SELECTED) { 1016 SBIC_TRACE(dev); 1017 return(1); 1018 } 1019 1020 /* 1021 * issue select 1022 */ 1023 SBIC_TC_PUT(regs, 0); 1024 SET_SBIC_selid(regs, target); 1025 SET_SBIC_timeo(regs, SBIC_TIMEOUT(250,dev->sc_clkfreq)); 1026 1027 /* 1028 * set sync or async 1029 */ 1030 if (dev->sc_sync[target].state == SYNC_DONE) 1031 SET_SBIC_syn(regs, SBIC_SYN (dev->sc_sync[target].offset, 1032 dev->sc_sync[target].period)); 1033 else 1034 SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period)); 1035 1036 GET_SBIC_asr(regs, asr); 1037 if( asr & (SBIC_ASR_INT|SBIC_ASR_BSY) ) { 1038 /* This means we got ourselves reselected upon */ 1039 /* printf("sbicselectbus: INT/BSY asr %02x\n", asr);*/ 1040 #ifdef DDB 1041 /* Debugger();*/ 1042 #endif 1043 SBIC_TRACE(dev); 1044 return 1; 1045 } 1046 1047 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN); 1048 1049 /* 1050 * wait for select (merged from seperate function may need 1051 * cleanup) 1052 */ 1053 WAIT_CIP(regs); 1054 do { 1055 asr = SBIC_WAIT(regs, SBIC_ASR_INT | SBIC_ASR_LCI, 0); 1056 if (asr & SBIC_ASR_LCI) { 1057 #ifdef DEBUG 1058 if (reselect_debug) 1059 printf("sbicselectbus: late LCI asr %02x\n", asr); 1060 #endif 1061 SBIC_TRACE(dev); 1062 return 1; 1063 } 1064 GET_SBIC_csr (regs, csr); 1065 CSR_TRACE('s',csr,asr,target); 1066 QPRINTF(("%02x ", csr)); 1067 if( csr == SBIC_CSR_RSLT_NI || csr == SBIC_CSR_RSLT_IFY) { 1068 #ifdef DEBUG 1069 if(reselect_debug) 1070 printf("sbicselectbus: reselected asr %02x\n", asr); 1071 #endif 1072 /* We need to handle this now so we don't lock up later */ 1073 sbicnextstate(dev, csr, asr); 1074 SBIC_TRACE(dev); 1075 return 1; 1076 } 1077 if( csr == SBIC_CSR_SLT || csr == SBIC_CSR_SLT_ATN) { 1078 panic("sbicselectbus: target issued select!"); 1079 return 1; 1080 } 1081 } while (csr != (SBIC_CSR_MIS_2|MESG_OUT_PHASE) 1082 && csr != (SBIC_CSR_MIS_2|CMD_PHASE) && csr != SBIC_CSR_SEL_TIMEO); 1083 1084 /* Enable (or not) reselection */ 1085 if(!sbic_enable_reselect && dev->nexus_list.tqh_first == NULL) 1086 SET_SBIC_rselid (regs, 0); 1087 else 1088 SET_SBIC_rselid (regs, SBIC_RID_ER); 1089 1090 if (csr == (SBIC_CSR_MIS_2|CMD_PHASE)) { 1091 dev->sc_flags |= SBICF_SELECTED; /* device ignored ATN */ 1092 GET_SBIC_selid(regs, id); 1093 dev->target = id; 1094 GET_SBIC_tlun(regs,dev->lun); 1095 if( dev->lun & SBIC_TLUN_VALID ) 1096 dev->lun &= SBIC_TLUN_MASK; 1097 else 1098 dev->lun = lun; 1099 } else if (csr == (SBIC_CSR_MIS_2|MESG_OUT_PHASE)) { 1100 /* 1101 * Send identify message 1102 * (SCSI-2 requires an identify msg (?)) 1103 */ 1104 GET_SBIC_selid(regs, id); 1105 dev->target = id; 1106 GET_SBIC_tlun(regs,dev->lun); 1107 if( dev->lun & SBIC_TLUN_VALID ) 1108 dev->lun &= SBIC_TLUN_MASK; 1109 else 1110 dev->lun = lun; 1111 /* 1112 * handle drives that don't want to be asked 1113 * whether to go sync at all. 1114 */ 1115 if (sbic_inhibit_sync[id] 1116 && dev->sc_sync[id].state == SYNC_START) { 1117 #ifdef DEBUG 1118 if (sync_debug) 1119 printf("Forcing target %d asynchronous.\n", id); 1120 #endif 1121 dev->sc_sync[id].offset = 0; 1122 dev->sc_sync[id].period = sbic_min_period; 1123 dev->sc_sync[id].state = SYNC_DONE; 1124 } 1125 1126 1127 if (dev->sc_sync[id].state != SYNC_START){ 1128 if( dev->sc_xs->flags & SCSI_POLL 1129 || (dev->sc_flags & SBICF_ICMD) 1130 || !sbic_enable_reselect ) 1131 SEND_BYTE (regs, MSG_IDENTIFY | lun); 1132 else 1133 SEND_BYTE (regs, MSG_IDENTIFY_DR | lun); 1134 } else { 1135 /* 1136 * try to initiate a sync transfer. 1137 * So compose the sync message we're going 1138 * to send to the target 1139 */ 1140 1141 #ifdef DEBUG 1142 if (sync_debug) 1143 printf("Sending sync request to target %d ... ", 1144 id); 1145 #endif 1146 /* 1147 * setup scsi message sync message request 1148 */ 1149 dev->sc_msg[0] = MSG_IDENTIFY | lun; 1150 dev->sc_msg[1] = MSG_EXT_MESSAGE; 1151 dev->sc_msg[2] = 3; 1152 dev->sc_msg[3] = MSG_SYNC_REQ; 1153 dev->sc_msg[4] = sbictoscsiperiod(dev, regs, 1154 sbic_min_period); 1155 dev->sc_msg[5] = sbic_max_offset; 1156 1157 if (sbicxfstart(regs, 6, MESG_OUT_PHASE, sbic_cmd_wait)) 1158 sbicxfout(regs, 6, dev->sc_msg, MESG_OUT_PHASE); 1159 1160 dev->sc_sync[id].state = SYNC_SENT; 1161 #ifdef DEBUG 1162 if (sync_debug) 1163 printf ("sent\n"); 1164 #endif 1165 } 1166 1167 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0); 1168 GET_SBIC_csr (regs, csr); 1169 CSR_TRACE('y',csr,asr,target); 1170 QPRINTF(("[%02x]", csr)); 1171 #ifdef DEBUG 1172 if (sync_debug && dev->sc_sync[id].state == SYNC_SENT) 1173 printf("csr-result of last msgout: 0x%x\n", csr); 1174 #endif 1175 1176 if (csr != SBIC_CSR_SEL_TIMEO) 1177 dev->sc_flags |= SBICF_SELECTED; 1178 } 1179 if (csr == SBIC_CSR_SEL_TIMEO) 1180 dev->sc_xs->error = XS_SELTIMEOUT; 1181 1182 QPRINTF(("\n")); 1183 1184 SBIC_TRACE(dev); 1185 return(csr == SBIC_CSR_SEL_TIMEO); 1186 } 1187 1188 int 1189 sbicxfstart(regs, len, phase, wait) 1190 sbic_regmap_p regs; 1191 int len, wait; 1192 u_char phase; 1193 { 1194 u_char id; 1195 1196 switch (phase) { 1197 case DATA_IN_PHASE: 1198 case MESG_IN_PHASE: 1199 GET_SBIC_selid (regs, id); 1200 id |= SBIC_SID_FROM_SCSI; 1201 SET_SBIC_selid (regs, id); 1202 SBIC_TC_PUT (regs, (unsigned)len); 1203 break; 1204 case DATA_OUT_PHASE: 1205 case MESG_OUT_PHASE: 1206 case CMD_PHASE: 1207 GET_SBIC_selid (regs, id); 1208 id &= ~SBIC_SID_FROM_SCSI; 1209 SET_SBIC_selid (regs, id); 1210 SBIC_TC_PUT (regs, (unsigned)len); 1211 break; 1212 default: 1213 SBIC_TC_PUT (regs, 0); 1214 } 1215 QPRINTF(("sbicxfstart %d, %d, %d\n", len, phase, wait)); 1216 1217 return(1); 1218 } 1219 1220 int 1221 sbicxfout(regs, len, bp, phase) 1222 sbic_regmap_p regs; 1223 int len; 1224 void *bp; 1225 int phase; 1226 { 1227 u_char orig_csr, asr, *buf; 1228 int wait; 1229 1230 buf = bp; 1231 wait = sbic_data_wait; 1232 1233 QPRINTF(("sbicxfout {%d} %02x %02x %02x %02x %02x " 1234 "%02x %02x %02x %02x %02x\n", len, buf[0], buf[1], buf[2], 1235 buf[3], buf[4], buf[5], buf[6], buf[7], buf[8], buf[9])); 1236 1237 GET_SBIC_csr (regs, orig_csr); 1238 CSR_TRACE('>',orig_csr,0,0); 1239 1240 /* 1241 * sigh.. WD-PROTO strikes again.. sending the command in one go 1242 * causes the chip to lock up if talking to certain (misbehaving?) 1243 * targets. Anyway, this procedure should work for all targets, but 1244 * it's slightly slower due to the overhead 1245 */ 1246 WAIT_CIP (regs); 1247 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1248 for (;len > 0; len--) { 1249 GET_SBIC_asr (regs, asr); 1250 while ((asr & SBIC_ASR_DBR) == 0) { 1251 if ((asr & SBIC_ASR_INT) || --wait < 0) { 1252 #ifdef DEBUG 1253 if (sbic_debug) 1254 printf("sbicxfout fail: l%d i%x w%d\n", 1255 len, asr, wait); 1256 #endif 1257 return (len); 1258 } 1259 /* DELAY(1);*/ 1260 GET_SBIC_asr (regs, asr); 1261 } 1262 1263 SET_SBIC_data (regs, *buf); 1264 buf++; 1265 } 1266 SBIC_TC_GET(regs, len); 1267 QPRINTF(("sbicxfout done %d bytes\n", len)); 1268 /* 1269 * this leaves with one csr to be read 1270 */ 1271 return(0); 1272 } 1273 1274 /* returns # bytes left to read */ 1275 int 1276 sbicxfin(regs, len, bp) 1277 sbic_regmap_p regs; 1278 int len; 1279 void *bp; 1280 { 1281 int wait; 1282 u_char *obp, *buf; 1283 u_char orig_csr, csr, asr; 1284 1285 wait = sbic_data_wait; 1286 obp = bp; 1287 buf = bp; 1288 1289 GET_SBIC_csr (regs, orig_csr); 1290 CSR_TRACE('<',orig_csr,0,0); 1291 1292 QPRINTF(("sbicxfin %d, csr=%02x\n", len, orig_csr)); 1293 1294 WAIT_CIP (regs); 1295 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1296 for (;len > 0; len--) { 1297 GET_SBIC_asr (regs, asr); 1298 if((asr & SBIC_ASR_PE)) { 1299 #ifdef DEBUG 1300 printf("sbicxfin parity error: l%d i%x w%d\n", 1301 len, asr, wait); 1302 /* return ((unsigned long)buf - (unsigned long)bp); */ 1303 #ifdef DDB 1304 Debugger(); 1305 #endif 1306 #endif 1307 } 1308 while ((asr & SBIC_ASR_DBR) == 0) { 1309 if ((asr & SBIC_ASR_INT) || --wait < 0) { 1310 #ifdef DEBUG 1311 if (sbic_debug) { 1312 QPRINTF(("sbicxfin fail:{%d} %02x %02x %02x %02x %02x %02x " 1313 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1314 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1315 printf("sbicxfin fail: l%d i%x w%d\n", 1316 len, asr, wait); 1317 } 1318 #endif 1319 return len; 1320 } 1321 1322 if( ! asr & SBIC_ASR_BSY ) { 1323 GET_SBIC_csr(regs, csr); 1324 CSR_TRACE('<',csr,asr,len); 1325 QPRINTF(("[CSR%02xASR%02x]", csr, asr)); 1326 } 1327 1328 /* DELAY(1);*/ 1329 GET_SBIC_asr (regs, asr); 1330 } 1331 1332 GET_SBIC_data (regs, *buf); 1333 /* QPRINTF(("asr=%02x, csr=%02x, data=%02x\n", asr, csr, *buf));*/ 1334 buf++; 1335 } 1336 1337 QPRINTF(("sbicxfin {%d} %02x %02x %02x %02x %02x %02x " 1338 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1339 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1340 1341 /* this leaves with one csr to be read */ 1342 return len; 1343 } 1344 1345 /* 1346 * SCSI 'immediate' command: issue a command to some SCSI device 1347 * and get back an 'immediate' response (i.e., do programmed xfer 1348 * to get the response data). 'cbuf' is a buffer containing a scsi 1349 * command of length clen bytes. 'buf' is a buffer of length 'len' 1350 * bytes for data. The transfer direction is determined by the device 1351 * (i.e., by the scsi bus data xfer phase). If 'len' is zero, the 1352 * command must supply no data. 1353 */ 1354 int 1355 sbicicmd(dev, target, lun, cbuf, clen, buf, len) 1356 struct sbic_softc *dev; 1357 void *cbuf, *buf; 1358 int clen, len; 1359 { 1360 sbic_regmap_p regs; 1361 u_char phase, csr, asr; 1362 int wait, i; 1363 struct sbic_acb *acb; 1364 1365 #define CSR_LOG_BUF_SIZE 0 1366 #if CSR_LOG_BUF_SIZE 1367 int bufptr; 1368 int csrbuf[CSR_LOG_BUF_SIZE]; 1369 bufptr=0; 1370 #endif 1371 1372 SBIC_TRACE(dev); 1373 regs = dev->sc_sbicp; 1374 acb = dev->sc_nexus; 1375 1376 /* Make sure pointers are OK */ 1377 dev->sc_last = dev->sc_cur = &acb->sc_pa; 1378 dev->sc_tcnt = acb->sc_tcnt = 0; 1379 acb->sc_pa.dc_count = 0; /* No DMA */ 1380 acb->sc_kv.dc_addr = buf; 1381 acb->sc_kv.dc_count = len; 1382 1383 #ifdef DEBUG 1384 routine = 3; 1385 debug_sbic_regs = regs; /* store this to allow debug calls */ 1386 if( data_pointer_debug > 1 ) 1387 printf("sbicicmd(%d,%d):%d\n", target, lun, 1388 acb->sc_kv.dc_count); 1389 #endif 1390 1391 /* 1392 * set the sbic into non-DMA mode 1393 */ 1394 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI /*| SBIC_CTL_HSP*/); 1395 1396 dev->sc_stat[0] = 0xff; 1397 dev->sc_msg[0] = 0xff; 1398 i = 1; /* pre-load */ 1399 1400 /* We're stealing the SCSI bus */ 1401 dev->sc_flags |= SBICF_ICMD; 1402 1403 do { 1404 /* 1405 * select the SCSI bus (it's an error if bus isn't free) 1406 */ 1407 if (!( dev->sc_flags & SBICF_SELECTED ) 1408 && sbicselectbus(dev, regs, target, lun, dev->sc_scsiaddr)) { 1409 /*printf("sbicicmd trying to select busy bus!\n");*/ 1410 dev->sc_flags &= ~SBICF_ICMD; 1411 return(-1); 1412 } 1413 1414 /* 1415 * Wait for a phase change (or error) then let the device sequence 1416 * us through the various SCSI phases. 1417 */ 1418 1419 wait = sbic_cmd_wait; 1420 1421 asr = GET_SBIC_asr (regs, asr); 1422 GET_SBIC_csr (regs, csr); 1423 CSR_TRACE('I',csr,asr,target); 1424 QPRINTF((">ASR:%02xCSR:%02x<", asr, csr)); 1425 1426 #if CSR_LOG_BUF_SIZE 1427 csrbuf[bufptr++] = csr; 1428 #endif 1429 1430 1431 switch (csr) { 1432 case SBIC_CSR_S_XFERRED: 1433 case SBIC_CSR_DISC: 1434 case SBIC_CSR_DISC_1: 1435 dev->sc_flags &= ~SBICF_SELECTED; 1436 GET_SBIC_cmd_phase (regs, phase); 1437 if (phase == 0x60) { 1438 GET_SBIC_tlun (regs, dev->sc_stat[0]); 1439 i = 0; /* done */ 1440 /* break; */ /* Bypass all the state gobldygook */ 1441 } else { 1442 #ifdef DEBUG 1443 if(reselect_debug>1) 1444 printf("sbicicmd: handling disconnect\n"); 1445 #endif 1446 i = SBIC_STATE_DISCONNECT; 1447 } 1448 break; 1449 1450 case SBIC_CSR_XFERRED|CMD_PHASE: 1451 case SBIC_CSR_MIS|CMD_PHASE: 1452 case SBIC_CSR_MIS_1|CMD_PHASE: 1453 case SBIC_CSR_MIS_2|CMD_PHASE: 1454 if (sbicxfstart(regs, clen, CMD_PHASE, sbic_cmd_wait)) 1455 if (sbicxfout(regs, clen, 1456 cbuf, CMD_PHASE)) 1457 i = sbicabort(dev, regs,"icmd sending cmd"); 1458 #if 0 1459 GET_SBIC_csr(regs, csr); /* Lets us reload tcount */ 1460 WAIT_CIP(regs); 1461 GET_SBIC_asr(regs, asr); 1462 CSR_TRACE('I',csr,asr,target); 1463 if( asr & (SBIC_ASR_BSY|SBIC_ASR_LCI|SBIC_ASR_CIP) ) 1464 printf("next: cmd sent asr %02x, csr %02x\n", 1465 asr, csr); 1466 #endif 1467 break; 1468 1469 #if 0 1470 case SBIC_CSR_XFERRED|DATA_OUT_PHASE: 1471 case SBIC_CSR_XFERRED|DATA_IN_PHASE: 1472 case SBIC_CSR_MIS|DATA_OUT_PHASE: 1473 case SBIC_CSR_MIS|DATA_IN_PHASE: 1474 case SBIC_CSR_MIS_1|DATA_OUT_PHASE: 1475 case SBIC_CSR_MIS_1|DATA_IN_PHASE: 1476 case SBIC_CSR_MIS_2|DATA_OUT_PHASE: 1477 case SBIC_CSR_MIS_2|DATA_IN_PHASE: 1478 if (acb->sc_kv.dc_count <= 0) 1479 i = sbicabort(dev, regs, "icmd out of data"); 1480 else { 1481 wait = sbic_data_wait; 1482 if (sbicxfstart(regs, 1483 acb->sc_kv.dc_count, 1484 SBIC_PHASE(csr), wait)) 1485 if (csr & 0x01) 1486 /* data in? */ 1487 i=sbicxfin(regs, 1488 acb->sc_kv.dc_count, 1489 acb->sc_kv.dc_addr); 1490 else 1491 i=sbicxfout(regs, 1492 acb->sc_kv.dc_count, 1493 acb->sc_kv.dc_addr, 1494 SBIC_PHASE(csr)); 1495 acb->sc_kv.dc_addr += 1496 (acb->sc_kv.dc_count - i); 1497 acb->sc_kv.dc_count = i; 1498 i = 1; 1499 } 1500 break; 1501 1502 #endif 1503 case SBIC_CSR_XFERRED|STATUS_PHASE: 1504 case SBIC_CSR_MIS|STATUS_PHASE: 1505 case SBIC_CSR_MIS_1|STATUS_PHASE: 1506 case SBIC_CSR_MIS_2|STATUS_PHASE: 1507 /* 1508 * the sbic does the status/cmd-complete reading ok, 1509 * so do this with its hi-level commands. 1510 */ 1511 #ifdef DEBUG 1512 if(sbic_debug) 1513 printf("SBICICMD status phase\n"); 1514 #endif 1515 SBIC_TC_PUT(regs, 0); 1516 SET_SBIC_cmd_phase(regs, 0x46); 1517 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1518 break; 1519 1520 #if THIS_IS_A_RESERVED_STATE 1521 case BUS_FREE_PHASE: /* This is not legal */ 1522 if( dev->sc_stat[0] != 0xff ) 1523 goto out; 1524 break; 1525 #endif 1526 1527 default: 1528 i = sbicnextstate(dev, csr, asr); 1529 } 1530 1531 /* 1532 * make sure the last command was taken, 1533 * ie. we're not hunting after an ignored command.. 1534 */ 1535 GET_SBIC_asr(regs, asr); 1536 1537 /* tapes may take a loooong time.. */ 1538 while (asr & SBIC_ASR_BSY){ 1539 if(asr & SBIC_ASR_DBR) { 1540 printf("sbicicmd: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", 1541 csr,asr); 1542 #ifdef DDB 1543 Debugger(); 1544 #endif 1545 /* SBIC is jammed */ 1546 /* DUNNO which direction */ 1547 /* Try old direction */ 1548 GET_SBIC_data(regs,i); 1549 GET_SBIC_asr(regs, asr); 1550 if( asr & SBIC_ASR_DBR) /* Wants us to write */ 1551 SET_SBIC_data(regs,i); 1552 } 1553 GET_SBIC_asr(regs, asr); 1554 } 1555 1556 /* 1557 * wait for last command to complete 1558 */ 1559 if (asr & SBIC_ASR_LCI) { 1560 printf("sbicicmd: last command ignored\n"); 1561 } 1562 else if( i == 1 ) /* Bsy */ 1563 SBIC_WAIT (regs, SBIC_ASR_INT, wait); 1564 1565 /* 1566 * do it again 1567 */ 1568 } while ( i > 0 && dev->sc_stat[0] == 0xff); 1569 1570 /* Sometimes we need to do an extra read of the CSR */ 1571 GET_SBIC_csr(regs, csr); 1572 CSR_TRACE('I',csr,asr,0xff); 1573 1574 #if CSR_LOG_BUF_SIZE 1575 if(reselect_debug>1) 1576 for(i=0; i<bufptr; i++) 1577 printf("CSR:%02x", csrbuf[i]); 1578 #endif 1579 1580 #ifdef DEBUG 1581 if(data_pointer_debug > 1) 1582 printf("sbicicmd done(%d,%d):%d =%d=\n", 1583 dev->target, lun, 1584 acb->sc_kv.dc_count, 1585 dev->sc_stat[0]); 1586 #endif 1587 1588 QPRINTF(("=STS:%02x=", dev->sc_stat[0])); 1589 dev->sc_flags &= ~SBICF_ICMD; 1590 1591 SBIC_TRACE(dev); 1592 return(dev->sc_stat[0]); 1593 } 1594 1595 /* 1596 * Finish SCSI xfer command: After the completion interrupt from 1597 * a read/write operation, sequence through the final phases in 1598 * programmed i/o. This routine is a lot like sbicicmd except we 1599 * skip (and don't allow) the select, cmd out and data in/out phases. 1600 */ 1601 void 1602 sbicxfdone(dev, regs, target) 1603 struct sbic_softc *dev; 1604 sbic_regmap_p regs; 1605 int target; 1606 { 1607 u_char phase, asr, csr; 1608 int s; 1609 1610 SBIC_TRACE(dev); 1611 QPRINTF(("{")); 1612 s = splbio(); 1613 1614 /* 1615 * have the sbic complete on its own 1616 */ 1617 SBIC_TC_PUT(regs, 0); 1618 SET_SBIC_cmd_phase(regs, 0x46); 1619 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1620 1621 do { 1622 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0); 1623 GET_SBIC_csr (regs, csr); 1624 CSR_TRACE('f',csr,asr,target); 1625 QPRINTF(("%02x:", csr)); 1626 } while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) 1627 && (csr != SBIC_CSR_S_XFERRED)); 1628 1629 dev->sc_flags &= ~SBICF_SELECTED; 1630 1631 GET_SBIC_cmd_phase (regs, phase); 1632 QPRINTF(("}%02x", phase)); 1633 if (phase == 0x60) 1634 GET_SBIC_tlun(regs, dev->sc_stat[0]); 1635 else 1636 sbicerror(dev, regs, csr); 1637 1638 QPRINTF(("=STS:%02x=\n", dev->sc_stat[0])); 1639 splx(s); 1640 SBIC_TRACE(dev); 1641 } 1642 1643 /* 1644 * No DMA chains 1645 */ 1646 1647 int 1648 sbicgo(dev, xs) 1649 struct sbic_softc *dev; 1650 struct scsipi_xfer *xs; 1651 { 1652 int i, dmaflags, count, usedma; 1653 u_char csr, asr, *addr; 1654 sbic_regmap_p regs; 1655 struct sbic_acb *acb; 1656 1657 SBIC_TRACE(dev); 1658 dev->target = xs->sc_link->scsipi_scsi.target; 1659 dev->lun = xs->sc_link->scsipi_scsi.lun; 1660 acb = dev->sc_nexus; 1661 regs = dev->sc_sbicp; 1662 1663 usedma = sbicdmaok(dev, xs); 1664 #ifdef DEBUG 1665 routine = 1; 1666 debug_sbic_regs = regs; /* store this to allow debug calls */ 1667 if( data_pointer_debug > 1 ) 1668 printf("sbicgo(%d,%d)\n", dev->target, dev->lun); 1669 #endif 1670 1671 /* 1672 * set the sbic into DMA mode 1673 */ 1674 if( usedma ) 1675 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI | 1676 SBIC_MACHINE_DMA_MODE); 1677 else 1678 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1679 1680 1681 /* 1682 * select the SCSI bus (it's an error if bus isn't free) 1683 */ 1684 if (sbicselectbus(dev, regs, dev->target, dev->lun, 1685 dev->sc_scsiaddr)) { 1686 /* printf("sbicgo: Trying to select busy bus!\n"); */ 1687 SBIC_TRACE(dev); 1688 return(0); /* Not done: needs to be rescheduled */ 1689 } 1690 dev->sc_stat[0] = 0xff; 1691 1692 /* 1693 * Calculate DMA chains now 1694 */ 1695 1696 dmaflags = 0; 1697 if (acb->flags & ACB_DATAIN) 1698 dmaflags |= DMAGO_READ; 1699 1700 1701 /* 1702 * Deal w/bounce buffers. 1703 */ 1704 1705 addr = acb->sc_kv.dc_addr; 1706 count = acb->sc_kv.dc_count; 1707 if (count && (char *)kvtop(addr) != acb->sc_pa.dc_addr) { /* XXXX check */ 1708 printf("sbic: DMA buffer mapping changed %p->%x\n", 1709 acb->sc_pa.dc_addr, kvtop(addr)); 1710 #ifdef DDB 1711 Debugger(); 1712 #endif 1713 } 1714 1715 #ifdef DEBUG 1716 ++sbicdma_ops; /* count total DMA operations */ 1717 #endif 1718 if (count && usedma && dev->sc_flags & SBICF_BADDMA && 1719 sbiccheckdmap(addr, count, dev->sc_dmamask)) { 1720 /* 1721 * need to bounce the dma. 1722 */ 1723 if (dmaflags & DMAGO_READ) { 1724 acb->flags |= ACB_BBUF; 1725 acb->sc_dmausrbuf = addr; 1726 acb->sc_dmausrlen = count; 1727 acb->sc_usrbufpa = (u_char *)kvtop(addr); 1728 if(!dev->sc_tinfo[dev->target].bounce) { 1729 printf("sbicgo: HELP! no bounce allocated for %d\n", 1730 dev->target); 1731 printf("xfer: (%p->%p,%lx)\n", acb->sc_dmausrbuf, 1732 acb->sc_usrbufpa, acb->sc_dmausrlen); 1733 dev->sc_tinfo[xs->sc_link->scsipi_scsi.target].bounce 1734 = (char *)alloc_z2mem(MAXPHYS); 1735 if (isztwomem(dev->sc_tinfo[xs->sc_link->scsipi_scsi.target].bounce)) 1736 printf("alloc ZII target %d bounce pa 0x%x\n", 1737 xs->sc_link->scsipi_scsi.target, 1738 kvtop(dev->sc_tinfo[xs->sc_link->scsipi_scsi.target].bounce)); 1739 else if (dev->sc_tinfo[xs->sc_link->scsipi_scsi.target].bounce) 1740 printf("alloc CHIP target %d bounce pa 0x%p\n", 1741 xs->sc_link->scsipi_scsi.target, 1742 PREP_DMA_MEM(dev->sc_tinfo[xs->sc_link->scsipi_scsi.target].bounce)); 1743 1744 printf("Allocating %d bounce at %x\n", 1745 dev->target, 1746 kvtop(dev->sc_tinfo[dev->target].bounce)); 1747 } 1748 } else { /* write: copy to dma buffer */ 1749 #ifdef DEBUG 1750 if(data_pointer_debug) 1751 printf("sbicgo: copying %x bytes to target %d bounce %x\n", 1752 count, dev->target, 1753 kvtop(dev->sc_tinfo[dev->target].bounce)); 1754 #endif 1755 bcopy (addr, dev->sc_tinfo[dev->target].bounce, count); 1756 } 1757 addr = dev->sc_tinfo[dev->target].bounce;/* and use dma buffer */ 1758 acb->sc_kv.dc_addr = addr; 1759 #ifdef DEBUG 1760 ++sbicdma_bounces; /* count number of bounced */ 1761 #endif 1762 } 1763 1764 /* 1765 * Allocate the DMA chain 1766 */ 1767 1768 /* Set start KVM addresses */ 1769 #if 0 1770 acb->sc_kv.dc_addr = addr; 1771 acb->sc_kv.dc_count = count; 1772 #endif 1773 1774 /* Mark end of segment */ 1775 acb->sc_tcnt = dev->sc_tcnt = 0; 1776 acb->sc_pa.dc_count = 0; 1777 1778 sbic_load_ptrs(dev, regs, dev->target, dev->lun); 1779 SBIC_TRACE(dev); 1780 /* Enable interrupts but don't do any DMA */ 1781 dev->sc_enintr(dev); 1782 if (usedma) { 1783 dev->sc_tcnt = dev->sc_dmago(dev, acb->sc_pa.dc_addr, 1784 acb->sc_pa.dc_count, 1785 dmaflags); 1786 #ifdef DEBUG 1787 dev->sc_dmatimo = dev->sc_tcnt ? 1 : 0; 1788 #endif 1789 } else 1790 dev->sc_dmacmd = 0; /* Don't use DMA */ 1791 dev->sc_flags |= SBICF_INDMA; 1792 /* SBIC_TC_PUT(regs, dev->sc_tcnt); */ /* XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX */ 1793 SBIC_TRACE(dev); 1794 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 1795 1796 /* 1797 * push the data cache ( I think this won't work (EH)) 1798 */ 1799 #if defined(M68040) || defined(M68060) 1800 if (mmutype == MMU_68040 && usedma && count) { 1801 dma_cachectl(addr, count); 1802 if (((u_int)addr & 0xF) || (((u_int)addr + count) & 0xF)) 1803 dev->sc_flags |= SBICF_DCFLUSH; 1804 } 1805 #endif 1806 1807 /* 1808 * enintr() also enables interrupts for the sbic 1809 */ 1810 #ifdef DEBUG 1811 if( data_pointer_debug > 1 ) 1812 printf("sbicgo dmago:%d(%p:%lx)\n", 1813 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 1814 #if 0 1815 /* 1816 * Hmm - this isn't right: asr and csr haven't been set yet. 1817 */ 1818 debug_asr = asr; 1819 debug_csr = csr; 1820 #endif 1821 #endif 1822 1823 /* 1824 * Lets cycle a while then let the interrupt handler take over 1825 */ 1826 1827 asr = GET_SBIC_asr(regs, asr); 1828 do { 1829 GET_SBIC_csr(regs, csr); 1830 CSR_TRACE('g',csr,asr,dev->target); 1831 #ifdef DEBUG 1832 debug_csr = csr; 1833 routine = 1; 1834 #endif 1835 QPRINTF(("go[0x%x]", csr)); 1836 1837 i = sbicnextstate(dev, csr, asr); 1838 1839 WAIT_CIP(regs); 1840 GET_SBIC_asr(regs, asr); 1841 #ifdef DEBUG 1842 debug_asr = asr; 1843 #endif 1844 if(asr & SBIC_ASR_LCI) printf("sbicgo: LCI asr:%02x csr:%02x\n", 1845 asr,csr); 1846 } while( i == SBIC_STATE_RUNNING 1847 && asr & (SBIC_ASR_INT|SBIC_ASR_LCI) ); 1848 1849 CSR_TRACE('g',csr,asr,i<<4); 1850 SBIC_TRACE(dev); 1851 if (i == SBIC_STATE_DONE && dev->sc_stat[0] == 0xff) printf("sbicgo: done & stat = 0xff\n"); 1852 if (i == SBIC_STATE_DONE && dev->sc_stat[0] != 0xff) { 1853 /* if( i == SBIC_STATE_DONE && dev->sc_stat[0] ) { */ 1854 /* Did we really finish that fast? */ 1855 return 1; 1856 } 1857 return 0; 1858 } 1859 1860 1861 int 1862 sbicintr(dev) 1863 struct sbic_softc *dev; 1864 { 1865 sbic_regmap_p regs; 1866 u_char asr, csr; 1867 int i; 1868 1869 regs = dev->sc_sbicp; 1870 1871 /* 1872 * pending interrupt? 1873 */ 1874 GET_SBIC_asr (regs, asr); 1875 if ((asr & SBIC_ASR_INT) == 0) 1876 return(0); 1877 1878 SBIC_TRACE(dev); 1879 do { 1880 GET_SBIC_csr(regs, csr); 1881 CSR_TRACE('i',csr,asr,dev->target); 1882 #ifdef DEBUG 1883 debug_csr = csr; 1884 routine = 2; 1885 #endif 1886 QPRINTF(("intr[0x%x]", csr)); 1887 1888 i = sbicnextstate(dev, csr, asr); 1889 1890 WAIT_CIP(regs); 1891 GET_SBIC_asr(regs, asr); 1892 #ifdef DEBUG 1893 debug_asr = asr; 1894 #endif 1895 #if 0 1896 if(asr & SBIC_ASR_LCI) printf("sbicintr: LCI asr:%02x csr:%02x\n", 1897 asr,csr); 1898 #endif 1899 } while(i == SBIC_STATE_RUNNING && 1900 asr & (SBIC_ASR_INT|SBIC_ASR_LCI)); 1901 CSR_TRACE('i',csr,asr,i<<4); 1902 SBIC_TRACE(dev); 1903 return(1); 1904 } 1905 1906 /* 1907 * Run commands and wait for disconnect 1908 */ 1909 int 1910 sbicpoll(dev) 1911 struct sbic_softc *dev; 1912 { 1913 sbic_regmap_p regs; 1914 u_char asr, csr; 1915 int i; 1916 1917 SBIC_TRACE(dev); 1918 regs = dev->sc_sbicp; 1919 1920 do { 1921 GET_SBIC_asr (regs, asr); 1922 #ifdef DEBUG 1923 debug_asr = asr; 1924 #endif 1925 GET_SBIC_csr(regs, csr); 1926 CSR_TRACE('p',csr,asr,dev->target); 1927 #ifdef DEBUG 1928 debug_csr = csr; 1929 routine = 2; 1930 #endif 1931 QPRINTF(("poll[0x%x]", csr)); 1932 1933 i = sbicnextstate(dev, csr, asr); 1934 1935 WAIT_CIP(regs); 1936 GET_SBIC_asr(regs, asr); 1937 /* tapes may take a loooong time.. */ 1938 while (asr & SBIC_ASR_BSY){ 1939 if(asr & SBIC_ASR_DBR) { 1940 printf("sbipoll: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", 1941 csr,asr); 1942 #ifdef DDB 1943 Debugger(); 1944 #endif 1945 /* SBIC is jammed */ 1946 /* DUNNO which direction */ 1947 /* Try old direction */ 1948 GET_SBIC_data(regs,i); 1949 GET_SBIC_asr(regs, asr); 1950 if( asr & SBIC_ASR_DBR) /* Wants us to write */ 1951 SET_SBIC_data(regs,i); 1952 } 1953 GET_SBIC_asr(regs, asr); 1954 } 1955 1956 if(asr & SBIC_ASR_LCI) printf("sbicpoll: LCI asr:%02x csr:%02x\n", 1957 asr,csr); 1958 else if( i == 1 ) /* BSY */ 1959 SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait); 1960 } while(i == SBIC_STATE_RUNNING); 1961 CSR_TRACE('p',csr,asr,i<<4); 1962 SBIC_TRACE(dev); 1963 return(1); 1964 } 1965 1966 /* 1967 * Handle a single msgin 1968 */ 1969 1970 int 1971 sbicmsgin(dev) 1972 struct sbic_softc *dev; 1973 { 1974 sbic_regmap_p regs; 1975 int recvlen; 1976 u_char asr, csr, *tmpaddr; 1977 1978 regs = dev->sc_sbicp; 1979 1980 dev->sc_msg[0] = 0xff; 1981 dev->sc_msg[1] = 0xff; 1982 1983 GET_SBIC_asr(regs, asr); 1984 #ifdef DEBUG 1985 if(reselect_debug>1) 1986 printf("sbicmsgin asr=%02x\n", asr); 1987 #endif 1988 1989 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 1990 1991 GET_SBIC_selid (regs, csr); 1992 SET_SBIC_selid (regs, csr | SBIC_SID_FROM_SCSI); 1993 1994 SBIC_TC_PUT(regs, 0); 1995 tmpaddr = dev->sc_msg; 1996 recvlen = 1; 1997 do { 1998 while( recvlen-- ) { 1999 asr = GET_SBIC_asr(regs, asr); 2000 GET_SBIC_csr(regs, csr); 2001 QPRINTF(("sbicmsgin ready to go (csr,asr)=(%02x,%02x)\n", 2002 csr, asr)); 2003 2004 RECV_BYTE(regs, *tmpaddr); 2005 CSR_TRACE('m',csr,asr,*tmpaddr); 2006 #if 1 2007 /* 2008 * get the command completion interrupt, or we 2009 * can't send a new command (LCI) 2010 */ 2011 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2012 GET_SBIC_csr(regs, csr); 2013 CSR_TRACE('X',csr,asr,dev->target); 2014 #else 2015 WAIT_CIP(regs); 2016 do { 2017 GET_SBIC_asr(regs, asr); 2018 csr = 0xff; 2019 GET_SBIC_csr(regs, csr); 2020 CSR_TRACE('X',csr,asr,dev->target); 2021 if( csr == 0xff ) 2022 printf("sbicmsgin waiting: csr %02x asr %02x\n", csr, asr); 2023 } while( csr == 0xff ); 2024 #endif 2025 #ifdef DEBUG 2026 if(reselect_debug>1) 2027 printf("sbicmsgin: got %02x csr %02x asr %02x\n", 2028 *tmpaddr, csr, asr); 2029 #endif 2030 #if do_parity_check 2031 if( asr & SBIC_ASR_PE ) { 2032 printf ("Parity error"); 2033 /* This code simply does not work. */ 2034 WAIT_CIP(regs); 2035 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2036 WAIT_CIP(regs); 2037 GET_SBIC_asr(regs, asr); 2038 WAIT_CIP(regs); 2039 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2040 WAIT_CIP(regs); 2041 if( !(asr & SBIC_ASR_LCI) ) 2042 /* Target wants to send garbled msg*/ 2043 continue; 2044 printf("--fixing\n"); 2045 /* loop until a msgout phase occurs on target */ 2046 while(csr & 0x07 != MESG_OUT_PHASE) { 2047 while( asr & SBIC_ASR_BSY && 2048 !(asr & SBIC_ASR_DBR|SBIC_ASR_INT) ) 2049 GET_SBIC_asr(regs, asr); 2050 if( asr & SBIC_ASR_DBR ) 2051 panic("msgin: jammed again!\n"); 2052 GET_SBIC_csr(regs, csr); 2053 CSR_TRACE('e',csr,asr,dev->target); 2054 if( csr & 0x07 != MESG_OUT_PHASE ) { 2055 sbicnextstate(dev, csr, asr); 2056 sbic_save_ptrs(dev, regs, 2057 dev->target, 2058 dev->lun); 2059 } 2060 } 2061 /* Should be msg out by now */ 2062 SEND_BYTE(regs, MSG_PARITY_ERROR); 2063 } 2064 else 2065 #endif 2066 tmpaddr++; 2067 2068 if(recvlen) { 2069 /* Clear ACK */ 2070 WAIT_CIP(regs); 2071 GET_SBIC_asr(regs, asr); 2072 GET_SBIC_csr(regs, csr); 2073 CSR_TRACE('X',csr,asr,dev->target); 2074 QPRINTF(("sbicmsgin pre byte CLR_ACK (csr,asr)=(%02x,%02x)\n", 2075 csr, asr)); 2076 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2077 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2078 } 2079 2080 }; 2081 2082 if(dev->sc_msg[0] == 0xff) { 2083 printf("sbicmsgin: sbic swallowed our message\n"); 2084 break; 2085 } 2086 #ifdef DEBUG 2087 if (sync_debug) 2088 printf("msgin done csr 0x%x asr 0x%x msg 0x%x\n", 2089 csr, asr, dev->sc_msg[0]); 2090 #endif 2091 /* 2092 * test whether this is a reply to our sync 2093 * request 2094 */ 2095 if (MSG_ISIDENTIFY(dev->sc_msg[0])) { 2096 QPRINTF(("IFFY")); 2097 #if 0 2098 /* There is an implied load-ptrs here */ 2099 sbic_load_ptrs(dev, regs, dev->target, dev->lun); 2100 #endif 2101 /* Got IFFY msg -- ack it */ 2102 } else if (dev->sc_msg[0] == MSG_REJECT 2103 && dev->sc_sync[dev->target].state == SYNC_SENT) { 2104 QPRINTF(("REJECT of SYN")); 2105 #ifdef DEBUG 2106 if (sync_debug) 2107 printf("target %d rejected sync, going async\n", 2108 dev->target); 2109 #endif 2110 dev->sc_sync[dev->target].period = sbic_min_period; 2111 dev->sc_sync[dev->target].offset = 0; 2112 dev->sc_sync[dev->target].state = SYNC_DONE; 2113 SET_SBIC_syn(regs, 2114 SBIC_SYN(dev->sc_sync[dev->target].offset, 2115 dev->sc_sync[dev->target].period)); 2116 } else if ((dev->sc_msg[0] == MSG_REJECT)) { 2117 QPRINTF(("REJECT")); 2118 /* 2119 * we'll never REJECt a REJECT message.. 2120 */ 2121 } else if ((dev->sc_msg[0] == MSG_SAVE_DATA_PTR)) { 2122 QPRINTF(("MSG_SAVE_DATA_PTR")); 2123 /* 2124 * don't reject this either. 2125 */ 2126 } else if ((dev->sc_msg[0] == MSG_DISCONNECT)) { 2127 QPRINTF(("DISCONNECT")); 2128 #ifdef DEBUG 2129 if( reselect_debug>1 && dev->sc_msg[0] == MSG_DISCONNECT ) 2130 printf("sbicmsgin: got disconnect msg %s\n", 2131 (dev->sc_flags & SBICF_ICMD)?"rejecting":""); 2132 #endif 2133 if( dev->sc_flags & SBICF_ICMD ) { 2134 /* We're in immediate mode. Prevent disconnects. */ 2135 /* prepare to reject the message, NACK */ 2136 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2137 WAIT_CIP(regs); 2138 } 2139 } else if (dev->sc_msg[0] == MSG_CMD_COMPLETE ) { 2140 QPRINTF(("CMD_COMPLETE")); 2141 /* !! KLUDGE ALERT !! quite a few drives don't seem to 2142 * really like the current way of sending the 2143 * sync-handshake together with the ident-message, and 2144 * they react by sending command-complete and 2145 * disconnecting right after returning the valid sync 2146 * handshake. So, all I can do is reselect the drive, 2147 * and hope it won't disconnect again. I don't think 2148 * this is valid behavior, but I can't help fixing a 2149 * problem that apparently exists. 2150 * 2151 * Note: we should not get here on `normal' command 2152 * completion, as that condition is handled by the 2153 * high-level sel&xfer resume command used to walk 2154 * thru status/cc-phase. 2155 */ 2156 2157 #ifdef DEBUG 2158 if (sync_debug) 2159 printf ("GOT MSG %d! target %d acting weird.." 2160 " waiting for disconnect...\n", 2161 dev->sc_msg[0], dev->target); 2162 #endif 2163 /* Check to see if sbic is handling this */ 2164 GET_SBIC_asr(regs, asr); 2165 if(asr & SBIC_ASR_BSY) 2166 return SBIC_STATE_RUNNING; 2167 2168 /* Let's try this: Assume it works and set status to 00 */ 2169 dev->sc_stat[0] = 0; 2170 } else if (dev->sc_msg[0] == MSG_EXT_MESSAGE 2171 && tmpaddr == &dev->sc_msg[1]) { 2172 QPRINTF(("ExtMSG\n")); 2173 /* Read in whole extended message */ 2174 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2175 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2176 GET_SBIC_asr(regs, asr); 2177 GET_SBIC_csr(regs, csr); 2178 QPRINTF(("CLR ACK asr %02x, csr %02x\n", asr, csr)); 2179 RECV_BYTE(regs, *tmpaddr); 2180 CSR_TRACE('x',csr,asr,*tmpaddr); 2181 /* Wait for command completion IRQ */ 2182 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2183 recvlen = *tmpaddr++; 2184 QPRINTF(("Recving ext msg, asr %02x csr %02x len %02x\n", 2185 asr, csr, recvlen)); 2186 } else if (dev->sc_msg[0] == MSG_EXT_MESSAGE && dev->sc_msg[1] == 3 2187 && dev->sc_msg[2] == MSG_SYNC_REQ) { 2188 QPRINTF(("SYN")); 2189 dev->sc_sync[dev->target].period = 2190 sbicfromscsiperiod(dev, 2191 regs, dev->sc_msg[3]); 2192 dev->sc_sync[dev->target].offset = dev->sc_msg[4]; 2193 dev->sc_sync[dev->target].state = SYNC_DONE; 2194 SET_SBIC_syn(regs, 2195 SBIC_SYN(dev->sc_sync[dev->target].offset, 2196 dev->sc_sync[dev->target].period)); 2197 printf("%s: target %d now synchronous," 2198 " period=%dns, offset=%d.\n", 2199 dev->sc_dev.dv_xname, dev->target, 2200 dev->sc_msg[3] * 4, dev->sc_msg[4]); 2201 } else { 2202 #ifdef DEBUG 2203 if (sbic_debug || sync_debug) 2204 printf ("sbicmsgin: Rejecting message 0x%02x\n", 2205 dev->sc_msg[0]); 2206 #endif 2207 /* prepare to reject the message, NACK */ 2208 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2209 WAIT_CIP(regs); 2210 } 2211 /* Clear ACK */ 2212 WAIT_CIP(regs); 2213 GET_SBIC_asr(regs, asr); 2214 GET_SBIC_csr(regs, csr); 2215 CSR_TRACE('X',csr,asr,dev->target); 2216 QPRINTF(("sbicmsgin pre CLR_ACK (csr,asr)=(%02x,%02x)%d\n", 2217 csr, asr, recvlen)); 2218 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2219 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2220 } 2221 #if 0 2222 while((csr == SBIC_CSR_MSGIN_W_ACK) 2223 || (SBIC_PHASE(csr) == MESG_IN_PHASE)); 2224 #else 2225 while (recvlen>0); 2226 #endif 2227 2228 QPRINTF(("sbicmsgin finished: csr %02x, asr %02x\n",csr, asr)); 2229 2230 /* Should still have one CSR to read */ 2231 return SBIC_STATE_RUNNING; 2232 } 2233 2234 2235 /* 2236 * sbicnextstate() 2237 * return: 2238 * 0 == done 2239 * 1 == working 2240 * 2 == disconnected 2241 * -1 == error 2242 */ 2243 int 2244 sbicnextstate(dev, csr, asr) 2245 struct sbic_softc *dev; 2246 u_char csr, asr; 2247 { 2248 sbic_regmap_p regs; 2249 struct sbic_acb *acb; 2250 int i, newtarget, newlun, wait; 2251 #if 0 2252 unsigned tcnt; 2253 #endif 2254 2255 i = 0; 2256 SBIC_TRACE(dev); 2257 regs = dev->sc_sbicp; 2258 acb = dev->sc_nexus; 2259 2260 QPRINTF(("next[%02x,%02x]",asr,csr)); 2261 2262 switch (csr) { 2263 case SBIC_CSR_XFERRED|CMD_PHASE: 2264 case SBIC_CSR_MIS|CMD_PHASE: 2265 case SBIC_CSR_MIS_1|CMD_PHASE: 2266 case SBIC_CSR_MIS_2|CMD_PHASE: 2267 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 2268 if (sbicxfstart(regs, acb->clen, CMD_PHASE, sbic_cmd_wait)) 2269 if (sbicxfout(regs, acb->clen, 2270 &acb->cmd, CMD_PHASE)) 2271 goto abort; 2272 break; 2273 2274 case SBIC_CSR_XFERRED|STATUS_PHASE: 2275 case SBIC_CSR_MIS|STATUS_PHASE: 2276 case SBIC_CSR_MIS_1|STATUS_PHASE: 2277 case SBIC_CSR_MIS_2|STATUS_PHASE: 2278 /* 2279 * this should be the normal i/o completion case. 2280 * get the status & cmd complete msg then let the 2281 * device driver look at what happened. 2282 */ 2283 sbicxfdone(dev,regs,dev->target); 2284 /* 2285 * check for overlapping cache line, flush if so 2286 */ 2287 #if defined(M68040) || defined(M68060) 2288 if (dev->sc_flags & SBICF_DCFLUSH) { 2289 #if 0 2290 printf("sbic: 68040/68060 DMA cache flush needs" 2291 "fixing? %x:%x\n", 2292 dev->sc_xs->data, dev->sc_xs->datalen); 2293 #endif 2294 } 2295 #endif 2296 #ifdef DEBUG 2297 if( data_pointer_debug > 1 ) 2298 printf("next dmastop: %d(%p:%lx)\n", 2299 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 2300 dev->sc_dmatimo = 0; 2301 #endif 2302 dev->sc_dmastop(dev); /* was dmafree */ 2303 if (acb->flags & ACB_BBUF) { 2304 if ((u_char *)kvtop(acb->sc_dmausrbuf) != acb->sc_usrbufpa) 2305 printf("%s: WARNING - buffer mapping changed %p->%x\n", 2306 dev->sc_dev.dv_xname, acb->sc_usrbufpa, 2307 kvtop(acb->sc_dmausrbuf)); 2308 #ifdef DEBUG 2309 if(data_pointer_debug) 2310 printf("sbicgo:copying %lx bytes from target %d bounce %x\n", 2311 acb->sc_dmausrlen, 2312 dev->target, 2313 kvtop(dev->sc_tinfo[dev->target].bounce)); 2314 #endif 2315 bcopy(dev->sc_tinfo[dev->target].bounce, 2316 acb->sc_dmausrbuf, 2317 acb->sc_dmausrlen); 2318 } 2319 dev->sc_flags &= ~(SBICF_INDMA | SBICF_DCFLUSH); 2320 sbic_scsidone(acb, dev->sc_stat[0]); 2321 SBIC_TRACE(dev); 2322 return SBIC_STATE_DONE; 2323 2324 case SBIC_CSR_XFERRED|DATA_OUT_PHASE: 2325 case SBIC_CSR_XFERRED|DATA_IN_PHASE: 2326 case SBIC_CSR_MIS|DATA_OUT_PHASE: 2327 case SBIC_CSR_MIS|DATA_IN_PHASE: 2328 case SBIC_CSR_MIS_1|DATA_OUT_PHASE: 2329 case SBIC_CSR_MIS_1|DATA_IN_PHASE: 2330 case SBIC_CSR_MIS_2|DATA_OUT_PHASE: 2331 case SBIC_CSR_MIS_2|DATA_IN_PHASE: 2332 if( dev->sc_xs->flags & SCSI_POLL || dev->sc_flags & SBICF_ICMD 2333 || acb->sc_dmacmd == 0 ) { 2334 /* Do PIO */ 2335 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2336 if (acb->sc_kv.dc_count <= 0) { 2337 printf("sbicnextstate:xfer count %d asr%x csr%x\n", 2338 acb->sc_kv.dc_count, asr, csr); 2339 goto abort; 2340 } 2341 wait = sbic_data_wait; 2342 if( sbicxfstart(regs, 2343 acb->sc_kv.dc_count, 2344 SBIC_PHASE(csr), wait)) 2345 if( SBIC_PHASE(csr) == DATA_IN_PHASE ) 2346 /* data in? */ 2347 i=sbicxfin(regs, 2348 acb->sc_kv.dc_count, 2349 acb->sc_kv.dc_addr); 2350 else 2351 i=sbicxfout(regs, 2352 acb->sc_kv.dc_count, 2353 acb->sc_kv.dc_addr, 2354 SBIC_PHASE(csr)); 2355 acb->sc_kv.dc_addr += 2356 (acb->sc_kv.dc_count - i); 2357 acb->sc_kv.dc_count = i; 2358 } else { 2359 if (acb->sc_kv.dc_count <= 0) { 2360 printf("sbicnextstate:xfer count %d asr%x csr%x\n", 2361 acb->sc_kv.dc_count, asr, csr); 2362 goto abort; 2363 } 2364 /* 2365 * do scatter-gather dma 2366 * hacking the controller chip, ouch.. 2367 */ 2368 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI | 2369 SBIC_MACHINE_DMA_MODE); 2370 /* 2371 * set next dma addr and dec count 2372 */ 2373 #if 0 2374 SBIC_TC_GET(regs, tcnt); 2375 dev->sc_cur->dc_count -= ((dev->sc_tcnt - tcnt) >> 1); 2376 dev->sc_cur->dc_addr += (dev->sc_tcnt - tcnt); 2377 dev->sc_tcnt = acb->sc_tcnt = tcnt; 2378 #else 2379 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 2380 sbic_load_ptrs(dev, regs, dev->target, dev->lun); 2381 #endif 2382 #ifdef DEBUG 2383 if( data_pointer_debug > 1 ) 2384 printf("next dmanext: %d(%p:%lx)\n", 2385 dev->target,dev->sc_cur->dc_addr, 2386 dev->sc_tcnt); 2387 dev->sc_dmatimo = 1; 2388 #endif 2389 dev->sc_tcnt = dev->sc_dmanext(dev); 2390 SBIC_TC_PUT(regs, (unsigned)dev->sc_tcnt); 2391 SET_SBIC_cmd(regs, SBIC_CMD_XFER_INFO); 2392 dev->sc_flags |= SBICF_INDMA; 2393 } 2394 break; 2395 2396 case SBIC_CSR_XFERRED|MESG_IN_PHASE: 2397 case SBIC_CSR_MIS|MESG_IN_PHASE: 2398 case SBIC_CSR_MIS_1|MESG_IN_PHASE: 2399 case SBIC_CSR_MIS_2|MESG_IN_PHASE: 2400 SBIC_TRACE(dev); 2401 return sbicmsgin(dev); 2402 2403 case SBIC_CSR_MSGIN_W_ACK: 2404 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); /* Dunno what I'm ACKing */ 2405 printf("Acking unknown msgin CSR:%02x",csr); 2406 break; 2407 2408 case SBIC_CSR_XFERRED|MESG_OUT_PHASE: 2409 case SBIC_CSR_MIS|MESG_OUT_PHASE: 2410 case SBIC_CSR_MIS_1|MESG_OUT_PHASE: 2411 case SBIC_CSR_MIS_2|MESG_OUT_PHASE: 2412 #ifdef DEBUG 2413 if (sync_debug) 2414 printf ("sending REJECT msg to last msg.\n"); 2415 #endif 2416 2417 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 2418 /* 2419 * should only get here on reject, 2420 * since it's always US that 2421 * initiate a sync transfer 2422 */ 2423 SEND_BYTE(regs, MSG_REJECT); 2424 WAIT_CIP(regs); 2425 if( asr & (SBIC_ASR_BSY|SBIC_ASR_LCI|SBIC_ASR_CIP) ) 2426 printf("next: REJECT sent asr %02x\n", asr); 2427 SBIC_TRACE(dev); 2428 return SBIC_STATE_RUNNING; 2429 2430 case SBIC_CSR_DISC: 2431 case SBIC_CSR_DISC_1: 2432 dev->sc_flags &= ~(SBICF_INDMA|SBICF_SELECTED); 2433 2434 /* Try to schedule another target */ 2435 #ifdef DEBUG 2436 if(reselect_debug>1) 2437 printf("sbicnext target %d disconnected\n", dev->target); 2438 #endif 2439 TAILQ_INSERT_HEAD(&dev->nexus_list, acb, chain); 2440 ++dev->sc_tinfo[dev->target].dconns; 2441 dev->sc_nexus = NULL; 2442 dev->sc_xs = NULL; 2443 2444 if( acb->xs->flags & SCSI_POLL 2445 || (dev->sc_flags & SBICF_ICMD) 2446 || !sbic_parallel_operations ) { 2447 SBIC_TRACE(dev); 2448 return SBIC_STATE_DISCONNECT; 2449 } 2450 sbic_sched(dev); 2451 SBIC_TRACE(dev); 2452 return SBIC_STATE_DISCONNECT; 2453 2454 case SBIC_CSR_RSLT_NI: 2455 case SBIC_CSR_RSLT_IFY: 2456 GET_SBIC_rselid(regs, newtarget); 2457 /* check SBIC_RID_SIV? */ 2458 newtarget &= SBIC_RID_MASK; 2459 if (csr == SBIC_CSR_RSLT_IFY) { 2460 /* Read IFY msg to avoid lockup */ 2461 GET_SBIC_data(regs, newlun); 2462 WAIT_CIP(regs); 2463 newlun &= SBIC_TLUN_MASK; 2464 CSR_TRACE('r',csr,asr,newtarget); 2465 } else { 2466 /* Need to get IFY message */ 2467 for (newlun = 256; newlun; --newlun) { 2468 GET_SBIC_asr(regs, asr); 2469 if (asr & SBIC_ASR_INT) 2470 break; 2471 delay(1); 2472 } 2473 newlun = 0; /* XXXX */ 2474 if ((asr & SBIC_ASR_INT) == 0) { 2475 #ifdef DEBUG 2476 if (reselect_debug) 2477 printf("RSLT_NI - no IFFY message? asr %x\n", asr); 2478 #endif 2479 } else { 2480 GET_SBIC_csr(regs,csr); 2481 CSR_TRACE('n',csr,asr,newtarget); 2482 if (csr == (SBIC_CSR_MIS | MESG_IN_PHASE) || 2483 csr == (SBIC_CSR_MIS_1 | MESG_IN_PHASE) || 2484 csr == (SBIC_CSR_MIS_2 | MESG_IN_PHASE)) { 2485 sbicmsgin(dev); 2486 newlun = dev->sc_msg[0] & 7; 2487 } else { 2488 printf("RSLT_NI - not MESG_IN_PHASE %x\n", 2489 csr); 2490 } 2491 } 2492 } 2493 #ifdef DEBUG 2494 if(reselect_debug>1 || (reselect_debug && csr==SBIC_CSR_RSLT_NI)) 2495 printf("sbicnext: reselect %s from targ %d lun %d\n", 2496 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", 2497 newtarget, newlun); 2498 #endif 2499 if (dev->sc_nexus) { 2500 #ifdef DEBUG 2501 if (reselect_debug > 1) 2502 printf("%s: reselect %s with active command\n", 2503 dev->sc_dev.dv_xname, 2504 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY"); 2505 #ifdef DDB 2506 /* Debugger();*/ 2507 #endif 2508 #endif 2509 TAILQ_INSERT_HEAD(&dev->ready_list, dev->sc_nexus, chain); 2510 dev->sc_tinfo[dev->target].lubusy &= ~(1 << dev->lun); 2511 dev->sc_nexus = NULL; 2512 dev->sc_xs = NULL; 2513 } 2514 /* Reload sync values for this target */ 2515 if (dev->sc_sync[newtarget].state == SYNC_DONE) 2516 SET_SBIC_syn(regs, SBIC_SYN (dev->sc_sync[newtarget].offset, 2517 dev->sc_sync[newtarget].period)); 2518 else 2519 SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period)); 2520 for (acb = dev->nexus_list.tqh_first; acb; 2521 acb = acb->chain.tqe_next) { 2522 if (acb->xs->sc_link->scsipi_scsi.target != newtarget || 2523 acb->xs->sc_link->scsipi_scsi.lun != newlun) 2524 continue; 2525 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 2526 dev->sc_nexus = acb; 2527 dev->sc_xs = acb->xs; 2528 dev->sc_flags |= SBICF_SELECTED; 2529 dev->target = newtarget; 2530 dev->lun = newlun; 2531 break; 2532 } 2533 if (acb == NULL) { 2534 printf("%s: reselect %s targ %d not in nexus_list %p\n", 2535 dev->sc_dev.dv_xname, 2536 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", newtarget, 2537 &dev->nexus_list.tqh_first); 2538 panic("bad reselect in sbic"); 2539 } 2540 if (csr == SBIC_CSR_RSLT_IFY) 2541 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2542 break; 2543 2544 default: 2545 abort: 2546 /* 2547 * Something unexpected happened -- deal with it. 2548 */ 2549 printf("sbicnextstate: aborting csr %02x asr %02x\n", csr, asr); 2550 #ifdef DDB 2551 Debugger(); 2552 #endif 2553 #ifdef DEBUG 2554 if( data_pointer_debug > 1 ) 2555 printf("next dmastop: %d(%p:%lx)\n", 2556 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 2557 dev->sc_dmatimo = 0; 2558 #endif 2559 dev->sc_dmastop(dev); 2560 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2561 sbicerror(dev, regs, csr); 2562 sbicabort(dev, regs, "next"); 2563 if (dev->sc_flags & SBICF_INDMA) { 2564 /* 2565 * check for overlapping cache line, flush if so 2566 */ 2567 #if defined(M68040) || defined(M68060) 2568 if (dev->sc_flags & SBICF_DCFLUSH) { 2569 #if 0 2570 printf("sbic: 68040/060 DMA cache flush needs" 2571 "fixing? %x:%x\n", 2572 dev->sc_xs->data, dev->sc_xs->datalen); 2573 #endif 2574 } 2575 #endif 2576 dev->sc_flags &= 2577 ~(SBICF_INDMA | SBICF_DCFLUSH); 2578 #ifdef DEBUG 2579 if( data_pointer_debug > 1 ) 2580 printf("next dmastop: %d(%p:%lx)\n", 2581 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 2582 dev->sc_dmatimo = 0; 2583 #endif 2584 dev->sc_dmastop(dev); 2585 sbic_scsidone(acb, -1); 2586 } 2587 SBIC_TRACE(dev); 2588 return SBIC_STATE_ERROR; 2589 } 2590 2591 SBIC_TRACE(dev); 2592 return(SBIC_STATE_RUNNING); 2593 } 2594 2595 2596 /* 2597 * Check if DMA can not be used with specified buffer 2598 */ 2599 2600 int 2601 sbiccheckdmap(bp, len, mask) 2602 void *bp; 2603 u_long len, mask; 2604 { 2605 u_char *buffer; 2606 u_long phy_buf; 2607 u_long phy_len; 2608 2609 buffer = bp; 2610 2611 if (len == 0) 2612 return(0); 2613 2614 while (len) { 2615 phy_buf = kvtop(buffer); 2616 if (len < (phy_len = NBPG - ((int) buffer & PGOFSET))) 2617 phy_len = len; 2618 if (phy_buf & mask) 2619 return(1); 2620 buffer += phy_len; 2621 len -= phy_len; 2622 } 2623 return(0); 2624 } 2625 2626 int 2627 sbictoscsiperiod(dev, regs, a) 2628 struct sbic_softc *dev; 2629 sbic_regmap_p regs; 2630 int a; 2631 { 2632 unsigned int fs; 2633 2634 /* 2635 * cycle = DIV / (2*CLK) 2636 * DIV = FS+2 2637 * best we can do is 200ns at 20Mhz, 2 cycles 2638 */ 2639 2640 GET_SBIC_myid(regs,fs); 2641 fs = (fs >>6) + 2; /* DIV */ 2642 fs = (fs * 10000) / (dev->sc_clkfreq<<1); /* Cycle, in ns */ 2643 if (a < 2) a = 8; /* map to Cycles */ 2644 return ((fs*a)>>2); /* in 4 ns units */ 2645 } 2646 2647 int 2648 sbicfromscsiperiod(dev, regs, p) 2649 struct sbic_softc *dev; 2650 sbic_regmap_p regs; 2651 int p; 2652 { 2653 register unsigned int fs, ret; 2654 2655 /* Just the inverse of the above */ 2656 2657 GET_SBIC_myid(regs,fs); 2658 fs = (fs >>6) + 2; /* DIV */ 2659 fs = (fs * 10000) / (dev->sc_clkfreq<<1); /* Cycle, in ns */ 2660 2661 ret = p << 2; /* in ns units */ 2662 ret = ret / fs; /* in Cycles */ 2663 if (ret < sbic_min_period) 2664 return(sbic_min_period); 2665 2666 /* verify rounding */ 2667 if (sbictoscsiperiod(dev, regs, ret) < p) 2668 ret++; 2669 return (ret >= 8) ? 0 : ret; 2670 } 2671 2672 #ifdef DEBUG 2673 2674 void 2675 sbicdumpstate() 2676 { 2677 u_char csr, asr; 2678 2679 GET_SBIC_asr(debug_sbic_regs,asr); 2680 GET_SBIC_csr(debug_sbic_regs,csr); 2681 printf("%s: asr:csr(%02x:%02x)->(%02x:%02x)\n", 2682 (routine==1)?"sbicgo": 2683 (routine==2)?"sbicintr": 2684 (routine==3)?"sbicicmd": 2685 (routine==4)?"sbicnext":"unknown", 2686 debug_asr, debug_csr, asr, csr); 2687 2688 } 2689 2690 void 2691 sbictimeout(dev) 2692 struct sbic_softc *dev; 2693 { 2694 int s, asr; 2695 2696 s = splbio(); 2697 if (dev->sc_dmatimo) { 2698 if (dev->sc_dmatimo > 1) { 2699 printf("%s: dma timeout #%d\n", 2700 dev->sc_dev.dv_xname, dev->sc_dmatimo - 1); 2701 GET_SBIC_asr(dev->sc_sbicp, asr); 2702 if( asr & SBIC_ASR_INT ) { 2703 /* We need to service a missed IRQ */ 2704 printf("Servicing a missed int:(%02x,%02x)->(%02x,??)\n", 2705 debug_asr, debug_csr, asr); 2706 sbicintr(dev); 2707 } 2708 sbicdumpstate(); 2709 } 2710 dev->sc_dmatimo++; 2711 } 2712 splx(s); 2713 timeout((void *)sbictimeout, dev, 30 * hz); 2714 } 2715 2716 void 2717 sbic_dump_acb(acb) 2718 struct sbic_acb *acb; 2719 { 2720 u_char *b = (u_char *) &acb->cmd; 2721 int i; 2722 2723 printf("acb@%p ", acb); 2724 if (acb->xs == NULL) { 2725 printf("<unused>\n"); 2726 return; 2727 } 2728 printf("(%d:%d) flags %2x clen %2d cmd ", 2729 acb->xs->sc_link->scsipi_scsi.target, 2730 acb->xs->sc_link->scsipi_scsi.lun, acb->flags, acb->clen); 2731 for (i = acb->clen; i; --i) 2732 printf(" %02x", *b++); 2733 printf("\n"); 2734 printf(" xs: %8p data %8p:%04x ", acb->xs, acb->xs->data, 2735 acb->xs->datalen); 2736 printf("va %8p:%04x ", acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 2737 printf("pa %8p:%04x tcnt %lx\n", acb->sc_pa.dc_addr, acb->sc_pa.dc_count, 2738 acb->sc_tcnt); 2739 } 2740 2741 void 2742 sbic_dump(dev) 2743 struct sbic_softc *dev; 2744 { 2745 sbic_regmap_p regs; 2746 u_char csr, asr; 2747 struct sbic_acb *acb; 2748 int s; 2749 int i; 2750 2751 s = splbio(); 2752 regs = dev->sc_sbicp; 2753 #if CSR_TRACE_SIZE 2754 printf("csr trace: "); 2755 i = csr_traceptr; 2756 do { 2757 printf("%c%02x%02x%02x ", csr_trace[i].whr, 2758 csr_trace[i].csr, csr_trace[i].asr, csr_trace[i].xtn); 2759 switch(csr_trace[i].whr) { 2760 case 'g': 2761 printf("go "); break; 2762 case 's': 2763 printf("select "); break; 2764 case 'y': 2765 printf("select+ "); break; 2766 case 'i': 2767 printf("intr "); break; 2768 case 'f': 2769 printf("finish "); break; 2770 case '>': 2771 printf("out "); break; 2772 case '<': 2773 printf("in "); break; 2774 case 'm': 2775 printf("msgin "); break; 2776 case 'x': 2777 printf("msginx "); break; 2778 case 'X': 2779 printf("msginX "); break; 2780 case 'r': 2781 printf("reselect "); break; 2782 case 'I': 2783 printf("icmd "); break; 2784 case 'a': 2785 printf("abort "); break; 2786 default: 2787 printf("? "); 2788 } 2789 switch(csr_trace[i].csr) { 2790 case 0x11: 2791 printf("INITIATOR"); break; 2792 case 0x16: 2793 printf("S_XFERRED"); break; 2794 case 0x20: 2795 printf("MSGIN_ACK"); break; 2796 case 0x41: 2797 printf("DISC"); break; 2798 case 0x42: 2799 printf("SEL_TIMEO"); break; 2800 case 0x80: 2801 printf("RSLT_NI"); break; 2802 case 0x81: 2803 printf("RSLT_IFY"); break; 2804 case 0x85: 2805 printf("DISC_1"); break; 2806 case 0x18: case 0x19: case 0x1a: 2807 case 0x1b: case 0x1e: case 0x1f: 2808 case 0x28: case 0x29: case 0x2a: 2809 case 0x2b: case 0x2e: case 0x2f: 2810 case 0x48: case 0x49: case 0x4a: 2811 case 0x4b: case 0x4e: case 0x4f: 2812 case 0x88: case 0x89: case 0x8a: 2813 case 0x8b: case 0x8e: case 0x8f: 2814 switch(csr_trace[i].csr & 0xf0) { 2815 case 0x10: 2816 printf("DONE_"); break; 2817 case 0x20: 2818 printf("STOP_"); break; 2819 case 0x40: 2820 printf("ERR_"); break; 2821 case 0x80: 2822 printf("REQ_"); break; 2823 } 2824 switch(csr_trace[i].csr & 7) { 2825 case 0: 2826 printf("DATA_OUT"); break; 2827 case 1: 2828 printf("DATA_IN"); break; 2829 case 2: 2830 printf("CMD"); break; 2831 case 3: 2832 printf("STATUS"); break; 2833 case 6: 2834 printf("MSG_OUT"); break; 2835 case 7: 2836 printf("MSG_IN"); break; 2837 default: 2838 printf("invld phs"); 2839 } 2840 break; 2841 default: printf("****"); break; 2842 } 2843 if (csr_trace[i].asr & SBIC_ASR_INT) 2844 printf(" ASR_INT"); 2845 if (csr_trace[i].asr & SBIC_ASR_LCI) 2846 printf(" ASR_LCI"); 2847 if (csr_trace[i].asr & SBIC_ASR_BSY) 2848 printf(" ASR_BSY"); 2849 if (csr_trace[i].asr & SBIC_ASR_CIP) 2850 printf(" ASR_CIP"); 2851 printf("\n"); 2852 i = (i + 1) & (CSR_TRACE_SIZE - 1); 2853 } while (i != csr_traceptr); 2854 #endif 2855 GET_SBIC_asr(regs, asr); 2856 if ((asr & SBIC_ASR_INT) == 0) 2857 GET_SBIC_csr(regs, csr); 2858 else 2859 csr = 0; 2860 printf("%s@%p regs %p asr %x csr %x\n", dev->sc_dev.dv_xname, 2861 dev, regs, asr, csr); 2862 if ((acb = dev->free_list.tqh_first)) { 2863 printf("Free list:\n"); 2864 while (acb) { 2865 sbic_dump_acb(acb); 2866 acb = acb->chain.tqe_next; 2867 } 2868 } 2869 if ((acb = dev->ready_list.tqh_first)) { 2870 printf("Ready list:\n"); 2871 while (acb) { 2872 sbic_dump_acb(acb); 2873 acb = acb->chain.tqe_next; 2874 } 2875 } 2876 if ((acb = dev->nexus_list.tqh_first)) { 2877 printf("Nexus list:\n"); 2878 while (acb) { 2879 sbic_dump_acb(acb); 2880 acb = acb->chain.tqe_next; 2881 } 2882 } 2883 if (dev->sc_nexus) { 2884 printf("nexus:\n"); 2885 sbic_dump_acb(dev->sc_nexus); 2886 } 2887 printf("sc_xs %p targ %d lun %d flags %x tcnt %lx dmacmd %x mask %lx\n", 2888 dev->sc_xs, dev->target, dev->lun, dev->sc_flags, dev->sc_tcnt, 2889 dev->sc_dmacmd, dev->sc_dmamask); 2890 for (i = 0; i < 8; ++i) { 2891 if (dev->sc_tinfo[i].cmds > 2) { 2892 printf("tgt %d: cmds %d disc %d senses %d lubusy %x\n", 2893 i, dev->sc_tinfo[i].cmds, 2894 dev->sc_tinfo[i].dconns, 2895 dev->sc_tinfo[i].senses, 2896 dev->sc_tinfo[i].lubusy); 2897 } 2898 } 2899 splx(s); 2900 } 2901 2902 #endif 2903
Indexes created Thu Oct 02 14:10:14 GMT 2025