sbic.c revision 1.40
1 /* $NetBSD: sbic.c,v 1.40 2000/06/26 14:20:30 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 1994 Christian E. Hopps 5 * Copyright (c) 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * Van Jacobson of Lawrence Berkeley Laboratory. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the University of 22 * California, Berkeley and its contributors. 23 * 4. Neither the name of the University nor the names of its contributors 24 * may be used to endorse or promote products derived from this software 25 * without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 37 * SUCH DAMAGE. 38 * 39 * @(#)scsi.c 7.5 (Berkeley) 5/4/91 40 */ 41 42 /* 43 * AMIGA AMD 33C93 scsi adaptor driver 44 */ 45 46 #include "opt_ddb.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/device.h> 51 #include <sys/kernel.h> /* For hz */ 52 #include <sys/disklabel.h> 53 #include <sys/dkstat.h> 54 #include <sys/buf.h> 55 #include <dev/scsipi/scsi_all.h> 56 #include <dev/scsipi/scsipi_all.h> 57 #include <dev/scsipi/scsiconf.h> 58 #include <vm/vm.h> 59 #include <uvm/uvm_extern.h> 60 #include <machine/pmap.h> 61 #include <machine/cpu.h> 62 #include <amiga/amiga/device.h> 63 #include <amiga/amiga/custom.h> 64 #include <amiga/amiga/isr.h> 65 #include <amiga/dev/dmavar.h> 66 #include <amiga/dev/sbicreg.h> 67 #include <amiga/dev/sbicvar.h> 68 69 /* These are for bounce buffers */ 70 #include <amiga/amiga/cc.h> 71 #include <amiga/dev/zbusvar.h> 72 73 #include <vm/pmap.h> 74 75 /* Since I can't find this in any other header files */ 76 #define SCSI_PHASE(reg) (reg&0x07) 77 78 /* 79 * SCSI delays 80 * In u-seconds, primarily for state changes on the SPC. 81 */ 82 #define SBIC_CMD_WAIT 50000 /* wait per step of 'immediate' cmds */ 83 #define SBIC_DATA_WAIT 50000 /* wait per data in/out step */ 84 #define SBIC_INIT_WAIT 50000 /* wait per step (both) during init */ 85 86 #define SBIC_WAIT(regs, until, timeo) sbicwait(regs, until, timeo, __LINE__) 87 88 int sbicicmd __P((struct sbic_softc *, int, int, void *, int, void *, int)); 89 int sbicgo __P((struct sbic_softc *, struct scsipi_xfer *)); 90 int sbicdmaok __P((struct sbic_softc *, struct scsipi_xfer *)); 91 int sbicwait __P((sbic_regmap_t, char, int , int)); 92 int sbiccheckdmap __P((void *, u_long, u_long)); 93 int sbicselectbus __P((struct sbic_softc *, sbic_regmap_t, u_char, u_char, u_char)); 94 int sbicxfstart __P((sbic_regmap_t, int, u_char, int)); 95 int sbicxfout __P((sbic_regmap_t regs, int, void *, int)); 96 int sbicfromscsiperiod __P((struct sbic_softc *, sbic_regmap_t, int)); 97 int sbictoscsiperiod __P((struct sbic_softc *, sbic_regmap_t, int)); 98 int sbicpoll __P((struct sbic_softc *)); 99 int sbicnextstate __P((struct sbic_softc *, u_char, u_char)); 100 int sbicmsgin __P((struct sbic_softc *)); 101 int sbicxfin __P((sbic_regmap_t regs, int, void *)); 102 int sbicabort __P((struct sbic_softc *, sbic_regmap_t, char *)); 103 void sbicxfdone __P((struct sbic_softc *, sbic_regmap_t, int)); 104 void sbicerror __P((struct sbic_softc *, sbic_regmap_t, u_char)); 105 void sbicstart __P((struct sbic_softc *)); 106 void sbicreset __P((struct sbic_softc *)); 107 void sbic_scsidone __P((struct sbic_acb *, int)); 108 void sbic_sched __P((struct sbic_softc *)); 109 void sbic_save_ptrs __P((struct sbic_softc *, sbic_regmap_t,int,int)); 110 void sbic_load_ptrs __P((struct sbic_softc *, sbic_regmap_t,int,int)); 111 #ifdef DEBUG 112 void sbicdumpstate __P((void)); 113 void sbic_dump_acb __P((struct sbic_acb *)); 114 #endif 115 116 /* 117 * Synch xfer parameters, and timing conversions 118 */ 119 int sbic_min_period = SBIC_SYN_MIN_PERIOD; /* in cycles = f(ICLK,FSn) */ 120 int sbic_max_offset = SBIC_SYN_MAX_OFFSET; /* pure number */ 121 122 int sbic_cmd_wait = SBIC_CMD_WAIT; 123 int sbic_data_wait = SBIC_DATA_WAIT; 124 int sbic_init_wait = SBIC_INIT_WAIT; 125 126 /* 127 * was broken before.. now if you want this you get it for all drives 128 * on sbic controllers. 129 */ 130 u_char sbic_inhibit_sync[8]; 131 int sbic_enable_reselect = 1; 132 int sbic_clock_override = 0; 133 int sbic_no_dma = 0; 134 int sbic_parallel_operations = 1; 135 136 #ifdef DEBUG 137 sbic_regmap_t debug_sbic_regs; 138 int sbicdma_ops = 0; /* total DMA operations */ 139 int sbicdma_bounces = 0; /* number operations using bounce buffer */ 140 int sbicdma_hits = 0; /* number of DMA chains that were contiguous */ 141 int sbicdma_misses = 0; /* number of DMA chains that were not contiguous */ 142 int sbicdma_saves = 0; 143 #define QPRINTF(a) if (sbic_debug > 1) printf a 144 int sbic_debug = 0; 145 int sync_debug = 0; 146 int sbic_dma_debug = 0; 147 int reselect_debug = 0; 148 int report_sense = 0; 149 int data_pointer_debug = 0; 150 u_char debug_asr, debug_csr, routine; 151 void sbictimeout __P((struct sbic_softc *dev)); 152 153 #define CSR_TRACE_SIZE 32 154 #if CSR_TRACE_SIZE 155 #define CSR_TRACE(w,c,a,x) do { \ 156 int s = splbio(); \ 157 csr_trace[csr_traceptr].whr = (w); csr_trace[csr_traceptr].csr = (c); \ 158 csr_trace[csr_traceptr].asr = (a); csr_trace[csr_traceptr].xtn = (x); \ 159 dma_cachectl((caddr_t)&csr_trace[csr_traceptr], sizeof(csr_trace[0])); \ 160 csr_traceptr = (csr_traceptr + 1) & (CSR_TRACE_SIZE - 1); \ 161 /* dma_cachectl((caddr_t)&csr_traceptr, sizeof(csr_traceptr));*/ \ 162 splx(s); \ 163 } while (0) 164 int csr_traceptr; 165 int csr_tracesize = CSR_TRACE_SIZE; 166 struct { 167 u_char whr; 168 u_char csr; 169 u_char asr; 170 u_char xtn; 171 } csr_trace[CSR_TRACE_SIZE]; 172 #else 173 #define CSR_TRACE(w,c,a,x) 174 #endif 175 176 #define SBIC_TRACE_SIZE 0 177 #if SBIC_TRACE_SIZE 178 #define SBIC_TRACE(dev) do { \ 179 int s = splbio(); \ 180 sbic_trace[sbic_traceptr].sp = &s; \ 181 sbic_trace[sbic_traceptr].line = __LINE__; \ 182 sbic_trace[sbic_traceptr].sr = s; \ 183 sbic_trace[sbic_traceptr].csr = csr_traceptr; \ 184 dma_cachectl(&sbic_trace[sbic_traceptr], sizeof(sbic_trace[0])); \ 185 sbic_traceptr = (sbic_traceptr + 1) & (SBIC_TRACE_SIZE - 1); \ 186 dma_cachectl(&sbic_traceptr, sizeof(sbic_traceptr)); \ 187 if (dev) dma_cachectl(dev, sizeof(*dev)); \ 188 splx(s); \ 189 } while (0) 190 int sbic_traceptr; 191 int sbic_tracesize = SBIC_TRACE_SIZE; 192 struct { 193 void *sp; 194 u_short line; 195 u_short sr; 196 int csr; 197 } sbic_trace[SBIC_TRACE_SIZE]; 198 #else 199 #define SBIC_TRACE(dev) 200 #endif 201 202 #else /* DEBUG */ 203 #define QPRINTF(a) 204 #define CSR_TRACE(w,c,a,x) 205 #define SBIC_TRACE(dev) 206 #endif /* DEBUG */ 207 208 /* 209 * default minphys routine for sbic based controllers 210 */ 211 void 212 sbic_minphys(bp) 213 struct buf *bp; 214 { 215 216 /* 217 * No max transfer at this level. 218 */ 219 minphys(bp); 220 } 221 222 /* 223 * Save DMA pointers. Take into account partial transfer. Shut down DMA. 224 */ 225 void 226 sbic_save_ptrs(dev, regs, target, lun) 227 struct sbic_softc *dev; 228 sbic_regmap_t regs; 229 int target, lun; 230 { 231 int count, asr, s; 232 struct sbic_acb* acb; 233 234 SBIC_TRACE(dev); 235 if( !dev->sc_cur ) return; 236 if( !(dev->sc_flags & SBICF_INDMA) ) return; /* DMA not active */ 237 238 s = splbio(); 239 240 acb = dev->sc_nexus; 241 count = -1; 242 do { 243 GET_SBIC_asr(regs, asr); 244 if( asr & SBIC_ASR_DBR ) { 245 printf("sbic_save_ptrs: asr %02x canceled!\n", asr); 246 splx(s); 247 SBIC_TRACE(dev); 248 return; 249 } 250 } while( asr & (SBIC_ASR_BSY|SBIC_ASR_CIP) ); 251 252 /* Save important state */ 253 /* must be done before dmastop */ 254 acb->sc_dmacmd = dev->sc_dmacmd; 255 SBIC_TC_GET(regs, count); 256 257 /* Shut down DMA ====CAREFUL==== */ 258 dev->sc_dmastop(dev); 259 dev->sc_flags &= ~SBICF_INDMA; 260 SBIC_TC_PUT(regs, 0); 261 262 #ifdef DEBUG 263 if(!count && sbic_debug) printf("%dcount0",target); 264 if(data_pointer_debug == -1) 265 printf("SBIC saving target %d data pointers from (%p,%x)%xASR:%02x", 266 target, dev->sc_cur->dc_addr, dev->sc_cur->dc_count, 267 acb->sc_dmacmd, asr); 268 #endif 269 270 /* Fixup partial xfers */ 271 acb->sc_kv.dc_addr += (dev->sc_tcnt - count); 272 acb->sc_kv.dc_count -= (dev->sc_tcnt - count); 273 acb->sc_pa.dc_addr += (dev->sc_tcnt - count); 274 acb->sc_pa.dc_count -= ((dev->sc_tcnt - count)>>1); 275 276 acb->sc_tcnt = dev->sc_tcnt = count; 277 #ifdef DEBUG 278 if(data_pointer_debug) 279 printf(" at (%p,%x):%x\n", 280 dev->sc_cur->dc_addr, dev->sc_cur->dc_count,count); 281 sbicdma_saves++; 282 #endif 283 splx(s); 284 SBIC_TRACE(dev); 285 } 286 287 288 /* 289 * DOES NOT RESTART DMA!!! 290 */ 291 void sbic_load_ptrs(dev, regs, target, lun) 292 struct sbic_softc *dev; 293 sbic_regmap_t regs; 294 int target, lun; 295 { 296 int s, count; 297 char* vaddr, * paddr; 298 struct sbic_acb *acb; 299 300 SBIC_TRACE(dev); 301 acb = dev->sc_nexus; 302 if( !acb->sc_kv.dc_count ) { 303 /* No data to xfer */ 304 SBIC_TRACE(dev); 305 return; 306 } 307 308 s = splbio(); 309 310 dev->sc_last = dev->sc_cur = &acb->sc_pa; 311 dev->sc_tcnt = acb->sc_tcnt; 312 dev->sc_dmacmd = acb->sc_dmacmd; 313 314 #ifdef DEBUG 315 sbicdma_ops++; 316 #endif 317 if( !dev->sc_tcnt ) { 318 /* sc_tcnt == 0 implies end of segment */ 319 320 /* do kvm to pa mappings */ 321 paddr = acb->sc_pa.dc_addr = 322 (char *) kvtop(acb->sc_kv.dc_addr); 323 324 vaddr = acb->sc_kv.dc_addr; 325 count = acb->sc_kv.dc_count; 326 for(count = (NBPG - ((int)vaddr & PGOFSET)); 327 count < acb->sc_kv.dc_count 328 && (char*)kvtop(vaddr + count + 4) == paddr + count + 4; 329 count += NBPG); 330 /* If it's all contiguous... */ 331 if(count > acb->sc_kv.dc_count ) { 332 count = acb->sc_kv.dc_count; 333 #ifdef DEBUG 334 sbicdma_hits++; 335 #endif 336 } else { 337 #ifdef DEBUG 338 sbicdma_misses++; 339 #endif 340 } 341 acb->sc_tcnt = count; 342 acb->sc_pa.dc_count = count >> 1; 343 344 #ifdef DEBUG 345 if(data_pointer_debug) 346 printf("DMA recalc:kv(%p,%x)pa(%p,%lx)\n", 347 acb->sc_kv.dc_addr, 348 acb->sc_kv.dc_count, 349 acb->sc_pa.dc_addr, 350 acb->sc_tcnt); 351 #endif 352 } 353 splx(s); 354 #ifdef DEBUG 355 if(data_pointer_debug) 356 printf("SBIC restoring target %d data pointers at (%p,%x)%x\n", 357 target, dev->sc_cur->dc_addr, dev->sc_cur->dc_count, 358 dev->sc_dmacmd); 359 #endif 360 SBIC_TRACE(dev); 361 } 362 363 /* 364 * used by specific sbic controller 365 * 366 * it appears that the higher level code does nothing with LUN's 367 * so I will too. I could plug it in, however so could they 368 * in scsi_scsipi_cmd(). 369 */ 370 int 371 sbic_scsicmd(xs) 372 struct scsipi_xfer *xs; 373 { 374 struct sbic_acb *acb; 375 struct sbic_softc *dev; 376 struct scsipi_link *slp; 377 int flags, s, stat; 378 379 slp = xs->sc_link; 380 dev = slp->adapter_softc; 381 SBIC_TRACE(dev); 382 flags = xs->xs_control; 383 384 if (flags & XS_CTL_DATA_UIO) 385 panic("sbic: scsi data uio requested"); 386 387 if (dev->sc_nexus && flags & XS_CTL_POLL) 388 panic("sbic_scsicmd: busy"); 389 390 if (slp->scsipi_scsi.target == slp->scsipi_scsi.adapter_target) 391 return ESCAPE_NOT_SUPPORTED; 392 393 s = splbio(); 394 acb = dev->free_list.tqh_first; 395 if (acb) 396 TAILQ_REMOVE(&dev->free_list, acb, chain); 397 splx(s); 398 399 if (acb == NULL) { 400 #ifdef DEBUG 401 printf("sbic_scsicmd: unable to queue request for target %d\n", 402 slp->scsipi_scsi.target); 403 #ifdef DDB 404 Debugger(); 405 #endif 406 #endif 407 xs->error = XS_DRIVER_STUFFUP; 408 SBIC_TRACE(dev); 409 return(TRY_AGAIN_LATER); 410 } 411 412 acb->flags = ACB_ACTIVE; 413 if (flags & XS_CTL_DATA_IN) 414 acb->flags |= ACB_DATAIN; 415 acb->xs = xs; 416 bcopy(xs->cmd, &acb->cmd, xs->cmdlen); 417 acb->clen = xs->cmdlen; 418 acb->sc_kv.dc_addr = xs->data; 419 acb->sc_kv.dc_count = xs->datalen; 420 acb->pa_addr = xs->data ? (char *)kvtop(xs->data) : 0; /* XXXX check */ 421 422 if (flags & XS_CTL_POLL) { 423 s = splbio(); 424 /* 425 * This has major side effects -- it locks up the machine 426 */ 427 428 dev->sc_flags |= SBICF_ICMD; 429 do { 430 while(dev->sc_nexus) 431 sbicpoll(dev); 432 dev->sc_nexus = acb; 433 dev->sc_stat[0] = -1; 434 dev->sc_xs = xs; 435 dev->target = slp->scsipi_scsi.target; 436 dev->lun = slp->scsipi_scsi.lun; 437 stat = sbicicmd(dev, slp->scsipi_scsi.target, slp->scsipi_scsi.lun, 438 &acb->cmd, acb->clen, 439 acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 440 } while (dev->sc_nexus != acb); 441 sbic_scsidone(acb, stat); 442 443 splx(s); 444 SBIC_TRACE(dev); 445 return(COMPLETE); 446 } 447 448 s = splbio(); 449 TAILQ_INSERT_TAIL(&dev->ready_list, acb, chain); 450 451 if (dev->sc_nexus) { 452 splx(s); 453 SBIC_TRACE(dev); 454 return(SUCCESSFULLY_QUEUED); 455 } 456 457 /* 458 * nothing is active, try to start it now. 459 */ 460 sbic_sched(dev); 461 splx(s); 462 463 SBIC_TRACE(dev); 464 /* TODO: add sbic_poll to do XS_CTL_POLL operations */ 465 #if 0 466 if (flags & XS_CTL_POLL) 467 return(COMPLETE); 468 #endif 469 return(SUCCESSFULLY_QUEUED); 470 } 471 472 /* 473 * attempt to start the next available command 474 */ 475 void 476 sbic_sched(dev) 477 struct sbic_softc *dev; 478 { 479 struct scsipi_xfer *xs; 480 struct scsipi_link *slp; 481 struct sbic_acb *acb; 482 int flags, /*phase,*/ stat, i; 483 484 SBIC_TRACE(dev); 485 if (dev->sc_nexus) 486 return; /* a command is current active */ 487 488 SBIC_TRACE(dev); 489 for (acb = dev->ready_list.tqh_first; acb; acb = acb->chain.tqe_next) { 490 slp = acb->xs->sc_link; 491 i = slp->scsipi_scsi.target; 492 if (!(dev->sc_tinfo[i].lubusy & (1 << slp->scsipi_scsi.lun))) { 493 struct sbic_tinfo *ti = &dev->sc_tinfo[i]; 494 495 TAILQ_REMOVE(&dev->ready_list, acb, chain); 496 dev->sc_nexus = acb; 497 slp = acb->xs->sc_link; 498 ti = &dev->sc_tinfo[slp->scsipi_scsi.target]; 499 ti->lubusy |= (1 << slp->scsipi_scsi.lun); 500 acb->sc_pa.dc_addr = acb->pa_addr; /* XXXX check */ 501 break; 502 } 503 } 504 505 SBIC_TRACE(dev); 506 if (acb == NULL) 507 return; /* did not find an available command */ 508 509 dev->sc_xs = xs = acb->xs; 510 slp = xs->sc_link; 511 flags = xs->xs_control; 512 513 if (flags & XS_CTL_RESET) 514 sbicreset(dev); 515 516 #ifdef DEBUG 517 if( data_pointer_debug > 1 ) 518 printf("sbic_sched(%d,%d)\n",slp->scsipi_scsi.target, 519 slp->scsipi_scsi.lun); 520 #endif 521 dev->sc_stat[0] = -1; 522 dev->target = slp->scsipi_scsi.target; 523 dev->lun = slp->scsipi_scsi.lun; 524 if ( flags & XS_CTL_POLL || ( !sbic_parallel_operations 525 && (sbicdmaok(dev, xs) == 0))) 526 stat = sbicicmd(dev, slp->scsipi_scsi.target, 527 slp->scsipi_scsi.lun, &acb->cmd, 528 acb->clen, acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 529 else if (sbicgo(dev, xs) == 0 && xs->error != XS_SELTIMEOUT) { 530 SBIC_TRACE(dev); 531 return; 532 } else 533 stat = dev->sc_stat[0]; 534 535 sbic_scsidone(acb, stat); 536 SBIC_TRACE(dev); 537 } 538 539 void 540 sbic_scsidone(acb, stat) 541 struct sbic_acb *acb; 542 int stat; 543 { 544 struct scsipi_xfer *xs; 545 struct scsipi_link *slp; 546 struct sbic_softc *dev; 547 int dosched = 0; 548 549 xs = acb->xs; 550 slp = xs->sc_link; 551 dev = slp->adapter_softc; 552 SBIC_TRACE(dev); 553 #ifdef DIAGNOSTIC 554 if (acb == NULL || xs == NULL) { 555 printf("sbic_scsidone -- (%d,%d) no scsi_xfer\n", 556 dev->target, dev->lun); 557 #ifdef DDB 558 Debugger(); 559 #endif 560 return; 561 } 562 #endif 563 /* 564 * is this right? 565 */ 566 xs->status = stat; 567 568 #ifdef DEBUG 569 if( data_pointer_debug > 1 ) 570 printf("scsidone: (%d,%d)->(%d,%d)%02x\n", 571 slp->scsipi_scsi.target, slp->scsipi_scsi.lun, 572 dev->target, dev->lun, stat); 573 if( xs->sc_link->scsipi_scsi.target == 574 dev->sc_link.scsipi_scsi.adapter_target ) 575 panic("target == hostid"); 576 #endif 577 578 if (xs->error == XS_NOERROR && !(acb->flags & ACB_CHKSENSE)) { 579 if (stat == SCSI_CHECK) { 580 /* Schedule a REQUEST SENSE */ 581 struct scsipi_sense *ss = (void *)&acb->cmd; 582 #ifdef DEBUG 583 if (report_sense) 584 printf("sbic_scsidone: autosense %02x targ %d lun %d", 585 acb->cmd.opcode, slp->scsipi_scsi.target, 586 slp->scsipi_scsi.lun); 587 #endif 588 bzero(ss, sizeof(*ss)); 589 ss->opcode = REQUEST_SENSE; 590 ss->byte2 = slp->scsipi_scsi.lun << 5; 591 ss->length = sizeof(struct scsipi_sense_data); 592 acb->clen = sizeof(*ss); 593 acb->sc_kv.dc_addr = (char *)&xs->sense.scsi_sense; 594 acb->sc_kv.dc_count = sizeof(struct scsipi_sense_data); 595 acb->pa_addr = (char *)kvtop((u_char *)&xs->sense.scsi_sense); /* XXX check */ 596 acb->flags = ACB_ACTIVE | ACB_CHKSENSE | ACB_DATAIN; 597 TAILQ_INSERT_HEAD(&dev->ready_list, acb, chain); 598 dev->sc_tinfo[slp->scsipi_scsi.target].lubusy &= 599 ~(1 << slp->scsipi_scsi.lun); 600 dev->sc_tinfo[slp->scsipi_scsi.target].senses++; 601 if (dev->sc_nexus == acb) { 602 dev->sc_nexus = NULL; 603 dev->sc_xs = NULL; 604 sbic_sched(dev); 605 } 606 SBIC_TRACE(dev); 607 return; 608 } 609 } 610 if (xs->error == XS_NOERROR && (acb->flags & ACB_CHKSENSE)) { 611 xs->error = XS_SENSE; 612 #ifdef DEBUG 613 if (report_sense) 614 printf(" => %02x %02x\n", xs->sense.scsi_sense.flags, 615 xs->sense.scsi_sense.extra_bytes[3]); 616 #endif 617 } else { 618 xs->resid = 0; /* XXXX */ 619 } 620 #if whataboutthisone 621 case SCSI_BUSY: 622 xs->error = XS_BUSY; 623 break; 624 #endif 625 xs->xs_status |= XS_STS_DONE; 626 627 /* 628 * Remove the ACB from whatever queue it's on. We have to do a bit of 629 * a hack to figure out which queue it's on. Note that it is *not* 630 * necessary to cdr down the ready queue, but we must cdr down the 631 * nexus queue and see if it's there, so we can mark the unit as no 632 * longer busy. This code is sickening, but it works. 633 */ 634 if (acb == dev->sc_nexus) { 635 dev->sc_nexus = NULL; 636 dev->sc_xs = NULL; 637 dev->sc_tinfo[slp->scsipi_scsi.target].lubusy &= 638 ~(1<<slp->scsipi_scsi.lun); 639 if (dev->ready_list.tqh_first) 640 dosched = 1; /* start next command */ 641 } else if (dev->ready_list.tqh_last == &acb->chain.tqe_next) { 642 TAILQ_REMOVE(&dev->ready_list, acb, chain); 643 } else { 644 register struct sbic_acb *acb2; 645 for (acb2 = dev->nexus_list.tqh_first; acb2; 646 acb2 = acb2->chain.tqe_next) { 647 if (acb2 == acb) { 648 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 649 dev->sc_tinfo[slp->scsipi_scsi.target].lubusy 650 &= ~(1<<slp->scsipi_scsi.lun); 651 break; 652 } 653 } 654 if (acb2) 655 ; 656 else if (acb->chain.tqe_next) { 657 TAILQ_REMOVE(&dev->ready_list, acb, chain); 658 } else { 659 printf("%s: can't find matching acb\n", 660 dev->sc_dev.dv_xname); 661 #ifdef DDB 662 Debugger(); 663 #endif 664 } 665 } 666 /* Put it on the free list. */ 667 acb->flags = ACB_FREE; 668 TAILQ_INSERT_HEAD(&dev->free_list, acb, chain); 669 670 dev->sc_tinfo[slp->scsipi_scsi.target].cmds++; 671 672 scsipi_done(xs); 673 674 if (dosched) 675 sbic_sched(dev); 676 SBIC_TRACE(dev); 677 } 678 679 int 680 sbicdmaok(dev, xs) 681 struct sbic_softc *dev; 682 struct scsipi_xfer *xs; 683 { 684 if (sbic_no_dma || !xs->datalen || xs->datalen & 0x1 || 685 (u_int)xs->data & 0x3) 686 return(0); 687 /* 688 * controller supports dma to any addresses? 689 */ 690 else if ((dev->sc_flags & SBICF_BADDMA) == 0) 691 return(1); 692 /* 693 * this address is ok for dma? 694 */ 695 else if (sbiccheckdmap(xs->data, xs->datalen, dev->sc_dmamask) == 0) 696 return(1); 697 /* 698 * we have a bounce buffer? 699 */ 700 else if (dev->sc_tinfo[xs->sc_link->scsipi_scsi.target].bounce) 701 return(1); 702 /* 703 * try to get one 704 */ 705 else if ((dev->sc_tinfo[xs->sc_link->scsipi_scsi.target].bounce 706 = (char *)alloc_z2mem(MAXPHYS))) { 707 if (isztwomem(dev->sc_tinfo[xs->sc_link->scsipi_scsi.target].bounce)) 708 printf("alloc ZII target %d bounce pa 0x%x\n", 709 xs->sc_link->scsipi_scsi.target, 710 kvtop(dev->sc_tinfo[xs->sc_link->scsipi_scsi.target].bounce)); 711 else if (dev->sc_tinfo[xs->sc_link->scsipi_scsi.target].bounce) 712 printf("alloc CHIP target %d bounce pa 0x%p\n", 713 xs->sc_link->scsipi_scsi.target, 714 PREP_DMA_MEM(dev->sc_tinfo[xs->sc_link->scsipi_scsi.target].bounce)); 715 return(1); 716 } 717 718 return(0); 719 } 720 721 722 int 723 sbicwait(regs, until, timeo, line) 724 sbic_regmap_t regs; 725 char until; 726 int timeo; 727 int line; 728 { 729 u_char val; 730 int csr; 731 732 SBIC_TRACE((struct sbic_softc *)0); 733 if (timeo == 0) 734 timeo = 1000000; /* some large value.. */ 735 736 GET_SBIC_asr(regs,val); 737 while ((val & until) == 0) { 738 if (timeo-- == 0) { 739 GET_SBIC_csr(regs, csr); 740 printf("sbicwait TIMEO @%d with asr=x%x csr=x%x\n", 741 line, val, csr); 742 #if defined(DDB) && defined(DEBUG) 743 Debugger(); 744 #endif 745 return(val); /* Maybe I should abort */ 746 break; 747 } 748 DELAY(1); 749 GET_SBIC_asr(regs,val); 750 } 751 SBIC_TRACE((struct sbic_softc *)0); 752 return(val); 753 } 754 755 int 756 sbicabort(dev, regs, where) 757 struct sbic_softc *dev; 758 sbic_regmap_t regs; 759 char *where; 760 { 761 u_char csr, asr; 762 763 GET_SBIC_asr(regs, asr); 764 GET_SBIC_csr(regs, csr); 765 766 printf ("%s: abort %s: csr = 0x%02x, asr = 0x%02x\n", 767 dev->sc_dev.dv_xname, where, csr, asr); 768 769 770 #if 0 771 /* Clean up running command */ 772 if (dev->sc_nexus != NULL) { 773 dev->sc_nexus->xs->error = XS_DRIVER_STUFFUP; 774 sbic_scsidone(dev->sc_nexus, dev->sc_stat[0]); 775 } 776 while (acb = dev->nexus_list.tqh_first) { 777 acb->xs->error = XS_DRIVER_STUFFUP; 778 sbic_scsidone(acb, -1 /*acb->stat[0]*/); 779 } 780 #endif 781 782 /* Clean up chip itself */ 783 if (dev->sc_flags & SBICF_SELECTED) { 784 while( asr & SBIC_ASR_DBR ) { 785 /* sbic is jammed w/data. need to clear it */ 786 /* But we don't know what direction it needs to go */ 787 GET_SBIC_data(regs, asr); 788 printf("%s: abort %s: clearing data buffer 0x%02x\n", 789 dev->sc_dev.dv_xname, where, asr); 790 GET_SBIC_asr(regs, asr); 791 if( asr & SBIC_ASR_DBR ) /* Not the read direction, then */ 792 SET_SBIC_data(regs, asr); 793 GET_SBIC_asr(regs, asr); 794 } 795 WAIT_CIP(regs); 796 printf("%s: sbicabort - sending ABORT command\n", dev->sc_dev.dv_xname); 797 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 798 WAIT_CIP(regs); 799 800 GET_SBIC_asr(regs, asr); 801 if (asr & (SBIC_ASR_BSY|SBIC_ASR_LCI)) { 802 /* ok, get more drastic.. */ 803 804 printf("%s: sbicabort - asr %x, trying to reset\n", dev->sc_dev.dv_xname, asr); 805 sbicreset(dev); 806 dev->sc_flags &= ~SBICF_SELECTED; 807 return -1; 808 } 809 printf("%s: sbicabort - sending DISC command\n", dev->sc_dev.dv_xname); 810 SET_SBIC_cmd(regs, SBIC_CMD_DISC); 811 812 do { 813 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0); 814 GET_SBIC_csr (regs, csr); 815 CSR_TRACE('a',csr,asr,0); 816 } while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) 817 && (csr != SBIC_CSR_CMD_INVALID)); 818 819 /* lets just hope it worked.. */ 820 dev->sc_flags &= ~SBICF_SELECTED; 821 } 822 return -1; 823 } 824 825 826 /* 827 * Initialize driver-private structures 828 */ 829 830 void 831 sbicinit(dev) 832 struct sbic_softc *dev; 833 { 834 sbic_regmap_t regs; 835 u_int i; 836 struct sbic_acb *acb; 837 u_int inhibit_sync; 838 839 extern u_long scsi_nosync; 840 extern int shift_nosync; 841 842 regs = dev->sc_sbic; 843 844 if ((dev->sc_flags & SBICF_ALIVE) == 0) { 845 TAILQ_INIT(&dev->ready_list); 846 TAILQ_INIT(&dev->nexus_list); 847 TAILQ_INIT(&dev->free_list); 848 callout_init(&dev->sc_timo_ch); 849 dev->sc_nexus = NULL; 850 dev->sc_xs = NULL; 851 acb = dev->sc_acb; 852 bzero(acb, sizeof(dev->sc_acb)); 853 for (i = 0; i < sizeof(dev->sc_acb) / sizeof(*acb); i++) { 854 TAILQ_INSERT_TAIL(&dev->free_list, acb, chain); 855 acb++; 856 } 857 bzero(dev->sc_tinfo, sizeof(dev->sc_tinfo)); 858 #ifdef DEBUG 859 /* make sure timeout is really not needed */ 860 callout_reset(&dev->sc_timo_ch, 30 * hz, 861 (void *)sbictimeout, dev); 862 #endif 863 864 } else panic("sbic: reinitializing driver!"); 865 866 dev->sc_flags |= SBICF_ALIVE; 867 dev->sc_flags &= ~SBICF_SELECTED; 868 869 /* initialize inhibit array */ 870 if (scsi_nosync) { 871 inhibit_sync = (scsi_nosync >> shift_nosync) & 0xff; 872 shift_nosync += 8; 873 #ifdef DEBUG 874 if (inhibit_sync) 875 printf("%s: Inhibiting synchronous transfer %02x\n", 876 dev->sc_dev.dv_xname, inhibit_sync); 877 #endif 878 for (i = 0; i < 8; ++i) 879 if (inhibit_sync & (1 << i)) 880 sbic_inhibit_sync[i] = 1; 881 } 882 883 sbicreset(dev); 884 } 885 886 void 887 sbicreset(dev) 888 struct sbic_softc *dev; 889 { 890 sbic_regmap_t regs; 891 u_int my_id, s; 892 u_char csr; 893 #if 0 894 u_int i; 895 struct sbic_acb *acb; 896 #endif 897 898 regs = dev->sc_sbic; 899 #if 0 900 if (dev->sc_flags & SBICF_ALIVE) { 901 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 902 WAIT_CIP(regs); 903 } 904 #else 905 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 906 WAIT_CIP(regs); 907 #endif 908 s = splbio(); 909 my_id = dev->sc_link.scsipi_scsi.adapter_target & SBIC_ID_MASK; 910 911 /* Enable advanced mode */ 912 my_id |= SBIC_ID_EAF /*| SBIC_ID_EHP*/ ; 913 SET_SBIC_myid(regs, my_id); 914 915 /* 916 * Disable interrupts (in dmainit) then reset the chip 917 */ 918 SET_SBIC_cmd(regs, SBIC_CMD_RESET); 919 DELAY(25); 920 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 921 GET_SBIC_csr(regs, csr); /* clears interrupt also */ 922 923 if (dev->sc_clkfreq < 110) 924 my_id |= SBIC_ID_FS_8_10; 925 else if (dev->sc_clkfreq < 160) 926 my_id |= SBIC_ID_FS_12_15; 927 else if (dev->sc_clkfreq < 210) 928 my_id |= SBIC_ID_FS_16_20; 929 930 SET_SBIC_myid(regs, my_id); 931 932 /* 933 * Set up various chip parameters 934 */ 935 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI /* | SBIC_CTL_HSP */ 936 | SBIC_MACHINE_DMA_MODE); 937 /* 938 * don't allow (re)selection (SBIC_RID_ES) 939 * until we can handle target mode!! 940 */ 941 SET_SBIC_rselid(regs, SBIC_RID_ER); 942 SET_SBIC_syn(regs, 0); /* asynch for now */ 943 944 /* 945 * anything else was zeroed by reset 946 */ 947 splx(s); 948 949 #if 0 950 if ((dev->sc_flags & SBICF_ALIVE) == 0) { 951 TAILQ_INIT(&dev->ready_list); 952 TAILQ_INIT(&dev->nexus_list); 953 TAILQ_INIT(&dev->free_list); 954 dev->sc_nexus = NULL; 955 dev->sc_xs = NULL; 956 acb = dev->sc_acb; 957 bzero(acb, sizeof(dev->sc_acb)); 958 for (i = 0; i < sizeof(dev->sc_acb) / sizeof(*acb); i++) { 959 TAILQ_INSERT_TAIL(&dev->free_list, acb, chain); 960 acb++; 961 } 962 bzero(dev->sc_tinfo, sizeof(dev->sc_tinfo)); 963 } else { 964 if (dev->sc_nexus != NULL) { 965 dev->sc_nexus->xs->error = XS_DRIVER_STUFFUP; 966 sbic_scsidone(dev->sc_nexus, dev->sc_stat[0]); 967 } 968 while (acb = dev->nexus_list.tqh_first) { 969 acb->xs->error = XS_DRIVER_STUFFUP; 970 sbic_scsidone(acb, -1 /*acb->stat[0]*/); 971 } 972 } 973 974 dev->sc_flags |= SBICF_ALIVE; 975 #endif 976 dev->sc_flags &= ~SBICF_SELECTED; 977 } 978 979 void 980 sbicerror(dev, regs, csr) 981 struct sbic_softc *dev; 982 sbic_regmap_t regs; 983 u_char csr; 984 { 985 struct scsipi_xfer *xs; 986 987 xs = dev->sc_xs; 988 989 #ifdef DIAGNOSTIC 990 if (xs == NULL) 991 panic("sbicerror"); 992 #endif 993 if (xs->xs_control & XS_CTL_SILENT) 994 return; 995 996 printf("%s: ", dev->sc_dev.dv_xname); 997 printf("csr == 0x%02x\n", csr); /* XXX */ 998 } 999 1000 /* 1001 * select the bus, return when selected or error. 1002 */ 1003 int 1004 sbicselectbus(dev, regs, target, lun, our_addr) 1005 struct sbic_softc *dev; 1006 sbic_regmap_t regs; 1007 u_char target, lun, our_addr; 1008 { 1009 u_char asr, csr, id; 1010 1011 SBIC_TRACE(dev); 1012 QPRINTF(("sbicselectbus %d\n", target)); 1013 1014 /* 1015 * if we're already selected, return (XXXX panic maybe?) 1016 */ 1017 if (dev->sc_flags & SBICF_SELECTED) { 1018 SBIC_TRACE(dev); 1019 return(1); 1020 } 1021 1022 /* 1023 * issue select 1024 */ 1025 SBIC_TC_PUT(regs, 0); 1026 SET_SBIC_selid(regs, target); 1027 SET_SBIC_timeo(regs, SBIC_TIMEOUT(250,dev->sc_clkfreq)); 1028 1029 /* 1030 * set sync or async 1031 */ 1032 if (dev->sc_sync[target].state == SYNC_DONE) 1033 SET_SBIC_syn(regs, SBIC_SYN (dev->sc_sync[target].offset, 1034 dev->sc_sync[target].period)); 1035 else 1036 SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period)); 1037 1038 GET_SBIC_asr(regs, asr); 1039 if( asr & (SBIC_ASR_INT|SBIC_ASR_BSY) ) { 1040 /* This means we got ourselves reselected upon */ 1041 /* printf("sbicselectbus: INT/BSY asr %02x\n", asr);*/ 1042 #ifdef DDB 1043 /* Debugger();*/ 1044 #endif 1045 SBIC_TRACE(dev); 1046 return 1; 1047 } 1048 1049 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN); 1050 1051 /* 1052 * wait for select (merged from seperate function may need 1053 * cleanup) 1054 */ 1055 WAIT_CIP(regs); 1056 do { 1057 asr = SBIC_WAIT(regs, SBIC_ASR_INT | SBIC_ASR_LCI, 0); 1058 if (asr & SBIC_ASR_LCI) { 1059 #ifdef DEBUG 1060 if (reselect_debug) 1061 printf("sbicselectbus: late LCI asr %02x\n", asr); 1062 #endif 1063 SBIC_TRACE(dev); 1064 return 1; 1065 } 1066 GET_SBIC_csr (regs, csr); 1067 CSR_TRACE('s',csr,asr,target); 1068 QPRINTF(("%02x ", csr)); 1069 if( csr == SBIC_CSR_RSLT_NI || csr == SBIC_CSR_RSLT_IFY) { 1070 #ifdef DEBUG 1071 if(reselect_debug) 1072 printf("sbicselectbus: reselected asr %02x\n", asr); 1073 #endif 1074 /* We need to handle this now so we don't lock up later */ 1075 sbicnextstate(dev, csr, asr); 1076 SBIC_TRACE(dev); 1077 return 1; 1078 } 1079 if( csr == SBIC_CSR_SLT || csr == SBIC_CSR_SLT_ATN) { 1080 panic("sbicselectbus: target issued select!"); 1081 return 1; 1082 } 1083 } while (csr != (SBIC_CSR_MIS_2|MESG_OUT_PHASE) 1084 && csr != (SBIC_CSR_MIS_2|CMD_PHASE) && csr != SBIC_CSR_SEL_TIMEO); 1085 1086 /* Enable (or not) reselection */ 1087 if(!sbic_enable_reselect && dev->nexus_list.tqh_first == NULL) 1088 SET_SBIC_rselid (regs, 0); 1089 else 1090 SET_SBIC_rselid (regs, SBIC_RID_ER); 1091 1092 if (csr == (SBIC_CSR_MIS_2|CMD_PHASE)) { 1093 dev->sc_flags |= SBICF_SELECTED; /* device ignored ATN */ 1094 GET_SBIC_selid(regs, id); 1095 dev->target = id; 1096 GET_SBIC_tlun(regs,dev->lun); 1097 if( dev->lun & SBIC_TLUN_VALID ) 1098 dev->lun &= SBIC_TLUN_MASK; 1099 else 1100 dev->lun = lun; 1101 } else if (csr == (SBIC_CSR_MIS_2|MESG_OUT_PHASE)) { 1102 /* 1103 * Send identify message 1104 * (SCSI-2 requires an identify msg (?)) 1105 */ 1106 GET_SBIC_selid(regs, id); 1107 dev->target = id; 1108 GET_SBIC_tlun(regs,dev->lun); 1109 if( dev->lun & SBIC_TLUN_VALID ) 1110 dev->lun &= SBIC_TLUN_MASK; 1111 else 1112 dev->lun = lun; 1113 /* 1114 * handle drives that don't want to be asked 1115 * whether to go sync at all. 1116 */ 1117 if (sbic_inhibit_sync[id] 1118 && dev->sc_sync[id].state == SYNC_START) { 1119 #ifdef DEBUG 1120 if (sync_debug) 1121 printf("Forcing target %d asynchronous.\n", id); 1122 #endif 1123 dev->sc_sync[id].offset = 0; 1124 dev->sc_sync[id].period = sbic_min_period; 1125 dev->sc_sync[id].state = SYNC_DONE; 1126 } 1127 1128 1129 if (dev->sc_sync[id].state != SYNC_START){ 1130 if( dev->sc_xs->xs_control & XS_CTL_POLL 1131 || (dev->sc_flags & SBICF_ICMD) 1132 || !sbic_enable_reselect ) 1133 SEND_BYTE (regs, MSG_IDENTIFY | lun); 1134 else 1135 SEND_BYTE (regs, MSG_IDENTIFY_DR | lun); 1136 } else { 1137 /* 1138 * try to initiate a sync transfer. 1139 * So compose the sync message we're going 1140 * to send to the target 1141 */ 1142 1143 #ifdef DEBUG 1144 if (sync_debug) 1145 printf("Sending sync request to target %d ... ", 1146 id); 1147 #endif 1148 /* 1149 * setup scsi message sync message request 1150 */ 1151 dev->sc_msg[0] = MSG_IDENTIFY | lun; 1152 dev->sc_msg[1] = MSG_EXT_MESSAGE; 1153 dev->sc_msg[2] = 3; 1154 dev->sc_msg[3] = MSG_SYNC_REQ; 1155 dev->sc_msg[4] = sbictoscsiperiod(dev, regs, 1156 sbic_min_period); 1157 dev->sc_msg[5] = sbic_max_offset; 1158 1159 if (sbicxfstart(regs, 6, MESG_OUT_PHASE, sbic_cmd_wait)) 1160 sbicxfout(regs, 6, dev->sc_msg, MESG_OUT_PHASE); 1161 1162 dev->sc_sync[id].state = SYNC_SENT; 1163 #ifdef DEBUG 1164 if (sync_debug) 1165 printf ("sent\n"); 1166 #endif 1167 } 1168 1169 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0); 1170 GET_SBIC_csr (regs, csr); 1171 CSR_TRACE('y',csr,asr,target); 1172 QPRINTF(("[%02x]", csr)); 1173 #ifdef DEBUG 1174 if (sync_debug && dev->sc_sync[id].state == SYNC_SENT) 1175 printf("csr-result of last msgout: 0x%x\n", csr); 1176 #endif 1177 1178 if (csr != SBIC_CSR_SEL_TIMEO) 1179 dev->sc_flags |= SBICF_SELECTED; 1180 } 1181 if (csr == SBIC_CSR_SEL_TIMEO) 1182 dev->sc_xs->error = XS_SELTIMEOUT; 1183 1184 QPRINTF(("\n")); 1185 1186 SBIC_TRACE(dev); 1187 return(csr == SBIC_CSR_SEL_TIMEO); 1188 } 1189 1190 int 1191 sbicxfstart(regs, len, phase, wait) 1192 sbic_regmap_t regs; 1193 int len, wait; 1194 u_char phase; 1195 { 1196 u_char id; 1197 1198 switch (phase) { 1199 case DATA_IN_PHASE: 1200 case MESG_IN_PHASE: 1201 GET_SBIC_selid (regs, id); 1202 id |= SBIC_SID_FROM_SCSI; 1203 SET_SBIC_selid (regs, id); 1204 SBIC_TC_PUT (regs, (unsigned)len); 1205 break; 1206 case DATA_OUT_PHASE: 1207 case MESG_OUT_PHASE: 1208 case CMD_PHASE: 1209 GET_SBIC_selid (regs, id); 1210 id &= ~SBIC_SID_FROM_SCSI; 1211 SET_SBIC_selid (regs, id); 1212 SBIC_TC_PUT (regs, (unsigned)len); 1213 break; 1214 default: 1215 SBIC_TC_PUT (regs, 0); 1216 } 1217 QPRINTF(("sbicxfstart %d, %d, %d\n", len, phase, wait)); 1218 1219 return(1); 1220 } 1221 1222 int 1223 sbicxfout(regs, len, bp, phase) 1224 sbic_regmap_t regs; 1225 int len; 1226 void *bp; 1227 int phase; 1228 { 1229 u_char orig_csr, asr, *buf; 1230 int wait; 1231 1232 buf = bp; 1233 wait = sbic_data_wait; 1234 1235 QPRINTF(("sbicxfout {%d} %02x %02x %02x %02x %02x " 1236 "%02x %02x %02x %02x %02x\n", len, buf[0], buf[1], buf[2], 1237 buf[3], buf[4], buf[5], buf[6], buf[7], buf[8], buf[9])); 1238 1239 GET_SBIC_csr (regs, orig_csr); 1240 CSR_TRACE('>',orig_csr,0,0); 1241 1242 /* 1243 * sigh.. WD-PROTO strikes again.. sending the command in one go 1244 * causes the chip to lock up if talking to certain (misbehaving?) 1245 * targets. Anyway, this procedure should work for all targets, but 1246 * it's slightly slower due to the overhead 1247 */ 1248 WAIT_CIP (regs); 1249 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1250 for (;len > 0; len--) { 1251 GET_SBIC_asr (regs, asr); 1252 while ((asr & SBIC_ASR_DBR) == 0) { 1253 if ((asr & SBIC_ASR_INT) || --wait < 0) { 1254 #ifdef DEBUG 1255 if (sbic_debug) 1256 printf("sbicxfout fail: l%d i%x w%d\n", 1257 len, asr, wait); 1258 #endif 1259 return (len); 1260 } 1261 /* DELAY(1);*/ 1262 GET_SBIC_asr (regs, asr); 1263 } 1264 1265 SET_SBIC_data (regs, *buf); 1266 buf++; 1267 } 1268 SBIC_TC_GET(regs, len); 1269 QPRINTF(("sbicxfout done %d bytes\n", len)); 1270 /* 1271 * this leaves with one csr to be read 1272 */ 1273 return(0); 1274 } 1275 1276 /* returns # bytes left to read */ 1277 int 1278 sbicxfin(regs, len, bp) 1279 sbic_regmap_t regs; 1280 int len; 1281 void *bp; 1282 { 1283 int wait; 1284 u_char *obp, *buf; 1285 u_char orig_csr, csr, asr; 1286 1287 wait = sbic_data_wait; 1288 obp = bp; 1289 buf = bp; 1290 1291 GET_SBIC_csr (regs, orig_csr); 1292 CSR_TRACE('<',orig_csr,0,0); 1293 1294 QPRINTF(("sbicxfin %d, csr=%02x\n", len, orig_csr)); 1295 1296 WAIT_CIP (regs); 1297 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1298 for (;len > 0; len--) { 1299 GET_SBIC_asr (regs, asr); 1300 if((asr & SBIC_ASR_PE)) { 1301 #ifdef DEBUG 1302 printf("sbicxfin parity error: l%d i%x w%d\n", 1303 len, asr, wait); 1304 /* return ((unsigned long)buf - (unsigned long)bp); */ 1305 #ifdef DDB 1306 Debugger(); 1307 #endif 1308 #endif 1309 } 1310 while ((asr & SBIC_ASR_DBR) == 0) { 1311 if ((asr & SBIC_ASR_INT) || --wait < 0) { 1312 #ifdef DEBUG 1313 if (sbic_debug) { 1314 QPRINTF(("sbicxfin fail:{%d} %02x %02x %02x %02x %02x %02x " 1315 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1316 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1317 printf("sbicxfin fail: l%d i%x w%d\n", 1318 len, asr, wait); 1319 } 1320 #endif 1321 return len; 1322 } 1323 1324 if( ! asr & SBIC_ASR_BSY ) { 1325 GET_SBIC_csr(regs, csr); 1326 CSR_TRACE('<',csr,asr,len); 1327 QPRINTF(("[CSR%02xASR%02x]", csr, asr)); 1328 } 1329 1330 /* DELAY(1);*/ 1331 GET_SBIC_asr (regs, asr); 1332 } 1333 1334 GET_SBIC_data (regs, *buf); 1335 /* QPRINTF(("asr=%02x, csr=%02x, data=%02x\n", asr, csr, *buf));*/ 1336 buf++; 1337 } 1338 1339 QPRINTF(("sbicxfin {%d} %02x %02x %02x %02x %02x %02x " 1340 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1341 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1342 1343 /* this leaves with one csr to be read */ 1344 return len; 1345 } 1346 1347 /* 1348 * SCSI 'immediate' command: issue a command to some SCSI device 1349 * and get back an 'immediate' response (i.e., do programmed xfer 1350 * to get the response data). 'cbuf' is a buffer containing a scsi 1351 * command of length clen bytes. 'buf' is a buffer of length 'len' 1352 * bytes for data. The transfer direction is determined by the device 1353 * (i.e., by the scsi bus data xfer phase). If 'len' is zero, the 1354 * command must supply no data. 1355 */ 1356 int 1357 sbicicmd(dev, target, lun, cbuf, clen, buf, len) 1358 struct sbic_softc *dev; 1359 void *cbuf, *buf; 1360 int clen, len; 1361 { 1362 sbic_regmap_t regs; 1363 u_char phase, csr, asr; 1364 int wait, i; 1365 struct sbic_acb *acb; 1366 1367 #define CSR_LOG_BUF_SIZE 0 1368 #if CSR_LOG_BUF_SIZE 1369 int bufptr; 1370 int csrbuf[CSR_LOG_BUF_SIZE]; 1371 bufptr=0; 1372 #endif 1373 1374 SBIC_TRACE(dev); 1375 regs = dev->sc_sbic; 1376 acb = dev->sc_nexus; 1377 1378 /* Make sure pointers are OK */ 1379 dev->sc_last = dev->sc_cur = &acb->sc_pa; 1380 dev->sc_tcnt = acb->sc_tcnt = 0; 1381 acb->sc_pa.dc_count = 0; /* No DMA */ 1382 acb->sc_kv.dc_addr = buf; 1383 acb->sc_kv.dc_count = len; 1384 1385 #ifdef DEBUG 1386 routine = 3; 1387 debug_sbic_regs = regs; /* store this to allow debug calls */ 1388 if( data_pointer_debug > 1 ) 1389 printf("sbicicmd(%d,%d):%d\n", target, lun, 1390 acb->sc_kv.dc_count); 1391 #endif 1392 1393 /* 1394 * set the sbic into non-DMA mode 1395 */ 1396 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI /*| SBIC_CTL_HSP*/); 1397 1398 dev->sc_stat[0] = 0xff; 1399 dev->sc_msg[0] = 0xff; 1400 i = 1; /* pre-load */ 1401 1402 /* We're stealing the SCSI bus */ 1403 dev->sc_flags |= SBICF_ICMD; 1404 1405 do { 1406 /* 1407 * select the SCSI bus (it's an error if bus isn't free) 1408 */ 1409 if (!( dev->sc_flags & SBICF_SELECTED ) 1410 && sbicselectbus(dev, regs, target, lun, dev->sc_scsiaddr)) { 1411 /* printf("sbicicmd: trying to select busy bus!\n"); */ 1412 dev->sc_flags &= ~SBICF_ICMD; 1413 return(-1); 1414 } 1415 1416 /* 1417 * Wait for a phase change (or error) then let the device sequence 1418 * us through the various SCSI phases. 1419 */ 1420 1421 wait = sbic_cmd_wait; 1422 1423 asr = GET_SBIC_asr (regs, asr); 1424 GET_SBIC_csr (regs, csr); 1425 CSR_TRACE('I',csr,asr,target); 1426 QPRINTF((">ASR:%02xCSR:%02x<", asr, csr)); 1427 1428 #if CSR_LOG_BUF_SIZE 1429 csrbuf[bufptr++] = csr; 1430 #endif 1431 1432 1433 switch (csr) { 1434 case SBIC_CSR_S_XFERRED: 1435 case SBIC_CSR_DISC: 1436 case SBIC_CSR_DISC_1: 1437 dev->sc_flags &= ~SBICF_SELECTED; 1438 GET_SBIC_cmd_phase (regs, phase); 1439 if (phase == 0x60) { 1440 GET_SBIC_tlun (regs, dev->sc_stat[0]); 1441 i = 0; /* done */ 1442 /* break; */ /* Bypass all the state gobldygook */ 1443 } else { 1444 #ifdef DEBUG 1445 if(reselect_debug>1) 1446 printf("sbicicmd: handling disconnect\n"); 1447 #endif 1448 i = SBIC_STATE_DISCONNECT; 1449 } 1450 break; 1451 1452 case SBIC_CSR_XFERRED|CMD_PHASE: 1453 case SBIC_CSR_MIS|CMD_PHASE: 1454 case SBIC_CSR_MIS_1|CMD_PHASE: 1455 case SBIC_CSR_MIS_2|CMD_PHASE: 1456 if (sbicxfstart(regs, clen, CMD_PHASE, sbic_cmd_wait)) 1457 if (sbicxfout(regs, clen, 1458 cbuf, CMD_PHASE)) 1459 i = sbicabort(dev, regs,"icmd sending cmd"); 1460 #if 0 1461 GET_SBIC_csr(regs, csr); /* Lets us reload tcount */ 1462 WAIT_CIP(regs); 1463 GET_SBIC_asr(regs, asr); 1464 CSR_TRACE('I',csr,asr,target); 1465 if( asr & (SBIC_ASR_BSY|SBIC_ASR_LCI|SBIC_ASR_CIP) ) 1466 printf("next: cmd sent asr %02x, csr %02x\n", 1467 asr, csr); 1468 #endif 1469 break; 1470 1471 #if 0 1472 case SBIC_CSR_XFERRED|DATA_OUT_PHASE: 1473 case SBIC_CSR_XFERRED|DATA_IN_PHASE: 1474 case SBIC_CSR_MIS|DATA_OUT_PHASE: 1475 case SBIC_CSR_MIS|DATA_IN_PHASE: 1476 case SBIC_CSR_MIS_1|DATA_OUT_PHASE: 1477 case SBIC_CSR_MIS_1|DATA_IN_PHASE: 1478 case SBIC_CSR_MIS_2|DATA_OUT_PHASE: 1479 case SBIC_CSR_MIS_2|DATA_IN_PHASE: 1480 if (acb->sc_kv.dc_count <= 0) 1481 i = sbicabort(dev, regs, "icmd out of data"); 1482 else { 1483 wait = sbic_data_wait; 1484 if (sbicxfstart(regs, 1485 acb->sc_kv.dc_count, 1486 SBIC_PHASE(csr), wait)) 1487 if (csr & 0x01) 1488 /* data in? */ 1489 i=sbicxfin(regs, 1490 acb->sc_kv.dc_count, 1491 acb->sc_kv.dc_addr); 1492 else 1493 i=sbicxfout(regs, 1494 acb->sc_kv.dc_count, 1495 acb->sc_kv.dc_addr, 1496 SBIC_PHASE(csr)); 1497 acb->sc_kv.dc_addr += 1498 (acb->sc_kv.dc_count - i); 1499 acb->sc_kv.dc_count = i; 1500 i = 1; 1501 } 1502 break; 1503 1504 #endif 1505 case SBIC_CSR_XFERRED|STATUS_PHASE: 1506 case SBIC_CSR_MIS|STATUS_PHASE: 1507 case SBIC_CSR_MIS_1|STATUS_PHASE: 1508 case SBIC_CSR_MIS_2|STATUS_PHASE: 1509 /* 1510 * the sbic does the status/cmd-complete reading ok, 1511 * so do this with its hi-level commands. 1512 */ 1513 #ifdef DEBUG 1514 if(sbic_debug) 1515 printf("SBICICMD status phase\n"); 1516 #endif 1517 SBIC_TC_PUT(regs, 0); 1518 SET_SBIC_cmd_phase(regs, 0x46); 1519 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1520 break; 1521 1522 #if THIS_IS_A_RESERVED_STATE 1523 case BUS_FREE_PHASE: /* This is not legal */ 1524 if( dev->sc_stat[0] != 0xff ) 1525 goto out; 1526 break; 1527 #endif 1528 1529 default: 1530 i = sbicnextstate(dev, csr, asr); 1531 } 1532 1533 /* 1534 * make sure the last command was taken, 1535 * ie. we're not hunting after an ignored command.. 1536 */ 1537 GET_SBIC_asr(regs, asr); 1538 1539 /* tapes may take a loooong time.. */ 1540 while (asr & SBIC_ASR_BSY){ 1541 if(asr & SBIC_ASR_DBR) { 1542 printf("sbicicmd: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", 1543 csr,asr); 1544 #ifdef DDB 1545 Debugger(); 1546 #endif 1547 /* SBIC is jammed */ 1548 /* DUNNO which direction */ 1549 /* Try old direction */ 1550 GET_SBIC_data(regs,i); 1551 GET_SBIC_asr(regs, asr); 1552 if( asr & SBIC_ASR_DBR) /* Wants us to write */ 1553 SET_SBIC_data(regs,i); 1554 } 1555 GET_SBIC_asr(regs, asr); 1556 } 1557 1558 /* 1559 * wait for last command to complete 1560 */ 1561 if (asr & SBIC_ASR_LCI) { 1562 printf("sbicicmd: last command ignored\n"); 1563 } 1564 else if( i == 1 ) /* Bsy */ 1565 SBIC_WAIT (regs, SBIC_ASR_INT, wait); 1566 1567 /* 1568 * do it again 1569 */ 1570 } while ( i > 0 && dev->sc_stat[0] == 0xff); 1571 1572 /* Sometimes we need to do an extra read of the CSR */ 1573 GET_SBIC_csr(regs, csr); 1574 CSR_TRACE('I',csr,asr,0xff); 1575 1576 #if CSR_LOG_BUF_SIZE 1577 if(reselect_debug>1) 1578 for(i=0; i<bufptr; i++) 1579 printf("CSR:%02x", csrbuf[i]); 1580 #endif 1581 1582 #ifdef DEBUG 1583 if(data_pointer_debug > 1) 1584 printf("sbicicmd done(%d,%d):%d =%d=\n", 1585 dev->target, lun, 1586 acb->sc_kv.dc_count, 1587 dev->sc_stat[0]); 1588 #endif 1589 1590 QPRINTF(("=STS:%02x=", dev->sc_stat[0])); 1591 dev->sc_flags &= ~SBICF_ICMD; 1592 1593 SBIC_TRACE(dev); 1594 return(dev->sc_stat[0]); 1595 } 1596 1597 /* 1598 * Finish SCSI xfer command: After the completion interrupt from 1599 * a read/write operation, sequence through the final phases in 1600 * programmed i/o. This routine is a lot like sbicicmd except we 1601 * skip (and don't allow) the select, cmd out and data in/out phases. 1602 */ 1603 void 1604 sbicxfdone(dev, regs, target) 1605 struct sbic_softc *dev; 1606 sbic_regmap_t regs; 1607 int target; 1608 { 1609 u_char phase, asr, csr; 1610 int s; 1611 1612 SBIC_TRACE(dev); 1613 QPRINTF(("{")); 1614 s = splbio(); 1615 1616 /* 1617 * have the sbic complete on its own 1618 */ 1619 SBIC_TC_PUT(regs, 0); 1620 SET_SBIC_cmd_phase(regs, 0x46); 1621 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1622 1623 do { 1624 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0); 1625 GET_SBIC_csr (regs, csr); 1626 CSR_TRACE('f',csr,asr,target); 1627 QPRINTF(("%02x:", csr)); 1628 } while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) 1629 && (csr != SBIC_CSR_S_XFERRED)); 1630 1631 dev->sc_flags &= ~SBICF_SELECTED; 1632 1633 GET_SBIC_cmd_phase (regs, phase); 1634 QPRINTF(("}%02x", phase)); 1635 if (phase == 0x60) 1636 GET_SBIC_tlun(regs, dev->sc_stat[0]); 1637 else 1638 sbicerror(dev, regs, csr); 1639 1640 QPRINTF(("=STS:%02x=\n", dev->sc_stat[0])); 1641 splx(s); 1642 SBIC_TRACE(dev); 1643 } 1644 1645 /* 1646 * No DMA chains 1647 */ 1648 1649 int 1650 sbicgo(dev, xs) 1651 struct sbic_softc *dev; 1652 struct scsipi_xfer *xs; 1653 { 1654 int i, dmaflags, count, usedma; 1655 u_char csr, asr, *addr; 1656 sbic_regmap_t regs; 1657 struct sbic_acb *acb; 1658 1659 SBIC_TRACE(dev); 1660 dev->target = xs->sc_link->scsipi_scsi.target; 1661 dev->lun = xs->sc_link->scsipi_scsi.lun; 1662 acb = dev->sc_nexus; 1663 regs = dev->sc_sbic; 1664 1665 usedma = sbicdmaok(dev, xs); 1666 #ifdef DEBUG 1667 routine = 1; 1668 debug_sbic_regs = regs; /* store this to allow debug calls */ 1669 if( data_pointer_debug > 1 ) 1670 printf("sbicgo(%d,%d)\n", dev->target, dev->lun); 1671 #endif 1672 1673 /* 1674 * set the sbic into DMA mode 1675 */ 1676 if( usedma ) 1677 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI | 1678 SBIC_MACHINE_DMA_MODE); 1679 else 1680 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1681 1682 1683 /* 1684 * select the SCSI bus (it's an error if bus isn't free) 1685 */ 1686 if (sbicselectbus(dev, regs, dev->target, dev->lun, 1687 dev->sc_scsiaddr)) { 1688 /* printf("sbicgo: Trying to select busy bus!\n"); */ 1689 SBIC_TRACE(dev); 1690 return(0); /* Not done: needs to be rescheduled */ 1691 } 1692 dev->sc_stat[0] = 0xff; 1693 1694 /* 1695 * Calculate DMA chains now 1696 */ 1697 1698 dmaflags = 0; 1699 if (acb->flags & ACB_DATAIN) 1700 dmaflags |= DMAGO_READ; 1701 1702 1703 /* 1704 * Deal w/bounce buffers. 1705 */ 1706 1707 addr = acb->sc_kv.dc_addr; 1708 count = acb->sc_kv.dc_count; 1709 if (count && (char *)kvtop(addr) != acb->sc_pa.dc_addr) { /* XXXX check */ 1710 printf("sbic: DMA buffer mapping changed %p->%x\n", 1711 acb->sc_pa.dc_addr, kvtop(addr)); 1712 #ifdef DDB 1713 Debugger(); 1714 #endif 1715 } 1716 1717 #ifdef DEBUG 1718 ++sbicdma_ops; /* count total DMA operations */ 1719 #endif 1720 if (count && usedma && dev->sc_flags & SBICF_BADDMA && 1721 sbiccheckdmap(addr, count, dev->sc_dmamask)) { 1722 /* 1723 * need to bounce the dma. 1724 */ 1725 if (dmaflags & DMAGO_READ) { 1726 acb->flags |= ACB_BBUF; 1727 acb->sc_dmausrbuf = addr; 1728 acb->sc_dmausrlen = count; 1729 acb->sc_usrbufpa = (u_char *)kvtop(addr); 1730 if(!dev->sc_tinfo[dev->target].bounce) { 1731 printf("sbicgo: HELP! no bounce allocated for %d\n", 1732 dev->target); 1733 printf("xfer: (%p->%p,%lx)\n", acb->sc_dmausrbuf, 1734 acb->sc_usrbufpa, acb->sc_dmausrlen); 1735 dev->sc_tinfo[xs->sc_link->scsipi_scsi.target].bounce 1736 = (char *)alloc_z2mem(MAXPHYS); 1737 if (isztwomem(dev->sc_tinfo[xs->sc_link->scsipi_scsi.target].bounce)) 1738 printf("alloc ZII target %d bounce pa 0x%x\n", 1739 xs->sc_link->scsipi_scsi.target, 1740 kvtop(dev->sc_tinfo[xs->sc_link->scsipi_scsi.target].bounce)); 1741 else if (dev->sc_tinfo[xs->sc_link->scsipi_scsi.target].bounce) 1742 printf("alloc CHIP target %d bounce pa 0x%p\n", 1743 xs->sc_link->scsipi_scsi.target, 1744 PREP_DMA_MEM(dev->sc_tinfo[xs->sc_link->scsipi_scsi.target].bounce)); 1745 1746 printf("Allocating %d bounce at %x\n", 1747 dev->target, 1748 kvtop(dev->sc_tinfo[dev->target].bounce)); 1749 } 1750 } else { /* write: copy to dma buffer */ 1751 #ifdef DEBUG 1752 if(data_pointer_debug) 1753 printf("sbicgo: copying %x bytes to target %d bounce %x\n", 1754 count, dev->target, 1755 kvtop(dev->sc_tinfo[dev->target].bounce)); 1756 #endif 1757 bcopy (addr, dev->sc_tinfo[dev->target].bounce, count); 1758 } 1759 addr = dev->sc_tinfo[dev->target].bounce;/* and use dma buffer */ 1760 acb->sc_kv.dc_addr = addr; 1761 #ifdef DEBUG 1762 ++sbicdma_bounces; /* count number of bounced */ 1763 #endif 1764 } 1765 1766 /* 1767 * Allocate the DMA chain 1768 */ 1769 1770 /* Set start KVM addresses */ 1771 #if 0 1772 acb->sc_kv.dc_addr = addr; 1773 acb->sc_kv.dc_count = count; 1774 #endif 1775 1776 /* Mark end of segment */ 1777 acb->sc_tcnt = dev->sc_tcnt = 0; 1778 acb->sc_pa.dc_count = 0; 1779 1780 sbic_load_ptrs(dev, regs, dev->target, dev->lun); 1781 SBIC_TRACE(dev); 1782 /* Enable interrupts but don't do any DMA */ 1783 dev->sc_enintr(dev); 1784 if (usedma) { 1785 dev->sc_tcnt = dev->sc_dmago(dev, acb->sc_pa.dc_addr, 1786 acb->sc_pa.dc_count, 1787 dmaflags); 1788 #ifdef DEBUG 1789 dev->sc_dmatimo = dev->sc_tcnt ? 1 : 0; 1790 #endif 1791 } else 1792 dev->sc_dmacmd = 0; /* Don't use DMA */ 1793 dev->sc_flags |= SBICF_INDMA; 1794 /* SBIC_TC_PUT(regs, dev->sc_tcnt); */ /* XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX */ 1795 SBIC_TRACE(dev); 1796 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 1797 1798 /* 1799 * push the data cache ( I think this won't work (EH)) 1800 */ 1801 #if defined(M68040) || defined(M68060) 1802 if (mmutype == MMU_68040 && usedma && count) { 1803 dma_cachectl(addr, count); 1804 if (((u_int)addr & 0xF) || (((u_int)addr + count) & 0xF)) 1805 dev->sc_flags |= SBICF_DCFLUSH; 1806 } 1807 #endif 1808 1809 /* 1810 * enintr() also enables interrupts for the sbic 1811 */ 1812 #ifdef DEBUG 1813 if( data_pointer_debug > 1 ) 1814 printf("sbicgo dmago:%d(%p:%lx)\n", 1815 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 1816 #if 0 1817 /* 1818 * Hmm - this isn't right: asr and csr haven't been set yet. 1819 */ 1820 debug_asr = asr; 1821 debug_csr = csr; 1822 #endif 1823 #endif 1824 1825 /* 1826 * Lets cycle a while then let the interrupt handler take over 1827 */ 1828 1829 asr = GET_SBIC_asr(regs, asr); 1830 do { 1831 GET_SBIC_csr(regs, csr); 1832 CSR_TRACE('g',csr,asr,dev->target); 1833 #ifdef DEBUG 1834 debug_csr = csr; 1835 routine = 1; 1836 #endif 1837 QPRINTF(("go[0x%x]", csr)); 1838 1839 i = sbicnextstate(dev, csr, asr); 1840 1841 WAIT_CIP(regs); 1842 GET_SBIC_asr(regs, asr); 1843 #ifdef DEBUG 1844 debug_asr = asr; 1845 #endif 1846 if(asr & SBIC_ASR_LCI) printf("sbicgo: LCI asr:%02x csr:%02x\n", 1847 asr,csr); 1848 } while( i == SBIC_STATE_RUNNING 1849 && asr & (SBIC_ASR_INT|SBIC_ASR_LCI) ); 1850 1851 CSR_TRACE('g',csr,asr,i<<4); 1852 SBIC_TRACE(dev); 1853 if (i == SBIC_STATE_DONE && dev->sc_stat[0] == 0xff) printf("sbicgo: done & stat = 0xff\n"); 1854 if (i == SBIC_STATE_DONE && dev->sc_stat[0] != 0xff) { 1855 /* if( i == SBIC_STATE_DONE && dev->sc_stat[0] ) { */ 1856 /* Did we really finish that fast? */ 1857 return 1; 1858 } 1859 return 0; 1860 } 1861 1862 1863 int 1864 sbicintr(dev) 1865 struct sbic_softc *dev; 1866 { 1867 sbic_regmap_t regs; 1868 u_char asr, csr; 1869 int i; 1870 1871 regs = dev->sc_sbic; 1872 1873 /* 1874 * pending interrupt? 1875 */ 1876 GET_SBIC_asr (regs, asr); 1877 if ((asr & SBIC_ASR_INT) == 0) 1878 return(0); 1879 1880 SBIC_TRACE(dev); 1881 do { 1882 GET_SBIC_csr(regs, csr); 1883 CSR_TRACE('i',csr,asr,dev->target); 1884 #ifdef DEBUG 1885 debug_csr = csr; 1886 routine = 2; 1887 #endif 1888 QPRINTF(("intr[0x%x]", csr)); 1889 1890 i = sbicnextstate(dev, csr, asr); 1891 1892 WAIT_CIP(regs); 1893 GET_SBIC_asr(regs, asr); 1894 #ifdef DEBUG 1895 debug_asr = asr; 1896 #endif 1897 #if 0 1898 if(asr & SBIC_ASR_LCI) printf("sbicintr: LCI asr:%02x csr:%02x\n", 1899 asr,csr); 1900 #endif 1901 } while(i == SBIC_STATE_RUNNING && 1902 asr & (SBIC_ASR_INT|SBIC_ASR_LCI)); 1903 CSR_TRACE('i',csr,asr,i<<4); 1904 SBIC_TRACE(dev); 1905 return(1); 1906 } 1907 1908 /* 1909 * Run commands and wait for disconnect 1910 */ 1911 int 1912 sbicpoll(dev) 1913 struct sbic_softc *dev; 1914 { 1915 sbic_regmap_t regs; 1916 u_char asr, csr; 1917 int i; 1918 1919 SBIC_TRACE(dev); 1920 regs = dev->sc_sbic; 1921 1922 do { 1923 GET_SBIC_asr (regs, asr); 1924 #ifdef DEBUG 1925 debug_asr = asr; 1926 #endif 1927 GET_SBIC_csr(regs, csr); 1928 CSR_TRACE('p',csr,asr,dev->target); 1929 #ifdef DEBUG 1930 debug_csr = csr; 1931 routine = 2; 1932 #endif 1933 QPRINTF(("poll[0x%x]", csr)); 1934 1935 i = sbicnextstate(dev, csr, asr); 1936 1937 WAIT_CIP(regs); 1938 GET_SBIC_asr(regs, asr); 1939 /* tapes may take a loooong time.. */ 1940 while (asr & SBIC_ASR_BSY){ 1941 if(asr & SBIC_ASR_DBR) { 1942 printf("sbipoll: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", 1943 csr,asr); 1944 #ifdef DDB 1945 Debugger(); 1946 #endif 1947 /* SBIC is jammed */ 1948 /* DUNNO which direction */ 1949 /* Try old direction */ 1950 GET_SBIC_data(regs,i); 1951 GET_SBIC_asr(regs, asr); 1952 if( asr & SBIC_ASR_DBR) /* Wants us to write */ 1953 SET_SBIC_data(regs,i); 1954 } 1955 GET_SBIC_asr(regs, asr); 1956 } 1957 1958 if(asr & SBIC_ASR_LCI) printf("sbicpoll: LCI asr:%02x csr:%02x\n", 1959 asr,csr); 1960 else if( i == 1 ) /* BSY */ 1961 SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait); 1962 } while(i == SBIC_STATE_RUNNING); 1963 CSR_TRACE('p',csr,asr,i<<4); 1964 SBIC_TRACE(dev); 1965 return(1); 1966 } 1967 1968 /* 1969 * Handle a single msgin 1970 */ 1971 1972 int 1973 sbicmsgin(dev) 1974 struct sbic_softc *dev; 1975 { 1976 sbic_regmap_t regs; 1977 int recvlen; 1978 u_char asr, csr, *tmpaddr; 1979 1980 regs = dev->sc_sbic; 1981 1982 dev->sc_msg[0] = 0xff; 1983 dev->sc_msg[1] = 0xff; 1984 1985 GET_SBIC_asr(regs, asr); 1986 #ifdef DEBUG 1987 if(reselect_debug>1) 1988 printf("sbicmsgin asr=%02x\n", asr); 1989 #endif 1990 1991 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 1992 1993 GET_SBIC_selid (regs, csr); 1994 SET_SBIC_selid (regs, csr | SBIC_SID_FROM_SCSI); 1995 1996 SBIC_TC_PUT(regs, 0); 1997 tmpaddr = dev->sc_msg; 1998 recvlen = 1; 1999 do { 2000 while( recvlen-- ) { 2001 asr = GET_SBIC_asr(regs, asr); 2002 GET_SBIC_csr(regs, csr); 2003 QPRINTF(("sbicmsgin ready to go (csr,asr)=(%02x,%02x)\n", 2004 csr, asr)); 2005 2006 RECV_BYTE(regs, *tmpaddr); 2007 CSR_TRACE('m',csr,asr,*tmpaddr); 2008 #if 1 2009 /* 2010 * get the command completion interrupt, or we 2011 * can't send a new command (LCI) 2012 */ 2013 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2014 GET_SBIC_csr(regs, csr); 2015 CSR_TRACE('X',csr,asr,dev->target); 2016 #else 2017 WAIT_CIP(regs); 2018 do { 2019 GET_SBIC_asr(regs, asr); 2020 csr = 0xff; 2021 GET_SBIC_csr(regs, csr); 2022 CSR_TRACE('X',csr,asr,dev->target); 2023 if( csr == 0xff ) 2024 printf("sbicmsgin waiting: csr %02x asr %02x\n", csr, asr); 2025 } while( csr == 0xff ); 2026 #endif 2027 #ifdef DEBUG 2028 if(reselect_debug>1) 2029 printf("sbicmsgin: got %02x csr %02x asr %02x\n", 2030 *tmpaddr, csr, asr); 2031 #endif 2032 #if do_parity_check 2033 if( asr & SBIC_ASR_PE ) { 2034 printf ("Parity error"); 2035 /* This code simply does not work. */ 2036 WAIT_CIP(regs); 2037 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2038 WAIT_CIP(regs); 2039 GET_SBIC_asr(regs, asr); 2040 WAIT_CIP(regs); 2041 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2042 WAIT_CIP(regs); 2043 if( !(asr & SBIC_ASR_LCI) ) 2044 /* Target wants to send garbled msg*/ 2045 continue; 2046 printf("--fixing\n"); 2047 /* loop until a msgout phase occurs on target */ 2048 while(csr & 0x07 != MESG_OUT_PHASE) { 2049 while( asr & SBIC_ASR_BSY && 2050 !(asr & SBIC_ASR_DBR|SBIC_ASR_INT) ) 2051 GET_SBIC_asr(regs, asr); 2052 if( asr & SBIC_ASR_DBR ) 2053 panic("msgin: jammed again!\n"); 2054 GET_SBIC_csr(regs, csr); 2055 CSR_TRACE('e',csr,asr,dev->target); 2056 if( csr & 0x07 != MESG_OUT_PHASE ) { 2057 sbicnextstate(dev, csr, asr); 2058 sbic_save_ptrs(dev, regs, 2059 dev->target, 2060 dev->lun); 2061 } 2062 } 2063 /* Should be msg out by now */ 2064 SEND_BYTE(regs, MSG_PARITY_ERROR); 2065 } 2066 else 2067 #endif 2068 tmpaddr++; 2069 2070 if(recvlen) { 2071 /* Clear ACK */ 2072 WAIT_CIP(regs); 2073 GET_SBIC_asr(regs, asr); 2074 GET_SBIC_csr(regs, csr); 2075 CSR_TRACE('X',csr,asr,dev->target); 2076 QPRINTF(("sbicmsgin pre byte CLR_ACK (csr,asr)=(%02x,%02x)\n", 2077 csr, asr)); 2078 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2079 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2080 } 2081 2082 }; 2083 2084 if(dev->sc_msg[0] == 0xff) { 2085 printf("sbicmsgin: sbic swallowed our message\n"); 2086 break; 2087 } 2088 #ifdef DEBUG 2089 if (sync_debug) 2090 printf("msgin done csr 0x%x asr 0x%x msg 0x%x\n", 2091 csr, asr, dev->sc_msg[0]); 2092 #endif 2093 /* 2094 * test whether this is a reply to our sync 2095 * request 2096 */ 2097 if (MSG_ISIDENTIFY(dev->sc_msg[0])) { 2098 QPRINTF(("IFFY")); 2099 #if 0 2100 /* There is an implied load-ptrs here */ 2101 sbic_load_ptrs(dev, regs, dev->target, dev->lun); 2102 #endif 2103 /* Got IFFY msg -- ack it */ 2104 } else if (dev->sc_msg[0] == MSG_REJECT 2105 && dev->sc_sync[dev->target].state == SYNC_SENT) { 2106 QPRINTF(("REJECT of SYN")); 2107 #ifdef DEBUG 2108 if (sync_debug) 2109 printf("target %d rejected sync, going async\n", 2110 dev->target); 2111 #endif 2112 dev->sc_sync[dev->target].period = sbic_min_period; 2113 dev->sc_sync[dev->target].offset = 0; 2114 dev->sc_sync[dev->target].state = SYNC_DONE; 2115 SET_SBIC_syn(regs, 2116 SBIC_SYN(dev->sc_sync[dev->target].offset, 2117 dev->sc_sync[dev->target].period)); 2118 } else if ((dev->sc_msg[0] == MSG_REJECT)) { 2119 QPRINTF(("REJECT")); 2120 /* 2121 * we'll never REJECt a REJECT message.. 2122 */ 2123 } else if ((dev->sc_msg[0] == MSG_SAVE_DATA_PTR)) { 2124 QPRINTF(("MSG_SAVE_DATA_PTR")); 2125 /* 2126 * don't reject this either. 2127 */ 2128 } else if ((dev->sc_msg[0] == MSG_DISCONNECT)) { 2129 QPRINTF(("DISCONNECT")); 2130 #ifdef DEBUG 2131 if( reselect_debug>1 && dev->sc_msg[0] == MSG_DISCONNECT ) 2132 printf("sbicmsgin: got disconnect msg %s\n", 2133 (dev->sc_flags & SBICF_ICMD)?"rejecting":""); 2134 #endif 2135 if( dev->sc_flags & SBICF_ICMD ) { 2136 /* We're in immediate mode. Prevent disconnects. */ 2137 /* prepare to reject the message, NACK */ 2138 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2139 WAIT_CIP(regs); 2140 } 2141 } else if (dev->sc_msg[0] == MSG_CMD_COMPLETE ) { 2142 QPRINTF(("CMD_COMPLETE")); 2143 /* !! KLUDGE ALERT !! quite a few drives don't seem to 2144 * really like the current way of sending the 2145 * sync-handshake together with the ident-message, and 2146 * they react by sending command-complete and 2147 * disconnecting right after returning the valid sync 2148 * handshake. So, all I can do is reselect the drive, 2149 * and hope it won't disconnect again. I don't think 2150 * this is valid behavior, but I can't help fixing a 2151 * problem that apparently exists. 2152 * 2153 * Note: we should not get here on `normal' command 2154 * completion, as that condition is handled by the 2155 * high-level sel&xfer resume command used to walk 2156 * thru status/cc-phase. 2157 */ 2158 2159 #ifdef DEBUG 2160 if (sync_debug) 2161 printf ("GOT MSG %d! target %d acting weird.." 2162 " waiting for disconnect...\n", 2163 dev->sc_msg[0], dev->target); 2164 #endif 2165 /* Check to see if sbic is handling this */ 2166 GET_SBIC_asr(regs, asr); 2167 if(asr & SBIC_ASR_BSY) 2168 return SBIC_STATE_RUNNING; 2169 2170 /* Let's try this: Assume it works and set status to 00 */ 2171 dev->sc_stat[0] = 0; 2172 } else if (dev->sc_msg[0] == MSG_EXT_MESSAGE 2173 && tmpaddr == &dev->sc_msg[1]) { 2174 QPRINTF(("ExtMSG\n")); 2175 /* Read in whole extended message */ 2176 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2177 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2178 GET_SBIC_asr(regs, asr); 2179 GET_SBIC_csr(regs, csr); 2180 QPRINTF(("CLR ACK asr %02x, csr %02x\n", asr, csr)); 2181 RECV_BYTE(regs, *tmpaddr); 2182 CSR_TRACE('x',csr,asr,*tmpaddr); 2183 /* Wait for command completion IRQ */ 2184 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2185 recvlen = *tmpaddr++; 2186 QPRINTF(("Recving ext msg, asr %02x csr %02x len %02x\n", 2187 asr, csr, recvlen)); 2188 } else if (dev->sc_msg[0] == MSG_EXT_MESSAGE && dev->sc_msg[1] == 3 2189 && dev->sc_msg[2] == MSG_SYNC_REQ) { 2190 QPRINTF(("SYN")); 2191 dev->sc_sync[dev->target].period = 2192 sbicfromscsiperiod(dev, 2193 regs, dev->sc_msg[3]); 2194 dev->sc_sync[dev->target].offset = dev->sc_msg[4]; 2195 dev->sc_sync[dev->target].state = SYNC_DONE; 2196 SET_SBIC_syn(regs, 2197 SBIC_SYN(dev->sc_sync[dev->target].offset, 2198 dev->sc_sync[dev->target].period)); 2199 printf("%s: target %d now synchronous," 2200 " period=%dns, offset=%d.\n", 2201 dev->sc_dev.dv_xname, dev->target, 2202 dev->sc_msg[3] * 4, dev->sc_msg[4]); 2203 } else { 2204 #ifdef DEBUG 2205 if (sbic_debug || sync_debug) 2206 printf ("sbicmsgin: Rejecting message 0x%02x\n", 2207 dev->sc_msg[0]); 2208 #endif 2209 /* prepare to reject the message, NACK */ 2210 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2211 WAIT_CIP(regs); 2212 } 2213 /* Clear ACK */ 2214 WAIT_CIP(regs); 2215 GET_SBIC_asr(regs, asr); 2216 GET_SBIC_csr(regs, csr); 2217 CSR_TRACE('X',csr,asr,dev->target); 2218 QPRINTF(("sbicmsgin pre CLR_ACK (csr,asr)=(%02x,%02x)%d\n", 2219 csr, asr, recvlen)); 2220 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2221 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2222 } 2223 #if 0 2224 while((csr == SBIC_CSR_MSGIN_W_ACK) 2225 || (SBIC_PHASE(csr) == MESG_IN_PHASE)); 2226 #else 2227 while (recvlen>0); 2228 #endif 2229 2230 QPRINTF(("sbicmsgin finished: csr %02x, asr %02x\n",csr, asr)); 2231 2232 /* Should still have one CSR to read */ 2233 return SBIC_STATE_RUNNING; 2234 } 2235 2236 2237 /* 2238 * sbicnextstate() 2239 * return: 2240 * 0 == done 2241 * 1 == working 2242 * 2 == disconnected 2243 * -1 == error 2244 */ 2245 int 2246 sbicnextstate(dev, csr, asr) 2247 struct sbic_softc *dev; 2248 u_char csr, asr; 2249 { 2250 sbic_regmap_t regs; 2251 struct sbic_acb *acb; 2252 int i, newtarget, newlun, wait; 2253 #if 0 2254 unsigned tcnt; 2255 #endif 2256 2257 i = 0; 2258 SBIC_TRACE(dev); 2259 regs = dev->sc_sbic; 2260 acb = dev->sc_nexus; 2261 2262 QPRINTF(("next[%02x,%02x]",asr,csr)); 2263 2264 switch (csr) { 2265 case SBIC_CSR_XFERRED|CMD_PHASE: 2266 case SBIC_CSR_MIS|CMD_PHASE: 2267 case SBIC_CSR_MIS_1|CMD_PHASE: 2268 case SBIC_CSR_MIS_2|CMD_PHASE: 2269 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 2270 if (sbicxfstart(regs, acb->clen, CMD_PHASE, sbic_cmd_wait)) 2271 if (sbicxfout(regs, acb->clen, 2272 &acb->cmd, CMD_PHASE)) 2273 goto abort; 2274 break; 2275 2276 case SBIC_CSR_XFERRED|STATUS_PHASE: 2277 case SBIC_CSR_MIS|STATUS_PHASE: 2278 case SBIC_CSR_MIS_1|STATUS_PHASE: 2279 case SBIC_CSR_MIS_2|STATUS_PHASE: 2280 /* 2281 * this should be the normal i/o completion case. 2282 * get the status & cmd complete msg then let the 2283 * device driver look at what happened. 2284 */ 2285 sbicxfdone(dev,regs,dev->target); 2286 /* 2287 * check for overlapping cache line, flush if so 2288 */ 2289 #if defined(M68040) || defined(M68060) 2290 if (dev->sc_flags & SBICF_DCFLUSH) { 2291 #if 0 2292 printf("sbic: 68040/68060 DMA cache flush needs" 2293 "fixing? %x:%x\n", 2294 dev->sc_xs->data, dev->sc_xs->datalen); 2295 #endif 2296 } 2297 #endif 2298 #ifdef DEBUG 2299 if( data_pointer_debug > 1 ) 2300 printf("next dmastop: %d(%p:%lx)\n", 2301 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 2302 dev->sc_dmatimo = 0; 2303 #endif 2304 dev->sc_dmastop(dev); /* was dmafree */ 2305 if (acb->flags & ACB_BBUF) { 2306 if ((u_char *)kvtop(acb->sc_dmausrbuf) != acb->sc_usrbufpa) 2307 printf("%s: WARNING - buffer mapping changed %p->%x\n", 2308 dev->sc_dev.dv_xname, acb->sc_usrbufpa, 2309 kvtop(acb->sc_dmausrbuf)); 2310 #ifdef DEBUG 2311 if(data_pointer_debug) 2312 printf("sbicgo:copying %lx bytes from target %d bounce %x\n", 2313 acb->sc_dmausrlen, 2314 dev->target, 2315 kvtop(dev->sc_tinfo[dev->target].bounce)); 2316 #endif 2317 bcopy(dev->sc_tinfo[dev->target].bounce, 2318 acb->sc_dmausrbuf, 2319 acb->sc_dmausrlen); 2320 } 2321 dev->sc_flags &= ~(SBICF_INDMA | SBICF_DCFLUSH); 2322 sbic_scsidone(acb, dev->sc_stat[0]); 2323 SBIC_TRACE(dev); 2324 return SBIC_STATE_DONE; 2325 2326 case SBIC_CSR_XFERRED|DATA_OUT_PHASE: 2327 case SBIC_CSR_XFERRED|DATA_IN_PHASE: 2328 case SBIC_CSR_MIS|DATA_OUT_PHASE: 2329 case SBIC_CSR_MIS|DATA_IN_PHASE: 2330 case SBIC_CSR_MIS_1|DATA_OUT_PHASE: 2331 case SBIC_CSR_MIS_1|DATA_IN_PHASE: 2332 case SBIC_CSR_MIS_2|DATA_OUT_PHASE: 2333 case SBIC_CSR_MIS_2|DATA_IN_PHASE: 2334 if( dev->sc_xs->xs_control & XS_CTL_POLL || dev->sc_flags & SBICF_ICMD 2335 || acb->sc_dmacmd == 0 ) { 2336 /* Do PIO */ 2337 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2338 if (acb->sc_kv.dc_count <= 0) { 2339 printf("sbicnextstate:xfer count %d asr%x csr%x\n", 2340 acb->sc_kv.dc_count, asr, csr); 2341 goto abort; 2342 } 2343 wait = sbic_data_wait; 2344 if( sbicxfstart(regs, 2345 acb->sc_kv.dc_count, 2346 SBIC_PHASE(csr), wait)) { 2347 if( SBIC_PHASE(csr) == DATA_IN_PHASE ) 2348 /* data in? */ 2349 i=sbicxfin(regs, 2350 acb->sc_kv.dc_count, 2351 acb->sc_kv.dc_addr); 2352 else 2353 i=sbicxfout(regs, 2354 acb->sc_kv.dc_count, 2355 acb->sc_kv.dc_addr, 2356 SBIC_PHASE(csr)); 2357 } 2358 acb->sc_kv.dc_addr += 2359 (acb->sc_kv.dc_count - i); 2360 acb->sc_kv.dc_count = i; 2361 } else { 2362 if (acb->sc_kv.dc_count <= 0) { 2363 printf("sbicnextstate:xfer count %d asr%x csr%x\n", 2364 acb->sc_kv.dc_count, asr, csr); 2365 goto abort; 2366 } 2367 /* 2368 * do scatter-gather dma 2369 * hacking the controller chip, ouch.. 2370 */ 2371 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI | 2372 SBIC_MACHINE_DMA_MODE); 2373 /* 2374 * set next dma addr and dec count 2375 */ 2376 #if 0 2377 SBIC_TC_GET(regs, tcnt); 2378 dev->sc_cur->dc_count -= ((dev->sc_tcnt - tcnt) >> 1); 2379 dev->sc_cur->dc_addr += (dev->sc_tcnt - tcnt); 2380 dev->sc_tcnt = acb->sc_tcnt = tcnt; 2381 #else 2382 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 2383 sbic_load_ptrs(dev, regs, dev->target, dev->lun); 2384 #endif 2385 #ifdef DEBUG 2386 if( data_pointer_debug > 1 ) 2387 printf("next dmanext: %d(%p:%lx)\n", 2388 dev->target,dev->sc_cur->dc_addr, 2389 dev->sc_tcnt); 2390 dev->sc_dmatimo = 1; 2391 #endif 2392 dev->sc_tcnt = dev->sc_dmanext(dev); 2393 SBIC_TC_PUT(regs, (unsigned)dev->sc_tcnt); 2394 SET_SBIC_cmd(regs, SBIC_CMD_XFER_INFO); 2395 dev->sc_flags |= SBICF_INDMA; 2396 } 2397 break; 2398 2399 case SBIC_CSR_XFERRED|MESG_IN_PHASE: 2400 case SBIC_CSR_MIS|MESG_IN_PHASE: 2401 case SBIC_CSR_MIS_1|MESG_IN_PHASE: 2402 case SBIC_CSR_MIS_2|MESG_IN_PHASE: 2403 SBIC_TRACE(dev); 2404 return sbicmsgin(dev); 2405 2406 case SBIC_CSR_MSGIN_W_ACK: 2407 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); /* Dunno what I'm ACKing */ 2408 printf("Acking unknown msgin CSR:%02x",csr); 2409 break; 2410 2411 case SBIC_CSR_XFERRED|MESG_OUT_PHASE: 2412 case SBIC_CSR_MIS|MESG_OUT_PHASE: 2413 case SBIC_CSR_MIS_1|MESG_OUT_PHASE: 2414 case SBIC_CSR_MIS_2|MESG_OUT_PHASE: 2415 #ifdef DEBUG 2416 if (sync_debug) 2417 printf ("sending REJECT msg to last msg.\n"); 2418 #endif 2419 2420 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 2421 /* 2422 * should only get here on reject, 2423 * since it's always US that 2424 * initiate a sync transfer 2425 */ 2426 SEND_BYTE(regs, MSG_REJECT); 2427 WAIT_CIP(regs); 2428 if( asr & (SBIC_ASR_BSY|SBIC_ASR_LCI|SBIC_ASR_CIP) ) 2429 printf("next: REJECT sent asr %02x\n", asr); 2430 SBIC_TRACE(dev); 2431 return SBIC_STATE_RUNNING; 2432 2433 case SBIC_CSR_DISC: 2434 case SBIC_CSR_DISC_1: 2435 dev->sc_flags &= ~(SBICF_INDMA|SBICF_SELECTED); 2436 2437 /* Try to schedule another target */ 2438 #ifdef DEBUG 2439 if(reselect_debug>1) 2440 printf("sbicnext target %d disconnected\n", dev->target); 2441 #endif 2442 TAILQ_INSERT_HEAD(&dev->nexus_list, acb, chain); 2443 ++dev->sc_tinfo[dev->target].dconns; 2444 dev->sc_nexus = NULL; 2445 dev->sc_xs = NULL; 2446 2447 if( acb->xs->xs_control & XS_CTL_POLL 2448 || (dev->sc_flags & SBICF_ICMD) 2449 || !sbic_parallel_operations ) { 2450 SBIC_TRACE(dev); 2451 return SBIC_STATE_DISCONNECT; 2452 } 2453 sbic_sched(dev); 2454 SBIC_TRACE(dev); 2455 return SBIC_STATE_DISCONNECT; 2456 2457 case SBIC_CSR_RSLT_NI: 2458 case SBIC_CSR_RSLT_IFY: 2459 GET_SBIC_rselid(regs, newtarget); 2460 /* check SBIC_RID_SIV? */ 2461 newtarget &= SBIC_RID_MASK; 2462 if (csr == SBIC_CSR_RSLT_IFY) { 2463 /* Read IFY msg to avoid lockup */ 2464 GET_SBIC_data(regs, newlun); 2465 WAIT_CIP(regs); 2466 newlun &= SBIC_TLUN_MASK; 2467 CSR_TRACE('r',csr,asr,newtarget); 2468 } else { 2469 /* Need to get IFY message */ 2470 for (newlun = 256; newlun; --newlun) { 2471 GET_SBIC_asr(regs, asr); 2472 if (asr & SBIC_ASR_INT) 2473 break; 2474 delay(1); 2475 } 2476 newlun = 0; /* XXXX */ 2477 if ((asr & SBIC_ASR_INT) == 0) { 2478 #ifdef DEBUG 2479 if (reselect_debug) 2480 printf("RSLT_NI - no IFFY message? asr %x\n", asr); 2481 #endif 2482 } else { 2483 GET_SBIC_csr(regs,csr); 2484 CSR_TRACE('n',csr,asr,newtarget); 2485 if (csr == (SBIC_CSR_MIS | MESG_IN_PHASE) || 2486 csr == (SBIC_CSR_MIS_1 | MESG_IN_PHASE) || 2487 csr == (SBIC_CSR_MIS_2 | MESG_IN_PHASE)) { 2488 sbicmsgin(dev); 2489 newlun = dev->sc_msg[0] & 7; 2490 } else { 2491 printf("RSLT_NI - not MESG_IN_PHASE %x\n", 2492 csr); 2493 } 2494 } 2495 } 2496 #ifdef DEBUG 2497 if(reselect_debug>1 || (reselect_debug && csr==SBIC_CSR_RSLT_NI)) 2498 printf("sbicnext: reselect %s from targ %d lun %d\n", 2499 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", 2500 newtarget, newlun); 2501 #endif 2502 if (dev->sc_nexus) { 2503 #ifdef DEBUG 2504 if (reselect_debug > 1) 2505 printf("%s: reselect %s with active command\n", 2506 dev->sc_dev.dv_xname, 2507 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY"); 2508 #ifdef DDB 2509 /* Debugger();*/ 2510 #endif 2511 #endif 2512 TAILQ_INSERT_HEAD(&dev->ready_list, dev->sc_nexus, chain); 2513 dev->sc_tinfo[dev->target].lubusy &= ~(1 << dev->lun); 2514 dev->sc_nexus = NULL; 2515 dev->sc_xs = NULL; 2516 } 2517 /* Reload sync values for this target */ 2518 if (dev->sc_sync[newtarget].state == SYNC_DONE) 2519 SET_SBIC_syn(regs, SBIC_SYN (dev->sc_sync[newtarget].offset, 2520 dev->sc_sync[newtarget].period)); 2521 else 2522 SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period)); 2523 for (acb = dev->nexus_list.tqh_first; acb; 2524 acb = acb->chain.tqe_next) { 2525 if (acb->xs->sc_link->scsipi_scsi.target != newtarget || 2526 acb->xs->sc_link->scsipi_scsi.lun != newlun) 2527 continue; 2528 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 2529 dev->sc_nexus = acb; 2530 dev->sc_xs = acb->xs; 2531 dev->sc_flags |= SBICF_SELECTED; 2532 dev->target = newtarget; 2533 dev->lun = newlun; 2534 break; 2535 } 2536 if (acb == NULL) { 2537 printf("%s: reselect %s targ %d not in nexus_list %p\n", 2538 dev->sc_dev.dv_xname, 2539 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", newtarget, 2540 &dev->nexus_list.tqh_first); 2541 panic("bad reselect in sbic"); 2542 } 2543 if (csr == SBIC_CSR_RSLT_IFY) 2544 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2545 break; 2546 2547 default: 2548 abort: 2549 /* 2550 * Something unexpected happened -- deal with it. 2551 */ 2552 printf("sbicnextstate: aborting csr %02x asr %02x\n", csr, asr); 2553 #ifdef DDB 2554 Debugger(); 2555 #endif 2556 #ifdef DEBUG 2557 if( data_pointer_debug > 1 ) 2558 printf("next dmastop: %d(%p:%lx)\n", 2559 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 2560 dev->sc_dmatimo = 0; 2561 #endif 2562 dev->sc_dmastop(dev); 2563 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2564 sbicerror(dev, regs, csr); 2565 sbicabort(dev, regs, "next"); 2566 if (dev->sc_flags & SBICF_INDMA) { 2567 /* 2568 * check for overlapping cache line, flush if so 2569 */ 2570 #if defined(M68040) || defined(M68060) 2571 if (dev->sc_flags & SBICF_DCFLUSH) { 2572 #if 0 2573 printf("sbic: 68040/060 DMA cache flush needs" 2574 "fixing? %x:%x\n", 2575 dev->sc_xs->data, dev->sc_xs->datalen); 2576 #endif 2577 } 2578 #endif 2579 dev->sc_flags &= 2580 ~(SBICF_INDMA | SBICF_DCFLUSH); 2581 #ifdef DEBUG 2582 if( data_pointer_debug > 1 ) 2583 printf("next dmastop: %d(%p:%lx)\n", 2584 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 2585 dev->sc_dmatimo = 0; 2586 #endif 2587 dev->sc_dmastop(dev); 2588 sbic_scsidone(acb, -1); 2589 } 2590 SBIC_TRACE(dev); 2591 return SBIC_STATE_ERROR; 2592 } 2593 2594 SBIC_TRACE(dev); 2595 return(SBIC_STATE_RUNNING); 2596 } 2597 2598 2599 /* 2600 * Check if DMA can not be used with specified buffer 2601 */ 2602 2603 int 2604 sbiccheckdmap(bp, len, mask) 2605 void *bp; 2606 u_long len, mask; 2607 { 2608 u_char *buffer; 2609 u_long phy_buf; 2610 u_long phy_len; 2611 2612 buffer = bp; 2613 2614 if (len == 0) 2615 return(0); 2616 2617 while (len) { 2618 phy_buf = kvtop(buffer); 2619 if (len < (phy_len = NBPG - ((int) buffer & PGOFSET))) 2620 phy_len = len; 2621 if (phy_buf & mask) 2622 return(1); 2623 buffer += phy_len; 2624 len -= phy_len; 2625 } 2626 return(0); 2627 } 2628 2629 int 2630 sbictoscsiperiod(dev, regs, a) 2631 struct sbic_softc *dev; 2632 sbic_regmap_t regs; 2633 int a; 2634 { 2635 unsigned int fs; 2636 2637 /* 2638 * cycle = DIV / (2*CLK) 2639 * DIV = FS+2 2640 * best we can do is 200ns at 20Mhz, 2 cycles 2641 */ 2642 2643 GET_SBIC_myid(regs,fs); 2644 fs = (fs >>6) + 2; /* DIV */ 2645 fs = (fs * 10000) / (dev->sc_clkfreq<<1); /* Cycle, in ns */ 2646 if (a < 2) a = 8; /* map to Cycles */ 2647 return ((fs*a)>>2); /* in 4 ns units */ 2648 } 2649 2650 int 2651 sbicfromscsiperiod(dev, regs, p) 2652 struct sbic_softc *dev; 2653 sbic_regmap_t regs; 2654 int p; 2655 { 2656 register unsigned int fs, ret; 2657 2658 /* Just the inverse of the above */ 2659 2660 GET_SBIC_myid(regs,fs); 2661 fs = (fs >>6) + 2; /* DIV */ 2662 fs = (fs * 10000) / (dev->sc_clkfreq<<1); /* Cycle, in ns */ 2663 2664 ret = p << 2; /* in ns units */ 2665 ret = ret / fs; /* in Cycles */ 2666 if (ret < sbic_min_period) 2667 return(sbic_min_period); 2668 2669 /* verify rounding */ 2670 if (sbictoscsiperiod(dev, regs, ret) < p) 2671 ret++; 2672 return (ret >= 8) ? 0 : ret; 2673 } 2674 2675 #ifdef DEBUG 2676 2677 void 2678 sbicdumpstate() 2679 { 2680 u_char csr, asr; 2681 2682 GET_SBIC_asr(debug_sbic_regs,asr); 2683 GET_SBIC_csr(debug_sbic_regs,csr); 2684 printf("%s: asr:csr(%02x:%02x)->(%02x:%02x)\n", 2685 (routine==1)?"sbicgo": 2686 (routine==2)?"sbicintr": 2687 (routine==3)?"sbicicmd": 2688 (routine==4)?"sbicnext":"unknown", 2689 debug_asr, debug_csr, asr, csr); 2690 2691 } 2692 2693 void 2694 sbictimeout(dev) 2695 struct sbic_softc *dev; 2696 { 2697 int s, asr; 2698 2699 s = splbio(); 2700 if (dev->sc_dmatimo) { 2701 if (dev->sc_dmatimo > 1) { 2702 printf("%s: dma timeout #%d\n", 2703 dev->sc_dev.dv_xname, dev->sc_dmatimo - 1); 2704 GET_SBIC_asr(dev->sc_sbic, asr); 2705 if( asr & SBIC_ASR_INT ) { 2706 /* We need to service a missed IRQ */ 2707 printf("Servicing a missed int:(%02x,%02x)->(%02x,??)\n", 2708 debug_asr, debug_csr, asr); 2709 sbicintr(dev); 2710 } 2711 sbicdumpstate(); 2712 } 2713 dev->sc_dmatimo++; 2714 } 2715 splx(s); 2716 callout_reset(&dev->sc_timo_ch, 30 * hz, 2717 (void *)sbictimeout, dev); 2718 } 2719 2720 void 2721 sbic_dump_acb(acb) 2722 struct sbic_acb *acb; 2723 { 2724 u_char *b = (u_char *) &acb->cmd; 2725 int i; 2726 2727 printf("acb@%p ", acb); 2728 if (acb->xs == NULL) { 2729 printf("<unused>\n"); 2730 return; 2731 } 2732 printf("(%d:%d) flags %2x clen %2d cmd ", 2733 acb->xs->sc_link->scsipi_scsi.target, 2734 acb->xs->sc_link->scsipi_scsi.lun, acb->flags, acb->clen); 2735 for (i = acb->clen; i; --i) 2736 printf(" %02x", *b++); 2737 printf("\n"); 2738 printf(" xs: %8p data %8p:%04x ", acb->xs, acb->xs->data, 2739 acb->xs->datalen); 2740 printf("va %8p:%04x ", acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 2741 printf("pa %8p:%04x tcnt %lx\n", acb->sc_pa.dc_addr, acb->sc_pa.dc_count, 2742 acb->sc_tcnt); 2743 } 2744 2745 void 2746 sbic_dump(dev) 2747 struct sbic_softc *dev; 2748 { 2749 sbic_regmap_t regs; 2750 u_char csr, asr; 2751 struct sbic_acb *acb; 2752 int s; 2753 int i; 2754 2755 s = splbio(); 2756 regs = dev->sc_sbic; 2757 #if CSR_TRACE_SIZE 2758 printf("csr trace: "); 2759 i = csr_traceptr; 2760 do { 2761 printf("%c%02x%02x%02x ", csr_trace[i].whr, 2762 csr_trace[i].csr, csr_trace[i].asr, csr_trace[i].xtn); 2763 switch(csr_trace[i].whr) { 2764 case 'g': 2765 printf("go "); break; 2766 case 's': 2767 printf("select "); break; 2768 case 'y': 2769 printf("select+ "); break; 2770 case 'i': 2771 printf("intr "); break; 2772 case 'f': 2773 printf("finish "); break; 2774 case '>': 2775 printf("out "); break; 2776 case '<': 2777 printf("in "); break; 2778 case 'm': 2779 printf("msgin "); break; 2780 case 'x': 2781 printf("msginx "); break; 2782 case 'X': 2783 printf("msginX "); break; 2784 case 'r': 2785 printf("reselect "); break; 2786 case 'I': 2787 printf("icmd "); break; 2788 case 'a': 2789 printf("abort "); break; 2790 default: 2791 printf("? "); 2792 } 2793 switch(csr_trace[i].csr) { 2794 case 0x11: 2795 printf("INITIATOR"); break; 2796 case 0x16: 2797 printf("S_XFERRED"); break; 2798 case 0x20: 2799 printf("MSGIN_ACK"); break; 2800 case 0x41: 2801 printf("DISC"); break; 2802 case 0x42: 2803 printf("SEL_TIMEO"); break; 2804 case 0x80: 2805 printf("RSLT_NI"); break; 2806 case 0x81: 2807 printf("RSLT_IFY"); break; 2808 case 0x85: 2809 printf("DISC_1"); break; 2810 case 0x18: case 0x19: case 0x1a: 2811 case 0x1b: case 0x1e: case 0x1f: 2812 case 0x28: case 0x29: case 0x2a: 2813 case 0x2b: case 0x2e: case 0x2f: 2814 case 0x48: case 0x49: case 0x4a: 2815 case 0x4b: case 0x4e: case 0x4f: 2816 case 0x88: case 0x89: case 0x8a: 2817 case 0x8b: case 0x8e: case 0x8f: 2818 switch(csr_trace[i].csr & 0xf0) { 2819 case 0x10: 2820 printf("DONE_"); break; 2821 case 0x20: 2822 printf("STOP_"); break; 2823 case 0x40: 2824 printf("ERR_"); break; 2825 case 0x80: 2826 printf("REQ_"); break; 2827 } 2828 switch(csr_trace[i].csr & 7) { 2829 case 0: 2830 printf("DATA_OUT"); break; 2831 case 1: 2832 printf("DATA_IN"); break; 2833 case 2: 2834 printf("CMD"); break; 2835 case 3: 2836 printf("STATUS"); break; 2837 case 6: 2838 printf("MSG_OUT"); break; 2839 case 7: 2840 printf("MSG_IN"); break; 2841 default: 2842 printf("invld phs"); 2843 } 2844 break; 2845 default: printf("****"); break; 2846 } 2847 if (csr_trace[i].asr & SBIC_ASR_INT) 2848 printf(" ASR_INT"); 2849 if (csr_trace[i].asr & SBIC_ASR_LCI) 2850 printf(" ASR_LCI"); 2851 if (csr_trace[i].asr & SBIC_ASR_BSY) 2852 printf(" ASR_BSY"); 2853 if (csr_trace[i].asr & SBIC_ASR_CIP) 2854 printf(" ASR_CIP"); 2855 printf("\n"); 2856 i = (i + 1) & (CSR_TRACE_SIZE - 1); 2857 } while (i != csr_traceptr); 2858 #endif 2859 GET_SBIC_asr(regs, asr); 2860 if ((asr & SBIC_ASR_INT) == 0) 2861 GET_SBIC_csr(regs, csr); 2862 else 2863 csr = 0; 2864 printf("%s@%p regs %p/%p asr %x csr %x\n", dev->sc_dev.dv_xname, 2865 dev, regs.sbic_asr_p, regs.sbic_value_p, asr, csr); 2866 if ((acb = dev->free_list.tqh_first)) { 2867 printf("Free list:\n"); 2868 while (acb) { 2869 sbic_dump_acb(acb); 2870 acb = acb->chain.tqe_next; 2871 } 2872 } 2873 if ((acb = dev->ready_list.tqh_first)) { 2874 printf("Ready list:\n"); 2875 while (acb) { 2876 sbic_dump_acb(acb); 2877 acb = acb->chain.tqe_next; 2878 } 2879 } 2880 if ((acb = dev->nexus_list.tqh_first)) { 2881 printf("Nexus list:\n"); 2882 while (acb) { 2883 sbic_dump_acb(acb); 2884 acb = acb->chain.tqe_next; 2885 } 2886 } 2887 if (dev->sc_nexus) { 2888 printf("nexus:\n"); 2889 sbic_dump_acb(dev->sc_nexus); 2890 } 2891 printf("sc_xs %p targ %d lun %d flags %x tcnt %lx dmacmd %x mask %lx\n", 2892 dev->sc_xs, dev->target, dev->lun, dev->sc_flags, dev->sc_tcnt, 2893 dev->sc_dmacmd, dev->sc_dmamask); 2894 for (i = 0; i < 8; ++i) { 2895 if (dev->sc_tinfo[i].cmds > 2) { 2896 printf("tgt %d: cmds %d disc %d senses %d lubusy %x\n", 2897 i, dev->sc_tinfo[i].cmds, 2898 dev->sc_tinfo[i].dconns, 2899 dev->sc_tinfo[i].senses, 2900 dev->sc_tinfo[i].lubusy); 2901 } 2902 } 2903 splx(s); 2904 } 2905 2906 #endif 2907
Indexes created Fri Sep 26 20:09:58 GMT 2025