sbic.c revision 1.41
1 /* $NetBSD: sbic.c,v 1.41 2000/06/27 04:18:52 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 1994 Christian E. Hopps 5 * Copyright (c) 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * Van Jacobson of Lawrence Berkeley Laboratory. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the University of 22 * California, Berkeley and its contributors. 23 * 4. Neither the name of the University nor the names of its contributors 24 * may be used to endorse or promote products derived from this software 25 * without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 37 * SUCH DAMAGE. 38 * 39 * @(#)scsi.c 7.5 (Berkeley) 5/4/91 40 */ 41 42 /* 43 * AMIGA AMD 33C93 scsi adaptor driver 44 */ 45 46 #include "opt_ddb.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/device.h> 51 #include <sys/kernel.h> /* For hz */ 52 #include <sys/disklabel.h> 53 #include <sys/dkstat.h> 54 #include <sys/buf.h> 55 #include <dev/scsipi/scsi_all.h> 56 #include <dev/scsipi/scsipi_all.h> 57 #include <dev/scsipi/scsiconf.h> 58 #include <vm/vm.h> 59 #include <uvm/uvm_extern.h> 60 #include <machine/cpu.h> 61 #include <amiga/amiga/device.h> 62 #include <amiga/amiga/custom.h> 63 #include <amiga/amiga/isr.h> 64 #include <amiga/dev/dmavar.h> 65 #include <amiga/dev/sbicreg.h> 66 #include <amiga/dev/sbicvar.h> 67 68 /* These are for bounce buffers */ 69 #include <amiga/amiga/cc.h> 70 #include <amiga/dev/zbusvar.h> 71 72 /* Since I can't find this in any other header files */ 73 #define SCSI_PHASE(reg) (reg&0x07) 74 75 /* 76 * SCSI delays 77 * In u-seconds, primarily for state changes on the SPC. 78 */ 79 #define SBIC_CMD_WAIT 50000 /* wait per step of 'immediate' cmds */ 80 #define SBIC_DATA_WAIT 50000 /* wait per data in/out step */ 81 #define SBIC_INIT_WAIT 50000 /* wait per step (both) during init */ 82 83 #define SBIC_WAIT(regs, until, timeo) sbicwait(regs, until, timeo, __LINE__) 84 85 int sbicicmd __P((struct sbic_softc *, int, int, void *, int, void *, int)); 86 int sbicgo __P((struct sbic_softc *, struct scsipi_xfer *)); 87 int sbicdmaok __P((struct sbic_softc *, struct scsipi_xfer *)); 88 int sbicwait __P((sbic_regmap_t, char, int , int)); 89 int sbiccheckdmap __P((void *, u_long, u_long)); 90 int sbicselectbus __P((struct sbic_softc *, sbic_regmap_t, u_char, u_char, u_char)); 91 int sbicxfstart __P((sbic_regmap_t, int, u_char, int)); 92 int sbicxfout __P((sbic_regmap_t regs, int, void *, int)); 93 int sbicfromscsiperiod __P((struct sbic_softc *, sbic_regmap_t, int)); 94 int sbictoscsiperiod __P((struct sbic_softc *, sbic_regmap_t, int)); 95 int sbicpoll __P((struct sbic_softc *)); 96 int sbicnextstate __P((struct sbic_softc *, u_char, u_char)); 97 int sbicmsgin __P((struct sbic_softc *)); 98 int sbicxfin __P((sbic_regmap_t regs, int, void *)); 99 int sbicabort __P((struct sbic_softc *, sbic_regmap_t, char *)); 100 void sbicxfdone __P((struct sbic_softc *, sbic_regmap_t, int)); 101 void sbicerror __P((struct sbic_softc *, sbic_regmap_t, u_char)); 102 void sbicstart __P((struct sbic_softc *)); 103 void sbicreset __P((struct sbic_softc *)); 104 void sbic_scsidone __P((struct sbic_acb *, int)); 105 void sbic_sched __P((struct sbic_softc *)); 106 void sbic_save_ptrs __P((struct sbic_softc *, sbic_regmap_t,int,int)); 107 void sbic_load_ptrs __P((struct sbic_softc *, sbic_regmap_t,int,int)); 108 #ifdef DEBUG 109 void sbicdumpstate __P((void)); 110 void sbic_dump_acb __P((struct sbic_acb *)); 111 #endif 112 113 /* 114 * Synch xfer parameters, and timing conversions 115 */ 116 int sbic_min_period = SBIC_SYN_MIN_PERIOD; /* in cycles = f(ICLK,FSn) */ 117 int sbic_max_offset = SBIC_SYN_MAX_OFFSET; /* pure number */ 118 119 int sbic_cmd_wait = SBIC_CMD_WAIT; 120 int sbic_data_wait = SBIC_DATA_WAIT; 121 int sbic_init_wait = SBIC_INIT_WAIT; 122 123 /* 124 * was broken before.. now if you want this you get it for all drives 125 * on sbic controllers. 126 */ 127 u_char sbic_inhibit_sync[8]; 128 int sbic_enable_reselect = 1; 129 int sbic_clock_override = 0; 130 int sbic_no_dma = 0; 131 int sbic_parallel_operations = 1; 132 133 #ifdef DEBUG 134 sbic_regmap_t debug_sbic_regs; 135 int sbicdma_ops = 0; /* total DMA operations */ 136 int sbicdma_bounces = 0; /* number operations using bounce buffer */ 137 int sbicdma_hits = 0; /* number of DMA chains that were contiguous */ 138 int sbicdma_misses = 0; /* number of DMA chains that were not contiguous */ 139 int sbicdma_saves = 0; 140 #define QPRINTF(a) if (sbic_debug > 1) printf a 141 int sbic_debug = 0; 142 int sync_debug = 0; 143 int sbic_dma_debug = 0; 144 int reselect_debug = 0; 145 int report_sense = 0; 146 int data_pointer_debug = 0; 147 u_char debug_asr, debug_csr, routine; 148 void sbictimeout __P((struct sbic_softc *dev)); 149 150 #define CSR_TRACE_SIZE 32 151 #if CSR_TRACE_SIZE 152 #define CSR_TRACE(w,c,a,x) do { \ 153 int s = splbio(); \ 154 csr_trace[csr_traceptr].whr = (w); csr_trace[csr_traceptr].csr = (c); \ 155 csr_trace[csr_traceptr].asr = (a); csr_trace[csr_traceptr].xtn = (x); \ 156 dma_cachectl((caddr_t)&csr_trace[csr_traceptr], sizeof(csr_trace[0])); \ 157 csr_traceptr = (csr_traceptr + 1) & (CSR_TRACE_SIZE - 1); \ 158 /* dma_cachectl((caddr_t)&csr_traceptr, sizeof(csr_traceptr));*/ \ 159 splx(s); \ 160 } while (0) 161 int csr_traceptr; 162 int csr_tracesize = CSR_TRACE_SIZE; 163 struct { 164 u_char whr; 165 u_char csr; 166 u_char asr; 167 u_char xtn; 168 } csr_trace[CSR_TRACE_SIZE]; 169 #else 170 #define CSR_TRACE(w,c,a,x) 171 #endif 172 173 #define SBIC_TRACE_SIZE 0 174 #if SBIC_TRACE_SIZE 175 #define SBIC_TRACE(dev) do { \ 176 int s = splbio(); \ 177 sbic_trace[sbic_traceptr].sp = &s; \ 178 sbic_trace[sbic_traceptr].line = __LINE__; \ 179 sbic_trace[sbic_traceptr].sr = s; \ 180 sbic_trace[sbic_traceptr].csr = csr_traceptr; \ 181 dma_cachectl(&sbic_trace[sbic_traceptr], sizeof(sbic_trace[0])); \ 182 sbic_traceptr = (sbic_traceptr + 1) & (SBIC_TRACE_SIZE - 1); \ 183 dma_cachectl(&sbic_traceptr, sizeof(sbic_traceptr)); \ 184 if (dev) dma_cachectl(dev, sizeof(*dev)); \ 185 splx(s); \ 186 } while (0) 187 int sbic_traceptr; 188 int sbic_tracesize = SBIC_TRACE_SIZE; 189 struct { 190 void *sp; 191 u_short line; 192 u_short sr; 193 int csr; 194 } sbic_trace[SBIC_TRACE_SIZE]; 195 #else 196 #define SBIC_TRACE(dev) 197 #endif 198 199 #else /* DEBUG */ 200 #define QPRINTF(a) 201 #define CSR_TRACE(w,c,a,x) 202 #define SBIC_TRACE(dev) 203 #endif /* DEBUG */ 204 205 /* 206 * default minphys routine for sbic based controllers 207 */ 208 void 209 sbic_minphys(bp) 210 struct buf *bp; 211 { 212 213 /* 214 * No max transfer at this level. 215 */ 216 minphys(bp); 217 } 218 219 /* 220 * Save DMA pointers. Take into account partial transfer. Shut down DMA. 221 */ 222 void 223 sbic_save_ptrs(dev, regs, target, lun) 224 struct sbic_softc *dev; 225 sbic_regmap_t regs; 226 int target, lun; 227 { 228 int count, asr, s; 229 struct sbic_acb* acb; 230 231 SBIC_TRACE(dev); 232 if( !dev->sc_cur ) return; 233 if( !(dev->sc_flags & SBICF_INDMA) ) return; /* DMA not active */ 234 235 s = splbio(); 236 237 acb = dev->sc_nexus; 238 count = -1; 239 do { 240 GET_SBIC_asr(regs, asr); 241 if( asr & SBIC_ASR_DBR ) { 242 printf("sbic_save_ptrs: asr %02x canceled!\n", asr); 243 splx(s); 244 SBIC_TRACE(dev); 245 return; 246 } 247 } while( asr & (SBIC_ASR_BSY|SBIC_ASR_CIP) ); 248 249 /* Save important state */ 250 /* must be done before dmastop */ 251 acb->sc_dmacmd = dev->sc_dmacmd; 252 SBIC_TC_GET(regs, count); 253 254 /* Shut down DMA ====CAREFUL==== */ 255 dev->sc_dmastop(dev); 256 dev->sc_flags &= ~SBICF_INDMA; 257 SBIC_TC_PUT(regs, 0); 258 259 #ifdef DEBUG 260 if(!count && sbic_debug) printf("%dcount0",target); 261 if(data_pointer_debug == -1) 262 printf("SBIC saving target %d data pointers from (%p,%x)%xASR:%02x", 263 target, dev->sc_cur->dc_addr, dev->sc_cur->dc_count, 264 acb->sc_dmacmd, asr); 265 #endif 266 267 /* Fixup partial xfers */ 268 acb->sc_kv.dc_addr += (dev->sc_tcnt - count); 269 acb->sc_kv.dc_count -= (dev->sc_tcnt - count); 270 acb->sc_pa.dc_addr += (dev->sc_tcnt - count); 271 acb->sc_pa.dc_count -= ((dev->sc_tcnt - count)>>1); 272 273 acb->sc_tcnt = dev->sc_tcnt = count; 274 #ifdef DEBUG 275 if(data_pointer_debug) 276 printf(" at (%p,%x):%x\n", 277 dev->sc_cur->dc_addr, dev->sc_cur->dc_count,count); 278 sbicdma_saves++; 279 #endif 280 splx(s); 281 SBIC_TRACE(dev); 282 } 283 284 285 /* 286 * DOES NOT RESTART DMA!!! 287 */ 288 void sbic_load_ptrs(dev, regs, target, lun) 289 struct sbic_softc *dev; 290 sbic_regmap_t regs; 291 int target, lun; 292 { 293 int s, count; 294 char* vaddr, * paddr; 295 struct sbic_acb *acb; 296 297 SBIC_TRACE(dev); 298 acb = dev->sc_nexus; 299 if( !acb->sc_kv.dc_count ) { 300 /* No data to xfer */ 301 SBIC_TRACE(dev); 302 return; 303 } 304 305 s = splbio(); 306 307 dev->sc_last = dev->sc_cur = &acb->sc_pa; 308 dev->sc_tcnt = acb->sc_tcnt; 309 dev->sc_dmacmd = acb->sc_dmacmd; 310 311 #ifdef DEBUG 312 sbicdma_ops++; 313 #endif 314 if( !dev->sc_tcnt ) { 315 /* sc_tcnt == 0 implies end of segment */ 316 317 /* do kvm to pa mappings */ 318 paddr = acb->sc_pa.dc_addr = 319 (char *) kvtop(acb->sc_kv.dc_addr); 320 321 vaddr = acb->sc_kv.dc_addr; 322 count = acb->sc_kv.dc_count; 323 for(count = (NBPG - ((int)vaddr & PGOFSET)); 324 count < acb->sc_kv.dc_count 325 && (char*)kvtop(vaddr + count + 4) == paddr + count + 4; 326 count += NBPG); 327 /* If it's all contiguous... */ 328 if(count > acb->sc_kv.dc_count ) { 329 count = acb->sc_kv.dc_count; 330 #ifdef DEBUG 331 sbicdma_hits++; 332 #endif 333 } else { 334 #ifdef DEBUG 335 sbicdma_misses++; 336 #endif 337 } 338 acb->sc_tcnt = count; 339 acb->sc_pa.dc_count = count >> 1; 340 341 #ifdef DEBUG 342 if(data_pointer_debug) 343 printf("DMA recalc:kv(%p,%x)pa(%p,%lx)\n", 344 acb->sc_kv.dc_addr, 345 acb->sc_kv.dc_count, 346 acb->sc_pa.dc_addr, 347 acb->sc_tcnt); 348 #endif 349 } 350 splx(s); 351 #ifdef DEBUG 352 if(data_pointer_debug) 353 printf("SBIC restoring target %d data pointers at (%p,%x)%x\n", 354 target, dev->sc_cur->dc_addr, dev->sc_cur->dc_count, 355 dev->sc_dmacmd); 356 #endif 357 SBIC_TRACE(dev); 358 } 359 360 /* 361 * used by specific sbic controller 362 * 363 * it appears that the higher level code does nothing with LUN's 364 * so I will too. I could plug it in, however so could they 365 * in scsi_scsipi_cmd(). 366 */ 367 int 368 sbic_scsicmd(xs) 369 struct scsipi_xfer *xs; 370 { 371 struct sbic_acb *acb; 372 struct sbic_softc *dev; 373 struct scsipi_link *slp; 374 int flags, s, stat; 375 376 slp = xs->sc_link; 377 dev = slp->adapter_softc; 378 SBIC_TRACE(dev); 379 flags = xs->xs_control; 380 381 if (flags & XS_CTL_DATA_UIO) 382 panic("sbic: scsi data uio requested"); 383 384 if (dev->sc_nexus && flags & XS_CTL_POLL) 385 panic("sbic_scsicmd: busy"); 386 387 if (slp->scsipi_scsi.target == slp->scsipi_scsi.adapter_target) 388 return ESCAPE_NOT_SUPPORTED; 389 390 s = splbio(); 391 acb = dev->free_list.tqh_first; 392 if (acb) 393 TAILQ_REMOVE(&dev->free_list, acb, chain); 394 splx(s); 395 396 if (acb == NULL) { 397 #ifdef DEBUG 398 printf("sbic_scsicmd: unable to queue request for target %d\n", 399 slp->scsipi_scsi.target); 400 #ifdef DDB 401 Debugger(); 402 #endif 403 #endif 404 xs->error = XS_DRIVER_STUFFUP; 405 SBIC_TRACE(dev); 406 return(TRY_AGAIN_LATER); 407 } 408 409 acb->flags = ACB_ACTIVE; 410 if (flags & XS_CTL_DATA_IN) 411 acb->flags |= ACB_DATAIN; 412 acb->xs = xs; 413 bcopy(xs->cmd, &acb->cmd, xs->cmdlen); 414 acb->clen = xs->cmdlen; 415 acb->sc_kv.dc_addr = xs->data; 416 acb->sc_kv.dc_count = xs->datalen; 417 acb->pa_addr = xs->data ? (char *)kvtop(xs->data) : 0; /* XXXX check */ 418 419 if (flags & XS_CTL_POLL) { 420 s = splbio(); 421 /* 422 * This has major side effects -- it locks up the machine 423 */ 424 425 dev->sc_flags |= SBICF_ICMD; 426 do { 427 while(dev->sc_nexus) 428 sbicpoll(dev); 429 dev->sc_nexus = acb; 430 dev->sc_stat[0] = -1; 431 dev->sc_xs = xs; 432 dev->target = slp->scsipi_scsi.target; 433 dev->lun = slp->scsipi_scsi.lun; 434 stat = sbicicmd(dev, slp->scsipi_scsi.target, slp->scsipi_scsi.lun, 435 &acb->cmd, acb->clen, 436 acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 437 } while (dev->sc_nexus != acb); 438 sbic_scsidone(acb, stat); 439 440 splx(s); 441 SBIC_TRACE(dev); 442 return(COMPLETE); 443 } 444 445 s = splbio(); 446 TAILQ_INSERT_TAIL(&dev->ready_list, acb, chain); 447 448 if (dev->sc_nexus) { 449 splx(s); 450 SBIC_TRACE(dev); 451 return(SUCCESSFULLY_QUEUED); 452 } 453 454 /* 455 * nothing is active, try to start it now. 456 */ 457 sbic_sched(dev); 458 splx(s); 459 460 SBIC_TRACE(dev); 461 /* TODO: add sbic_poll to do XS_CTL_POLL operations */ 462 #if 0 463 if (flags & XS_CTL_POLL) 464 return(COMPLETE); 465 #endif 466 return(SUCCESSFULLY_QUEUED); 467 } 468 469 /* 470 * attempt to start the next available command 471 */ 472 void 473 sbic_sched(dev) 474 struct sbic_softc *dev; 475 { 476 struct scsipi_xfer *xs; 477 struct scsipi_link *slp; 478 struct sbic_acb *acb; 479 int flags, /*phase,*/ stat, i; 480 481 SBIC_TRACE(dev); 482 if (dev->sc_nexus) 483 return; /* a command is current active */ 484 485 SBIC_TRACE(dev); 486 for (acb = dev->ready_list.tqh_first; acb; acb = acb->chain.tqe_next) { 487 slp = acb->xs->sc_link; 488 i = slp->scsipi_scsi.target; 489 if (!(dev->sc_tinfo[i].lubusy & (1 << slp->scsipi_scsi.lun))) { 490 struct sbic_tinfo *ti = &dev->sc_tinfo[i]; 491 492 TAILQ_REMOVE(&dev->ready_list, acb, chain); 493 dev->sc_nexus = acb; 494 slp = acb->xs->sc_link; 495 ti = &dev->sc_tinfo[slp->scsipi_scsi.target]; 496 ti->lubusy |= (1 << slp->scsipi_scsi.lun); 497 acb->sc_pa.dc_addr = acb->pa_addr; /* XXXX check */ 498 break; 499 } 500 } 501 502 SBIC_TRACE(dev); 503 if (acb == NULL) 504 return; /* did not find an available command */ 505 506 dev->sc_xs = xs = acb->xs; 507 slp = xs->sc_link; 508 flags = xs->xs_control; 509 510 if (flags & XS_CTL_RESET) 511 sbicreset(dev); 512 513 #ifdef DEBUG 514 if( data_pointer_debug > 1 ) 515 printf("sbic_sched(%d,%d)\n",slp->scsipi_scsi.target, 516 slp->scsipi_scsi.lun); 517 #endif 518 dev->sc_stat[0] = -1; 519 dev->target = slp->scsipi_scsi.target; 520 dev->lun = slp->scsipi_scsi.lun; 521 if ( flags & XS_CTL_POLL || ( !sbic_parallel_operations 522 && (sbicdmaok(dev, xs) == 0))) 523 stat = sbicicmd(dev, slp->scsipi_scsi.target, 524 slp->scsipi_scsi.lun, &acb->cmd, 525 acb->clen, acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 526 else if (sbicgo(dev, xs) == 0 && xs->error != XS_SELTIMEOUT) { 527 SBIC_TRACE(dev); 528 return; 529 } else 530 stat = dev->sc_stat[0]; 531 532 sbic_scsidone(acb, stat); 533 SBIC_TRACE(dev); 534 } 535 536 void 537 sbic_scsidone(acb, stat) 538 struct sbic_acb *acb; 539 int stat; 540 { 541 struct scsipi_xfer *xs; 542 struct scsipi_link *slp; 543 struct sbic_softc *dev; 544 int dosched = 0; 545 546 xs = acb->xs; 547 slp = xs->sc_link; 548 dev = slp->adapter_softc; 549 SBIC_TRACE(dev); 550 #ifdef DIAGNOSTIC 551 if (acb == NULL || xs == NULL) { 552 printf("sbic_scsidone -- (%d,%d) no scsi_xfer\n", 553 dev->target, dev->lun); 554 #ifdef DDB 555 Debugger(); 556 #endif 557 return; 558 } 559 #endif 560 /* 561 * is this right? 562 */ 563 xs->status = stat; 564 565 #ifdef DEBUG 566 if( data_pointer_debug > 1 ) 567 printf("scsidone: (%d,%d)->(%d,%d)%02x\n", 568 slp->scsipi_scsi.target, slp->scsipi_scsi.lun, 569 dev->target, dev->lun, stat); 570 if( xs->sc_link->scsipi_scsi.target == 571 dev->sc_link.scsipi_scsi.adapter_target ) 572 panic("target == hostid"); 573 #endif 574 575 if (xs->error == XS_NOERROR && !(acb->flags & ACB_CHKSENSE)) { 576 if (stat == SCSI_CHECK) { 577 /* Schedule a REQUEST SENSE */ 578 struct scsipi_sense *ss = (void *)&acb->cmd; 579 #ifdef DEBUG 580 if (report_sense) 581 printf("sbic_scsidone: autosense %02x targ %d lun %d", 582 acb->cmd.opcode, slp->scsipi_scsi.target, 583 slp->scsipi_scsi.lun); 584 #endif 585 bzero(ss, sizeof(*ss)); 586 ss->opcode = REQUEST_SENSE; 587 ss->byte2 = slp->scsipi_scsi.lun << 5; 588 ss->length = sizeof(struct scsipi_sense_data); 589 acb->clen = sizeof(*ss); 590 acb->sc_kv.dc_addr = (char *)&xs->sense.scsi_sense; 591 acb->sc_kv.dc_count = sizeof(struct scsipi_sense_data); 592 acb->pa_addr = (char *)kvtop((u_char *)&xs->sense.scsi_sense); /* XXX check */ 593 acb->flags = ACB_ACTIVE | ACB_CHKSENSE | ACB_DATAIN; 594 TAILQ_INSERT_HEAD(&dev->ready_list, acb, chain); 595 dev->sc_tinfo[slp->scsipi_scsi.target].lubusy &= 596 ~(1 << slp->scsipi_scsi.lun); 597 dev->sc_tinfo[slp->scsipi_scsi.target].senses++; 598 if (dev->sc_nexus == acb) { 599 dev->sc_nexus = NULL; 600 dev->sc_xs = NULL; 601 sbic_sched(dev); 602 } 603 SBIC_TRACE(dev); 604 return; 605 } 606 } 607 if (xs->error == XS_NOERROR && (acb->flags & ACB_CHKSENSE)) { 608 xs->error = XS_SENSE; 609 #ifdef DEBUG 610 if (report_sense) 611 printf(" => %02x %02x\n", xs->sense.scsi_sense.flags, 612 xs->sense.scsi_sense.extra_bytes[3]); 613 #endif 614 } else { 615 xs->resid = 0; /* XXXX */ 616 } 617 #if whataboutthisone 618 case SCSI_BUSY: 619 xs->error = XS_BUSY; 620 break; 621 #endif 622 xs->xs_status |= XS_STS_DONE; 623 624 /* 625 * Remove the ACB from whatever queue it's on. We have to do a bit of 626 * a hack to figure out which queue it's on. Note that it is *not* 627 * necessary to cdr down the ready queue, but we must cdr down the 628 * nexus queue and see if it's there, so we can mark the unit as no 629 * longer busy. This code is sickening, but it works. 630 */ 631 if (acb == dev->sc_nexus) { 632 dev->sc_nexus = NULL; 633 dev->sc_xs = NULL; 634 dev->sc_tinfo[slp->scsipi_scsi.target].lubusy &= 635 ~(1<<slp->scsipi_scsi.lun); 636 if (dev->ready_list.tqh_first) 637 dosched = 1; /* start next command */ 638 } else if (dev->ready_list.tqh_last == &acb->chain.tqe_next) { 639 TAILQ_REMOVE(&dev->ready_list, acb, chain); 640 } else { 641 register struct sbic_acb *acb2; 642 for (acb2 = dev->nexus_list.tqh_first; acb2; 643 acb2 = acb2->chain.tqe_next) { 644 if (acb2 == acb) { 645 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 646 dev->sc_tinfo[slp->scsipi_scsi.target].lubusy 647 &= ~(1<<slp->scsipi_scsi.lun); 648 break; 649 } 650 } 651 if (acb2) 652 ; 653 else if (acb->chain.tqe_next) { 654 TAILQ_REMOVE(&dev->ready_list, acb, chain); 655 } else { 656 printf("%s: can't find matching acb\n", 657 dev->sc_dev.dv_xname); 658 #ifdef DDB 659 Debugger(); 660 #endif 661 } 662 } 663 /* Put it on the free list. */ 664 acb->flags = ACB_FREE; 665 TAILQ_INSERT_HEAD(&dev->free_list, acb, chain); 666 667 dev->sc_tinfo[slp->scsipi_scsi.target].cmds++; 668 669 scsipi_done(xs); 670 671 if (dosched) 672 sbic_sched(dev); 673 SBIC_TRACE(dev); 674 } 675 676 int 677 sbicdmaok(dev, xs) 678 struct sbic_softc *dev; 679 struct scsipi_xfer *xs; 680 { 681 if (sbic_no_dma || !xs->datalen || xs->datalen & 0x1 || 682 (u_int)xs->data & 0x3) 683 return(0); 684 /* 685 * controller supports dma to any addresses? 686 */ 687 else if ((dev->sc_flags & SBICF_BADDMA) == 0) 688 return(1); 689 /* 690 * this address is ok for dma? 691 */ 692 else if (sbiccheckdmap(xs->data, xs->datalen, dev->sc_dmamask) == 0) 693 return(1); 694 /* 695 * we have a bounce buffer? 696 */ 697 else if (dev->sc_tinfo[xs->sc_link->scsipi_scsi.target].bounce) 698 return(1); 699 /* 700 * try to get one 701 */ 702 else if ((dev->sc_tinfo[xs->sc_link->scsipi_scsi.target].bounce 703 = (char *)alloc_z2mem(MAXPHYS))) { 704 if (isztwomem(dev->sc_tinfo[xs->sc_link->scsipi_scsi.target].bounce)) 705 printf("alloc ZII target %d bounce pa 0x%x\n", 706 xs->sc_link->scsipi_scsi.target, 707 kvtop(dev->sc_tinfo[xs->sc_link->scsipi_scsi.target].bounce)); 708 else if (dev->sc_tinfo[xs->sc_link->scsipi_scsi.target].bounce) 709 printf("alloc CHIP target %d bounce pa 0x%p\n", 710 xs->sc_link->scsipi_scsi.target, 711 PREP_DMA_MEM(dev->sc_tinfo[xs->sc_link->scsipi_scsi.target].bounce)); 712 return(1); 713 } 714 715 return(0); 716 } 717 718 719 int 720 sbicwait(regs, until, timeo, line) 721 sbic_regmap_t regs; 722 char until; 723 int timeo; 724 int line; 725 { 726 u_char val; 727 int csr; 728 729 SBIC_TRACE((struct sbic_softc *)0); 730 if (timeo == 0) 731 timeo = 1000000; /* some large value.. */ 732 733 GET_SBIC_asr(regs,val); 734 while ((val & until) == 0) { 735 if (timeo-- == 0) { 736 GET_SBIC_csr(regs, csr); 737 printf("sbicwait TIMEO @%d with asr=x%x csr=x%x\n", 738 line, val, csr); 739 #if defined(DDB) && defined(DEBUG) 740 Debugger(); 741 #endif 742 return(val); /* Maybe I should abort */ 743 break; 744 } 745 DELAY(1); 746 GET_SBIC_asr(regs,val); 747 } 748 SBIC_TRACE((struct sbic_softc *)0); 749 return(val); 750 } 751 752 int 753 sbicabort(dev, regs, where) 754 struct sbic_softc *dev; 755 sbic_regmap_t regs; 756 char *where; 757 { 758 u_char csr, asr; 759 760 GET_SBIC_asr(regs, asr); 761 GET_SBIC_csr(regs, csr); 762 763 printf ("%s: abort %s: csr = 0x%02x, asr = 0x%02x\n", 764 dev->sc_dev.dv_xname, where, csr, asr); 765 766 767 #if 0 768 /* Clean up running command */ 769 if (dev->sc_nexus != NULL) { 770 dev->sc_nexus->xs->error = XS_DRIVER_STUFFUP; 771 sbic_scsidone(dev->sc_nexus, dev->sc_stat[0]); 772 } 773 while (acb = dev->nexus_list.tqh_first) { 774 acb->xs->error = XS_DRIVER_STUFFUP; 775 sbic_scsidone(acb, -1 /*acb->stat[0]*/); 776 } 777 #endif 778 779 /* Clean up chip itself */ 780 if (dev->sc_flags & SBICF_SELECTED) { 781 while( asr & SBIC_ASR_DBR ) { 782 /* sbic is jammed w/data. need to clear it */ 783 /* But we don't know what direction it needs to go */ 784 GET_SBIC_data(regs, asr); 785 printf("%s: abort %s: clearing data buffer 0x%02x\n", 786 dev->sc_dev.dv_xname, where, asr); 787 GET_SBIC_asr(regs, asr); 788 if( asr & SBIC_ASR_DBR ) /* Not the read direction, then */ 789 SET_SBIC_data(regs, asr); 790 GET_SBIC_asr(regs, asr); 791 } 792 WAIT_CIP(regs); 793 printf("%s: sbicabort - sending ABORT command\n", dev->sc_dev.dv_xname); 794 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 795 WAIT_CIP(regs); 796 797 GET_SBIC_asr(regs, asr); 798 if (asr & (SBIC_ASR_BSY|SBIC_ASR_LCI)) { 799 /* ok, get more drastic.. */ 800 801 printf("%s: sbicabort - asr %x, trying to reset\n", dev->sc_dev.dv_xname, asr); 802 sbicreset(dev); 803 dev->sc_flags &= ~SBICF_SELECTED; 804 return -1; 805 } 806 printf("%s: sbicabort - sending DISC command\n", dev->sc_dev.dv_xname); 807 SET_SBIC_cmd(regs, SBIC_CMD_DISC); 808 809 do { 810 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0); 811 GET_SBIC_csr (regs, csr); 812 CSR_TRACE('a',csr,asr,0); 813 } while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) 814 && (csr != SBIC_CSR_CMD_INVALID)); 815 816 /* lets just hope it worked.. */ 817 dev->sc_flags &= ~SBICF_SELECTED; 818 } 819 return -1; 820 } 821 822 823 /* 824 * Initialize driver-private structures 825 */ 826 827 void 828 sbicinit(dev) 829 struct sbic_softc *dev; 830 { 831 sbic_regmap_t regs; 832 u_int i; 833 struct sbic_acb *acb; 834 u_int inhibit_sync; 835 836 extern u_long scsi_nosync; 837 extern int shift_nosync; 838 839 regs = dev->sc_sbic; 840 841 if ((dev->sc_flags & SBICF_ALIVE) == 0) { 842 TAILQ_INIT(&dev->ready_list); 843 TAILQ_INIT(&dev->nexus_list); 844 TAILQ_INIT(&dev->free_list); 845 callout_init(&dev->sc_timo_ch); 846 dev->sc_nexus = NULL; 847 dev->sc_xs = NULL; 848 acb = dev->sc_acb; 849 bzero(acb, sizeof(dev->sc_acb)); 850 for (i = 0; i < sizeof(dev->sc_acb) / sizeof(*acb); i++) { 851 TAILQ_INSERT_TAIL(&dev->free_list, acb, chain); 852 acb++; 853 } 854 bzero(dev->sc_tinfo, sizeof(dev->sc_tinfo)); 855 #ifdef DEBUG 856 /* make sure timeout is really not needed */ 857 callout_reset(&dev->sc_timo_ch, 30 * hz, 858 (void *)sbictimeout, dev); 859 #endif 860 861 } else panic("sbic: reinitializing driver!"); 862 863 dev->sc_flags |= SBICF_ALIVE; 864 dev->sc_flags &= ~SBICF_SELECTED; 865 866 /* initialize inhibit array */ 867 if (scsi_nosync) { 868 inhibit_sync = (scsi_nosync >> shift_nosync) & 0xff; 869 shift_nosync += 8; 870 #ifdef DEBUG 871 if (inhibit_sync) 872 printf("%s: Inhibiting synchronous transfer %02x\n", 873 dev->sc_dev.dv_xname, inhibit_sync); 874 #endif 875 for (i = 0; i < 8; ++i) 876 if (inhibit_sync & (1 << i)) 877 sbic_inhibit_sync[i] = 1; 878 } 879 880 sbicreset(dev); 881 } 882 883 void 884 sbicreset(dev) 885 struct sbic_softc *dev; 886 { 887 sbic_regmap_t regs; 888 u_int my_id, s; 889 u_char csr; 890 #if 0 891 u_int i; 892 struct sbic_acb *acb; 893 #endif 894 895 regs = dev->sc_sbic; 896 #if 0 897 if (dev->sc_flags & SBICF_ALIVE) { 898 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 899 WAIT_CIP(regs); 900 } 901 #else 902 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 903 WAIT_CIP(regs); 904 #endif 905 s = splbio(); 906 my_id = dev->sc_link.scsipi_scsi.adapter_target & SBIC_ID_MASK; 907 908 /* Enable advanced mode */ 909 my_id |= SBIC_ID_EAF /*| SBIC_ID_EHP*/ ; 910 SET_SBIC_myid(regs, my_id); 911 912 /* 913 * Disable interrupts (in dmainit) then reset the chip 914 */ 915 SET_SBIC_cmd(regs, SBIC_CMD_RESET); 916 DELAY(25); 917 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 918 GET_SBIC_csr(regs, csr); /* clears interrupt also */ 919 920 if (dev->sc_clkfreq < 110) 921 my_id |= SBIC_ID_FS_8_10; 922 else if (dev->sc_clkfreq < 160) 923 my_id |= SBIC_ID_FS_12_15; 924 else if (dev->sc_clkfreq < 210) 925 my_id |= SBIC_ID_FS_16_20; 926 927 SET_SBIC_myid(regs, my_id); 928 929 /* 930 * Set up various chip parameters 931 */ 932 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI /* | SBIC_CTL_HSP */ 933 | SBIC_MACHINE_DMA_MODE); 934 /* 935 * don't allow (re)selection (SBIC_RID_ES) 936 * until we can handle target mode!! 937 */ 938 SET_SBIC_rselid(regs, SBIC_RID_ER); 939 SET_SBIC_syn(regs, 0); /* asynch for now */ 940 941 /* 942 * anything else was zeroed by reset 943 */ 944 splx(s); 945 946 #if 0 947 if ((dev->sc_flags & SBICF_ALIVE) == 0) { 948 TAILQ_INIT(&dev->ready_list); 949 TAILQ_INIT(&dev->nexus_list); 950 TAILQ_INIT(&dev->free_list); 951 dev->sc_nexus = NULL; 952 dev->sc_xs = NULL; 953 acb = dev->sc_acb; 954 bzero(acb, sizeof(dev->sc_acb)); 955 for (i = 0; i < sizeof(dev->sc_acb) / sizeof(*acb); i++) { 956 TAILQ_INSERT_TAIL(&dev->free_list, acb, chain); 957 acb++; 958 } 959 bzero(dev->sc_tinfo, sizeof(dev->sc_tinfo)); 960 } else { 961 if (dev->sc_nexus != NULL) { 962 dev->sc_nexus->xs->error = XS_DRIVER_STUFFUP; 963 sbic_scsidone(dev->sc_nexus, dev->sc_stat[0]); 964 } 965 while (acb = dev->nexus_list.tqh_first) { 966 acb->xs->error = XS_DRIVER_STUFFUP; 967 sbic_scsidone(acb, -1 /*acb->stat[0]*/); 968 } 969 } 970 971 dev->sc_flags |= SBICF_ALIVE; 972 #endif 973 dev->sc_flags &= ~SBICF_SELECTED; 974 } 975 976 void 977 sbicerror(dev, regs, csr) 978 struct sbic_softc *dev; 979 sbic_regmap_t regs; 980 u_char csr; 981 { 982 struct scsipi_xfer *xs; 983 984 xs = dev->sc_xs; 985 986 #ifdef DIAGNOSTIC 987 if (xs == NULL) 988 panic("sbicerror"); 989 #endif 990 if (xs->xs_control & XS_CTL_SILENT) 991 return; 992 993 printf("%s: ", dev->sc_dev.dv_xname); 994 printf("csr == 0x%02x\n", csr); /* XXX */ 995 } 996 997 /* 998 * select the bus, return when selected or error. 999 */ 1000 int 1001 sbicselectbus(dev, regs, target, lun, our_addr) 1002 struct sbic_softc *dev; 1003 sbic_regmap_t regs; 1004 u_char target, lun, our_addr; 1005 { 1006 u_char asr, csr, id; 1007 1008 SBIC_TRACE(dev); 1009 QPRINTF(("sbicselectbus %d\n", target)); 1010 1011 /* 1012 * if we're already selected, return (XXXX panic maybe?) 1013 */ 1014 if (dev->sc_flags & SBICF_SELECTED) { 1015 SBIC_TRACE(dev); 1016 return(1); 1017 } 1018 1019 /* 1020 * issue select 1021 */ 1022 SBIC_TC_PUT(regs, 0); 1023 SET_SBIC_selid(regs, target); 1024 SET_SBIC_timeo(regs, SBIC_TIMEOUT(250,dev->sc_clkfreq)); 1025 1026 /* 1027 * set sync or async 1028 */ 1029 if (dev->sc_sync[target].state == SYNC_DONE) 1030 SET_SBIC_syn(regs, SBIC_SYN (dev->sc_sync[target].offset, 1031 dev->sc_sync[target].period)); 1032 else 1033 SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period)); 1034 1035 GET_SBIC_asr(regs, asr); 1036 if( asr & (SBIC_ASR_INT|SBIC_ASR_BSY) ) { 1037 /* This means we got ourselves reselected upon */ 1038 /* printf("sbicselectbus: INT/BSY asr %02x\n", asr);*/ 1039 #ifdef DDB 1040 /* Debugger();*/ 1041 #endif 1042 SBIC_TRACE(dev); 1043 return 1; 1044 } 1045 1046 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN); 1047 1048 /* 1049 * wait for select (merged from seperate function may need 1050 * cleanup) 1051 */ 1052 WAIT_CIP(regs); 1053 do { 1054 asr = SBIC_WAIT(regs, SBIC_ASR_INT | SBIC_ASR_LCI, 0); 1055 if (asr & SBIC_ASR_LCI) { 1056 #ifdef DEBUG 1057 if (reselect_debug) 1058 printf("sbicselectbus: late LCI asr %02x\n", asr); 1059 #endif 1060 SBIC_TRACE(dev); 1061 return 1; 1062 } 1063 GET_SBIC_csr (regs, csr); 1064 CSR_TRACE('s',csr,asr,target); 1065 QPRINTF(("%02x ", csr)); 1066 if( csr == SBIC_CSR_RSLT_NI || csr == SBIC_CSR_RSLT_IFY) { 1067 #ifdef DEBUG 1068 if(reselect_debug) 1069 printf("sbicselectbus: reselected asr %02x\n", asr); 1070 #endif 1071 /* We need to handle this now so we don't lock up later */ 1072 sbicnextstate(dev, csr, asr); 1073 SBIC_TRACE(dev); 1074 return 1; 1075 } 1076 if( csr == SBIC_CSR_SLT || csr == SBIC_CSR_SLT_ATN) { 1077 panic("sbicselectbus: target issued select!"); 1078 return 1; 1079 } 1080 } while (csr != (SBIC_CSR_MIS_2|MESG_OUT_PHASE) 1081 && csr != (SBIC_CSR_MIS_2|CMD_PHASE) && csr != SBIC_CSR_SEL_TIMEO); 1082 1083 /* Enable (or not) reselection */ 1084 if(!sbic_enable_reselect && dev->nexus_list.tqh_first == NULL) 1085 SET_SBIC_rselid (regs, 0); 1086 else 1087 SET_SBIC_rselid (regs, SBIC_RID_ER); 1088 1089 if (csr == (SBIC_CSR_MIS_2|CMD_PHASE)) { 1090 dev->sc_flags |= SBICF_SELECTED; /* device ignored ATN */ 1091 GET_SBIC_selid(regs, id); 1092 dev->target = id; 1093 GET_SBIC_tlun(regs,dev->lun); 1094 if( dev->lun & SBIC_TLUN_VALID ) 1095 dev->lun &= SBIC_TLUN_MASK; 1096 else 1097 dev->lun = lun; 1098 } else if (csr == (SBIC_CSR_MIS_2|MESG_OUT_PHASE)) { 1099 /* 1100 * Send identify message 1101 * (SCSI-2 requires an identify msg (?)) 1102 */ 1103 GET_SBIC_selid(regs, id); 1104 dev->target = id; 1105 GET_SBIC_tlun(regs,dev->lun); 1106 if( dev->lun & SBIC_TLUN_VALID ) 1107 dev->lun &= SBIC_TLUN_MASK; 1108 else 1109 dev->lun = lun; 1110 /* 1111 * handle drives that don't want to be asked 1112 * whether to go sync at all. 1113 */ 1114 if (sbic_inhibit_sync[id] 1115 && dev->sc_sync[id].state == SYNC_START) { 1116 #ifdef DEBUG 1117 if (sync_debug) 1118 printf("Forcing target %d asynchronous.\n", id); 1119 #endif 1120 dev->sc_sync[id].offset = 0; 1121 dev->sc_sync[id].period = sbic_min_period; 1122 dev->sc_sync[id].state = SYNC_DONE; 1123 } 1124 1125 1126 if (dev->sc_sync[id].state != SYNC_START){ 1127 if( dev->sc_xs->xs_control & XS_CTL_POLL 1128 || (dev->sc_flags & SBICF_ICMD) 1129 || !sbic_enable_reselect ) 1130 SEND_BYTE (regs, MSG_IDENTIFY | lun); 1131 else 1132 SEND_BYTE (regs, MSG_IDENTIFY_DR | lun); 1133 } else { 1134 /* 1135 * try to initiate a sync transfer. 1136 * So compose the sync message we're going 1137 * to send to the target 1138 */ 1139 1140 #ifdef DEBUG 1141 if (sync_debug) 1142 printf("Sending sync request to target %d ... ", 1143 id); 1144 #endif 1145 /* 1146 * setup scsi message sync message request 1147 */ 1148 dev->sc_msg[0] = MSG_IDENTIFY | lun; 1149 dev->sc_msg[1] = MSG_EXT_MESSAGE; 1150 dev->sc_msg[2] = 3; 1151 dev->sc_msg[3] = MSG_SYNC_REQ; 1152 dev->sc_msg[4] = sbictoscsiperiod(dev, regs, 1153 sbic_min_period); 1154 dev->sc_msg[5] = sbic_max_offset; 1155 1156 if (sbicxfstart(regs, 6, MESG_OUT_PHASE, sbic_cmd_wait)) 1157 sbicxfout(regs, 6, dev->sc_msg, MESG_OUT_PHASE); 1158 1159 dev->sc_sync[id].state = SYNC_SENT; 1160 #ifdef DEBUG 1161 if (sync_debug) 1162 printf ("sent\n"); 1163 #endif 1164 } 1165 1166 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0); 1167 GET_SBIC_csr (regs, csr); 1168 CSR_TRACE('y',csr,asr,target); 1169 QPRINTF(("[%02x]", csr)); 1170 #ifdef DEBUG 1171 if (sync_debug && dev->sc_sync[id].state == SYNC_SENT) 1172 printf("csr-result of last msgout: 0x%x\n", csr); 1173 #endif 1174 1175 if (csr != SBIC_CSR_SEL_TIMEO) 1176 dev->sc_flags |= SBICF_SELECTED; 1177 } 1178 if (csr == SBIC_CSR_SEL_TIMEO) 1179 dev->sc_xs->error = XS_SELTIMEOUT; 1180 1181 QPRINTF(("\n")); 1182 1183 SBIC_TRACE(dev); 1184 return(csr == SBIC_CSR_SEL_TIMEO); 1185 } 1186 1187 int 1188 sbicxfstart(regs, len, phase, wait) 1189 sbic_regmap_t regs; 1190 int len, wait; 1191 u_char phase; 1192 { 1193 u_char id; 1194 1195 switch (phase) { 1196 case DATA_IN_PHASE: 1197 case MESG_IN_PHASE: 1198 GET_SBIC_selid (regs, id); 1199 id |= SBIC_SID_FROM_SCSI; 1200 SET_SBIC_selid (regs, id); 1201 SBIC_TC_PUT (regs, (unsigned)len); 1202 break; 1203 case DATA_OUT_PHASE: 1204 case MESG_OUT_PHASE: 1205 case CMD_PHASE: 1206 GET_SBIC_selid (regs, id); 1207 id &= ~SBIC_SID_FROM_SCSI; 1208 SET_SBIC_selid (regs, id); 1209 SBIC_TC_PUT (regs, (unsigned)len); 1210 break; 1211 default: 1212 SBIC_TC_PUT (regs, 0); 1213 } 1214 QPRINTF(("sbicxfstart %d, %d, %d\n", len, phase, wait)); 1215 1216 return(1); 1217 } 1218 1219 int 1220 sbicxfout(regs, len, bp, phase) 1221 sbic_regmap_t regs; 1222 int len; 1223 void *bp; 1224 int phase; 1225 { 1226 u_char orig_csr, asr, *buf; 1227 int wait; 1228 1229 buf = bp; 1230 wait = sbic_data_wait; 1231 1232 QPRINTF(("sbicxfout {%d} %02x %02x %02x %02x %02x " 1233 "%02x %02x %02x %02x %02x\n", len, buf[0], buf[1], buf[2], 1234 buf[3], buf[4], buf[5], buf[6], buf[7], buf[8], buf[9])); 1235 1236 GET_SBIC_csr (regs, orig_csr); 1237 CSR_TRACE('>',orig_csr,0,0); 1238 1239 /* 1240 * sigh.. WD-PROTO strikes again.. sending the command in one go 1241 * causes the chip to lock up if talking to certain (misbehaving?) 1242 * targets. Anyway, this procedure should work for all targets, but 1243 * it's slightly slower due to the overhead 1244 */ 1245 WAIT_CIP (regs); 1246 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1247 for (;len > 0; len--) { 1248 GET_SBIC_asr (regs, asr); 1249 while ((asr & SBIC_ASR_DBR) == 0) { 1250 if ((asr & SBIC_ASR_INT) || --wait < 0) { 1251 #ifdef DEBUG 1252 if (sbic_debug) 1253 printf("sbicxfout fail: l%d i%x w%d\n", 1254 len, asr, wait); 1255 #endif 1256 return (len); 1257 } 1258 /* DELAY(1);*/ 1259 GET_SBIC_asr (regs, asr); 1260 } 1261 1262 SET_SBIC_data (regs, *buf); 1263 buf++; 1264 } 1265 SBIC_TC_GET(regs, len); 1266 QPRINTF(("sbicxfout done %d bytes\n", len)); 1267 /* 1268 * this leaves with one csr to be read 1269 */ 1270 return(0); 1271 } 1272 1273 /* returns # bytes left to read */ 1274 int 1275 sbicxfin(regs, len, bp) 1276 sbic_regmap_t regs; 1277 int len; 1278 void *bp; 1279 { 1280 int wait; 1281 u_char *obp, *buf; 1282 u_char orig_csr, csr, asr; 1283 1284 wait = sbic_data_wait; 1285 obp = bp; 1286 buf = bp; 1287 1288 GET_SBIC_csr (regs, orig_csr); 1289 CSR_TRACE('<',orig_csr,0,0); 1290 1291 QPRINTF(("sbicxfin %d, csr=%02x\n", len, orig_csr)); 1292 1293 WAIT_CIP (regs); 1294 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1295 for (;len > 0; len--) { 1296 GET_SBIC_asr (regs, asr); 1297 if((asr & SBIC_ASR_PE)) { 1298 #ifdef DEBUG 1299 printf("sbicxfin parity error: l%d i%x w%d\n", 1300 len, asr, wait); 1301 /* return ((unsigned long)buf - (unsigned long)bp); */ 1302 #ifdef DDB 1303 Debugger(); 1304 #endif 1305 #endif 1306 } 1307 while ((asr & SBIC_ASR_DBR) == 0) { 1308 if ((asr & SBIC_ASR_INT) || --wait < 0) { 1309 #ifdef DEBUG 1310 if (sbic_debug) { 1311 QPRINTF(("sbicxfin fail:{%d} %02x %02x %02x %02x %02x %02x " 1312 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1313 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1314 printf("sbicxfin fail: l%d i%x w%d\n", 1315 len, asr, wait); 1316 } 1317 #endif 1318 return len; 1319 } 1320 1321 if( ! asr & SBIC_ASR_BSY ) { 1322 GET_SBIC_csr(regs, csr); 1323 CSR_TRACE('<',csr,asr,len); 1324 QPRINTF(("[CSR%02xASR%02x]", csr, asr)); 1325 } 1326 1327 /* DELAY(1);*/ 1328 GET_SBIC_asr (regs, asr); 1329 } 1330 1331 GET_SBIC_data (regs, *buf); 1332 /* QPRINTF(("asr=%02x, csr=%02x, data=%02x\n", asr, csr, *buf));*/ 1333 buf++; 1334 } 1335 1336 QPRINTF(("sbicxfin {%d} %02x %02x %02x %02x %02x %02x " 1337 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1338 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1339 1340 /* this leaves with one csr to be read */ 1341 return len; 1342 } 1343 1344 /* 1345 * SCSI 'immediate' command: issue a command to some SCSI device 1346 * and get back an 'immediate' response (i.e., do programmed xfer 1347 * to get the response data). 'cbuf' is a buffer containing a scsi 1348 * command of length clen bytes. 'buf' is a buffer of length 'len' 1349 * bytes for data. The transfer direction is determined by the device 1350 * (i.e., by the scsi bus data xfer phase). If 'len' is zero, the 1351 * command must supply no data. 1352 */ 1353 int 1354 sbicicmd(dev, target, lun, cbuf, clen, buf, len) 1355 struct sbic_softc *dev; 1356 void *cbuf, *buf; 1357 int clen, len; 1358 { 1359 sbic_regmap_t regs; 1360 u_char phase, csr, asr; 1361 int wait, i; 1362 struct sbic_acb *acb; 1363 1364 #define CSR_LOG_BUF_SIZE 0 1365 #if CSR_LOG_BUF_SIZE 1366 int bufptr; 1367 int csrbuf[CSR_LOG_BUF_SIZE]; 1368 bufptr=0; 1369 #endif 1370 1371 SBIC_TRACE(dev); 1372 regs = dev->sc_sbic; 1373 acb = dev->sc_nexus; 1374 1375 /* Make sure pointers are OK */ 1376 dev->sc_last = dev->sc_cur = &acb->sc_pa; 1377 dev->sc_tcnt = acb->sc_tcnt = 0; 1378 acb->sc_pa.dc_count = 0; /* No DMA */ 1379 acb->sc_kv.dc_addr = buf; 1380 acb->sc_kv.dc_count = len; 1381 1382 #ifdef DEBUG 1383 routine = 3; 1384 debug_sbic_regs = regs; /* store this to allow debug calls */ 1385 if( data_pointer_debug > 1 ) 1386 printf("sbicicmd(%d,%d):%d\n", target, lun, 1387 acb->sc_kv.dc_count); 1388 #endif 1389 1390 /* 1391 * set the sbic into non-DMA mode 1392 */ 1393 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI /*| SBIC_CTL_HSP*/); 1394 1395 dev->sc_stat[0] = 0xff; 1396 dev->sc_msg[0] = 0xff; 1397 i = 1; /* pre-load */ 1398 1399 /* We're stealing the SCSI bus */ 1400 dev->sc_flags |= SBICF_ICMD; 1401 1402 do { 1403 /* 1404 * select the SCSI bus (it's an error if bus isn't free) 1405 */ 1406 if (!( dev->sc_flags & SBICF_SELECTED ) 1407 && sbicselectbus(dev, regs, target, lun, dev->sc_scsiaddr)) { 1408 /* printf("sbicicmd: trying to select busy bus!\n"); */ 1409 dev->sc_flags &= ~SBICF_ICMD; 1410 return(-1); 1411 } 1412 1413 /* 1414 * Wait for a phase change (or error) then let the device sequence 1415 * us through the various SCSI phases. 1416 */ 1417 1418 wait = sbic_cmd_wait; 1419 1420 asr = GET_SBIC_asr (regs, asr); 1421 GET_SBIC_csr (regs, csr); 1422 CSR_TRACE('I',csr,asr,target); 1423 QPRINTF((">ASR:%02xCSR:%02x<", asr, csr)); 1424 1425 #if CSR_LOG_BUF_SIZE 1426 csrbuf[bufptr++] = csr; 1427 #endif 1428 1429 1430 switch (csr) { 1431 case SBIC_CSR_S_XFERRED: 1432 case SBIC_CSR_DISC: 1433 case SBIC_CSR_DISC_1: 1434 dev->sc_flags &= ~SBICF_SELECTED; 1435 GET_SBIC_cmd_phase (regs, phase); 1436 if (phase == 0x60) { 1437 GET_SBIC_tlun (regs, dev->sc_stat[0]); 1438 i = 0; /* done */ 1439 /* break; */ /* Bypass all the state gobldygook */ 1440 } else { 1441 #ifdef DEBUG 1442 if(reselect_debug>1) 1443 printf("sbicicmd: handling disconnect\n"); 1444 #endif 1445 i = SBIC_STATE_DISCONNECT; 1446 } 1447 break; 1448 1449 case SBIC_CSR_XFERRED|CMD_PHASE: 1450 case SBIC_CSR_MIS|CMD_PHASE: 1451 case SBIC_CSR_MIS_1|CMD_PHASE: 1452 case SBIC_CSR_MIS_2|CMD_PHASE: 1453 if (sbicxfstart(regs, clen, CMD_PHASE, sbic_cmd_wait)) 1454 if (sbicxfout(regs, clen, 1455 cbuf, CMD_PHASE)) 1456 i = sbicabort(dev, regs,"icmd sending cmd"); 1457 #if 0 1458 GET_SBIC_csr(regs, csr); /* Lets us reload tcount */ 1459 WAIT_CIP(regs); 1460 GET_SBIC_asr(regs, asr); 1461 CSR_TRACE('I',csr,asr,target); 1462 if( asr & (SBIC_ASR_BSY|SBIC_ASR_LCI|SBIC_ASR_CIP) ) 1463 printf("next: cmd sent asr %02x, csr %02x\n", 1464 asr, csr); 1465 #endif 1466 break; 1467 1468 #if 0 1469 case SBIC_CSR_XFERRED|DATA_OUT_PHASE: 1470 case SBIC_CSR_XFERRED|DATA_IN_PHASE: 1471 case SBIC_CSR_MIS|DATA_OUT_PHASE: 1472 case SBIC_CSR_MIS|DATA_IN_PHASE: 1473 case SBIC_CSR_MIS_1|DATA_OUT_PHASE: 1474 case SBIC_CSR_MIS_1|DATA_IN_PHASE: 1475 case SBIC_CSR_MIS_2|DATA_OUT_PHASE: 1476 case SBIC_CSR_MIS_2|DATA_IN_PHASE: 1477 if (acb->sc_kv.dc_count <= 0) 1478 i = sbicabort(dev, regs, "icmd out of data"); 1479 else { 1480 wait = sbic_data_wait; 1481 if (sbicxfstart(regs, 1482 acb->sc_kv.dc_count, 1483 SBIC_PHASE(csr), wait)) 1484 if (csr & 0x01) 1485 /* data in? */ 1486 i=sbicxfin(regs, 1487 acb->sc_kv.dc_count, 1488 acb->sc_kv.dc_addr); 1489 else 1490 i=sbicxfout(regs, 1491 acb->sc_kv.dc_count, 1492 acb->sc_kv.dc_addr, 1493 SBIC_PHASE(csr)); 1494 acb->sc_kv.dc_addr += 1495 (acb->sc_kv.dc_count - i); 1496 acb->sc_kv.dc_count = i; 1497 i = 1; 1498 } 1499 break; 1500 1501 #endif 1502 case SBIC_CSR_XFERRED|STATUS_PHASE: 1503 case SBIC_CSR_MIS|STATUS_PHASE: 1504 case SBIC_CSR_MIS_1|STATUS_PHASE: 1505 case SBIC_CSR_MIS_2|STATUS_PHASE: 1506 /* 1507 * the sbic does the status/cmd-complete reading ok, 1508 * so do this with its hi-level commands. 1509 */ 1510 #ifdef DEBUG 1511 if(sbic_debug) 1512 printf("SBICICMD status phase\n"); 1513 #endif 1514 SBIC_TC_PUT(regs, 0); 1515 SET_SBIC_cmd_phase(regs, 0x46); 1516 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1517 break; 1518 1519 #if THIS_IS_A_RESERVED_STATE 1520 case BUS_FREE_PHASE: /* This is not legal */ 1521 if( dev->sc_stat[0] != 0xff ) 1522 goto out; 1523 break; 1524 #endif 1525 1526 default: 1527 i = sbicnextstate(dev, csr, asr); 1528 } 1529 1530 /* 1531 * make sure the last command was taken, 1532 * ie. we're not hunting after an ignored command.. 1533 */ 1534 GET_SBIC_asr(regs, asr); 1535 1536 /* tapes may take a loooong time.. */ 1537 while (asr & SBIC_ASR_BSY){ 1538 if(asr & SBIC_ASR_DBR) { 1539 printf("sbicicmd: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", 1540 csr,asr); 1541 #ifdef DDB 1542 Debugger(); 1543 #endif 1544 /* SBIC is jammed */ 1545 /* DUNNO which direction */ 1546 /* Try old direction */ 1547 GET_SBIC_data(regs,i); 1548 GET_SBIC_asr(regs, asr); 1549 if( asr & SBIC_ASR_DBR) /* Wants us to write */ 1550 SET_SBIC_data(regs,i); 1551 } 1552 GET_SBIC_asr(regs, asr); 1553 } 1554 1555 /* 1556 * wait for last command to complete 1557 */ 1558 if (asr & SBIC_ASR_LCI) { 1559 printf("sbicicmd: last command ignored\n"); 1560 } 1561 else if( i == 1 ) /* Bsy */ 1562 SBIC_WAIT (regs, SBIC_ASR_INT, wait); 1563 1564 /* 1565 * do it again 1566 */ 1567 } while ( i > 0 && dev->sc_stat[0] == 0xff); 1568 1569 /* Sometimes we need to do an extra read of the CSR */ 1570 GET_SBIC_csr(regs, csr); 1571 CSR_TRACE('I',csr,asr,0xff); 1572 1573 #if CSR_LOG_BUF_SIZE 1574 if(reselect_debug>1) 1575 for(i=0; i<bufptr; i++) 1576 printf("CSR:%02x", csrbuf[i]); 1577 #endif 1578 1579 #ifdef DEBUG 1580 if(data_pointer_debug > 1) 1581 printf("sbicicmd done(%d,%d):%d =%d=\n", 1582 dev->target, lun, 1583 acb->sc_kv.dc_count, 1584 dev->sc_stat[0]); 1585 #endif 1586 1587 QPRINTF(("=STS:%02x=", dev->sc_stat[0])); 1588 dev->sc_flags &= ~SBICF_ICMD; 1589 1590 SBIC_TRACE(dev); 1591 return(dev->sc_stat[0]); 1592 } 1593 1594 /* 1595 * Finish SCSI xfer command: After the completion interrupt from 1596 * a read/write operation, sequence through the final phases in 1597 * programmed i/o. This routine is a lot like sbicicmd except we 1598 * skip (and don't allow) the select, cmd out and data in/out phases. 1599 */ 1600 void 1601 sbicxfdone(dev, regs, target) 1602 struct sbic_softc *dev; 1603 sbic_regmap_t regs; 1604 int target; 1605 { 1606 u_char phase, asr, csr; 1607 int s; 1608 1609 SBIC_TRACE(dev); 1610 QPRINTF(("{")); 1611 s = splbio(); 1612 1613 /* 1614 * have the sbic complete on its own 1615 */ 1616 SBIC_TC_PUT(regs, 0); 1617 SET_SBIC_cmd_phase(regs, 0x46); 1618 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1619 1620 do { 1621 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0); 1622 GET_SBIC_csr (regs, csr); 1623 CSR_TRACE('f',csr,asr,target); 1624 QPRINTF(("%02x:", csr)); 1625 } while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) 1626 && (csr != SBIC_CSR_S_XFERRED)); 1627 1628 dev->sc_flags &= ~SBICF_SELECTED; 1629 1630 GET_SBIC_cmd_phase (regs, phase); 1631 QPRINTF(("}%02x", phase)); 1632 if (phase == 0x60) 1633 GET_SBIC_tlun(regs, dev->sc_stat[0]); 1634 else 1635 sbicerror(dev, regs, csr); 1636 1637 QPRINTF(("=STS:%02x=\n", dev->sc_stat[0])); 1638 splx(s); 1639 SBIC_TRACE(dev); 1640 } 1641 1642 /* 1643 * No DMA chains 1644 */ 1645 1646 int 1647 sbicgo(dev, xs) 1648 struct sbic_softc *dev; 1649 struct scsipi_xfer *xs; 1650 { 1651 int i, dmaflags, count, usedma; 1652 u_char csr, asr, *addr; 1653 sbic_regmap_t regs; 1654 struct sbic_acb *acb; 1655 1656 SBIC_TRACE(dev); 1657 dev->target = xs->sc_link->scsipi_scsi.target; 1658 dev->lun = xs->sc_link->scsipi_scsi.lun; 1659 acb = dev->sc_nexus; 1660 regs = dev->sc_sbic; 1661 1662 usedma = sbicdmaok(dev, xs); 1663 #ifdef DEBUG 1664 routine = 1; 1665 debug_sbic_regs = regs; /* store this to allow debug calls */ 1666 if( data_pointer_debug > 1 ) 1667 printf("sbicgo(%d,%d)\n", dev->target, dev->lun); 1668 #endif 1669 1670 /* 1671 * set the sbic into DMA mode 1672 */ 1673 if( usedma ) 1674 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI | 1675 SBIC_MACHINE_DMA_MODE); 1676 else 1677 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1678 1679 1680 /* 1681 * select the SCSI bus (it's an error if bus isn't free) 1682 */ 1683 if (sbicselectbus(dev, regs, dev->target, dev->lun, 1684 dev->sc_scsiaddr)) { 1685 /* printf("sbicgo: Trying to select busy bus!\n"); */ 1686 SBIC_TRACE(dev); 1687 return(0); /* Not done: needs to be rescheduled */ 1688 } 1689 dev->sc_stat[0] = 0xff; 1690 1691 /* 1692 * Calculate DMA chains now 1693 */ 1694 1695 dmaflags = 0; 1696 if (acb->flags & ACB_DATAIN) 1697 dmaflags |= DMAGO_READ; 1698 1699 1700 /* 1701 * Deal w/bounce buffers. 1702 */ 1703 1704 addr = acb->sc_kv.dc_addr; 1705 count = acb->sc_kv.dc_count; 1706 if (count && (char *)kvtop(addr) != acb->sc_pa.dc_addr) { /* XXXX check */ 1707 printf("sbic: DMA buffer mapping changed %p->%x\n", 1708 acb->sc_pa.dc_addr, kvtop(addr)); 1709 #ifdef DDB 1710 Debugger(); 1711 #endif 1712 } 1713 1714 #ifdef DEBUG 1715 ++sbicdma_ops; /* count total DMA operations */ 1716 #endif 1717 if (count && usedma && dev->sc_flags & SBICF_BADDMA && 1718 sbiccheckdmap(addr, count, dev->sc_dmamask)) { 1719 /* 1720 * need to bounce the dma. 1721 */ 1722 if (dmaflags & DMAGO_READ) { 1723 acb->flags |= ACB_BBUF; 1724 acb->sc_dmausrbuf = addr; 1725 acb->sc_dmausrlen = count; 1726 acb->sc_usrbufpa = (u_char *)kvtop(addr); 1727 if(!dev->sc_tinfo[dev->target].bounce) { 1728 printf("sbicgo: HELP! no bounce allocated for %d\n", 1729 dev->target); 1730 printf("xfer: (%p->%p,%lx)\n", acb->sc_dmausrbuf, 1731 acb->sc_usrbufpa, acb->sc_dmausrlen); 1732 dev->sc_tinfo[xs->sc_link->scsipi_scsi.target].bounce 1733 = (char *)alloc_z2mem(MAXPHYS); 1734 if (isztwomem(dev->sc_tinfo[xs->sc_link->scsipi_scsi.target].bounce)) 1735 printf("alloc ZII target %d bounce pa 0x%x\n", 1736 xs->sc_link->scsipi_scsi.target, 1737 kvtop(dev->sc_tinfo[xs->sc_link->scsipi_scsi.target].bounce)); 1738 else if (dev->sc_tinfo[xs->sc_link->scsipi_scsi.target].bounce) 1739 printf("alloc CHIP target %d bounce pa 0x%p\n", 1740 xs->sc_link->scsipi_scsi.target, 1741 PREP_DMA_MEM(dev->sc_tinfo[xs->sc_link->scsipi_scsi.target].bounce)); 1742 1743 printf("Allocating %d bounce at %x\n", 1744 dev->target, 1745 kvtop(dev->sc_tinfo[dev->target].bounce)); 1746 } 1747 } else { /* write: copy to dma buffer */ 1748 #ifdef DEBUG 1749 if(data_pointer_debug) 1750 printf("sbicgo: copying %x bytes to target %d bounce %x\n", 1751 count, dev->target, 1752 kvtop(dev->sc_tinfo[dev->target].bounce)); 1753 #endif 1754 bcopy (addr, dev->sc_tinfo[dev->target].bounce, count); 1755 } 1756 addr = dev->sc_tinfo[dev->target].bounce;/* and use dma buffer */ 1757 acb->sc_kv.dc_addr = addr; 1758 #ifdef DEBUG 1759 ++sbicdma_bounces; /* count number of bounced */ 1760 #endif 1761 } 1762 1763 /* 1764 * Allocate the DMA chain 1765 */ 1766 1767 /* Set start KVM addresses */ 1768 #if 0 1769 acb->sc_kv.dc_addr = addr; 1770 acb->sc_kv.dc_count = count; 1771 #endif 1772 1773 /* Mark end of segment */ 1774 acb->sc_tcnt = dev->sc_tcnt = 0; 1775 acb->sc_pa.dc_count = 0; 1776 1777 sbic_load_ptrs(dev, regs, dev->target, dev->lun); 1778 SBIC_TRACE(dev); 1779 /* Enable interrupts but don't do any DMA */ 1780 dev->sc_enintr(dev); 1781 if (usedma) { 1782 dev->sc_tcnt = dev->sc_dmago(dev, acb->sc_pa.dc_addr, 1783 acb->sc_pa.dc_count, 1784 dmaflags); 1785 #ifdef DEBUG 1786 dev->sc_dmatimo = dev->sc_tcnt ? 1 : 0; 1787 #endif 1788 } else 1789 dev->sc_dmacmd = 0; /* Don't use DMA */ 1790 dev->sc_flags |= SBICF_INDMA; 1791 /* SBIC_TC_PUT(regs, dev->sc_tcnt); */ /* XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX */ 1792 SBIC_TRACE(dev); 1793 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 1794 1795 /* 1796 * push the data cache ( I think this won't work (EH)) 1797 */ 1798 #if defined(M68040) || defined(M68060) 1799 if (mmutype == MMU_68040 && usedma && count) { 1800 dma_cachectl(addr, count); 1801 if (((u_int)addr & 0xF) || (((u_int)addr + count) & 0xF)) 1802 dev->sc_flags |= SBICF_DCFLUSH; 1803 } 1804 #endif 1805 1806 /* 1807 * enintr() also enables interrupts for the sbic 1808 */ 1809 #ifdef DEBUG 1810 if( data_pointer_debug > 1 ) 1811 printf("sbicgo dmago:%d(%p:%lx)\n", 1812 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 1813 #if 0 1814 /* 1815 * Hmm - this isn't right: asr and csr haven't been set yet. 1816 */ 1817 debug_asr = asr; 1818 debug_csr = csr; 1819 #endif 1820 #endif 1821 1822 /* 1823 * Lets cycle a while then let the interrupt handler take over 1824 */ 1825 1826 asr = GET_SBIC_asr(regs, asr); 1827 do { 1828 GET_SBIC_csr(regs, csr); 1829 CSR_TRACE('g',csr,asr,dev->target); 1830 #ifdef DEBUG 1831 debug_csr = csr; 1832 routine = 1; 1833 #endif 1834 QPRINTF(("go[0x%x]", csr)); 1835 1836 i = sbicnextstate(dev, csr, asr); 1837 1838 WAIT_CIP(regs); 1839 GET_SBIC_asr(regs, asr); 1840 #ifdef DEBUG 1841 debug_asr = asr; 1842 #endif 1843 if(asr & SBIC_ASR_LCI) printf("sbicgo: LCI asr:%02x csr:%02x\n", 1844 asr,csr); 1845 } while( i == SBIC_STATE_RUNNING 1846 && asr & (SBIC_ASR_INT|SBIC_ASR_LCI) ); 1847 1848 CSR_TRACE('g',csr,asr,i<<4); 1849 SBIC_TRACE(dev); 1850 if (i == SBIC_STATE_DONE && dev->sc_stat[0] == 0xff) printf("sbicgo: done & stat = 0xff\n"); 1851 if (i == SBIC_STATE_DONE && dev->sc_stat[0] != 0xff) { 1852 /* if( i == SBIC_STATE_DONE && dev->sc_stat[0] ) { */ 1853 /* Did we really finish that fast? */ 1854 return 1; 1855 } 1856 return 0; 1857 } 1858 1859 1860 int 1861 sbicintr(dev) 1862 struct sbic_softc *dev; 1863 { 1864 sbic_regmap_t regs; 1865 u_char asr, csr; 1866 int i; 1867 1868 regs = dev->sc_sbic; 1869 1870 /* 1871 * pending interrupt? 1872 */ 1873 GET_SBIC_asr (regs, asr); 1874 if ((asr & SBIC_ASR_INT) == 0) 1875 return(0); 1876 1877 SBIC_TRACE(dev); 1878 do { 1879 GET_SBIC_csr(regs, csr); 1880 CSR_TRACE('i',csr,asr,dev->target); 1881 #ifdef DEBUG 1882 debug_csr = csr; 1883 routine = 2; 1884 #endif 1885 QPRINTF(("intr[0x%x]", csr)); 1886 1887 i = sbicnextstate(dev, csr, asr); 1888 1889 WAIT_CIP(regs); 1890 GET_SBIC_asr(regs, asr); 1891 #ifdef DEBUG 1892 debug_asr = asr; 1893 #endif 1894 #if 0 1895 if(asr & SBIC_ASR_LCI) printf("sbicintr: LCI asr:%02x csr:%02x\n", 1896 asr,csr); 1897 #endif 1898 } while(i == SBIC_STATE_RUNNING && 1899 asr & (SBIC_ASR_INT|SBIC_ASR_LCI)); 1900 CSR_TRACE('i',csr,asr,i<<4); 1901 SBIC_TRACE(dev); 1902 return(1); 1903 } 1904 1905 /* 1906 * Run commands and wait for disconnect 1907 */ 1908 int 1909 sbicpoll(dev) 1910 struct sbic_softc *dev; 1911 { 1912 sbic_regmap_t regs; 1913 u_char asr, csr; 1914 int i; 1915 1916 SBIC_TRACE(dev); 1917 regs = dev->sc_sbic; 1918 1919 do { 1920 GET_SBIC_asr (regs, asr); 1921 #ifdef DEBUG 1922 debug_asr = asr; 1923 #endif 1924 GET_SBIC_csr(regs, csr); 1925 CSR_TRACE('p',csr,asr,dev->target); 1926 #ifdef DEBUG 1927 debug_csr = csr; 1928 routine = 2; 1929 #endif 1930 QPRINTF(("poll[0x%x]", csr)); 1931 1932 i = sbicnextstate(dev, csr, asr); 1933 1934 WAIT_CIP(regs); 1935 GET_SBIC_asr(regs, asr); 1936 /* tapes may take a loooong time.. */ 1937 while (asr & SBIC_ASR_BSY){ 1938 if(asr & SBIC_ASR_DBR) { 1939 printf("sbipoll: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", 1940 csr,asr); 1941 #ifdef DDB 1942 Debugger(); 1943 #endif 1944 /* SBIC is jammed */ 1945 /* DUNNO which direction */ 1946 /* Try old direction */ 1947 GET_SBIC_data(regs,i); 1948 GET_SBIC_asr(regs, asr); 1949 if( asr & SBIC_ASR_DBR) /* Wants us to write */ 1950 SET_SBIC_data(regs,i); 1951 } 1952 GET_SBIC_asr(regs, asr); 1953 } 1954 1955 if(asr & SBIC_ASR_LCI) printf("sbicpoll: LCI asr:%02x csr:%02x\n", 1956 asr,csr); 1957 else if( i == 1 ) /* BSY */ 1958 SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait); 1959 } while(i == SBIC_STATE_RUNNING); 1960 CSR_TRACE('p',csr,asr,i<<4); 1961 SBIC_TRACE(dev); 1962 return(1); 1963 } 1964 1965 /* 1966 * Handle a single msgin 1967 */ 1968 1969 int 1970 sbicmsgin(dev) 1971 struct sbic_softc *dev; 1972 { 1973 sbic_regmap_t regs; 1974 int recvlen; 1975 u_char asr, csr, *tmpaddr; 1976 1977 regs = dev->sc_sbic; 1978 1979 dev->sc_msg[0] = 0xff; 1980 dev->sc_msg[1] = 0xff; 1981 1982 GET_SBIC_asr(regs, asr); 1983 #ifdef DEBUG 1984 if(reselect_debug>1) 1985 printf("sbicmsgin asr=%02x\n", asr); 1986 #endif 1987 1988 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 1989 1990 GET_SBIC_selid (regs, csr); 1991 SET_SBIC_selid (regs, csr | SBIC_SID_FROM_SCSI); 1992 1993 SBIC_TC_PUT(regs, 0); 1994 tmpaddr = dev->sc_msg; 1995 recvlen = 1; 1996 do { 1997 while( recvlen-- ) { 1998 asr = GET_SBIC_asr(regs, asr); 1999 GET_SBIC_csr(regs, csr); 2000 QPRINTF(("sbicmsgin ready to go (csr,asr)=(%02x,%02x)\n", 2001 csr, asr)); 2002 2003 RECV_BYTE(regs, *tmpaddr); 2004 CSR_TRACE('m',csr,asr,*tmpaddr); 2005 #if 1 2006 /* 2007 * get the command completion interrupt, or we 2008 * can't send a new command (LCI) 2009 */ 2010 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2011 GET_SBIC_csr(regs, csr); 2012 CSR_TRACE('X',csr,asr,dev->target); 2013 #else 2014 WAIT_CIP(regs); 2015 do { 2016 GET_SBIC_asr(regs, asr); 2017 csr = 0xff; 2018 GET_SBIC_csr(regs, csr); 2019 CSR_TRACE('X',csr,asr,dev->target); 2020 if( csr == 0xff ) 2021 printf("sbicmsgin waiting: csr %02x asr %02x\n", csr, asr); 2022 } while( csr == 0xff ); 2023 #endif 2024 #ifdef DEBUG 2025 if(reselect_debug>1) 2026 printf("sbicmsgin: got %02x csr %02x asr %02x\n", 2027 *tmpaddr, csr, asr); 2028 #endif 2029 #if do_parity_check 2030 if( asr & SBIC_ASR_PE ) { 2031 printf ("Parity error"); 2032 /* This code simply does not work. */ 2033 WAIT_CIP(regs); 2034 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2035 WAIT_CIP(regs); 2036 GET_SBIC_asr(regs, asr); 2037 WAIT_CIP(regs); 2038 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2039 WAIT_CIP(regs); 2040 if( !(asr & SBIC_ASR_LCI) ) 2041 /* Target wants to send garbled msg*/ 2042 continue; 2043 printf("--fixing\n"); 2044 /* loop until a msgout phase occurs on target */ 2045 while(csr & 0x07 != MESG_OUT_PHASE) { 2046 while( asr & SBIC_ASR_BSY && 2047 !(asr & SBIC_ASR_DBR|SBIC_ASR_INT) ) 2048 GET_SBIC_asr(regs, asr); 2049 if( asr & SBIC_ASR_DBR ) 2050 panic("msgin: jammed again!\n"); 2051 GET_SBIC_csr(regs, csr); 2052 CSR_TRACE('e',csr,asr,dev->target); 2053 if( csr & 0x07 != MESG_OUT_PHASE ) { 2054 sbicnextstate(dev, csr, asr); 2055 sbic_save_ptrs(dev, regs, 2056 dev->target, 2057 dev->lun); 2058 } 2059 } 2060 /* Should be msg out by now */ 2061 SEND_BYTE(regs, MSG_PARITY_ERROR); 2062 } 2063 else 2064 #endif 2065 tmpaddr++; 2066 2067 if(recvlen) { 2068 /* Clear ACK */ 2069 WAIT_CIP(regs); 2070 GET_SBIC_asr(regs, asr); 2071 GET_SBIC_csr(regs, csr); 2072 CSR_TRACE('X',csr,asr,dev->target); 2073 QPRINTF(("sbicmsgin pre byte CLR_ACK (csr,asr)=(%02x,%02x)\n", 2074 csr, asr)); 2075 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2076 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2077 } 2078 2079 }; 2080 2081 if(dev->sc_msg[0] == 0xff) { 2082 printf("sbicmsgin: sbic swallowed our message\n"); 2083 break; 2084 } 2085 #ifdef DEBUG 2086 if (sync_debug) 2087 printf("msgin done csr 0x%x asr 0x%x msg 0x%x\n", 2088 csr, asr, dev->sc_msg[0]); 2089 #endif 2090 /* 2091 * test whether this is a reply to our sync 2092 * request 2093 */ 2094 if (MSG_ISIDENTIFY(dev->sc_msg[0])) { 2095 QPRINTF(("IFFY")); 2096 #if 0 2097 /* There is an implied load-ptrs here */ 2098 sbic_load_ptrs(dev, regs, dev->target, dev->lun); 2099 #endif 2100 /* Got IFFY msg -- ack it */ 2101 } else if (dev->sc_msg[0] == MSG_REJECT 2102 && dev->sc_sync[dev->target].state == SYNC_SENT) { 2103 QPRINTF(("REJECT of SYN")); 2104 #ifdef DEBUG 2105 if (sync_debug) 2106 printf("target %d rejected sync, going async\n", 2107 dev->target); 2108 #endif 2109 dev->sc_sync[dev->target].period = sbic_min_period; 2110 dev->sc_sync[dev->target].offset = 0; 2111 dev->sc_sync[dev->target].state = SYNC_DONE; 2112 SET_SBIC_syn(regs, 2113 SBIC_SYN(dev->sc_sync[dev->target].offset, 2114 dev->sc_sync[dev->target].period)); 2115 } else if ((dev->sc_msg[0] == MSG_REJECT)) { 2116 QPRINTF(("REJECT")); 2117 /* 2118 * we'll never REJECt a REJECT message.. 2119 */ 2120 } else if ((dev->sc_msg[0] == MSG_SAVE_DATA_PTR)) { 2121 QPRINTF(("MSG_SAVE_DATA_PTR")); 2122 /* 2123 * don't reject this either. 2124 */ 2125 } else if ((dev->sc_msg[0] == MSG_DISCONNECT)) { 2126 QPRINTF(("DISCONNECT")); 2127 #ifdef DEBUG 2128 if( reselect_debug>1 && dev->sc_msg[0] == MSG_DISCONNECT ) 2129 printf("sbicmsgin: got disconnect msg %s\n", 2130 (dev->sc_flags & SBICF_ICMD)?"rejecting":""); 2131 #endif 2132 if( dev->sc_flags & SBICF_ICMD ) { 2133 /* We're in immediate mode. Prevent disconnects. */ 2134 /* prepare to reject the message, NACK */ 2135 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2136 WAIT_CIP(regs); 2137 } 2138 } else if (dev->sc_msg[0] == MSG_CMD_COMPLETE ) { 2139 QPRINTF(("CMD_COMPLETE")); 2140 /* !! KLUDGE ALERT !! quite a few drives don't seem to 2141 * really like the current way of sending the 2142 * sync-handshake together with the ident-message, and 2143 * they react by sending command-complete and 2144 * disconnecting right after returning the valid sync 2145 * handshake. So, all I can do is reselect the drive, 2146 * and hope it won't disconnect again. I don't think 2147 * this is valid behavior, but I can't help fixing a 2148 * problem that apparently exists. 2149 * 2150 * Note: we should not get here on `normal' command 2151 * completion, as that condition is handled by the 2152 * high-level sel&xfer resume command used to walk 2153 * thru status/cc-phase. 2154 */ 2155 2156 #ifdef DEBUG 2157 if (sync_debug) 2158 printf ("GOT MSG %d! target %d acting weird.." 2159 " waiting for disconnect...\n", 2160 dev->sc_msg[0], dev->target); 2161 #endif 2162 /* Check to see if sbic is handling this */ 2163 GET_SBIC_asr(regs, asr); 2164 if(asr & SBIC_ASR_BSY) 2165 return SBIC_STATE_RUNNING; 2166 2167 /* Let's try this: Assume it works and set status to 00 */ 2168 dev->sc_stat[0] = 0; 2169 } else if (dev->sc_msg[0] == MSG_EXT_MESSAGE 2170 && tmpaddr == &dev->sc_msg[1]) { 2171 QPRINTF(("ExtMSG\n")); 2172 /* Read in whole extended message */ 2173 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2174 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2175 GET_SBIC_asr(regs, asr); 2176 GET_SBIC_csr(regs, csr); 2177 QPRINTF(("CLR ACK asr %02x, csr %02x\n", asr, csr)); 2178 RECV_BYTE(regs, *tmpaddr); 2179 CSR_TRACE('x',csr,asr,*tmpaddr); 2180 /* Wait for command completion IRQ */ 2181 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2182 recvlen = *tmpaddr++; 2183 QPRINTF(("Recving ext msg, asr %02x csr %02x len %02x\n", 2184 asr, csr, recvlen)); 2185 } else if (dev->sc_msg[0] == MSG_EXT_MESSAGE && dev->sc_msg[1] == 3 2186 && dev->sc_msg[2] == MSG_SYNC_REQ) { 2187 QPRINTF(("SYN")); 2188 dev->sc_sync[dev->target].period = 2189 sbicfromscsiperiod(dev, 2190 regs, dev->sc_msg[3]); 2191 dev->sc_sync[dev->target].offset = dev->sc_msg[4]; 2192 dev->sc_sync[dev->target].state = SYNC_DONE; 2193 SET_SBIC_syn(regs, 2194 SBIC_SYN(dev->sc_sync[dev->target].offset, 2195 dev->sc_sync[dev->target].period)); 2196 printf("%s: target %d now synchronous," 2197 " period=%dns, offset=%d.\n", 2198 dev->sc_dev.dv_xname, dev->target, 2199 dev->sc_msg[3] * 4, dev->sc_msg[4]); 2200 } else { 2201 #ifdef DEBUG 2202 if (sbic_debug || sync_debug) 2203 printf ("sbicmsgin: Rejecting message 0x%02x\n", 2204 dev->sc_msg[0]); 2205 #endif 2206 /* prepare to reject the message, NACK */ 2207 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2208 WAIT_CIP(regs); 2209 } 2210 /* Clear ACK */ 2211 WAIT_CIP(regs); 2212 GET_SBIC_asr(regs, asr); 2213 GET_SBIC_csr(regs, csr); 2214 CSR_TRACE('X',csr,asr,dev->target); 2215 QPRINTF(("sbicmsgin pre CLR_ACK (csr,asr)=(%02x,%02x)%d\n", 2216 csr, asr, recvlen)); 2217 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2218 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2219 } 2220 #if 0 2221 while((csr == SBIC_CSR_MSGIN_W_ACK) 2222 || (SBIC_PHASE(csr) == MESG_IN_PHASE)); 2223 #else 2224 while (recvlen>0); 2225 #endif 2226 2227 QPRINTF(("sbicmsgin finished: csr %02x, asr %02x\n",csr, asr)); 2228 2229 /* Should still have one CSR to read */ 2230 return SBIC_STATE_RUNNING; 2231 } 2232 2233 2234 /* 2235 * sbicnextstate() 2236 * return: 2237 * 0 == done 2238 * 1 == working 2239 * 2 == disconnected 2240 * -1 == error 2241 */ 2242 int 2243 sbicnextstate(dev, csr, asr) 2244 struct sbic_softc *dev; 2245 u_char csr, asr; 2246 { 2247 sbic_regmap_t regs; 2248 struct sbic_acb *acb; 2249 int i, newtarget, newlun, wait; 2250 #if 0 2251 unsigned tcnt; 2252 #endif 2253 2254 i = 0; 2255 SBIC_TRACE(dev); 2256 regs = dev->sc_sbic; 2257 acb = dev->sc_nexus; 2258 2259 QPRINTF(("next[%02x,%02x]",asr,csr)); 2260 2261 switch (csr) { 2262 case SBIC_CSR_XFERRED|CMD_PHASE: 2263 case SBIC_CSR_MIS|CMD_PHASE: 2264 case SBIC_CSR_MIS_1|CMD_PHASE: 2265 case SBIC_CSR_MIS_2|CMD_PHASE: 2266 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 2267 if (sbicxfstart(regs, acb->clen, CMD_PHASE, sbic_cmd_wait)) 2268 if (sbicxfout(regs, acb->clen, 2269 &acb->cmd, CMD_PHASE)) 2270 goto abort; 2271 break; 2272 2273 case SBIC_CSR_XFERRED|STATUS_PHASE: 2274 case SBIC_CSR_MIS|STATUS_PHASE: 2275 case SBIC_CSR_MIS_1|STATUS_PHASE: 2276 case SBIC_CSR_MIS_2|STATUS_PHASE: 2277 /* 2278 * this should be the normal i/o completion case. 2279 * get the status & cmd complete msg then let the 2280 * device driver look at what happened. 2281 */ 2282 sbicxfdone(dev,regs,dev->target); 2283 /* 2284 * check for overlapping cache line, flush if so 2285 */ 2286 #if defined(M68040) || defined(M68060) 2287 if (dev->sc_flags & SBICF_DCFLUSH) { 2288 #if 0 2289 printf("sbic: 68040/68060 DMA cache flush needs" 2290 "fixing? %x:%x\n", 2291 dev->sc_xs->data, dev->sc_xs->datalen); 2292 #endif 2293 } 2294 #endif 2295 #ifdef DEBUG 2296 if( data_pointer_debug > 1 ) 2297 printf("next dmastop: %d(%p:%lx)\n", 2298 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 2299 dev->sc_dmatimo = 0; 2300 #endif 2301 dev->sc_dmastop(dev); /* was dmafree */ 2302 if (acb->flags & ACB_BBUF) { 2303 if ((u_char *)kvtop(acb->sc_dmausrbuf) != acb->sc_usrbufpa) 2304 printf("%s: WARNING - buffer mapping changed %p->%x\n", 2305 dev->sc_dev.dv_xname, acb->sc_usrbufpa, 2306 kvtop(acb->sc_dmausrbuf)); 2307 #ifdef DEBUG 2308 if(data_pointer_debug) 2309 printf("sbicgo:copying %lx bytes from target %d bounce %x\n", 2310 acb->sc_dmausrlen, 2311 dev->target, 2312 kvtop(dev->sc_tinfo[dev->target].bounce)); 2313 #endif 2314 bcopy(dev->sc_tinfo[dev->target].bounce, 2315 acb->sc_dmausrbuf, 2316 acb->sc_dmausrlen); 2317 } 2318 dev->sc_flags &= ~(SBICF_INDMA | SBICF_DCFLUSH); 2319 sbic_scsidone(acb, dev->sc_stat[0]); 2320 SBIC_TRACE(dev); 2321 return SBIC_STATE_DONE; 2322 2323 case SBIC_CSR_XFERRED|DATA_OUT_PHASE: 2324 case SBIC_CSR_XFERRED|DATA_IN_PHASE: 2325 case SBIC_CSR_MIS|DATA_OUT_PHASE: 2326 case SBIC_CSR_MIS|DATA_IN_PHASE: 2327 case SBIC_CSR_MIS_1|DATA_OUT_PHASE: 2328 case SBIC_CSR_MIS_1|DATA_IN_PHASE: 2329 case SBIC_CSR_MIS_2|DATA_OUT_PHASE: 2330 case SBIC_CSR_MIS_2|DATA_IN_PHASE: 2331 if( dev->sc_xs->xs_control & XS_CTL_POLL || dev->sc_flags & SBICF_ICMD 2332 || acb->sc_dmacmd == 0 ) { 2333 /* Do PIO */ 2334 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2335 if (acb->sc_kv.dc_count <= 0) { 2336 printf("sbicnextstate:xfer count %d asr%x csr%x\n", 2337 acb->sc_kv.dc_count, asr, csr); 2338 goto abort; 2339 } 2340 wait = sbic_data_wait; 2341 if( sbicxfstart(regs, 2342 acb->sc_kv.dc_count, 2343 SBIC_PHASE(csr), wait)) { 2344 if( SBIC_PHASE(csr) == DATA_IN_PHASE ) 2345 /* data in? */ 2346 i=sbicxfin(regs, 2347 acb->sc_kv.dc_count, 2348 acb->sc_kv.dc_addr); 2349 else 2350 i=sbicxfout(regs, 2351 acb->sc_kv.dc_count, 2352 acb->sc_kv.dc_addr, 2353 SBIC_PHASE(csr)); 2354 } 2355 acb->sc_kv.dc_addr += 2356 (acb->sc_kv.dc_count - i); 2357 acb->sc_kv.dc_count = i; 2358 } else { 2359 if (acb->sc_kv.dc_count <= 0) { 2360 printf("sbicnextstate:xfer count %d asr%x csr%x\n", 2361 acb->sc_kv.dc_count, asr, csr); 2362 goto abort; 2363 } 2364 /* 2365 * do scatter-gather dma 2366 * hacking the controller chip, ouch.. 2367 */ 2368 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI | 2369 SBIC_MACHINE_DMA_MODE); 2370 /* 2371 * set next dma addr and dec count 2372 */ 2373 #if 0 2374 SBIC_TC_GET(regs, tcnt); 2375 dev->sc_cur->dc_count -= ((dev->sc_tcnt - tcnt) >> 1); 2376 dev->sc_cur->dc_addr += (dev->sc_tcnt - tcnt); 2377 dev->sc_tcnt = acb->sc_tcnt = tcnt; 2378 #else 2379 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 2380 sbic_load_ptrs(dev, regs, dev->target, dev->lun); 2381 #endif 2382 #ifdef DEBUG 2383 if( data_pointer_debug > 1 ) 2384 printf("next dmanext: %d(%p:%lx)\n", 2385 dev->target,dev->sc_cur->dc_addr, 2386 dev->sc_tcnt); 2387 dev->sc_dmatimo = 1; 2388 #endif 2389 dev->sc_tcnt = dev->sc_dmanext(dev); 2390 SBIC_TC_PUT(regs, (unsigned)dev->sc_tcnt); 2391 SET_SBIC_cmd(regs, SBIC_CMD_XFER_INFO); 2392 dev->sc_flags |= SBICF_INDMA; 2393 } 2394 break; 2395 2396 case SBIC_CSR_XFERRED|MESG_IN_PHASE: 2397 case SBIC_CSR_MIS|MESG_IN_PHASE: 2398 case SBIC_CSR_MIS_1|MESG_IN_PHASE: 2399 case SBIC_CSR_MIS_2|MESG_IN_PHASE: 2400 SBIC_TRACE(dev); 2401 return sbicmsgin(dev); 2402 2403 case SBIC_CSR_MSGIN_W_ACK: 2404 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); /* Dunno what I'm ACKing */ 2405 printf("Acking unknown msgin CSR:%02x",csr); 2406 break; 2407 2408 case SBIC_CSR_XFERRED|MESG_OUT_PHASE: 2409 case SBIC_CSR_MIS|MESG_OUT_PHASE: 2410 case SBIC_CSR_MIS_1|MESG_OUT_PHASE: 2411 case SBIC_CSR_MIS_2|MESG_OUT_PHASE: 2412 #ifdef DEBUG 2413 if (sync_debug) 2414 printf ("sending REJECT msg to last msg.\n"); 2415 #endif 2416 2417 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 2418 /* 2419 * should only get here on reject, 2420 * since it's always US that 2421 * initiate a sync transfer 2422 */ 2423 SEND_BYTE(regs, MSG_REJECT); 2424 WAIT_CIP(regs); 2425 if( asr & (SBIC_ASR_BSY|SBIC_ASR_LCI|SBIC_ASR_CIP) ) 2426 printf("next: REJECT sent asr %02x\n", asr); 2427 SBIC_TRACE(dev); 2428 return SBIC_STATE_RUNNING; 2429 2430 case SBIC_CSR_DISC: 2431 case SBIC_CSR_DISC_1: 2432 dev->sc_flags &= ~(SBICF_INDMA|SBICF_SELECTED); 2433 2434 /* Try to schedule another target */ 2435 #ifdef DEBUG 2436 if(reselect_debug>1) 2437 printf("sbicnext target %d disconnected\n", dev->target); 2438 #endif 2439 TAILQ_INSERT_HEAD(&dev->nexus_list, acb, chain); 2440 ++dev->sc_tinfo[dev->target].dconns; 2441 dev->sc_nexus = NULL; 2442 dev->sc_xs = NULL; 2443 2444 if( acb->xs->xs_control & XS_CTL_POLL 2445 || (dev->sc_flags & SBICF_ICMD) 2446 || !sbic_parallel_operations ) { 2447 SBIC_TRACE(dev); 2448 return SBIC_STATE_DISCONNECT; 2449 } 2450 sbic_sched(dev); 2451 SBIC_TRACE(dev); 2452 return SBIC_STATE_DISCONNECT; 2453 2454 case SBIC_CSR_RSLT_NI: 2455 case SBIC_CSR_RSLT_IFY: 2456 GET_SBIC_rselid(regs, newtarget); 2457 /* check SBIC_RID_SIV? */ 2458 newtarget &= SBIC_RID_MASK; 2459 if (csr == SBIC_CSR_RSLT_IFY) { 2460 /* Read IFY msg to avoid lockup */ 2461 GET_SBIC_data(regs, newlun); 2462 WAIT_CIP(regs); 2463 newlun &= SBIC_TLUN_MASK; 2464 CSR_TRACE('r',csr,asr,newtarget); 2465 } else { 2466 /* Need to get IFY message */ 2467 for (newlun = 256; newlun; --newlun) { 2468 GET_SBIC_asr(regs, asr); 2469 if (asr & SBIC_ASR_INT) 2470 break; 2471 delay(1); 2472 } 2473 newlun = 0; /* XXXX */ 2474 if ((asr & SBIC_ASR_INT) == 0) { 2475 #ifdef DEBUG 2476 if (reselect_debug) 2477 printf("RSLT_NI - no IFFY message? asr %x\n", asr); 2478 #endif 2479 } else { 2480 GET_SBIC_csr(regs,csr); 2481 CSR_TRACE('n',csr,asr,newtarget); 2482 if (csr == (SBIC_CSR_MIS | MESG_IN_PHASE) || 2483 csr == (SBIC_CSR_MIS_1 | MESG_IN_PHASE) || 2484 csr == (SBIC_CSR_MIS_2 | MESG_IN_PHASE)) { 2485 sbicmsgin(dev); 2486 newlun = dev->sc_msg[0] & 7; 2487 } else { 2488 printf("RSLT_NI - not MESG_IN_PHASE %x\n", 2489 csr); 2490 } 2491 } 2492 } 2493 #ifdef DEBUG 2494 if(reselect_debug>1 || (reselect_debug && csr==SBIC_CSR_RSLT_NI)) 2495 printf("sbicnext: reselect %s from targ %d lun %d\n", 2496 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", 2497 newtarget, newlun); 2498 #endif 2499 if (dev->sc_nexus) { 2500 #ifdef DEBUG 2501 if (reselect_debug > 1) 2502 printf("%s: reselect %s with active command\n", 2503 dev->sc_dev.dv_xname, 2504 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY"); 2505 #ifdef DDB 2506 /* Debugger();*/ 2507 #endif 2508 #endif 2509 TAILQ_INSERT_HEAD(&dev->ready_list, dev->sc_nexus, chain); 2510 dev->sc_tinfo[dev->target].lubusy &= ~(1 << dev->lun); 2511 dev->sc_nexus = NULL; 2512 dev->sc_xs = NULL; 2513 } 2514 /* Reload sync values for this target */ 2515 if (dev->sc_sync[newtarget].state == SYNC_DONE) 2516 SET_SBIC_syn(regs, SBIC_SYN (dev->sc_sync[newtarget].offset, 2517 dev->sc_sync[newtarget].period)); 2518 else 2519 SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period)); 2520 for (acb = dev->nexus_list.tqh_first; acb; 2521 acb = acb->chain.tqe_next) { 2522 if (acb->xs->sc_link->scsipi_scsi.target != newtarget || 2523 acb->xs->sc_link->scsipi_scsi.lun != newlun) 2524 continue; 2525 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 2526 dev->sc_nexus = acb; 2527 dev->sc_xs = acb->xs; 2528 dev->sc_flags |= SBICF_SELECTED; 2529 dev->target = newtarget; 2530 dev->lun = newlun; 2531 break; 2532 } 2533 if (acb == NULL) { 2534 printf("%s: reselect %s targ %d not in nexus_list %p\n", 2535 dev->sc_dev.dv_xname, 2536 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", newtarget, 2537 &dev->nexus_list.tqh_first); 2538 panic("bad reselect in sbic"); 2539 } 2540 if (csr == SBIC_CSR_RSLT_IFY) 2541 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2542 break; 2543 2544 default: 2545 abort: 2546 /* 2547 * Something unexpected happened -- deal with it. 2548 */ 2549 printf("sbicnextstate: aborting csr %02x asr %02x\n", csr, asr); 2550 #ifdef DDB 2551 Debugger(); 2552 #endif 2553 #ifdef DEBUG 2554 if( data_pointer_debug > 1 ) 2555 printf("next dmastop: %d(%p:%lx)\n", 2556 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 2557 dev->sc_dmatimo = 0; 2558 #endif 2559 dev->sc_dmastop(dev); 2560 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2561 sbicerror(dev, regs, csr); 2562 sbicabort(dev, regs, "next"); 2563 if (dev->sc_flags & SBICF_INDMA) { 2564 /* 2565 * check for overlapping cache line, flush if so 2566 */ 2567 #if defined(M68040) || defined(M68060) 2568 if (dev->sc_flags & SBICF_DCFLUSH) { 2569 #if 0 2570 printf("sbic: 68040/060 DMA cache flush needs" 2571 "fixing? %x:%x\n", 2572 dev->sc_xs->data, dev->sc_xs->datalen); 2573 #endif 2574 } 2575 #endif 2576 dev->sc_flags &= 2577 ~(SBICF_INDMA | SBICF_DCFLUSH); 2578 #ifdef DEBUG 2579 if( data_pointer_debug > 1 ) 2580 printf("next dmastop: %d(%p:%lx)\n", 2581 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 2582 dev->sc_dmatimo = 0; 2583 #endif 2584 dev->sc_dmastop(dev); 2585 sbic_scsidone(acb, -1); 2586 } 2587 SBIC_TRACE(dev); 2588 return SBIC_STATE_ERROR; 2589 } 2590 2591 SBIC_TRACE(dev); 2592 return(SBIC_STATE_RUNNING); 2593 } 2594 2595 2596 /* 2597 * Check if DMA can not be used with specified buffer 2598 */ 2599 2600 int 2601 sbiccheckdmap(bp, len, mask) 2602 void *bp; 2603 u_long len, mask; 2604 { 2605 u_char *buffer; 2606 u_long phy_buf; 2607 u_long phy_len; 2608 2609 buffer = bp; 2610 2611 if (len == 0) 2612 return(0); 2613 2614 while (len) { 2615 phy_buf = kvtop(buffer); 2616 if (len < (phy_len = NBPG - ((int) buffer & PGOFSET))) 2617 phy_len = len; 2618 if (phy_buf & mask) 2619 return(1); 2620 buffer += phy_len; 2621 len -= phy_len; 2622 } 2623 return(0); 2624 } 2625 2626 int 2627 sbictoscsiperiod(dev, regs, a) 2628 struct sbic_softc *dev; 2629 sbic_regmap_t regs; 2630 int a; 2631 { 2632 unsigned int fs; 2633 2634 /* 2635 * cycle = DIV / (2*CLK) 2636 * DIV = FS+2 2637 * best we can do is 200ns at 20Mhz, 2 cycles 2638 */ 2639 2640 GET_SBIC_myid(regs,fs); 2641 fs = (fs >>6) + 2; /* DIV */ 2642 fs = (fs * 10000) / (dev->sc_clkfreq<<1); /* Cycle, in ns */ 2643 if (a < 2) a = 8; /* map to Cycles */ 2644 return ((fs*a)>>2); /* in 4 ns units */ 2645 } 2646 2647 int 2648 sbicfromscsiperiod(dev, regs, p) 2649 struct sbic_softc *dev; 2650 sbic_regmap_t regs; 2651 int p; 2652 { 2653 register unsigned int fs, ret; 2654 2655 /* Just the inverse of the above */ 2656 2657 GET_SBIC_myid(regs,fs); 2658 fs = (fs >>6) + 2; /* DIV */ 2659 fs = (fs * 10000) / (dev->sc_clkfreq<<1); /* Cycle, in ns */ 2660 2661 ret = p << 2; /* in ns units */ 2662 ret = ret / fs; /* in Cycles */ 2663 if (ret < sbic_min_period) 2664 return(sbic_min_period); 2665 2666 /* verify rounding */ 2667 if (sbictoscsiperiod(dev, regs, ret) < p) 2668 ret++; 2669 return (ret >= 8) ? 0 : ret; 2670 } 2671 2672 #ifdef DEBUG 2673 2674 void 2675 sbicdumpstate() 2676 { 2677 u_char csr, asr; 2678 2679 GET_SBIC_asr(debug_sbic_regs,asr); 2680 GET_SBIC_csr(debug_sbic_regs,csr); 2681 printf("%s: asr:csr(%02x:%02x)->(%02x:%02x)\n", 2682 (routine==1)?"sbicgo": 2683 (routine==2)?"sbicintr": 2684 (routine==3)?"sbicicmd": 2685 (routine==4)?"sbicnext":"unknown", 2686 debug_asr, debug_csr, asr, csr); 2687 2688 } 2689 2690 void 2691 sbictimeout(dev) 2692 struct sbic_softc *dev; 2693 { 2694 int s, asr; 2695 2696 s = splbio(); 2697 if (dev->sc_dmatimo) { 2698 if (dev->sc_dmatimo > 1) { 2699 printf("%s: dma timeout #%d\n", 2700 dev->sc_dev.dv_xname, dev->sc_dmatimo - 1); 2701 GET_SBIC_asr(dev->sc_sbic, asr); 2702 if( asr & SBIC_ASR_INT ) { 2703 /* We need to service a missed IRQ */ 2704 printf("Servicing a missed int:(%02x,%02x)->(%02x,??)\n", 2705 debug_asr, debug_csr, asr); 2706 sbicintr(dev); 2707 } 2708 sbicdumpstate(); 2709 } 2710 dev->sc_dmatimo++; 2711 } 2712 splx(s); 2713 callout_reset(&dev->sc_timo_ch, 30 * hz, 2714 (void *)sbictimeout, dev); 2715 } 2716 2717 void 2718 sbic_dump_acb(acb) 2719 struct sbic_acb *acb; 2720 { 2721 u_char *b = (u_char *) &acb->cmd; 2722 int i; 2723 2724 printf("acb@%p ", acb); 2725 if (acb->xs == NULL) { 2726 printf("<unused>\n"); 2727 return; 2728 } 2729 printf("(%d:%d) flags %2x clen %2d cmd ", 2730 acb->xs->sc_link->scsipi_scsi.target, 2731 acb->xs->sc_link->scsipi_scsi.lun, acb->flags, acb->clen); 2732 for (i = acb->clen; i; --i) 2733 printf(" %02x", *b++); 2734 printf("\n"); 2735 printf(" xs: %8p data %8p:%04x ", acb->xs, acb->xs->data, 2736 acb->xs->datalen); 2737 printf("va %8p:%04x ", acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 2738 printf("pa %8p:%04x tcnt %lx\n", acb->sc_pa.dc_addr, acb->sc_pa.dc_count, 2739 acb->sc_tcnt); 2740 } 2741 2742 void 2743 sbic_dump(dev) 2744 struct sbic_softc *dev; 2745 { 2746 sbic_regmap_t regs; 2747 u_char csr, asr; 2748 struct sbic_acb *acb; 2749 int s; 2750 int i; 2751 2752 s = splbio(); 2753 regs = dev->sc_sbic; 2754 #if CSR_TRACE_SIZE 2755 printf("csr trace: "); 2756 i = csr_traceptr; 2757 do { 2758 printf("%c%02x%02x%02x ", csr_trace[i].whr, 2759 csr_trace[i].csr, csr_trace[i].asr, csr_trace[i].xtn); 2760 switch(csr_trace[i].whr) { 2761 case 'g': 2762 printf("go "); break; 2763 case 's': 2764 printf("select "); break; 2765 case 'y': 2766 printf("select+ "); break; 2767 case 'i': 2768 printf("intr "); break; 2769 case 'f': 2770 printf("finish "); break; 2771 case '>': 2772 printf("out "); break; 2773 case '<': 2774 printf("in "); break; 2775 case 'm': 2776 printf("msgin "); break; 2777 case 'x': 2778 printf("msginx "); break; 2779 case 'X': 2780 printf("msginX "); break; 2781 case 'r': 2782 printf("reselect "); break; 2783 case 'I': 2784 printf("icmd "); break; 2785 case 'a': 2786 printf("abort "); break; 2787 default: 2788 printf("? "); 2789 } 2790 switch(csr_trace[i].csr) { 2791 case 0x11: 2792 printf("INITIATOR"); break; 2793 case 0x16: 2794 printf("S_XFERRED"); break; 2795 case 0x20: 2796 printf("MSGIN_ACK"); break; 2797 case 0x41: 2798 printf("DISC"); break; 2799 case 0x42: 2800 printf("SEL_TIMEO"); break; 2801 case 0x80: 2802 printf("RSLT_NI"); break; 2803 case 0x81: 2804 printf("RSLT_IFY"); break; 2805 case 0x85: 2806 printf("DISC_1"); break; 2807 case 0x18: case 0x19: case 0x1a: 2808 case 0x1b: case 0x1e: case 0x1f: 2809 case 0x28: case 0x29: case 0x2a: 2810 case 0x2b: case 0x2e: case 0x2f: 2811 case 0x48: case 0x49: case 0x4a: 2812 case 0x4b: case 0x4e: case 0x4f: 2813 case 0x88: case 0x89: case 0x8a: 2814 case 0x8b: case 0x8e: case 0x8f: 2815 switch(csr_trace[i].csr & 0xf0) { 2816 case 0x10: 2817 printf("DONE_"); break; 2818 case 0x20: 2819 printf("STOP_"); break; 2820 case 0x40: 2821 printf("ERR_"); break; 2822 case 0x80: 2823 printf("REQ_"); break; 2824 } 2825 switch(csr_trace[i].csr & 7) { 2826 case 0: 2827 printf("DATA_OUT"); break; 2828 case 1: 2829 printf("DATA_IN"); break; 2830 case 2: 2831 printf("CMD"); break; 2832 case 3: 2833 printf("STATUS"); break; 2834 case 6: 2835 printf("MSG_OUT"); break; 2836 case 7: 2837 printf("MSG_IN"); break; 2838 default: 2839 printf("invld phs"); 2840 } 2841 break; 2842 default: printf("****"); break; 2843 } 2844 if (csr_trace[i].asr & SBIC_ASR_INT) 2845 printf(" ASR_INT"); 2846 if (csr_trace[i].asr & SBIC_ASR_LCI) 2847 printf(" ASR_LCI"); 2848 if (csr_trace[i].asr & SBIC_ASR_BSY) 2849 printf(" ASR_BSY"); 2850 if (csr_trace[i].asr & SBIC_ASR_CIP) 2851 printf(" ASR_CIP"); 2852 printf("\n"); 2853 i = (i + 1) & (CSR_TRACE_SIZE - 1); 2854 } while (i != csr_traceptr); 2855 #endif 2856 GET_SBIC_asr(regs, asr); 2857 if ((asr & SBIC_ASR_INT) == 0) 2858 GET_SBIC_csr(regs, csr); 2859 else 2860 csr = 0; 2861 printf("%s@%p regs %p/%p asr %x csr %x\n", dev->sc_dev.dv_xname, 2862 dev, regs.sbic_asr_p, regs.sbic_value_p, asr, csr); 2863 if ((acb = dev->free_list.tqh_first)) { 2864 printf("Free list:\n"); 2865 while (acb) { 2866 sbic_dump_acb(acb); 2867 acb = acb->chain.tqe_next; 2868 } 2869 } 2870 if ((acb = dev->ready_list.tqh_first)) { 2871 printf("Ready list:\n"); 2872 while (acb) { 2873 sbic_dump_acb(acb); 2874 acb = acb->chain.tqe_next; 2875 } 2876 } 2877 if ((acb = dev->nexus_list.tqh_first)) { 2878 printf("Nexus list:\n"); 2879 while (acb) { 2880 sbic_dump_acb(acb); 2881 acb = acb->chain.tqe_next; 2882 } 2883 } 2884 if (dev->sc_nexus) { 2885 printf("nexus:\n"); 2886 sbic_dump_acb(dev->sc_nexus); 2887 } 2888 printf("sc_xs %p targ %d lun %d flags %x tcnt %lx dmacmd %x mask %lx\n", 2889 dev->sc_xs, dev->target, dev->lun, dev->sc_flags, dev->sc_tcnt, 2890 dev->sc_dmacmd, dev->sc_dmamask); 2891 for (i = 0; i < 8; ++i) { 2892 if (dev->sc_tinfo[i].cmds > 2) { 2893 printf("tgt %d: cmds %d disc %d senses %d lubusy %x\n", 2894 i, dev->sc_tinfo[i].cmds, 2895 dev->sc_tinfo[i].dconns, 2896 dev->sc_tinfo[i].senses, 2897 dev->sc_tinfo[i].lubusy); 2898 } 2899 } 2900 splx(s); 2901 } 2902 2903 #endif 2904
Indexes created Thu Oct 02 14:10:14 GMT 2025