sbic.c revision 1.42
1 /* $NetBSD: sbic.c,v 1.42 2000/06/29 08:44:05 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 1994 Christian E. Hopps 5 * Copyright (c) 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * Van Jacobson of Lawrence Berkeley Laboratory. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the University of 22 * California, Berkeley and its contributors. 23 * 4. Neither the name of the University nor the names of its contributors 24 * may be used to endorse or promote products derived from this software 25 * without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 37 * SUCH DAMAGE. 38 * 39 * @(#)scsi.c 7.5 (Berkeley) 5/4/91 40 */ 41 42 /* 43 * AMIGA AMD 33C93 scsi adaptor driver 44 */ 45 46 #include "opt_ddb.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/device.h> 51 #include <sys/kernel.h> /* For hz */ 52 #include <sys/disklabel.h> 53 #include <sys/dkstat.h> 54 #include <sys/buf.h> 55 #include <dev/scsipi/scsi_all.h> 56 #include <dev/scsipi/scsipi_all.h> 57 #include <dev/scsipi/scsiconf.h> 58 #include <uvm/uvm_extern.h> 59 #include <machine/cpu.h> 60 #include <amiga/amiga/device.h> 61 #include <amiga/amiga/custom.h> 62 #include <amiga/amiga/isr.h> 63 #include <amiga/dev/dmavar.h> 64 #include <amiga/dev/sbicreg.h> 65 #include <amiga/dev/sbicvar.h> 66 67 /* These are for bounce buffers */ 68 #include <amiga/amiga/cc.h> 69 #include <amiga/dev/zbusvar.h> 70 71 /* Since I can't find this in any other header files */ 72 #define SCSI_PHASE(reg) (reg&0x07) 73 74 /* 75 * SCSI delays 76 * In u-seconds, primarily for state changes on the SPC. 77 */ 78 #define SBIC_CMD_WAIT 50000 /* wait per step of 'immediate' cmds */ 79 #define SBIC_DATA_WAIT 50000 /* wait per data in/out step */ 80 #define SBIC_INIT_WAIT 50000 /* wait per step (both) during init */ 81 82 #define SBIC_WAIT(regs, until, timeo) sbicwait(regs, until, timeo, __LINE__) 83 84 int sbicicmd __P((struct sbic_softc *, int, int, void *, int, void *, int)); 85 int sbicgo __P((struct sbic_softc *, struct scsipi_xfer *)); 86 int sbicdmaok __P((struct sbic_softc *, struct scsipi_xfer *)); 87 int sbicwait __P((sbic_regmap_t, char, int , int)); 88 int sbiccheckdmap __P((void *, u_long, u_long)); 89 int sbicselectbus __P((struct sbic_softc *, sbic_regmap_t, u_char, u_char, u_char)); 90 int sbicxfstart __P((sbic_regmap_t, int, u_char, int)); 91 int sbicxfout __P((sbic_regmap_t regs, int, void *, int)); 92 int sbicfromscsiperiod __P((struct sbic_softc *, sbic_regmap_t, int)); 93 int sbictoscsiperiod __P((struct sbic_softc *, sbic_regmap_t, int)); 94 int sbicpoll __P((struct sbic_softc *)); 95 int sbicnextstate __P((struct sbic_softc *, u_char, u_char)); 96 int sbicmsgin __P((struct sbic_softc *)); 97 int sbicxfin __P((sbic_regmap_t regs, int, void *)); 98 int sbicabort __P((struct sbic_softc *, sbic_regmap_t, char *)); 99 void sbicxfdone __P((struct sbic_softc *, sbic_regmap_t, int)); 100 void sbicerror __P((struct sbic_softc *, sbic_regmap_t, u_char)); 101 void sbicstart __P((struct sbic_softc *)); 102 void sbicreset __P((struct sbic_softc *)); 103 void sbic_scsidone __P((struct sbic_acb *, int)); 104 void sbic_sched __P((struct sbic_softc *)); 105 void sbic_save_ptrs __P((struct sbic_softc *, sbic_regmap_t,int,int)); 106 void sbic_load_ptrs __P((struct sbic_softc *, sbic_regmap_t,int,int)); 107 #ifdef DEBUG 108 void sbicdumpstate __P((void)); 109 void sbic_dump_acb __P((struct sbic_acb *)); 110 #endif 111 112 /* 113 * Synch xfer parameters, and timing conversions 114 */ 115 int sbic_min_period = SBIC_SYN_MIN_PERIOD; /* in cycles = f(ICLK,FSn) */ 116 int sbic_max_offset = SBIC_SYN_MAX_OFFSET; /* pure number */ 117 118 int sbic_cmd_wait = SBIC_CMD_WAIT; 119 int sbic_data_wait = SBIC_DATA_WAIT; 120 int sbic_init_wait = SBIC_INIT_WAIT; 121 122 /* 123 * was broken before.. now if you want this you get it for all drives 124 * on sbic controllers. 125 */ 126 u_char sbic_inhibit_sync[8]; 127 int sbic_enable_reselect = 1; 128 int sbic_clock_override = 0; 129 int sbic_no_dma = 0; 130 int sbic_parallel_operations = 1; 131 132 #ifdef DEBUG 133 sbic_regmap_t debug_sbic_regs; 134 int sbicdma_ops = 0; /* total DMA operations */ 135 int sbicdma_bounces = 0; /* number operations using bounce buffer */ 136 int sbicdma_hits = 0; /* number of DMA chains that were contiguous */ 137 int sbicdma_misses = 0; /* number of DMA chains that were not contiguous */ 138 int sbicdma_saves = 0; 139 #define QPRINTF(a) if (sbic_debug > 1) printf a 140 int sbic_debug = 0; 141 int sync_debug = 0; 142 int sbic_dma_debug = 0; 143 int reselect_debug = 0; 144 int report_sense = 0; 145 int data_pointer_debug = 0; 146 u_char debug_asr, debug_csr, routine; 147 void sbictimeout __P((struct sbic_softc *dev)); 148 149 #define CSR_TRACE_SIZE 32 150 #if CSR_TRACE_SIZE 151 #define CSR_TRACE(w,c,a,x) do { \ 152 int s = splbio(); \ 153 csr_trace[csr_traceptr].whr = (w); csr_trace[csr_traceptr].csr = (c); \ 154 csr_trace[csr_traceptr].asr = (a); csr_trace[csr_traceptr].xtn = (x); \ 155 dma_cachectl((caddr_t)&csr_trace[csr_traceptr], sizeof(csr_trace[0])); \ 156 csr_traceptr = (csr_traceptr + 1) & (CSR_TRACE_SIZE - 1); \ 157 /* dma_cachectl((caddr_t)&csr_traceptr, sizeof(csr_traceptr));*/ \ 158 splx(s); \ 159 } while (0) 160 int csr_traceptr; 161 int csr_tracesize = CSR_TRACE_SIZE; 162 struct { 163 u_char whr; 164 u_char csr; 165 u_char asr; 166 u_char xtn; 167 } csr_trace[CSR_TRACE_SIZE]; 168 #else 169 #define CSR_TRACE(w,c,a,x) 170 #endif 171 172 #define SBIC_TRACE_SIZE 0 173 #if SBIC_TRACE_SIZE 174 #define SBIC_TRACE(dev) do { \ 175 int s = splbio(); \ 176 sbic_trace[sbic_traceptr].sp = &s; \ 177 sbic_trace[sbic_traceptr].line = __LINE__; \ 178 sbic_trace[sbic_traceptr].sr = s; \ 179 sbic_trace[sbic_traceptr].csr = csr_traceptr; \ 180 dma_cachectl(&sbic_trace[sbic_traceptr], sizeof(sbic_trace[0])); \ 181 sbic_traceptr = (sbic_traceptr + 1) & (SBIC_TRACE_SIZE - 1); \ 182 dma_cachectl(&sbic_traceptr, sizeof(sbic_traceptr)); \ 183 if (dev) dma_cachectl(dev, sizeof(*dev)); \ 184 splx(s); \ 185 } while (0) 186 int sbic_traceptr; 187 int sbic_tracesize = SBIC_TRACE_SIZE; 188 struct { 189 void *sp; 190 u_short line; 191 u_short sr; 192 int csr; 193 } sbic_trace[SBIC_TRACE_SIZE]; 194 #else 195 #define SBIC_TRACE(dev) 196 #endif 197 198 #else /* DEBUG */ 199 #define QPRINTF(a) 200 #define CSR_TRACE(w,c,a,x) 201 #define SBIC_TRACE(dev) 202 #endif /* DEBUG */ 203 204 /* 205 * default minphys routine for sbic based controllers 206 */ 207 void 208 sbic_minphys(bp) 209 struct buf *bp; 210 { 211 212 /* 213 * No max transfer at this level. 214 */ 215 minphys(bp); 216 } 217 218 /* 219 * Save DMA pointers. Take into account partial transfer. Shut down DMA. 220 */ 221 void 222 sbic_save_ptrs(dev, regs, target, lun) 223 struct sbic_softc *dev; 224 sbic_regmap_t regs; 225 int target, lun; 226 { 227 int count, asr, s; 228 struct sbic_acb* acb; 229 230 SBIC_TRACE(dev); 231 if( !dev->sc_cur ) return; 232 if( !(dev->sc_flags & SBICF_INDMA) ) return; /* DMA not active */ 233 234 s = splbio(); 235 236 acb = dev->sc_nexus; 237 count = -1; 238 do { 239 GET_SBIC_asr(regs, asr); 240 if( asr & SBIC_ASR_DBR ) { 241 printf("sbic_save_ptrs: asr %02x canceled!\n", asr); 242 splx(s); 243 SBIC_TRACE(dev); 244 return; 245 } 246 } while( asr & (SBIC_ASR_BSY|SBIC_ASR_CIP) ); 247 248 /* Save important state */ 249 /* must be done before dmastop */ 250 acb->sc_dmacmd = dev->sc_dmacmd; 251 SBIC_TC_GET(regs, count); 252 253 /* Shut down DMA ====CAREFUL==== */ 254 dev->sc_dmastop(dev); 255 dev->sc_flags &= ~SBICF_INDMA; 256 SBIC_TC_PUT(regs, 0); 257 258 #ifdef DEBUG 259 if(!count && sbic_debug) printf("%dcount0",target); 260 if(data_pointer_debug == -1) 261 printf("SBIC saving target %d data pointers from (%p,%x)%xASR:%02x", 262 target, dev->sc_cur->dc_addr, dev->sc_cur->dc_count, 263 acb->sc_dmacmd, asr); 264 #endif 265 266 /* Fixup partial xfers */ 267 acb->sc_kv.dc_addr += (dev->sc_tcnt - count); 268 acb->sc_kv.dc_count -= (dev->sc_tcnt - count); 269 acb->sc_pa.dc_addr += (dev->sc_tcnt - count); 270 acb->sc_pa.dc_count -= ((dev->sc_tcnt - count)>>1); 271 272 acb->sc_tcnt = dev->sc_tcnt = count; 273 #ifdef DEBUG 274 if(data_pointer_debug) 275 printf(" at (%p,%x):%x\n", 276 dev->sc_cur->dc_addr, dev->sc_cur->dc_count,count); 277 sbicdma_saves++; 278 #endif 279 splx(s); 280 SBIC_TRACE(dev); 281 } 282 283 284 /* 285 * DOES NOT RESTART DMA!!! 286 */ 287 void sbic_load_ptrs(dev, regs, target, lun) 288 struct sbic_softc *dev; 289 sbic_regmap_t regs; 290 int target, lun; 291 { 292 int s, count; 293 char* vaddr, * paddr; 294 struct sbic_acb *acb; 295 296 SBIC_TRACE(dev); 297 acb = dev->sc_nexus; 298 if( !acb->sc_kv.dc_count ) { 299 /* No data to xfer */ 300 SBIC_TRACE(dev); 301 return; 302 } 303 304 s = splbio(); 305 306 dev->sc_last = dev->sc_cur = &acb->sc_pa; 307 dev->sc_tcnt = acb->sc_tcnt; 308 dev->sc_dmacmd = acb->sc_dmacmd; 309 310 #ifdef DEBUG 311 sbicdma_ops++; 312 #endif 313 if( !dev->sc_tcnt ) { 314 /* sc_tcnt == 0 implies end of segment */ 315 316 /* do kvm to pa mappings */ 317 paddr = acb->sc_pa.dc_addr = 318 (char *) kvtop(acb->sc_kv.dc_addr); 319 320 vaddr = acb->sc_kv.dc_addr; 321 count = acb->sc_kv.dc_count; 322 for(count = (NBPG - ((int)vaddr & PGOFSET)); 323 count < acb->sc_kv.dc_count 324 && (char*)kvtop(vaddr + count + 4) == paddr + count + 4; 325 count += NBPG); 326 /* If it's all contiguous... */ 327 if(count > acb->sc_kv.dc_count ) { 328 count = acb->sc_kv.dc_count; 329 #ifdef DEBUG 330 sbicdma_hits++; 331 #endif 332 } else { 333 #ifdef DEBUG 334 sbicdma_misses++; 335 #endif 336 } 337 acb->sc_tcnt = count; 338 acb->sc_pa.dc_count = count >> 1; 339 340 #ifdef DEBUG 341 if(data_pointer_debug) 342 printf("DMA recalc:kv(%p,%x)pa(%p,%lx)\n", 343 acb->sc_kv.dc_addr, 344 acb->sc_kv.dc_count, 345 acb->sc_pa.dc_addr, 346 acb->sc_tcnt); 347 #endif 348 } 349 splx(s); 350 #ifdef DEBUG 351 if(data_pointer_debug) 352 printf("SBIC restoring target %d data pointers at (%p,%x)%x\n", 353 target, dev->sc_cur->dc_addr, dev->sc_cur->dc_count, 354 dev->sc_dmacmd); 355 #endif 356 SBIC_TRACE(dev); 357 } 358 359 /* 360 * used by specific sbic controller 361 * 362 * it appears that the higher level code does nothing with LUN's 363 * so I will too. I could plug it in, however so could they 364 * in scsi_scsipi_cmd(). 365 */ 366 int 367 sbic_scsicmd(xs) 368 struct scsipi_xfer *xs; 369 { 370 struct sbic_acb *acb; 371 struct sbic_softc *dev; 372 struct scsipi_link *slp; 373 int flags, s, stat; 374 375 slp = xs->sc_link; 376 dev = slp->adapter_softc; 377 SBIC_TRACE(dev); 378 flags = xs->xs_control; 379 380 if (flags & XS_CTL_DATA_UIO) 381 panic("sbic: scsi data uio requested"); 382 383 if (dev->sc_nexus && flags & XS_CTL_POLL) 384 panic("sbic_scsicmd: busy"); 385 386 if (slp->scsipi_scsi.target == slp->scsipi_scsi.adapter_target) 387 return ESCAPE_NOT_SUPPORTED; 388 389 s = splbio(); 390 acb = dev->free_list.tqh_first; 391 if (acb) 392 TAILQ_REMOVE(&dev->free_list, acb, chain); 393 splx(s); 394 395 if (acb == NULL) { 396 #ifdef DEBUG 397 printf("sbic_scsicmd: unable to queue request for target %d\n", 398 slp->scsipi_scsi.target); 399 #ifdef DDB 400 Debugger(); 401 #endif 402 #endif 403 xs->error = XS_DRIVER_STUFFUP; 404 SBIC_TRACE(dev); 405 return(TRY_AGAIN_LATER); 406 } 407 408 acb->flags = ACB_ACTIVE; 409 if (flags & XS_CTL_DATA_IN) 410 acb->flags |= ACB_DATAIN; 411 acb->xs = xs; 412 bcopy(xs->cmd, &acb->cmd, xs->cmdlen); 413 acb->clen = xs->cmdlen; 414 acb->sc_kv.dc_addr = xs->data; 415 acb->sc_kv.dc_count = xs->datalen; 416 acb->pa_addr = xs->data ? (char *)kvtop(xs->data) : 0; /* XXXX check */ 417 418 if (flags & XS_CTL_POLL) { 419 s = splbio(); 420 /* 421 * This has major side effects -- it locks up the machine 422 */ 423 424 dev->sc_flags |= SBICF_ICMD; 425 do { 426 while(dev->sc_nexus) 427 sbicpoll(dev); 428 dev->sc_nexus = acb; 429 dev->sc_stat[0] = -1; 430 dev->sc_xs = xs; 431 dev->target = slp->scsipi_scsi.target; 432 dev->lun = slp->scsipi_scsi.lun; 433 stat = sbicicmd(dev, slp->scsipi_scsi.target, slp->scsipi_scsi.lun, 434 &acb->cmd, acb->clen, 435 acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 436 } while (dev->sc_nexus != acb); 437 sbic_scsidone(acb, stat); 438 439 splx(s); 440 SBIC_TRACE(dev); 441 return(COMPLETE); 442 } 443 444 s = splbio(); 445 TAILQ_INSERT_TAIL(&dev->ready_list, acb, chain); 446 447 if (dev->sc_nexus) { 448 splx(s); 449 SBIC_TRACE(dev); 450 return(SUCCESSFULLY_QUEUED); 451 } 452 453 /* 454 * nothing is active, try to start it now. 455 */ 456 sbic_sched(dev); 457 splx(s); 458 459 SBIC_TRACE(dev); 460 /* TODO: add sbic_poll to do XS_CTL_POLL operations */ 461 #if 0 462 if (flags & XS_CTL_POLL) 463 return(COMPLETE); 464 #endif 465 return(SUCCESSFULLY_QUEUED); 466 } 467 468 /* 469 * attempt to start the next available command 470 */ 471 void 472 sbic_sched(dev) 473 struct sbic_softc *dev; 474 { 475 struct scsipi_xfer *xs; 476 struct scsipi_link *slp; 477 struct sbic_acb *acb; 478 int flags, /*phase,*/ stat, i; 479 480 SBIC_TRACE(dev); 481 if (dev->sc_nexus) 482 return; /* a command is current active */ 483 484 SBIC_TRACE(dev); 485 for (acb = dev->ready_list.tqh_first; acb; acb = acb->chain.tqe_next) { 486 slp = acb->xs->sc_link; 487 i = slp->scsipi_scsi.target; 488 if (!(dev->sc_tinfo[i].lubusy & (1 << slp->scsipi_scsi.lun))) { 489 struct sbic_tinfo *ti = &dev->sc_tinfo[i]; 490 491 TAILQ_REMOVE(&dev->ready_list, acb, chain); 492 dev->sc_nexus = acb; 493 slp = acb->xs->sc_link; 494 ti = &dev->sc_tinfo[slp->scsipi_scsi.target]; 495 ti->lubusy |= (1 << slp->scsipi_scsi.lun); 496 acb->sc_pa.dc_addr = acb->pa_addr; /* XXXX check */ 497 break; 498 } 499 } 500 501 SBIC_TRACE(dev); 502 if (acb == NULL) 503 return; /* did not find an available command */ 504 505 dev->sc_xs = xs = acb->xs; 506 slp = xs->sc_link; 507 flags = xs->xs_control; 508 509 if (flags & XS_CTL_RESET) 510 sbicreset(dev); 511 512 #ifdef DEBUG 513 if( data_pointer_debug > 1 ) 514 printf("sbic_sched(%d,%d)\n",slp->scsipi_scsi.target, 515 slp->scsipi_scsi.lun); 516 #endif 517 dev->sc_stat[0] = -1; 518 dev->target = slp->scsipi_scsi.target; 519 dev->lun = slp->scsipi_scsi.lun; 520 if ( flags & XS_CTL_POLL || ( !sbic_parallel_operations 521 && (sbicdmaok(dev, xs) == 0))) 522 stat = sbicicmd(dev, slp->scsipi_scsi.target, 523 slp->scsipi_scsi.lun, &acb->cmd, 524 acb->clen, acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 525 else if (sbicgo(dev, xs) == 0 && xs->error != XS_SELTIMEOUT) { 526 SBIC_TRACE(dev); 527 return; 528 } else 529 stat = dev->sc_stat[0]; 530 531 sbic_scsidone(acb, stat); 532 SBIC_TRACE(dev); 533 } 534 535 void 536 sbic_scsidone(acb, stat) 537 struct sbic_acb *acb; 538 int stat; 539 { 540 struct scsipi_xfer *xs; 541 struct scsipi_link *slp; 542 struct sbic_softc *dev; 543 int dosched = 0; 544 545 xs = acb->xs; 546 slp = xs->sc_link; 547 dev = slp->adapter_softc; 548 SBIC_TRACE(dev); 549 #ifdef DIAGNOSTIC 550 if (acb == NULL || xs == NULL) { 551 printf("sbic_scsidone -- (%d,%d) no scsi_xfer\n", 552 dev->target, dev->lun); 553 #ifdef DDB 554 Debugger(); 555 #endif 556 return; 557 } 558 #endif 559 /* 560 * is this right? 561 */ 562 xs->status = stat; 563 564 #ifdef DEBUG 565 if( data_pointer_debug > 1 ) 566 printf("scsidone: (%d,%d)->(%d,%d)%02x\n", 567 slp->scsipi_scsi.target, slp->scsipi_scsi.lun, 568 dev->target, dev->lun, stat); 569 if( xs->sc_link->scsipi_scsi.target == 570 dev->sc_link.scsipi_scsi.adapter_target ) 571 panic("target == hostid"); 572 #endif 573 574 if (xs->error == XS_NOERROR && !(acb->flags & ACB_CHKSENSE)) { 575 if (stat == SCSI_CHECK) { 576 /* Schedule a REQUEST SENSE */ 577 struct scsipi_sense *ss = (void *)&acb->cmd; 578 #ifdef DEBUG 579 if (report_sense) 580 printf("sbic_scsidone: autosense %02x targ %d lun %d", 581 acb->cmd.opcode, slp->scsipi_scsi.target, 582 slp->scsipi_scsi.lun); 583 #endif 584 bzero(ss, sizeof(*ss)); 585 ss->opcode = REQUEST_SENSE; 586 ss->byte2 = slp->scsipi_scsi.lun << 5; 587 ss->length = sizeof(struct scsipi_sense_data); 588 acb->clen = sizeof(*ss); 589 acb->sc_kv.dc_addr = (char *)&xs->sense.scsi_sense; 590 acb->sc_kv.dc_count = sizeof(struct scsipi_sense_data); 591 acb->pa_addr = (char *)kvtop((u_char *)&xs->sense.scsi_sense); /* XXX check */ 592 acb->flags = ACB_ACTIVE | ACB_CHKSENSE | ACB_DATAIN; 593 TAILQ_INSERT_HEAD(&dev->ready_list, acb, chain); 594 dev->sc_tinfo[slp->scsipi_scsi.target].lubusy &= 595 ~(1 << slp->scsipi_scsi.lun); 596 dev->sc_tinfo[slp->scsipi_scsi.target].senses++; 597 if (dev->sc_nexus == acb) { 598 dev->sc_nexus = NULL; 599 dev->sc_xs = NULL; 600 sbic_sched(dev); 601 } 602 SBIC_TRACE(dev); 603 return; 604 } 605 } 606 if (xs->error == XS_NOERROR && (acb->flags & ACB_CHKSENSE)) { 607 xs->error = XS_SENSE; 608 #ifdef DEBUG 609 if (report_sense) 610 printf(" => %02x %02x\n", xs->sense.scsi_sense.flags, 611 xs->sense.scsi_sense.extra_bytes[3]); 612 #endif 613 } else { 614 xs->resid = 0; /* XXXX */ 615 } 616 #if whataboutthisone 617 case SCSI_BUSY: 618 xs->error = XS_BUSY; 619 break; 620 #endif 621 xs->xs_status |= XS_STS_DONE; 622 623 /* 624 * Remove the ACB from whatever queue it's on. We have to do a bit of 625 * a hack to figure out which queue it's on. Note that it is *not* 626 * necessary to cdr down the ready queue, but we must cdr down the 627 * nexus queue and see if it's there, so we can mark the unit as no 628 * longer busy. This code is sickening, but it works. 629 */ 630 if (acb == dev->sc_nexus) { 631 dev->sc_nexus = NULL; 632 dev->sc_xs = NULL; 633 dev->sc_tinfo[slp->scsipi_scsi.target].lubusy &= 634 ~(1<<slp->scsipi_scsi.lun); 635 if (dev->ready_list.tqh_first) 636 dosched = 1; /* start next command */ 637 } else if (dev->ready_list.tqh_last == &acb->chain.tqe_next) { 638 TAILQ_REMOVE(&dev->ready_list, acb, chain); 639 } else { 640 register struct sbic_acb *acb2; 641 for (acb2 = dev->nexus_list.tqh_first; acb2; 642 acb2 = acb2->chain.tqe_next) { 643 if (acb2 == acb) { 644 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 645 dev->sc_tinfo[slp->scsipi_scsi.target].lubusy 646 &= ~(1<<slp->scsipi_scsi.lun); 647 break; 648 } 649 } 650 if (acb2) 651 ; 652 else if (acb->chain.tqe_next) { 653 TAILQ_REMOVE(&dev->ready_list, acb, chain); 654 } else { 655 printf("%s: can't find matching acb\n", 656 dev->sc_dev.dv_xname); 657 #ifdef DDB 658 Debugger(); 659 #endif 660 } 661 } 662 /* Put it on the free list. */ 663 acb->flags = ACB_FREE; 664 TAILQ_INSERT_HEAD(&dev->free_list, acb, chain); 665 666 dev->sc_tinfo[slp->scsipi_scsi.target].cmds++; 667 668 scsipi_done(xs); 669 670 if (dosched) 671 sbic_sched(dev); 672 SBIC_TRACE(dev); 673 } 674 675 int 676 sbicdmaok(dev, xs) 677 struct sbic_softc *dev; 678 struct scsipi_xfer *xs; 679 { 680 if (sbic_no_dma || !xs->datalen || xs->datalen & 0x1 || 681 (u_int)xs->data & 0x3) 682 return(0); 683 /* 684 * controller supports dma to any addresses? 685 */ 686 else if ((dev->sc_flags & SBICF_BADDMA) == 0) 687 return(1); 688 /* 689 * this address is ok for dma? 690 */ 691 else if (sbiccheckdmap(xs->data, xs->datalen, dev->sc_dmamask) == 0) 692 return(1); 693 /* 694 * we have a bounce buffer? 695 */ 696 else if (dev->sc_tinfo[xs->sc_link->scsipi_scsi.target].bounce) 697 return(1); 698 /* 699 * try to get one 700 */ 701 else if ((dev->sc_tinfo[xs->sc_link->scsipi_scsi.target].bounce 702 = (char *)alloc_z2mem(MAXPHYS))) { 703 if (isztwomem(dev->sc_tinfo[xs->sc_link->scsipi_scsi.target].bounce)) 704 printf("alloc ZII target %d bounce pa 0x%x\n", 705 xs->sc_link->scsipi_scsi.target, 706 kvtop(dev->sc_tinfo[xs->sc_link->scsipi_scsi.target].bounce)); 707 else if (dev->sc_tinfo[xs->sc_link->scsipi_scsi.target].bounce) 708 printf("alloc CHIP target %d bounce pa 0x%p\n", 709 xs->sc_link->scsipi_scsi.target, 710 PREP_DMA_MEM(dev->sc_tinfo[xs->sc_link->scsipi_scsi.target].bounce)); 711 return(1); 712 } 713 714 return(0); 715 } 716 717 718 int 719 sbicwait(regs, until, timeo, line) 720 sbic_regmap_t regs; 721 char until; 722 int timeo; 723 int line; 724 { 725 u_char val; 726 int csr; 727 728 SBIC_TRACE((struct sbic_softc *)0); 729 if (timeo == 0) 730 timeo = 1000000; /* some large value.. */ 731 732 GET_SBIC_asr(regs,val); 733 while ((val & until) == 0) { 734 if (timeo-- == 0) { 735 GET_SBIC_csr(regs, csr); 736 printf("sbicwait TIMEO @%d with asr=x%x csr=x%x\n", 737 line, val, csr); 738 #if defined(DDB) && defined(DEBUG) 739 Debugger(); 740 #endif 741 return(val); /* Maybe I should abort */ 742 break; 743 } 744 DELAY(1); 745 GET_SBIC_asr(regs,val); 746 } 747 SBIC_TRACE((struct sbic_softc *)0); 748 return(val); 749 } 750 751 int 752 sbicabort(dev, regs, where) 753 struct sbic_softc *dev; 754 sbic_regmap_t regs; 755 char *where; 756 { 757 u_char csr, asr; 758 759 GET_SBIC_asr(regs, asr); 760 GET_SBIC_csr(regs, csr); 761 762 printf ("%s: abort %s: csr = 0x%02x, asr = 0x%02x\n", 763 dev->sc_dev.dv_xname, where, csr, asr); 764 765 766 #if 0 767 /* Clean up running command */ 768 if (dev->sc_nexus != NULL) { 769 dev->sc_nexus->xs->error = XS_DRIVER_STUFFUP; 770 sbic_scsidone(dev->sc_nexus, dev->sc_stat[0]); 771 } 772 while (acb = dev->nexus_list.tqh_first) { 773 acb->xs->error = XS_DRIVER_STUFFUP; 774 sbic_scsidone(acb, -1 /*acb->stat[0]*/); 775 } 776 #endif 777 778 /* Clean up chip itself */ 779 if (dev->sc_flags & SBICF_SELECTED) { 780 while( asr & SBIC_ASR_DBR ) { 781 /* sbic is jammed w/data. need to clear it */ 782 /* But we don't know what direction it needs to go */ 783 GET_SBIC_data(regs, asr); 784 printf("%s: abort %s: clearing data buffer 0x%02x\n", 785 dev->sc_dev.dv_xname, where, asr); 786 GET_SBIC_asr(regs, asr); 787 if( asr & SBIC_ASR_DBR ) /* Not the read direction, then */ 788 SET_SBIC_data(regs, asr); 789 GET_SBIC_asr(regs, asr); 790 } 791 WAIT_CIP(regs); 792 printf("%s: sbicabort - sending ABORT command\n", dev->sc_dev.dv_xname); 793 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 794 WAIT_CIP(regs); 795 796 GET_SBIC_asr(regs, asr); 797 if (asr & (SBIC_ASR_BSY|SBIC_ASR_LCI)) { 798 /* ok, get more drastic.. */ 799 800 printf("%s: sbicabort - asr %x, trying to reset\n", dev->sc_dev.dv_xname, asr); 801 sbicreset(dev); 802 dev->sc_flags &= ~SBICF_SELECTED; 803 return -1; 804 } 805 printf("%s: sbicabort - sending DISC command\n", dev->sc_dev.dv_xname); 806 SET_SBIC_cmd(regs, SBIC_CMD_DISC); 807 808 do { 809 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0); 810 GET_SBIC_csr (regs, csr); 811 CSR_TRACE('a',csr,asr,0); 812 } while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) 813 && (csr != SBIC_CSR_CMD_INVALID)); 814 815 /* lets just hope it worked.. */ 816 dev->sc_flags &= ~SBICF_SELECTED; 817 } 818 return -1; 819 } 820 821 822 /* 823 * Initialize driver-private structures 824 */ 825 826 void 827 sbicinit(dev) 828 struct sbic_softc *dev; 829 { 830 sbic_regmap_t regs; 831 u_int i; 832 struct sbic_acb *acb; 833 u_int inhibit_sync; 834 835 extern u_long scsi_nosync; 836 extern int shift_nosync; 837 838 regs = dev->sc_sbic; 839 840 if ((dev->sc_flags & SBICF_ALIVE) == 0) { 841 TAILQ_INIT(&dev->ready_list); 842 TAILQ_INIT(&dev->nexus_list); 843 TAILQ_INIT(&dev->free_list); 844 callout_init(&dev->sc_timo_ch); 845 dev->sc_nexus = NULL; 846 dev->sc_xs = NULL; 847 acb = dev->sc_acb; 848 bzero(acb, sizeof(dev->sc_acb)); 849 for (i = 0; i < sizeof(dev->sc_acb) / sizeof(*acb); i++) { 850 TAILQ_INSERT_TAIL(&dev->free_list, acb, chain); 851 acb++; 852 } 853 bzero(dev->sc_tinfo, sizeof(dev->sc_tinfo)); 854 #ifdef DEBUG 855 /* make sure timeout is really not needed */ 856 callout_reset(&dev->sc_timo_ch, 30 * hz, 857 (void *)sbictimeout, dev); 858 #endif 859 860 } else panic("sbic: reinitializing driver!"); 861 862 dev->sc_flags |= SBICF_ALIVE; 863 dev->sc_flags &= ~SBICF_SELECTED; 864 865 /* initialize inhibit array */ 866 if (scsi_nosync) { 867 inhibit_sync = (scsi_nosync >> shift_nosync) & 0xff; 868 shift_nosync += 8; 869 #ifdef DEBUG 870 if (inhibit_sync) 871 printf("%s: Inhibiting synchronous transfer %02x\n", 872 dev->sc_dev.dv_xname, inhibit_sync); 873 #endif 874 for (i = 0; i < 8; ++i) 875 if (inhibit_sync & (1 << i)) 876 sbic_inhibit_sync[i] = 1; 877 } 878 879 sbicreset(dev); 880 } 881 882 void 883 sbicreset(dev) 884 struct sbic_softc *dev; 885 { 886 sbic_regmap_t regs; 887 u_int my_id, s; 888 u_char csr; 889 #if 0 890 u_int i; 891 struct sbic_acb *acb; 892 #endif 893 894 regs = dev->sc_sbic; 895 #if 0 896 if (dev->sc_flags & SBICF_ALIVE) { 897 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 898 WAIT_CIP(regs); 899 } 900 #else 901 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 902 WAIT_CIP(regs); 903 #endif 904 s = splbio(); 905 my_id = dev->sc_link.scsipi_scsi.adapter_target & SBIC_ID_MASK; 906 907 /* Enable advanced mode */ 908 my_id |= SBIC_ID_EAF /*| SBIC_ID_EHP*/ ; 909 SET_SBIC_myid(regs, my_id); 910 911 /* 912 * Disable interrupts (in dmainit) then reset the chip 913 */ 914 SET_SBIC_cmd(regs, SBIC_CMD_RESET); 915 DELAY(25); 916 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 917 GET_SBIC_csr(regs, csr); /* clears interrupt also */ 918 919 if (dev->sc_clkfreq < 110) 920 my_id |= SBIC_ID_FS_8_10; 921 else if (dev->sc_clkfreq < 160) 922 my_id |= SBIC_ID_FS_12_15; 923 else if (dev->sc_clkfreq < 210) 924 my_id |= SBIC_ID_FS_16_20; 925 926 SET_SBIC_myid(regs, my_id); 927 928 /* 929 * Set up various chip parameters 930 */ 931 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI /* | SBIC_CTL_HSP */ 932 | SBIC_MACHINE_DMA_MODE); 933 /* 934 * don't allow (re)selection (SBIC_RID_ES) 935 * until we can handle target mode!! 936 */ 937 SET_SBIC_rselid(regs, SBIC_RID_ER); 938 SET_SBIC_syn(regs, 0); /* asynch for now */ 939 940 /* 941 * anything else was zeroed by reset 942 */ 943 splx(s); 944 945 #if 0 946 if ((dev->sc_flags & SBICF_ALIVE) == 0) { 947 TAILQ_INIT(&dev->ready_list); 948 TAILQ_INIT(&dev->nexus_list); 949 TAILQ_INIT(&dev->free_list); 950 dev->sc_nexus = NULL; 951 dev->sc_xs = NULL; 952 acb = dev->sc_acb; 953 bzero(acb, sizeof(dev->sc_acb)); 954 for (i = 0; i < sizeof(dev->sc_acb) / sizeof(*acb); i++) { 955 TAILQ_INSERT_TAIL(&dev->free_list, acb, chain); 956 acb++; 957 } 958 bzero(dev->sc_tinfo, sizeof(dev->sc_tinfo)); 959 } else { 960 if (dev->sc_nexus != NULL) { 961 dev->sc_nexus->xs->error = XS_DRIVER_STUFFUP; 962 sbic_scsidone(dev->sc_nexus, dev->sc_stat[0]); 963 } 964 while (acb = dev->nexus_list.tqh_first) { 965 acb->xs->error = XS_DRIVER_STUFFUP; 966 sbic_scsidone(acb, -1 /*acb->stat[0]*/); 967 } 968 } 969 970 dev->sc_flags |= SBICF_ALIVE; 971 #endif 972 dev->sc_flags &= ~SBICF_SELECTED; 973 } 974 975 void 976 sbicerror(dev, regs, csr) 977 struct sbic_softc *dev; 978 sbic_regmap_t regs; 979 u_char csr; 980 { 981 struct scsipi_xfer *xs; 982 983 xs = dev->sc_xs; 984 985 #ifdef DIAGNOSTIC 986 if (xs == NULL) 987 panic("sbicerror"); 988 #endif 989 if (xs->xs_control & XS_CTL_SILENT) 990 return; 991 992 printf("%s: ", dev->sc_dev.dv_xname); 993 printf("csr == 0x%02x\n", csr); /* XXX */ 994 } 995 996 /* 997 * select the bus, return when selected or error. 998 */ 999 int 1000 sbicselectbus(dev, regs, target, lun, our_addr) 1001 struct sbic_softc *dev; 1002 sbic_regmap_t regs; 1003 u_char target, lun, our_addr; 1004 { 1005 u_char asr, csr, id; 1006 1007 SBIC_TRACE(dev); 1008 QPRINTF(("sbicselectbus %d\n", target)); 1009 1010 /* 1011 * if we're already selected, return (XXXX panic maybe?) 1012 */ 1013 if (dev->sc_flags & SBICF_SELECTED) { 1014 SBIC_TRACE(dev); 1015 return(1); 1016 } 1017 1018 /* 1019 * issue select 1020 */ 1021 SBIC_TC_PUT(regs, 0); 1022 SET_SBIC_selid(regs, target); 1023 SET_SBIC_timeo(regs, SBIC_TIMEOUT(250,dev->sc_clkfreq)); 1024 1025 /* 1026 * set sync or async 1027 */ 1028 if (dev->sc_sync[target].state == SYNC_DONE) 1029 SET_SBIC_syn(regs, SBIC_SYN (dev->sc_sync[target].offset, 1030 dev->sc_sync[target].period)); 1031 else 1032 SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period)); 1033 1034 GET_SBIC_asr(regs, asr); 1035 if( asr & (SBIC_ASR_INT|SBIC_ASR_BSY) ) { 1036 /* This means we got ourselves reselected upon */ 1037 /* printf("sbicselectbus: INT/BSY asr %02x\n", asr);*/ 1038 #ifdef DDB 1039 /* Debugger();*/ 1040 #endif 1041 SBIC_TRACE(dev); 1042 return 1; 1043 } 1044 1045 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN); 1046 1047 /* 1048 * wait for select (merged from seperate function may need 1049 * cleanup) 1050 */ 1051 WAIT_CIP(regs); 1052 do { 1053 asr = SBIC_WAIT(regs, SBIC_ASR_INT | SBIC_ASR_LCI, 0); 1054 if (asr & SBIC_ASR_LCI) { 1055 #ifdef DEBUG 1056 if (reselect_debug) 1057 printf("sbicselectbus: late LCI asr %02x\n", asr); 1058 #endif 1059 SBIC_TRACE(dev); 1060 return 1; 1061 } 1062 GET_SBIC_csr (regs, csr); 1063 CSR_TRACE('s',csr,asr,target); 1064 QPRINTF(("%02x ", csr)); 1065 if( csr == SBIC_CSR_RSLT_NI || csr == SBIC_CSR_RSLT_IFY) { 1066 #ifdef DEBUG 1067 if(reselect_debug) 1068 printf("sbicselectbus: reselected asr %02x\n", asr); 1069 #endif 1070 /* We need to handle this now so we don't lock up later */ 1071 sbicnextstate(dev, csr, asr); 1072 SBIC_TRACE(dev); 1073 return 1; 1074 } 1075 if( csr == SBIC_CSR_SLT || csr == SBIC_CSR_SLT_ATN) { 1076 panic("sbicselectbus: target issued select!"); 1077 return 1; 1078 } 1079 } while (csr != (SBIC_CSR_MIS_2|MESG_OUT_PHASE) 1080 && csr != (SBIC_CSR_MIS_2|CMD_PHASE) && csr != SBIC_CSR_SEL_TIMEO); 1081 1082 /* Enable (or not) reselection */ 1083 if(!sbic_enable_reselect && dev->nexus_list.tqh_first == NULL) 1084 SET_SBIC_rselid (regs, 0); 1085 else 1086 SET_SBIC_rselid (regs, SBIC_RID_ER); 1087 1088 if (csr == (SBIC_CSR_MIS_2|CMD_PHASE)) { 1089 dev->sc_flags |= SBICF_SELECTED; /* device ignored ATN */ 1090 GET_SBIC_selid(regs, id); 1091 dev->target = id; 1092 GET_SBIC_tlun(regs,dev->lun); 1093 if( dev->lun & SBIC_TLUN_VALID ) 1094 dev->lun &= SBIC_TLUN_MASK; 1095 else 1096 dev->lun = lun; 1097 } else if (csr == (SBIC_CSR_MIS_2|MESG_OUT_PHASE)) { 1098 /* 1099 * Send identify message 1100 * (SCSI-2 requires an identify msg (?)) 1101 */ 1102 GET_SBIC_selid(regs, id); 1103 dev->target = id; 1104 GET_SBIC_tlun(regs,dev->lun); 1105 if( dev->lun & SBIC_TLUN_VALID ) 1106 dev->lun &= SBIC_TLUN_MASK; 1107 else 1108 dev->lun = lun; 1109 /* 1110 * handle drives that don't want to be asked 1111 * whether to go sync at all. 1112 */ 1113 if (sbic_inhibit_sync[id] 1114 && dev->sc_sync[id].state == SYNC_START) { 1115 #ifdef DEBUG 1116 if (sync_debug) 1117 printf("Forcing target %d asynchronous.\n", id); 1118 #endif 1119 dev->sc_sync[id].offset = 0; 1120 dev->sc_sync[id].period = sbic_min_period; 1121 dev->sc_sync[id].state = SYNC_DONE; 1122 } 1123 1124 1125 if (dev->sc_sync[id].state != SYNC_START){ 1126 if( dev->sc_xs->xs_control & XS_CTL_POLL 1127 || (dev->sc_flags & SBICF_ICMD) 1128 || !sbic_enable_reselect ) 1129 SEND_BYTE (regs, MSG_IDENTIFY | lun); 1130 else 1131 SEND_BYTE (regs, MSG_IDENTIFY_DR | lun); 1132 } else { 1133 /* 1134 * try to initiate a sync transfer. 1135 * So compose the sync message we're going 1136 * to send to the target 1137 */ 1138 1139 #ifdef DEBUG 1140 if (sync_debug) 1141 printf("Sending sync request to target %d ... ", 1142 id); 1143 #endif 1144 /* 1145 * setup scsi message sync message request 1146 */ 1147 dev->sc_msg[0] = MSG_IDENTIFY | lun; 1148 dev->sc_msg[1] = MSG_EXT_MESSAGE; 1149 dev->sc_msg[2] = 3; 1150 dev->sc_msg[3] = MSG_SYNC_REQ; 1151 dev->sc_msg[4] = sbictoscsiperiod(dev, regs, 1152 sbic_min_period); 1153 dev->sc_msg[5] = sbic_max_offset; 1154 1155 if (sbicxfstart(regs, 6, MESG_OUT_PHASE, sbic_cmd_wait)) 1156 sbicxfout(regs, 6, dev->sc_msg, MESG_OUT_PHASE); 1157 1158 dev->sc_sync[id].state = SYNC_SENT; 1159 #ifdef DEBUG 1160 if (sync_debug) 1161 printf ("sent\n"); 1162 #endif 1163 } 1164 1165 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0); 1166 GET_SBIC_csr (regs, csr); 1167 CSR_TRACE('y',csr,asr,target); 1168 QPRINTF(("[%02x]", csr)); 1169 #ifdef DEBUG 1170 if (sync_debug && dev->sc_sync[id].state == SYNC_SENT) 1171 printf("csr-result of last msgout: 0x%x\n", csr); 1172 #endif 1173 1174 if (csr != SBIC_CSR_SEL_TIMEO) 1175 dev->sc_flags |= SBICF_SELECTED; 1176 } 1177 if (csr == SBIC_CSR_SEL_TIMEO) 1178 dev->sc_xs->error = XS_SELTIMEOUT; 1179 1180 QPRINTF(("\n")); 1181 1182 SBIC_TRACE(dev); 1183 return(csr == SBIC_CSR_SEL_TIMEO); 1184 } 1185 1186 int 1187 sbicxfstart(regs, len, phase, wait) 1188 sbic_regmap_t regs; 1189 int len, wait; 1190 u_char phase; 1191 { 1192 u_char id; 1193 1194 switch (phase) { 1195 case DATA_IN_PHASE: 1196 case MESG_IN_PHASE: 1197 GET_SBIC_selid (regs, id); 1198 id |= SBIC_SID_FROM_SCSI; 1199 SET_SBIC_selid (regs, id); 1200 SBIC_TC_PUT (regs, (unsigned)len); 1201 break; 1202 case DATA_OUT_PHASE: 1203 case MESG_OUT_PHASE: 1204 case CMD_PHASE: 1205 GET_SBIC_selid (regs, id); 1206 id &= ~SBIC_SID_FROM_SCSI; 1207 SET_SBIC_selid (regs, id); 1208 SBIC_TC_PUT (regs, (unsigned)len); 1209 break; 1210 default: 1211 SBIC_TC_PUT (regs, 0); 1212 } 1213 QPRINTF(("sbicxfstart %d, %d, %d\n", len, phase, wait)); 1214 1215 return(1); 1216 } 1217 1218 int 1219 sbicxfout(regs, len, bp, phase) 1220 sbic_regmap_t regs; 1221 int len; 1222 void *bp; 1223 int phase; 1224 { 1225 u_char orig_csr, asr, *buf; 1226 int wait; 1227 1228 buf = bp; 1229 wait = sbic_data_wait; 1230 1231 QPRINTF(("sbicxfout {%d} %02x %02x %02x %02x %02x " 1232 "%02x %02x %02x %02x %02x\n", len, buf[0], buf[1], buf[2], 1233 buf[3], buf[4], buf[5], buf[6], buf[7], buf[8], buf[9])); 1234 1235 GET_SBIC_csr (regs, orig_csr); 1236 CSR_TRACE('>',orig_csr,0,0); 1237 1238 /* 1239 * sigh.. WD-PROTO strikes again.. sending the command in one go 1240 * causes the chip to lock up if talking to certain (misbehaving?) 1241 * targets. Anyway, this procedure should work for all targets, but 1242 * it's slightly slower due to the overhead 1243 */ 1244 WAIT_CIP (regs); 1245 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1246 for (;len > 0; len--) { 1247 GET_SBIC_asr (regs, asr); 1248 while ((asr & SBIC_ASR_DBR) == 0) { 1249 if ((asr & SBIC_ASR_INT) || --wait < 0) { 1250 #ifdef DEBUG 1251 if (sbic_debug) 1252 printf("sbicxfout fail: l%d i%x w%d\n", 1253 len, asr, wait); 1254 #endif 1255 return (len); 1256 } 1257 /* DELAY(1);*/ 1258 GET_SBIC_asr (regs, asr); 1259 } 1260 1261 SET_SBIC_data (regs, *buf); 1262 buf++; 1263 } 1264 SBIC_TC_GET(regs, len); 1265 QPRINTF(("sbicxfout done %d bytes\n", len)); 1266 /* 1267 * this leaves with one csr to be read 1268 */ 1269 return(0); 1270 } 1271 1272 /* returns # bytes left to read */ 1273 int 1274 sbicxfin(regs, len, bp) 1275 sbic_regmap_t regs; 1276 int len; 1277 void *bp; 1278 { 1279 int wait; 1280 u_char *obp, *buf; 1281 u_char orig_csr, csr, asr; 1282 1283 wait = sbic_data_wait; 1284 obp = bp; 1285 buf = bp; 1286 1287 GET_SBIC_csr (regs, orig_csr); 1288 CSR_TRACE('<',orig_csr,0,0); 1289 1290 QPRINTF(("sbicxfin %d, csr=%02x\n", len, orig_csr)); 1291 1292 WAIT_CIP (regs); 1293 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1294 for (;len > 0; len--) { 1295 GET_SBIC_asr (regs, asr); 1296 if((asr & SBIC_ASR_PE)) { 1297 #ifdef DEBUG 1298 printf("sbicxfin parity error: l%d i%x w%d\n", 1299 len, asr, wait); 1300 /* return ((unsigned long)buf - (unsigned long)bp); */ 1301 #ifdef DDB 1302 Debugger(); 1303 #endif 1304 #endif 1305 } 1306 while ((asr & SBIC_ASR_DBR) == 0) { 1307 if ((asr & SBIC_ASR_INT) || --wait < 0) { 1308 #ifdef DEBUG 1309 if (sbic_debug) { 1310 QPRINTF(("sbicxfin fail:{%d} %02x %02x %02x %02x %02x %02x " 1311 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1312 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1313 printf("sbicxfin fail: l%d i%x w%d\n", 1314 len, asr, wait); 1315 } 1316 #endif 1317 return len; 1318 } 1319 1320 if( ! asr & SBIC_ASR_BSY ) { 1321 GET_SBIC_csr(regs, csr); 1322 CSR_TRACE('<',csr,asr,len); 1323 QPRINTF(("[CSR%02xASR%02x]", csr, asr)); 1324 } 1325 1326 /* DELAY(1);*/ 1327 GET_SBIC_asr (regs, asr); 1328 } 1329 1330 GET_SBIC_data (regs, *buf); 1331 /* QPRINTF(("asr=%02x, csr=%02x, data=%02x\n", asr, csr, *buf));*/ 1332 buf++; 1333 } 1334 1335 QPRINTF(("sbicxfin {%d} %02x %02x %02x %02x %02x %02x " 1336 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1337 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1338 1339 /* this leaves with one csr to be read */ 1340 return len; 1341 } 1342 1343 /* 1344 * SCSI 'immediate' command: issue a command to some SCSI device 1345 * and get back an 'immediate' response (i.e., do programmed xfer 1346 * to get the response data). 'cbuf' is a buffer containing a scsi 1347 * command of length clen bytes. 'buf' is a buffer of length 'len' 1348 * bytes for data. The transfer direction is determined by the device 1349 * (i.e., by the scsi bus data xfer phase). If 'len' is zero, the 1350 * command must supply no data. 1351 */ 1352 int 1353 sbicicmd(dev, target, lun, cbuf, clen, buf, len) 1354 struct sbic_softc *dev; 1355 void *cbuf, *buf; 1356 int clen, len; 1357 { 1358 sbic_regmap_t regs; 1359 u_char phase, csr, asr; 1360 int wait, i; 1361 struct sbic_acb *acb; 1362 1363 #define CSR_LOG_BUF_SIZE 0 1364 #if CSR_LOG_BUF_SIZE 1365 int bufptr; 1366 int csrbuf[CSR_LOG_BUF_SIZE]; 1367 bufptr=0; 1368 #endif 1369 1370 SBIC_TRACE(dev); 1371 regs = dev->sc_sbic; 1372 acb = dev->sc_nexus; 1373 1374 /* Make sure pointers are OK */ 1375 dev->sc_last = dev->sc_cur = &acb->sc_pa; 1376 dev->sc_tcnt = acb->sc_tcnt = 0; 1377 acb->sc_pa.dc_count = 0; /* No DMA */ 1378 acb->sc_kv.dc_addr = buf; 1379 acb->sc_kv.dc_count = len; 1380 1381 #ifdef DEBUG 1382 routine = 3; 1383 debug_sbic_regs = regs; /* store this to allow debug calls */ 1384 if( data_pointer_debug > 1 ) 1385 printf("sbicicmd(%d,%d):%d\n", target, lun, 1386 acb->sc_kv.dc_count); 1387 #endif 1388 1389 /* 1390 * set the sbic into non-DMA mode 1391 */ 1392 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI /*| SBIC_CTL_HSP*/); 1393 1394 dev->sc_stat[0] = 0xff; 1395 dev->sc_msg[0] = 0xff; 1396 i = 1; /* pre-load */ 1397 1398 /* We're stealing the SCSI bus */ 1399 dev->sc_flags |= SBICF_ICMD; 1400 1401 do { 1402 /* 1403 * select the SCSI bus (it's an error if bus isn't free) 1404 */ 1405 if (!( dev->sc_flags & SBICF_SELECTED ) 1406 && sbicselectbus(dev, regs, target, lun, dev->sc_scsiaddr)) { 1407 /* printf("sbicicmd: trying to select busy bus!\n"); */ 1408 dev->sc_flags &= ~SBICF_ICMD; 1409 return(-1); 1410 } 1411 1412 /* 1413 * Wait for a phase change (or error) then let the device sequence 1414 * us through the various SCSI phases. 1415 */ 1416 1417 wait = sbic_cmd_wait; 1418 1419 asr = GET_SBIC_asr (regs, asr); 1420 GET_SBIC_csr (regs, csr); 1421 CSR_TRACE('I',csr,asr,target); 1422 QPRINTF((">ASR:%02xCSR:%02x<", asr, csr)); 1423 1424 #if CSR_LOG_BUF_SIZE 1425 csrbuf[bufptr++] = csr; 1426 #endif 1427 1428 1429 switch (csr) { 1430 case SBIC_CSR_S_XFERRED: 1431 case SBIC_CSR_DISC: 1432 case SBIC_CSR_DISC_1: 1433 dev->sc_flags &= ~SBICF_SELECTED; 1434 GET_SBIC_cmd_phase (regs, phase); 1435 if (phase == 0x60) { 1436 GET_SBIC_tlun (regs, dev->sc_stat[0]); 1437 i = 0; /* done */ 1438 /* break; */ /* Bypass all the state gobldygook */ 1439 } else { 1440 #ifdef DEBUG 1441 if(reselect_debug>1) 1442 printf("sbicicmd: handling disconnect\n"); 1443 #endif 1444 i = SBIC_STATE_DISCONNECT; 1445 } 1446 break; 1447 1448 case SBIC_CSR_XFERRED|CMD_PHASE: 1449 case SBIC_CSR_MIS|CMD_PHASE: 1450 case SBIC_CSR_MIS_1|CMD_PHASE: 1451 case SBIC_CSR_MIS_2|CMD_PHASE: 1452 if (sbicxfstart(regs, clen, CMD_PHASE, sbic_cmd_wait)) 1453 if (sbicxfout(regs, clen, 1454 cbuf, CMD_PHASE)) 1455 i = sbicabort(dev, regs,"icmd sending cmd"); 1456 #if 0 1457 GET_SBIC_csr(regs, csr); /* Lets us reload tcount */ 1458 WAIT_CIP(regs); 1459 GET_SBIC_asr(regs, asr); 1460 CSR_TRACE('I',csr,asr,target); 1461 if( asr & (SBIC_ASR_BSY|SBIC_ASR_LCI|SBIC_ASR_CIP) ) 1462 printf("next: cmd sent asr %02x, csr %02x\n", 1463 asr, csr); 1464 #endif 1465 break; 1466 1467 #if 0 1468 case SBIC_CSR_XFERRED|DATA_OUT_PHASE: 1469 case SBIC_CSR_XFERRED|DATA_IN_PHASE: 1470 case SBIC_CSR_MIS|DATA_OUT_PHASE: 1471 case SBIC_CSR_MIS|DATA_IN_PHASE: 1472 case SBIC_CSR_MIS_1|DATA_OUT_PHASE: 1473 case SBIC_CSR_MIS_1|DATA_IN_PHASE: 1474 case SBIC_CSR_MIS_2|DATA_OUT_PHASE: 1475 case SBIC_CSR_MIS_2|DATA_IN_PHASE: 1476 if (acb->sc_kv.dc_count <= 0) 1477 i = sbicabort(dev, regs, "icmd out of data"); 1478 else { 1479 wait = sbic_data_wait; 1480 if (sbicxfstart(regs, 1481 acb->sc_kv.dc_count, 1482 SBIC_PHASE(csr), wait)) 1483 if (csr & 0x01) 1484 /* data in? */ 1485 i=sbicxfin(regs, 1486 acb->sc_kv.dc_count, 1487 acb->sc_kv.dc_addr); 1488 else 1489 i=sbicxfout(regs, 1490 acb->sc_kv.dc_count, 1491 acb->sc_kv.dc_addr, 1492 SBIC_PHASE(csr)); 1493 acb->sc_kv.dc_addr += 1494 (acb->sc_kv.dc_count - i); 1495 acb->sc_kv.dc_count = i; 1496 i = 1; 1497 } 1498 break; 1499 1500 #endif 1501 case SBIC_CSR_XFERRED|STATUS_PHASE: 1502 case SBIC_CSR_MIS|STATUS_PHASE: 1503 case SBIC_CSR_MIS_1|STATUS_PHASE: 1504 case SBIC_CSR_MIS_2|STATUS_PHASE: 1505 /* 1506 * the sbic does the status/cmd-complete reading ok, 1507 * so do this with its hi-level commands. 1508 */ 1509 #ifdef DEBUG 1510 if(sbic_debug) 1511 printf("SBICICMD status phase\n"); 1512 #endif 1513 SBIC_TC_PUT(regs, 0); 1514 SET_SBIC_cmd_phase(regs, 0x46); 1515 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1516 break; 1517 1518 #if THIS_IS_A_RESERVED_STATE 1519 case BUS_FREE_PHASE: /* This is not legal */ 1520 if( dev->sc_stat[0] != 0xff ) 1521 goto out; 1522 break; 1523 #endif 1524 1525 default: 1526 i = sbicnextstate(dev, csr, asr); 1527 } 1528 1529 /* 1530 * make sure the last command was taken, 1531 * ie. we're not hunting after an ignored command.. 1532 */ 1533 GET_SBIC_asr(regs, asr); 1534 1535 /* tapes may take a loooong time.. */ 1536 while (asr & SBIC_ASR_BSY){ 1537 if(asr & SBIC_ASR_DBR) { 1538 printf("sbicicmd: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", 1539 csr,asr); 1540 #ifdef DDB 1541 Debugger(); 1542 #endif 1543 /* SBIC is jammed */ 1544 /* DUNNO which direction */ 1545 /* Try old direction */ 1546 GET_SBIC_data(regs,i); 1547 GET_SBIC_asr(regs, asr); 1548 if( asr & SBIC_ASR_DBR) /* Wants us to write */ 1549 SET_SBIC_data(regs,i); 1550 } 1551 GET_SBIC_asr(regs, asr); 1552 } 1553 1554 /* 1555 * wait for last command to complete 1556 */ 1557 if (asr & SBIC_ASR_LCI) { 1558 printf("sbicicmd: last command ignored\n"); 1559 } 1560 else if( i == 1 ) /* Bsy */ 1561 SBIC_WAIT (regs, SBIC_ASR_INT, wait); 1562 1563 /* 1564 * do it again 1565 */ 1566 } while ( i > 0 && dev->sc_stat[0] == 0xff); 1567 1568 /* Sometimes we need to do an extra read of the CSR */ 1569 GET_SBIC_csr(regs, csr); 1570 CSR_TRACE('I',csr,asr,0xff); 1571 1572 #if CSR_LOG_BUF_SIZE 1573 if(reselect_debug>1) 1574 for(i=0; i<bufptr; i++) 1575 printf("CSR:%02x", csrbuf[i]); 1576 #endif 1577 1578 #ifdef DEBUG 1579 if(data_pointer_debug > 1) 1580 printf("sbicicmd done(%d,%d):%d =%d=\n", 1581 dev->target, lun, 1582 acb->sc_kv.dc_count, 1583 dev->sc_stat[0]); 1584 #endif 1585 1586 QPRINTF(("=STS:%02x=", dev->sc_stat[0])); 1587 dev->sc_flags &= ~SBICF_ICMD; 1588 1589 SBIC_TRACE(dev); 1590 return(dev->sc_stat[0]); 1591 } 1592 1593 /* 1594 * Finish SCSI xfer command: After the completion interrupt from 1595 * a read/write operation, sequence through the final phases in 1596 * programmed i/o. This routine is a lot like sbicicmd except we 1597 * skip (and don't allow) the select, cmd out and data in/out phases. 1598 */ 1599 void 1600 sbicxfdone(dev, regs, target) 1601 struct sbic_softc *dev; 1602 sbic_regmap_t regs; 1603 int target; 1604 { 1605 u_char phase, asr, csr; 1606 int s; 1607 1608 SBIC_TRACE(dev); 1609 QPRINTF(("{")); 1610 s = splbio(); 1611 1612 /* 1613 * have the sbic complete on its own 1614 */ 1615 SBIC_TC_PUT(regs, 0); 1616 SET_SBIC_cmd_phase(regs, 0x46); 1617 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1618 1619 do { 1620 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0); 1621 GET_SBIC_csr (regs, csr); 1622 CSR_TRACE('f',csr,asr,target); 1623 QPRINTF(("%02x:", csr)); 1624 } while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) 1625 && (csr != SBIC_CSR_S_XFERRED)); 1626 1627 dev->sc_flags &= ~SBICF_SELECTED; 1628 1629 GET_SBIC_cmd_phase (regs, phase); 1630 QPRINTF(("}%02x", phase)); 1631 if (phase == 0x60) 1632 GET_SBIC_tlun(regs, dev->sc_stat[0]); 1633 else 1634 sbicerror(dev, regs, csr); 1635 1636 QPRINTF(("=STS:%02x=\n", dev->sc_stat[0])); 1637 splx(s); 1638 SBIC_TRACE(dev); 1639 } 1640 1641 /* 1642 * No DMA chains 1643 */ 1644 1645 int 1646 sbicgo(dev, xs) 1647 struct sbic_softc *dev; 1648 struct scsipi_xfer *xs; 1649 { 1650 int i, dmaflags, count, usedma; 1651 u_char csr, asr, *addr; 1652 sbic_regmap_t regs; 1653 struct sbic_acb *acb; 1654 1655 SBIC_TRACE(dev); 1656 dev->target = xs->sc_link->scsipi_scsi.target; 1657 dev->lun = xs->sc_link->scsipi_scsi.lun; 1658 acb = dev->sc_nexus; 1659 regs = dev->sc_sbic; 1660 1661 usedma = sbicdmaok(dev, xs); 1662 #ifdef DEBUG 1663 routine = 1; 1664 debug_sbic_regs = regs; /* store this to allow debug calls */ 1665 if( data_pointer_debug > 1 ) 1666 printf("sbicgo(%d,%d)\n", dev->target, dev->lun); 1667 #endif 1668 1669 /* 1670 * set the sbic into DMA mode 1671 */ 1672 if( usedma ) 1673 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI | 1674 SBIC_MACHINE_DMA_MODE); 1675 else 1676 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1677 1678 1679 /* 1680 * select the SCSI bus (it's an error if bus isn't free) 1681 */ 1682 if (sbicselectbus(dev, regs, dev->target, dev->lun, 1683 dev->sc_scsiaddr)) { 1684 /* printf("sbicgo: Trying to select busy bus!\n"); */ 1685 SBIC_TRACE(dev); 1686 return(0); /* Not done: needs to be rescheduled */ 1687 } 1688 dev->sc_stat[0] = 0xff; 1689 1690 /* 1691 * Calculate DMA chains now 1692 */ 1693 1694 dmaflags = 0; 1695 if (acb->flags & ACB_DATAIN) 1696 dmaflags |= DMAGO_READ; 1697 1698 1699 /* 1700 * Deal w/bounce buffers. 1701 */ 1702 1703 addr = acb->sc_kv.dc_addr; 1704 count = acb->sc_kv.dc_count; 1705 if (count && (char *)kvtop(addr) != acb->sc_pa.dc_addr) { /* XXXX check */ 1706 printf("sbic: DMA buffer mapping changed %p->%x\n", 1707 acb->sc_pa.dc_addr, kvtop(addr)); 1708 #ifdef DDB 1709 Debugger(); 1710 #endif 1711 } 1712 1713 #ifdef DEBUG 1714 ++sbicdma_ops; /* count total DMA operations */ 1715 #endif 1716 if (count && usedma && dev->sc_flags & SBICF_BADDMA && 1717 sbiccheckdmap(addr, count, dev->sc_dmamask)) { 1718 /* 1719 * need to bounce the dma. 1720 */ 1721 if (dmaflags & DMAGO_READ) { 1722 acb->flags |= ACB_BBUF; 1723 acb->sc_dmausrbuf = addr; 1724 acb->sc_dmausrlen = count; 1725 acb->sc_usrbufpa = (u_char *)kvtop(addr); 1726 if(!dev->sc_tinfo[dev->target].bounce) { 1727 printf("sbicgo: HELP! no bounce allocated for %d\n", 1728 dev->target); 1729 printf("xfer: (%p->%p,%lx)\n", acb->sc_dmausrbuf, 1730 acb->sc_usrbufpa, acb->sc_dmausrlen); 1731 dev->sc_tinfo[xs->sc_link->scsipi_scsi.target].bounce 1732 = (char *)alloc_z2mem(MAXPHYS); 1733 if (isztwomem(dev->sc_tinfo[xs->sc_link->scsipi_scsi.target].bounce)) 1734 printf("alloc ZII target %d bounce pa 0x%x\n", 1735 xs->sc_link->scsipi_scsi.target, 1736 kvtop(dev->sc_tinfo[xs->sc_link->scsipi_scsi.target].bounce)); 1737 else if (dev->sc_tinfo[xs->sc_link->scsipi_scsi.target].bounce) 1738 printf("alloc CHIP target %d bounce pa 0x%p\n", 1739 xs->sc_link->scsipi_scsi.target, 1740 PREP_DMA_MEM(dev->sc_tinfo[xs->sc_link->scsipi_scsi.target].bounce)); 1741 1742 printf("Allocating %d bounce at %x\n", 1743 dev->target, 1744 kvtop(dev->sc_tinfo[dev->target].bounce)); 1745 } 1746 } else { /* write: copy to dma buffer */ 1747 #ifdef DEBUG 1748 if(data_pointer_debug) 1749 printf("sbicgo: copying %x bytes to target %d bounce %x\n", 1750 count, dev->target, 1751 kvtop(dev->sc_tinfo[dev->target].bounce)); 1752 #endif 1753 bcopy (addr, dev->sc_tinfo[dev->target].bounce, count); 1754 } 1755 addr = dev->sc_tinfo[dev->target].bounce;/* and use dma buffer */ 1756 acb->sc_kv.dc_addr = addr; 1757 #ifdef DEBUG 1758 ++sbicdma_bounces; /* count number of bounced */ 1759 #endif 1760 } 1761 1762 /* 1763 * Allocate the DMA chain 1764 */ 1765 1766 /* Set start KVM addresses */ 1767 #if 0 1768 acb->sc_kv.dc_addr = addr; 1769 acb->sc_kv.dc_count = count; 1770 #endif 1771 1772 /* Mark end of segment */ 1773 acb->sc_tcnt = dev->sc_tcnt = 0; 1774 acb->sc_pa.dc_count = 0; 1775 1776 sbic_load_ptrs(dev, regs, dev->target, dev->lun); 1777 SBIC_TRACE(dev); 1778 /* Enable interrupts but don't do any DMA */ 1779 dev->sc_enintr(dev); 1780 if (usedma) { 1781 dev->sc_tcnt = dev->sc_dmago(dev, acb->sc_pa.dc_addr, 1782 acb->sc_pa.dc_count, 1783 dmaflags); 1784 #ifdef DEBUG 1785 dev->sc_dmatimo = dev->sc_tcnt ? 1 : 0; 1786 #endif 1787 } else 1788 dev->sc_dmacmd = 0; /* Don't use DMA */ 1789 dev->sc_flags |= SBICF_INDMA; 1790 /* SBIC_TC_PUT(regs, dev->sc_tcnt); */ /* XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX */ 1791 SBIC_TRACE(dev); 1792 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 1793 1794 /* 1795 * push the data cache ( I think this won't work (EH)) 1796 */ 1797 #if defined(M68040) || defined(M68060) 1798 if (mmutype == MMU_68040 && usedma && count) { 1799 dma_cachectl(addr, count); 1800 if (((u_int)addr & 0xF) || (((u_int)addr + count) & 0xF)) 1801 dev->sc_flags |= SBICF_DCFLUSH; 1802 } 1803 #endif 1804 1805 /* 1806 * enintr() also enables interrupts for the sbic 1807 */ 1808 #ifdef DEBUG 1809 if( data_pointer_debug > 1 ) 1810 printf("sbicgo dmago:%d(%p:%lx)\n", 1811 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 1812 #if 0 1813 /* 1814 * Hmm - this isn't right: asr and csr haven't been set yet. 1815 */ 1816 debug_asr = asr; 1817 debug_csr = csr; 1818 #endif 1819 #endif 1820 1821 /* 1822 * Lets cycle a while then let the interrupt handler take over 1823 */ 1824 1825 asr = GET_SBIC_asr(regs, asr); 1826 do { 1827 GET_SBIC_csr(regs, csr); 1828 CSR_TRACE('g',csr,asr,dev->target); 1829 #ifdef DEBUG 1830 debug_csr = csr; 1831 routine = 1; 1832 #endif 1833 QPRINTF(("go[0x%x]", csr)); 1834 1835 i = sbicnextstate(dev, csr, asr); 1836 1837 WAIT_CIP(regs); 1838 GET_SBIC_asr(regs, asr); 1839 #ifdef DEBUG 1840 debug_asr = asr; 1841 #endif 1842 if(asr & SBIC_ASR_LCI) printf("sbicgo: LCI asr:%02x csr:%02x\n", 1843 asr,csr); 1844 } while( i == SBIC_STATE_RUNNING 1845 && asr & (SBIC_ASR_INT|SBIC_ASR_LCI) ); 1846 1847 CSR_TRACE('g',csr,asr,i<<4); 1848 SBIC_TRACE(dev); 1849 if (i == SBIC_STATE_DONE && dev->sc_stat[0] == 0xff) printf("sbicgo: done & stat = 0xff\n"); 1850 if (i == SBIC_STATE_DONE && dev->sc_stat[0] != 0xff) { 1851 /* if( i == SBIC_STATE_DONE && dev->sc_stat[0] ) { */ 1852 /* Did we really finish that fast? */ 1853 return 1; 1854 } 1855 return 0; 1856 } 1857 1858 1859 int 1860 sbicintr(dev) 1861 struct sbic_softc *dev; 1862 { 1863 sbic_regmap_t regs; 1864 u_char asr, csr; 1865 int i; 1866 1867 regs = dev->sc_sbic; 1868 1869 /* 1870 * pending interrupt? 1871 */ 1872 GET_SBIC_asr (regs, asr); 1873 if ((asr & SBIC_ASR_INT) == 0) 1874 return(0); 1875 1876 SBIC_TRACE(dev); 1877 do { 1878 GET_SBIC_csr(regs, csr); 1879 CSR_TRACE('i',csr,asr,dev->target); 1880 #ifdef DEBUG 1881 debug_csr = csr; 1882 routine = 2; 1883 #endif 1884 QPRINTF(("intr[0x%x]", csr)); 1885 1886 i = sbicnextstate(dev, csr, asr); 1887 1888 WAIT_CIP(regs); 1889 GET_SBIC_asr(regs, asr); 1890 #ifdef DEBUG 1891 debug_asr = asr; 1892 #endif 1893 #if 0 1894 if(asr & SBIC_ASR_LCI) printf("sbicintr: LCI asr:%02x csr:%02x\n", 1895 asr,csr); 1896 #endif 1897 } while(i == SBIC_STATE_RUNNING && 1898 asr & (SBIC_ASR_INT|SBIC_ASR_LCI)); 1899 CSR_TRACE('i',csr,asr,i<<4); 1900 SBIC_TRACE(dev); 1901 return(1); 1902 } 1903 1904 /* 1905 * Run commands and wait for disconnect 1906 */ 1907 int 1908 sbicpoll(dev) 1909 struct sbic_softc *dev; 1910 { 1911 sbic_regmap_t regs; 1912 u_char asr, csr; 1913 int i; 1914 1915 SBIC_TRACE(dev); 1916 regs = dev->sc_sbic; 1917 1918 do { 1919 GET_SBIC_asr (regs, asr); 1920 #ifdef DEBUG 1921 debug_asr = asr; 1922 #endif 1923 GET_SBIC_csr(regs, csr); 1924 CSR_TRACE('p',csr,asr,dev->target); 1925 #ifdef DEBUG 1926 debug_csr = csr; 1927 routine = 2; 1928 #endif 1929 QPRINTF(("poll[0x%x]", csr)); 1930 1931 i = sbicnextstate(dev, csr, asr); 1932 1933 WAIT_CIP(regs); 1934 GET_SBIC_asr(regs, asr); 1935 /* tapes may take a loooong time.. */ 1936 while (asr & SBIC_ASR_BSY){ 1937 if(asr & SBIC_ASR_DBR) { 1938 printf("sbipoll: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", 1939 csr,asr); 1940 #ifdef DDB 1941 Debugger(); 1942 #endif 1943 /* SBIC is jammed */ 1944 /* DUNNO which direction */ 1945 /* Try old direction */ 1946 GET_SBIC_data(regs,i); 1947 GET_SBIC_asr(regs, asr); 1948 if( asr & SBIC_ASR_DBR) /* Wants us to write */ 1949 SET_SBIC_data(regs,i); 1950 } 1951 GET_SBIC_asr(regs, asr); 1952 } 1953 1954 if(asr & SBIC_ASR_LCI) printf("sbicpoll: LCI asr:%02x csr:%02x\n", 1955 asr,csr); 1956 else if( i == 1 ) /* BSY */ 1957 SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait); 1958 } while(i == SBIC_STATE_RUNNING); 1959 CSR_TRACE('p',csr,asr,i<<4); 1960 SBIC_TRACE(dev); 1961 return(1); 1962 } 1963 1964 /* 1965 * Handle a single msgin 1966 */ 1967 1968 int 1969 sbicmsgin(dev) 1970 struct sbic_softc *dev; 1971 { 1972 sbic_regmap_t regs; 1973 int recvlen; 1974 u_char asr, csr, *tmpaddr; 1975 1976 regs = dev->sc_sbic; 1977 1978 dev->sc_msg[0] = 0xff; 1979 dev->sc_msg[1] = 0xff; 1980 1981 GET_SBIC_asr(regs, asr); 1982 #ifdef DEBUG 1983 if(reselect_debug>1) 1984 printf("sbicmsgin asr=%02x\n", asr); 1985 #endif 1986 1987 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 1988 1989 GET_SBIC_selid (regs, csr); 1990 SET_SBIC_selid (regs, csr | SBIC_SID_FROM_SCSI); 1991 1992 SBIC_TC_PUT(regs, 0); 1993 tmpaddr = dev->sc_msg; 1994 recvlen = 1; 1995 do { 1996 while( recvlen-- ) { 1997 asr = GET_SBIC_asr(regs, asr); 1998 GET_SBIC_csr(regs, csr); 1999 QPRINTF(("sbicmsgin ready to go (csr,asr)=(%02x,%02x)\n", 2000 csr, asr)); 2001 2002 RECV_BYTE(regs, *tmpaddr); 2003 CSR_TRACE('m',csr,asr,*tmpaddr); 2004 #if 1 2005 /* 2006 * get the command completion interrupt, or we 2007 * can't send a new command (LCI) 2008 */ 2009 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2010 GET_SBIC_csr(regs, csr); 2011 CSR_TRACE('X',csr,asr,dev->target); 2012 #else 2013 WAIT_CIP(regs); 2014 do { 2015 GET_SBIC_asr(regs, asr); 2016 csr = 0xff; 2017 GET_SBIC_csr(regs, csr); 2018 CSR_TRACE('X',csr,asr,dev->target); 2019 if( csr == 0xff ) 2020 printf("sbicmsgin waiting: csr %02x asr %02x\n", csr, asr); 2021 } while( csr == 0xff ); 2022 #endif 2023 #ifdef DEBUG 2024 if(reselect_debug>1) 2025 printf("sbicmsgin: got %02x csr %02x asr %02x\n", 2026 *tmpaddr, csr, asr); 2027 #endif 2028 #if do_parity_check 2029 if( asr & SBIC_ASR_PE ) { 2030 printf ("Parity error"); 2031 /* This code simply does not work. */ 2032 WAIT_CIP(regs); 2033 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2034 WAIT_CIP(regs); 2035 GET_SBIC_asr(regs, asr); 2036 WAIT_CIP(regs); 2037 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2038 WAIT_CIP(regs); 2039 if( !(asr & SBIC_ASR_LCI) ) 2040 /* Target wants to send garbled msg*/ 2041 continue; 2042 printf("--fixing\n"); 2043 /* loop until a msgout phase occurs on target */ 2044 while(csr & 0x07 != MESG_OUT_PHASE) { 2045 while( asr & SBIC_ASR_BSY && 2046 !(asr & SBIC_ASR_DBR|SBIC_ASR_INT) ) 2047 GET_SBIC_asr(regs, asr); 2048 if( asr & SBIC_ASR_DBR ) 2049 panic("msgin: jammed again!\n"); 2050 GET_SBIC_csr(regs, csr); 2051 CSR_TRACE('e',csr,asr,dev->target); 2052 if( csr & 0x07 != MESG_OUT_PHASE ) { 2053 sbicnextstate(dev, csr, asr); 2054 sbic_save_ptrs(dev, regs, 2055 dev->target, 2056 dev->lun); 2057 } 2058 } 2059 /* Should be msg out by now */ 2060 SEND_BYTE(regs, MSG_PARITY_ERROR); 2061 } 2062 else 2063 #endif 2064 tmpaddr++; 2065 2066 if(recvlen) { 2067 /* Clear ACK */ 2068 WAIT_CIP(regs); 2069 GET_SBIC_asr(regs, asr); 2070 GET_SBIC_csr(regs, csr); 2071 CSR_TRACE('X',csr,asr,dev->target); 2072 QPRINTF(("sbicmsgin pre byte CLR_ACK (csr,asr)=(%02x,%02x)\n", 2073 csr, asr)); 2074 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2075 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2076 } 2077 2078 }; 2079 2080 if(dev->sc_msg[0] == 0xff) { 2081 printf("sbicmsgin: sbic swallowed our message\n"); 2082 break; 2083 } 2084 #ifdef DEBUG 2085 if (sync_debug) 2086 printf("msgin done csr 0x%x asr 0x%x msg 0x%x\n", 2087 csr, asr, dev->sc_msg[0]); 2088 #endif 2089 /* 2090 * test whether this is a reply to our sync 2091 * request 2092 */ 2093 if (MSG_ISIDENTIFY(dev->sc_msg[0])) { 2094 QPRINTF(("IFFY")); 2095 #if 0 2096 /* There is an implied load-ptrs here */ 2097 sbic_load_ptrs(dev, regs, dev->target, dev->lun); 2098 #endif 2099 /* Got IFFY msg -- ack it */ 2100 } else if (dev->sc_msg[0] == MSG_REJECT 2101 && dev->sc_sync[dev->target].state == SYNC_SENT) { 2102 QPRINTF(("REJECT of SYN")); 2103 #ifdef DEBUG 2104 if (sync_debug) 2105 printf("target %d rejected sync, going async\n", 2106 dev->target); 2107 #endif 2108 dev->sc_sync[dev->target].period = sbic_min_period; 2109 dev->sc_sync[dev->target].offset = 0; 2110 dev->sc_sync[dev->target].state = SYNC_DONE; 2111 SET_SBIC_syn(regs, 2112 SBIC_SYN(dev->sc_sync[dev->target].offset, 2113 dev->sc_sync[dev->target].period)); 2114 } else if ((dev->sc_msg[0] == MSG_REJECT)) { 2115 QPRINTF(("REJECT")); 2116 /* 2117 * we'll never REJECt a REJECT message.. 2118 */ 2119 } else if ((dev->sc_msg[0] == MSG_SAVE_DATA_PTR)) { 2120 QPRINTF(("MSG_SAVE_DATA_PTR")); 2121 /* 2122 * don't reject this either. 2123 */ 2124 } else if ((dev->sc_msg[0] == MSG_DISCONNECT)) { 2125 QPRINTF(("DISCONNECT")); 2126 #ifdef DEBUG 2127 if( reselect_debug>1 && dev->sc_msg[0] == MSG_DISCONNECT ) 2128 printf("sbicmsgin: got disconnect msg %s\n", 2129 (dev->sc_flags & SBICF_ICMD)?"rejecting":""); 2130 #endif 2131 if( dev->sc_flags & SBICF_ICMD ) { 2132 /* We're in immediate mode. Prevent disconnects. */ 2133 /* prepare to reject the message, NACK */ 2134 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2135 WAIT_CIP(regs); 2136 } 2137 } else if (dev->sc_msg[0] == MSG_CMD_COMPLETE ) { 2138 QPRINTF(("CMD_COMPLETE")); 2139 /* !! KLUDGE ALERT !! quite a few drives don't seem to 2140 * really like the current way of sending the 2141 * sync-handshake together with the ident-message, and 2142 * they react by sending command-complete and 2143 * disconnecting right after returning the valid sync 2144 * handshake. So, all I can do is reselect the drive, 2145 * and hope it won't disconnect again. I don't think 2146 * this is valid behavior, but I can't help fixing a 2147 * problem that apparently exists. 2148 * 2149 * Note: we should not get here on `normal' command 2150 * completion, as that condition is handled by the 2151 * high-level sel&xfer resume command used to walk 2152 * thru status/cc-phase. 2153 */ 2154 2155 #ifdef DEBUG 2156 if (sync_debug) 2157 printf ("GOT MSG %d! target %d acting weird.." 2158 " waiting for disconnect...\n", 2159 dev->sc_msg[0], dev->target); 2160 #endif 2161 /* Check to see if sbic is handling this */ 2162 GET_SBIC_asr(regs, asr); 2163 if(asr & SBIC_ASR_BSY) 2164 return SBIC_STATE_RUNNING; 2165 2166 /* Let's try this: Assume it works and set status to 00 */ 2167 dev->sc_stat[0] = 0; 2168 } else if (dev->sc_msg[0] == MSG_EXT_MESSAGE 2169 && tmpaddr == &dev->sc_msg[1]) { 2170 QPRINTF(("ExtMSG\n")); 2171 /* Read in whole extended message */ 2172 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2173 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2174 GET_SBIC_asr(regs, asr); 2175 GET_SBIC_csr(regs, csr); 2176 QPRINTF(("CLR ACK asr %02x, csr %02x\n", asr, csr)); 2177 RECV_BYTE(regs, *tmpaddr); 2178 CSR_TRACE('x',csr,asr,*tmpaddr); 2179 /* Wait for command completion IRQ */ 2180 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2181 recvlen = *tmpaddr++; 2182 QPRINTF(("Recving ext msg, asr %02x csr %02x len %02x\n", 2183 asr, csr, recvlen)); 2184 } else if (dev->sc_msg[0] == MSG_EXT_MESSAGE && dev->sc_msg[1] == 3 2185 && dev->sc_msg[2] == MSG_SYNC_REQ) { 2186 QPRINTF(("SYN")); 2187 dev->sc_sync[dev->target].period = 2188 sbicfromscsiperiod(dev, 2189 regs, dev->sc_msg[3]); 2190 dev->sc_sync[dev->target].offset = dev->sc_msg[4]; 2191 dev->sc_sync[dev->target].state = SYNC_DONE; 2192 SET_SBIC_syn(regs, 2193 SBIC_SYN(dev->sc_sync[dev->target].offset, 2194 dev->sc_sync[dev->target].period)); 2195 printf("%s: target %d now synchronous," 2196 " period=%dns, offset=%d.\n", 2197 dev->sc_dev.dv_xname, dev->target, 2198 dev->sc_msg[3] * 4, dev->sc_msg[4]); 2199 } else { 2200 #ifdef DEBUG 2201 if (sbic_debug || sync_debug) 2202 printf ("sbicmsgin: Rejecting message 0x%02x\n", 2203 dev->sc_msg[0]); 2204 #endif 2205 /* prepare to reject the message, NACK */ 2206 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2207 WAIT_CIP(regs); 2208 } 2209 /* Clear ACK */ 2210 WAIT_CIP(regs); 2211 GET_SBIC_asr(regs, asr); 2212 GET_SBIC_csr(regs, csr); 2213 CSR_TRACE('X',csr,asr,dev->target); 2214 QPRINTF(("sbicmsgin pre CLR_ACK (csr,asr)=(%02x,%02x)%d\n", 2215 csr, asr, recvlen)); 2216 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2217 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2218 } 2219 #if 0 2220 while((csr == SBIC_CSR_MSGIN_W_ACK) 2221 || (SBIC_PHASE(csr) == MESG_IN_PHASE)); 2222 #else 2223 while (recvlen>0); 2224 #endif 2225 2226 QPRINTF(("sbicmsgin finished: csr %02x, asr %02x\n",csr, asr)); 2227 2228 /* Should still have one CSR to read */ 2229 return SBIC_STATE_RUNNING; 2230 } 2231 2232 2233 /* 2234 * sbicnextstate() 2235 * return: 2236 * 0 == done 2237 * 1 == working 2238 * 2 == disconnected 2239 * -1 == error 2240 */ 2241 int 2242 sbicnextstate(dev, csr, asr) 2243 struct sbic_softc *dev; 2244 u_char csr, asr; 2245 { 2246 sbic_regmap_t regs; 2247 struct sbic_acb *acb; 2248 int i, newtarget, newlun, wait; 2249 #if 0 2250 unsigned tcnt; 2251 #endif 2252 2253 i = 0; 2254 SBIC_TRACE(dev); 2255 regs = dev->sc_sbic; 2256 acb = dev->sc_nexus; 2257 2258 QPRINTF(("next[%02x,%02x]",asr,csr)); 2259 2260 switch (csr) { 2261 case SBIC_CSR_XFERRED|CMD_PHASE: 2262 case SBIC_CSR_MIS|CMD_PHASE: 2263 case SBIC_CSR_MIS_1|CMD_PHASE: 2264 case SBIC_CSR_MIS_2|CMD_PHASE: 2265 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 2266 if (sbicxfstart(regs, acb->clen, CMD_PHASE, sbic_cmd_wait)) 2267 if (sbicxfout(regs, acb->clen, 2268 &acb->cmd, CMD_PHASE)) 2269 goto abort; 2270 break; 2271 2272 case SBIC_CSR_XFERRED|STATUS_PHASE: 2273 case SBIC_CSR_MIS|STATUS_PHASE: 2274 case SBIC_CSR_MIS_1|STATUS_PHASE: 2275 case SBIC_CSR_MIS_2|STATUS_PHASE: 2276 /* 2277 * this should be the normal i/o completion case. 2278 * get the status & cmd complete msg then let the 2279 * device driver look at what happened. 2280 */ 2281 sbicxfdone(dev,regs,dev->target); 2282 /* 2283 * check for overlapping cache line, flush if so 2284 */ 2285 #if defined(M68040) || defined(M68060) 2286 if (dev->sc_flags & SBICF_DCFLUSH) { 2287 #if 0 2288 printf("sbic: 68040/68060 DMA cache flush needs" 2289 "fixing? %x:%x\n", 2290 dev->sc_xs->data, dev->sc_xs->datalen); 2291 #endif 2292 } 2293 #endif 2294 #ifdef DEBUG 2295 if( data_pointer_debug > 1 ) 2296 printf("next dmastop: %d(%p:%lx)\n", 2297 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 2298 dev->sc_dmatimo = 0; 2299 #endif 2300 dev->sc_dmastop(dev); /* was dmafree */ 2301 if (acb->flags & ACB_BBUF) { 2302 if ((u_char *)kvtop(acb->sc_dmausrbuf) != acb->sc_usrbufpa) 2303 printf("%s: WARNING - buffer mapping changed %p->%x\n", 2304 dev->sc_dev.dv_xname, acb->sc_usrbufpa, 2305 kvtop(acb->sc_dmausrbuf)); 2306 #ifdef DEBUG 2307 if(data_pointer_debug) 2308 printf("sbicgo:copying %lx bytes from target %d bounce %x\n", 2309 acb->sc_dmausrlen, 2310 dev->target, 2311 kvtop(dev->sc_tinfo[dev->target].bounce)); 2312 #endif 2313 bcopy(dev->sc_tinfo[dev->target].bounce, 2314 acb->sc_dmausrbuf, 2315 acb->sc_dmausrlen); 2316 } 2317 dev->sc_flags &= ~(SBICF_INDMA | SBICF_DCFLUSH); 2318 sbic_scsidone(acb, dev->sc_stat[0]); 2319 SBIC_TRACE(dev); 2320 return SBIC_STATE_DONE; 2321 2322 case SBIC_CSR_XFERRED|DATA_OUT_PHASE: 2323 case SBIC_CSR_XFERRED|DATA_IN_PHASE: 2324 case SBIC_CSR_MIS|DATA_OUT_PHASE: 2325 case SBIC_CSR_MIS|DATA_IN_PHASE: 2326 case SBIC_CSR_MIS_1|DATA_OUT_PHASE: 2327 case SBIC_CSR_MIS_1|DATA_IN_PHASE: 2328 case SBIC_CSR_MIS_2|DATA_OUT_PHASE: 2329 case SBIC_CSR_MIS_2|DATA_IN_PHASE: 2330 if( dev->sc_xs->xs_control & XS_CTL_POLL || dev->sc_flags & SBICF_ICMD 2331 || acb->sc_dmacmd == 0 ) { 2332 /* Do PIO */ 2333 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2334 if (acb->sc_kv.dc_count <= 0) { 2335 printf("sbicnextstate:xfer count %d asr%x csr%x\n", 2336 acb->sc_kv.dc_count, asr, csr); 2337 goto abort; 2338 } 2339 wait = sbic_data_wait; 2340 if( sbicxfstart(regs, 2341 acb->sc_kv.dc_count, 2342 SBIC_PHASE(csr), wait)) { 2343 if( SBIC_PHASE(csr) == DATA_IN_PHASE ) 2344 /* data in? */ 2345 i=sbicxfin(regs, 2346 acb->sc_kv.dc_count, 2347 acb->sc_kv.dc_addr); 2348 else 2349 i=sbicxfout(regs, 2350 acb->sc_kv.dc_count, 2351 acb->sc_kv.dc_addr, 2352 SBIC_PHASE(csr)); 2353 } 2354 acb->sc_kv.dc_addr += 2355 (acb->sc_kv.dc_count - i); 2356 acb->sc_kv.dc_count = i; 2357 } else { 2358 if (acb->sc_kv.dc_count <= 0) { 2359 printf("sbicnextstate:xfer count %d asr%x csr%x\n", 2360 acb->sc_kv.dc_count, asr, csr); 2361 goto abort; 2362 } 2363 /* 2364 * do scatter-gather dma 2365 * hacking the controller chip, ouch.. 2366 */ 2367 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI | 2368 SBIC_MACHINE_DMA_MODE); 2369 /* 2370 * set next dma addr and dec count 2371 */ 2372 #if 0 2373 SBIC_TC_GET(regs, tcnt); 2374 dev->sc_cur->dc_count -= ((dev->sc_tcnt - tcnt) >> 1); 2375 dev->sc_cur->dc_addr += (dev->sc_tcnt - tcnt); 2376 dev->sc_tcnt = acb->sc_tcnt = tcnt; 2377 #else 2378 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 2379 sbic_load_ptrs(dev, regs, dev->target, dev->lun); 2380 #endif 2381 #ifdef DEBUG 2382 if( data_pointer_debug > 1 ) 2383 printf("next dmanext: %d(%p:%lx)\n", 2384 dev->target,dev->sc_cur->dc_addr, 2385 dev->sc_tcnt); 2386 dev->sc_dmatimo = 1; 2387 #endif 2388 dev->sc_tcnt = dev->sc_dmanext(dev); 2389 SBIC_TC_PUT(regs, (unsigned)dev->sc_tcnt); 2390 SET_SBIC_cmd(regs, SBIC_CMD_XFER_INFO); 2391 dev->sc_flags |= SBICF_INDMA; 2392 } 2393 break; 2394 2395 case SBIC_CSR_XFERRED|MESG_IN_PHASE: 2396 case SBIC_CSR_MIS|MESG_IN_PHASE: 2397 case SBIC_CSR_MIS_1|MESG_IN_PHASE: 2398 case SBIC_CSR_MIS_2|MESG_IN_PHASE: 2399 SBIC_TRACE(dev); 2400 return sbicmsgin(dev); 2401 2402 case SBIC_CSR_MSGIN_W_ACK: 2403 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); /* Dunno what I'm ACKing */ 2404 printf("Acking unknown msgin CSR:%02x",csr); 2405 break; 2406 2407 case SBIC_CSR_XFERRED|MESG_OUT_PHASE: 2408 case SBIC_CSR_MIS|MESG_OUT_PHASE: 2409 case SBIC_CSR_MIS_1|MESG_OUT_PHASE: 2410 case SBIC_CSR_MIS_2|MESG_OUT_PHASE: 2411 #ifdef DEBUG 2412 if (sync_debug) 2413 printf ("sending REJECT msg to last msg.\n"); 2414 #endif 2415 2416 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 2417 /* 2418 * should only get here on reject, 2419 * since it's always US that 2420 * initiate a sync transfer 2421 */ 2422 SEND_BYTE(regs, MSG_REJECT); 2423 WAIT_CIP(regs); 2424 if( asr & (SBIC_ASR_BSY|SBIC_ASR_LCI|SBIC_ASR_CIP) ) 2425 printf("next: REJECT sent asr %02x\n", asr); 2426 SBIC_TRACE(dev); 2427 return SBIC_STATE_RUNNING; 2428 2429 case SBIC_CSR_DISC: 2430 case SBIC_CSR_DISC_1: 2431 dev->sc_flags &= ~(SBICF_INDMA|SBICF_SELECTED); 2432 2433 /* Try to schedule another target */ 2434 #ifdef DEBUG 2435 if(reselect_debug>1) 2436 printf("sbicnext target %d disconnected\n", dev->target); 2437 #endif 2438 TAILQ_INSERT_HEAD(&dev->nexus_list, acb, chain); 2439 ++dev->sc_tinfo[dev->target].dconns; 2440 dev->sc_nexus = NULL; 2441 dev->sc_xs = NULL; 2442 2443 if( acb->xs->xs_control & XS_CTL_POLL 2444 || (dev->sc_flags & SBICF_ICMD) 2445 || !sbic_parallel_operations ) { 2446 SBIC_TRACE(dev); 2447 return SBIC_STATE_DISCONNECT; 2448 } 2449 sbic_sched(dev); 2450 SBIC_TRACE(dev); 2451 return SBIC_STATE_DISCONNECT; 2452 2453 case SBIC_CSR_RSLT_NI: 2454 case SBIC_CSR_RSLT_IFY: 2455 GET_SBIC_rselid(regs, newtarget); 2456 /* check SBIC_RID_SIV? */ 2457 newtarget &= SBIC_RID_MASK; 2458 if (csr == SBIC_CSR_RSLT_IFY) { 2459 /* Read IFY msg to avoid lockup */ 2460 GET_SBIC_data(regs, newlun); 2461 WAIT_CIP(regs); 2462 newlun &= SBIC_TLUN_MASK; 2463 CSR_TRACE('r',csr,asr,newtarget); 2464 } else { 2465 /* Need to get IFY message */ 2466 for (newlun = 256; newlun; --newlun) { 2467 GET_SBIC_asr(regs, asr); 2468 if (asr & SBIC_ASR_INT) 2469 break; 2470 delay(1); 2471 } 2472 newlun = 0; /* XXXX */ 2473 if ((asr & SBIC_ASR_INT) == 0) { 2474 #ifdef DEBUG 2475 if (reselect_debug) 2476 printf("RSLT_NI - no IFFY message? asr %x\n", asr); 2477 #endif 2478 } else { 2479 GET_SBIC_csr(regs,csr); 2480 CSR_TRACE('n',csr,asr,newtarget); 2481 if (csr == (SBIC_CSR_MIS | MESG_IN_PHASE) || 2482 csr == (SBIC_CSR_MIS_1 | MESG_IN_PHASE) || 2483 csr == (SBIC_CSR_MIS_2 | MESG_IN_PHASE)) { 2484 sbicmsgin(dev); 2485 newlun = dev->sc_msg[0] & 7; 2486 } else { 2487 printf("RSLT_NI - not MESG_IN_PHASE %x\n", 2488 csr); 2489 } 2490 } 2491 } 2492 #ifdef DEBUG 2493 if(reselect_debug>1 || (reselect_debug && csr==SBIC_CSR_RSLT_NI)) 2494 printf("sbicnext: reselect %s from targ %d lun %d\n", 2495 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", 2496 newtarget, newlun); 2497 #endif 2498 if (dev->sc_nexus) { 2499 #ifdef DEBUG 2500 if (reselect_debug > 1) 2501 printf("%s: reselect %s with active command\n", 2502 dev->sc_dev.dv_xname, 2503 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY"); 2504 #ifdef DDB 2505 /* Debugger();*/ 2506 #endif 2507 #endif 2508 TAILQ_INSERT_HEAD(&dev->ready_list, dev->sc_nexus, chain); 2509 dev->sc_tinfo[dev->target].lubusy &= ~(1 << dev->lun); 2510 dev->sc_nexus = NULL; 2511 dev->sc_xs = NULL; 2512 } 2513 /* Reload sync values for this target */ 2514 if (dev->sc_sync[newtarget].state == SYNC_DONE) 2515 SET_SBIC_syn(regs, SBIC_SYN (dev->sc_sync[newtarget].offset, 2516 dev->sc_sync[newtarget].period)); 2517 else 2518 SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period)); 2519 for (acb = dev->nexus_list.tqh_first; acb; 2520 acb = acb->chain.tqe_next) { 2521 if (acb->xs->sc_link->scsipi_scsi.target != newtarget || 2522 acb->xs->sc_link->scsipi_scsi.lun != newlun) 2523 continue; 2524 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 2525 dev->sc_nexus = acb; 2526 dev->sc_xs = acb->xs; 2527 dev->sc_flags |= SBICF_SELECTED; 2528 dev->target = newtarget; 2529 dev->lun = newlun; 2530 break; 2531 } 2532 if (acb == NULL) { 2533 printf("%s: reselect %s targ %d not in nexus_list %p\n", 2534 dev->sc_dev.dv_xname, 2535 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", newtarget, 2536 &dev->nexus_list.tqh_first); 2537 panic("bad reselect in sbic"); 2538 } 2539 if (csr == SBIC_CSR_RSLT_IFY) 2540 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2541 break; 2542 2543 default: 2544 abort: 2545 /* 2546 * Something unexpected happened -- deal with it. 2547 */ 2548 printf("sbicnextstate: aborting csr %02x asr %02x\n", csr, asr); 2549 #ifdef DDB 2550 Debugger(); 2551 #endif 2552 #ifdef DEBUG 2553 if( data_pointer_debug > 1 ) 2554 printf("next dmastop: %d(%p:%lx)\n", 2555 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 2556 dev->sc_dmatimo = 0; 2557 #endif 2558 dev->sc_dmastop(dev); 2559 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2560 sbicerror(dev, regs, csr); 2561 sbicabort(dev, regs, "next"); 2562 if (dev->sc_flags & SBICF_INDMA) { 2563 /* 2564 * check for overlapping cache line, flush if so 2565 */ 2566 #if defined(M68040) || defined(M68060) 2567 if (dev->sc_flags & SBICF_DCFLUSH) { 2568 #if 0 2569 printf("sbic: 68040/060 DMA cache flush needs" 2570 "fixing? %x:%x\n", 2571 dev->sc_xs->data, dev->sc_xs->datalen); 2572 #endif 2573 } 2574 #endif 2575 dev->sc_flags &= 2576 ~(SBICF_INDMA | SBICF_DCFLUSH); 2577 #ifdef DEBUG 2578 if( data_pointer_debug > 1 ) 2579 printf("next dmastop: %d(%p:%lx)\n", 2580 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 2581 dev->sc_dmatimo = 0; 2582 #endif 2583 dev->sc_dmastop(dev); 2584 sbic_scsidone(acb, -1); 2585 } 2586 SBIC_TRACE(dev); 2587 return SBIC_STATE_ERROR; 2588 } 2589 2590 SBIC_TRACE(dev); 2591 return(SBIC_STATE_RUNNING); 2592 } 2593 2594 2595 /* 2596 * Check if DMA can not be used with specified buffer 2597 */ 2598 2599 int 2600 sbiccheckdmap(bp, len, mask) 2601 void *bp; 2602 u_long len, mask; 2603 { 2604 u_char *buffer; 2605 u_long phy_buf; 2606 u_long phy_len; 2607 2608 buffer = bp; 2609 2610 if (len == 0) 2611 return(0); 2612 2613 while (len) { 2614 phy_buf = kvtop(buffer); 2615 if (len < (phy_len = NBPG - ((int) buffer & PGOFSET))) 2616 phy_len = len; 2617 if (phy_buf & mask) 2618 return(1); 2619 buffer += phy_len; 2620 len -= phy_len; 2621 } 2622 return(0); 2623 } 2624 2625 int 2626 sbictoscsiperiod(dev, regs, a) 2627 struct sbic_softc *dev; 2628 sbic_regmap_t regs; 2629 int a; 2630 { 2631 unsigned int fs; 2632 2633 /* 2634 * cycle = DIV / (2*CLK) 2635 * DIV = FS+2 2636 * best we can do is 200ns at 20Mhz, 2 cycles 2637 */ 2638 2639 GET_SBIC_myid(regs,fs); 2640 fs = (fs >>6) + 2; /* DIV */ 2641 fs = (fs * 10000) / (dev->sc_clkfreq<<1); /* Cycle, in ns */ 2642 if (a < 2) a = 8; /* map to Cycles */ 2643 return ((fs*a)>>2); /* in 4 ns units */ 2644 } 2645 2646 int 2647 sbicfromscsiperiod(dev, regs, p) 2648 struct sbic_softc *dev; 2649 sbic_regmap_t regs; 2650 int p; 2651 { 2652 register unsigned int fs, ret; 2653 2654 /* Just the inverse of the above */ 2655 2656 GET_SBIC_myid(regs,fs); 2657 fs = (fs >>6) + 2; /* DIV */ 2658 fs = (fs * 10000) / (dev->sc_clkfreq<<1); /* Cycle, in ns */ 2659 2660 ret = p << 2; /* in ns units */ 2661 ret = ret / fs; /* in Cycles */ 2662 if (ret < sbic_min_period) 2663 return(sbic_min_period); 2664 2665 /* verify rounding */ 2666 if (sbictoscsiperiod(dev, regs, ret) < p) 2667 ret++; 2668 return (ret >= 8) ? 0 : ret; 2669 } 2670 2671 #ifdef DEBUG 2672 2673 void 2674 sbicdumpstate() 2675 { 2676 u_char csr, asr; 2677 2678 GET_SBIC_asr(debug_sbic_regs,asr); 2679 GET_SBIC_csr(debug_sbic_regs,csr); 2680 printf("%s: asr:csr(%02x:%02x)->(%02x:%02x)\n", 2681 (routine==1)?"sbicgo": 2682 (routine==2)?"sbicintr": 2683 (routine==3)?"sbicicmd": 2684 (routine==4)?"sbicnext":"unknown", 2685 debug_asr, debug_csr, asr, csr); 2686 2687 } 2688 2689 void 2690 sbictimeout(dev) 2691 struct sbic_softc *dev; 2692 { 2693 int s, asr; 2694 2695 s = splbio(); 2696 if (dev->sc_dmatimo) { 2697 if (dev->sc_dmatimo > 1) { 2698 printf("%s: dma timeout #%d\n", 2699 dev->sc_dev.dv_xname, dev->sc_dmatimo - 1); 2700 GET_SBIC_asr(dev->sc_sbic, asr); 2701 if( asr & SBIC_ASR_INT ) { 2702 /* We need to service a missed IRQ */ 2703 printf("Servicing a missed int:(%02x,%02x)->(%02x,??)\n", 2704 debug_asr, debug_csr, asr); 2705 sbicintr(dev); 2706 } 2707 sbicdumpstate(); 2708 } 2709 dev->sc_dmatimo++; 2710 } 2711 splx(s); 2712 callout_reset(&dev->sc_timo_ch, 30 * hz, 2713 (void *)sbictimeout, dev); 2714 } 2715 2716 void 2717 sbic_dump_acb(acb) 2718 struct sbic_acb *acb; 2719 { 2720 u_char *b = (u_char *) &acb->cmd; 2721 int i; 2722 2723 printf("acb@%p ", acb); 2724 if (acb->xs == NULL) { 2725 printf("<unused>\n"); 2726 return; 2727 } 2728 printf("(%d:%d) flags %2x clen %2d cmd ", 2729 acb->xs->sc_link->scsipi_scsi.target, 2730 acb->xs->sc_link->scsipi_scsi.lun, acb->flags, acb->clen); 2731 for (i = acb->clen; i; --i) 2732 printf(" %02x", *b++); 2733 printf("\n"); 2734 printf(" xs: %8p data %8p:%04x ", acb->xs, acb->xs->data, 2735 acb->xs->datalen); 2736 printf("va %8p:%04x ", acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 2737 printf("pa %8p:%04x tcnt %lx\n", acb->sc_pa.dc_addr, acb->sc_pa.dc_count, 2738 acb->sc_tcnt); 2739 } 2740 2741 void 2742 sbic_dump(dev) 2743 struct sbic_softc *dev; 2744 { 2745 sbic_regmap_t regs; 2746 u_char csr, asr; 2747 struct sbic_acb *acb; 2748 int s; 2749 int i; 2750 2751 s = splbio(); 2752 regs = dev->sc_sbic; 2753 #if CSR_TRACE_SIZE 2754 printf("csr trace: "); 2755 i = csr_traceptr; 2756 do { 2757 printf("%c%02x%02x%02x ", csr_trace[i].whr, 2758 csr_trace[i].csr, csr_trace[i].asr, csr_trace[i].xtn); 2759 switch(csr_trace[i].whr) { 2760 case 'g': 2761 printf("go "); break; 2762 case 's': 2763 printf("select "); break; 2764 case 'y': 2765 printf("select+ "); break; 2766 case 'i': 2767 printf("intr "); break; 2768 case 'f': 2769 printf("finish "); break; 2770 case '>': 2771 printf("out "); break; 2772 case '<': 2773 printf("in "); break; 2774 case 'm': 2775 printf("msgin "); break; 2776 case 'x': 2777 printf("msginx "); break; 2778 case 'X': 2779 printf("msginX "); break; 2780 case 'r': 2781 printf("reselect "); break; 2782 case 'I': 2783 printf("icmd "); break; 2784 case 'a': 2785 printf("abort "); break; 2786 default: 2787 printf("? "); 2788 } 2789 switch(csr_trace[i].csr) { 2790 case 0x11: 2791 printf("INITIATOR"); break; 2792 case 0x16: 2793 printf("S_XFERRED"); break; 2794 case 0x20: 2795 printf("MSGIN_ACK"); break; 2796 case 0x41: 2797 printf("DISC"); break; 2798 case 0x42: 2799 printf("SEL_TIMEO"); break; 2800 case 0x80: 2801 printf("RSLT_NI"); break; 2802 case 0x81: 2803 printf("RSLT_IFY"); break; 2804 case 0x85: 2805 printf("DISC_1"); break; 2806 case 0x18: case 0x19: case 0x1a: 2807 case 0x1b: case 0x1e: case 0x1f: 2808 case 0x28: case 0x29: case 0x2a: 2809 case 0x2b: case 0x2e: case 0x2f: 2810 case 0x48: case 0x49: case 0x4a: 2811 case 0x4b: case 0x4e: case 0x4f: 2812 case 0x88: case 0x89: case 0x8a: 2813 case 0x8b: case 0x8e: case 0x8f: 2814 switch(csr_trace[i].csr & 0xf0) { 2815 case 0x10: 2816 printf("DONE_"); break; 2817 case 0x20: 2818 printf("STOP_"); break; 2819 case 0x40: 2820 printf("ERR_"); break; 2821 case 0x80: 2822 printf("REQ_"); break; 2823 } 2824 switch(csr_trace[i].csr & 7) { 2825 case 0: 2826 printf("DATA_OUT"); break; 2827 case 1: 2828 printf("DATA_IN"); break; 2829 case 2: 2830 printf("CMD"); break; 2831 case 3: 2832 printf("STATUS"); break; 2833 case 6: 2834 printf("MSG_OUT"); break; 2835 case 7: 2836 printf("MSG_IN"); break; 2837 default: 2838 printf("invld phs"); 2839 } 2840 break; 2841 default: printf("****"); break; 2842 } 2843 if (csr_trace[i].asr & SBIC_ASR_INT) 2844 printf(" ASR_INT"); 2845 if (csr_trace[i].asr & SBIC_ASR_LCI) 2846 printf(" ASR_LCI"); 2847 if (csr_trace[i].asr & SBIC_ASR_BSY) 2848 printf(" ASR_BSY"); 2849 if (csr_trace[i].asr & SBIC_ASR_CIP) 2850 printf(" ASR_CIP"); 2851 printf("\n"); 2852 i = (i + 1) & (CSR_TRACE_SIZE - 1); 2853 } while (i != csr_traceptr); 2854 #endif 2855 GET_SBIC_asr(regs, asr); 2856 if ((asr & SBIC_ASR_INT) == 0) 2857 GET_SBIC_csr(regs, csr); 2858 else 2859 csr = 0; 2860 printf("%s@%p regs %p/%p asr %x csr %x\n", dev->sc_dev.dv_xname, 2861 dev, regs.sbic_asr_p, regs.sbic_value_p, asr, csr); 2862 if ((acb = dev->free_list.tqh_first)) { 2863 printf("Free list:\n"); 2864 while (acb) { 2865 sbic_dump_acb(acb); 2866 acb = acb->chain.tqe_next; 2867 } 2868 } 2869 if ((acb = dev->ready_list.tqh_first)) { 2870 printf("Ready list:\n"); 2871 while (acb) { 2872 sbic_dump_acb(acb); 2873 acb = acb->chain.tqe_next; 2874 } 2875 } 2876 if ((acb = dev->nexus_list.tqh_first)) { 2877 printf("Nexus list:\n"); 2878 while (acb) { 2879 sbic_dump_acb(acb); 2880 acb = acb->chain.tqe_next; 2881 } 2882 } 2883 if (dev->sc_nexus) { 2884 printf("nexus:\n"); 2885 sbic_dump_acb(dev->sc_nexus); 2886 } 2887 printf("sc_xs %p targ %d lun %d flags %x tcnt %lx dmacmd %x mask %lx\n", 2888 dev->sc_xs, dev->target, dev->lun, dev->sc_flags, dev->sc_tcnt, 2889 dev->sc_dmacmd, dev->sc_dmamask); 2890 for (i = 0; i < 8; ++i) { 2891 if (dev->sc_tinfo[i].cmds > 2) { 2892 printf("tgt %d: cmds %d disc %d senses %d lubusy %x\n", 2893 i, dev->sc_tinfo[i].cmds, 2894 dev->sc_tinfo[i].dconns, 2895 dev->sc_tinfo[i].senses, 2896 dev->sc_tinfo[i].lubusy); 2897 } 2898 } 2899 splx(s); 2900 } 2901 2902 #endif 2903
Indexes created Thu Oct 02 14:10:14 GMT 2025