sbic.c revision 1.44
1 /* $NetBSD: sbic.c,v 1.44 2001/07/22 13:34:03 wiz Exp $ */ 2 3 /* 4 * Copyright (c) 1994 Christian E. Hopps 5 * Copyright (c) 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * Van Jacobson of Lawrence Berkeley Laboratory. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the University of 22 * California, Berkeley and its contributors. 23 * 4. Neither the name of the University nor the names of its contributors 24 * may be used to endorse or promote products derived from this software 25 * without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 37 * SUCH DAMAGE. 38 * 39 * @(#)scsi.c 7.5 (Berkeley) 5/4/91 40 */ 41 42 /* 43 * AMIGA AMD 33C93 scsi adaptor driver 44 */ 45 46 #include "opt_ddb.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/device.h> 51 #include <sys/kernel.h> /* For hz */ 52 #include <sys/disklabel.h> 53 #include <sys/dkstat.h> 54 #include <sys/buf.h> 55 #include <dev/scsipi/scsi_all.h> 56 #include <dev/scsipi/scsipi_all.h> 57 #include <dev/scsipi/scsiconf.h> 58 #include <uvm/uvm_extern.h> 59 #include <machine/cpu.h> 60 #include <amiga/amiga/device.h> 61 #include <amiga/amiga/custom.h> 62 #include <amiga/amiga/isr.h> 63 #include <amiga/dev/dmavar.h> 64 #include <amiga/dev/sbicreg.h> 65 #include <amiga/dev/sbicvar.h> 66 67 /* These are for bounce buffers */ 68 #include <amiga/amiga/cc.h> 69 #include <amiga/dev/zbusvar.h> 70 71 /* Since I can't find this in any other header files */ 72 #define SCSI_PHASE(reg) (reg&0x07) 73 74 /* 75 * SCSI delays 76 * In u-seconds, primarily for state changes on the SPC. 77 */ 78 #define SBIC_CMD_WAIT 50000 /* wait per step of 'immediate' cmds */ 79 #define SBIC_DATA_WAIT 50000 /* wait per data in/out step */ 80 #define SBIC_INIT_WAIT 50000 /* wait per step (both) during init */ 81 82 #define SBIC_WAIT(regs, until, timeo) sbicwait(regs, until, timeo, __LINE__) 83 84 int sbicicmd __P((struct sbic_softc *, int, int, void *, int, void *, int)); 85 int sbicgo __P((struct sbic_softc *, struct scsipi_xfer *)); 86 int sbicdmaok __P((struct sbic_softc *, struct scsipi_xfer *)); 87 int sbicwait __P((sbic_regmap_t, char, int , int)); 88 int sbiccheckdmap __P((void *, u_long, u_long)); 89 int sbicselectbus __P((struct sbic_softc *, sbic_regmap_t, u_char, u_char, u_char)); 90 int sbicxfstart __P((sbic_regmap_t, int, u_char, int)); 91 int sbicxfout __P((sbic_regmap_t regs, int, void *, int)); 92 int sbicfromscsiperiod __P((struct sbic_softc *, sbic_regmap_t, int)); 93 int sbictoscsiperiod __P((struct sbic_softc *, sbic_regmap_t, int)); 94 int sbicpoll __P((struct sbic_softc *)); 95 int sbicnextstate __P((struct sbic_softc *, u_char, u_char)); 96 int sbicmsgin __P((struct sbic_softc *)); 97 int sbicxfin __P((sbic_regmap_t regs, int, void *)); 98 int sbicabort __P((struct sbic_softc *, sbic_regmap_t, char *)); 99 void sbicxfdone __P((struct sbic_softc *, sbic_regmap_t, int)); 100 void sbicerror __P((struct sbic_softc *, sbic_regmap_t, u_char)); 101 void sbicstart __P((struct sbic_softc *)); 102 void sbicreset __P((struct sbic_softc *)); 103 void sbic_scsidone __P((struct sbic_acb *, int)); 104 void sbic_sched __P((struct sbic_softc *)); 105 void sbic_save_ptrs __P((struct sbic_softc *, sbic_regmap_t,int,int)); 106 void sbic_load_ptrs __P((struct sbic_softc *, sbic_regmap_t,int,int)); 107 #ifdef DEBUG 108 void sbicdumpstate __P((void)); 109 void sbic_dump_acb __P((struct sbic_acb *)); 110 #endif 111 112 /* 113 * Synch xfer parameters, and timing conversions 114 */ 115 int sbic_min_period = SBIC_SYN_MIN_PERIOD; /* in cycles = f(ICLK,FSn) */ 116 int sbic_max_offset = SBIC_SYN_MAX_OFFSET; /* pure number */ 117 118 int sbic_cmd_wait = SBIC_CMD_WAIT; 119 int sbic_data_wait = SBIC_DATA_WAIT; 120 int sbic_init_wait = SBIC_INIT_WAIT; 121 122 /* 123 * was broken before.. now if you want this you get it for all drives 124 * on sbic controllers. 125 */ 126 u_char sbic_inhibit_sync[8]; 127 int sbic_enable_reselect = 1; 128 int sbic_clock_override = 0; 129 int sbic_no_dma = 0; 130 int sbic_parallel_operations = 1; 131 132 #ifdef DEBUG 133 sbic_regmap_t debug_sbic_regs; 134 int sbicdma_ops = 0; /* total DMA operations */ 135 int sbicdma_bounces = 0; /* number operations using bounce buffer */ 136 int sbicdma_hits = 0; /* number of DMA chains that were contiguous */ 137 int sbicdma_misses = 0; /* number of DMA chains that were not contiguous */ 138 int sbicdma_saves = 0; 139 #define QPRINTF(a) if (sbic_debug > 1) printf a 140 int sbic_debug = 0; 141 int sync_debug = 0; 142 int sbic_dma_debug = 0; 143 int reselect_debug = 0; 144 int data_pointer_debug = 0; 145 u_char debug_asr, debug_csr, routine; 146 void sbictimeout __P((struct sbic_softc *dev)); 147 148 #define CSR_TRACE_SIZE 32 149 #if CSR_TRACE_SIZE 150 #define CSR_TRACE(w,c,a,x) do { \ 151 int s = splbio(); \ 152 csr_trace[csr_traceptr].whr = (w); csr_trace[csr_traceptr].csr = (c); \ 153 csr_trace[csr_traceptr].asr = (a); csr_trace[csr_traceptr].xtn = (x); \ 154 dma_cachectl((caddr_t)&csr_trace[csr_traceptr], sizeof(csr_trace[0])); \ 155 csr_traceptr = (csr_traceptr + 1) & (CSR_TRACE_SIZE - 1); \ 156 /* dma_cachectl((caddr_t)&csr_traceptr, sizeof(csr_traceptr));*/ \ 157 splx(s); \ 158 } while (0) 159 int csr_traceptr; 160 int csr_tracesize = CSR_TRACE_SIZE; 161 struct { 162 u_char whr; 163 u_char csr; 164 u_char asr; 165 u_char xtn; 166 } csr_trace[CSR_TRACE_SIZE]; 167 #else 168 #define CSR_TRACE(w,c,a,x) 169 #endif 170 171 #define SBIC_TRACE_SIZE 0 172 #if SBIC_TRACE_SIZE 173 #define SBIC_TRACE(dev) do { \ 174 int s = splbio(); \ 175 sbic_trace[sbic_traceptr].sp = &s; \ 176 sbic_trace[sbic_traceptr].line = __LINE__; \ 177 sbic_trace[sbic_traceptr].sr = s; \ 178 sbic_trace[sbic_traceptr].csr = csr_traceptr; \ 179 dma_cachectl(&sbic_trace[sbic_traceptr], sizeof(sbic_trace[0])); \ 180 sbic_traceptr = (sbic_traceptr + 1) & (SBIC_TRACE_SIZE - 1); \ 181 dma_cachectl(&sbic_traceptr, sizeof(sbic_traceptr)); \ 182 if (dev) dma_cachectl(dev, sizeof(*dev)); \ 183 splx(s); \ 184 } while (0) 185 int sbic_traceptr; 186 int sbic_tracesize = SBIC_TRACE_SIZE; 187 struct { 188 void *sp; 189 u_short line; 190 u_short sr; 191 int csr; 192 } sbic_trace[SBIC_TRACE_SIZE]; 193 #else 194 #define SBIC_TRACE(dev) 195 #endif 196 197 #else /* DEBUG */ 198 #define QPRINTF(a) 199 #define CSR_TRACE(w,c,a,x) 200 #define SBIC_TRACE(dev) 201 #endif /* DEBUG */ 202 203 /* 204 * default minphys routine for sbic based controllers 205 */ 206 void 207 sbic_minphys(bp) 208 struct buf *bp; 209 { 210 211 /* 212 * No max transfer at this level. 213 */ 214 minphys(bp); 215 } 216 217 /* 218 * Save DMA pointers. Take into account partial transfer. Shut down DMA. 219 */ 220 void 221 sbic_save_ptrs(dev, regs, target, lun) 222 struct sbic_softc *dev; 223 sbic_regmap_t regs; 224 int target, lun; 225 { 226 int count, asr, s; 227 struct sbic_acb* acb; 228 229 SBIC_TRACE(dev); 230 if( !dev->sc_cur ) return; 231 if( !(dev->sc_flags & SBICF_INDMA) ) return; /* DMA not active */ 232 233 s = splbio(); 234 235 acb = dev->sc_nexus; 236 count = -1; 237 do { 238 GET_SBIC_asr(regs, asr); 239 if( asr & SBIC_ASR_DBR ) { 240 printf("sbic_save_ptrs: asr %02x canceled!\n", asr); 241 splx(s); 242 SBIC_TRACE(dev); 243 return; 244 } 245 } while( asr & (SBIC_ASR_BSY|SBIC_ASR_CIP) ); 246 247 /* Save important state */ 248 /* must be done before dmastop */ 249 acb->sc_dmacmd = dev->sc_dmacmd; 250 SBIC_TC_GET(regs, count); 251 252 /* Shut down DMA ====CAREFUL==== */ 253 dev->sc_dmastop(dev); 254 dev->sc_flags &= ~SBICF_INDMA; 255 SBIC_TC_PUT(regs, 0); 256 257 #ifdef DEBUG 258 if(!count && sbic_debug) printf("%dcount0",target); 259 if(data_pointer_debug == -1) 260 printf("SBIC saving target %d data pointers from (%p,%x)%xASR:%02x", 261 target, dev->sc_cur->dc_addr, dev->sc_cur->dc_count, 262 acb->sc_dmacmd, asr); 263 #endif 264 265 /* Fixup partial xfers */ 266 acb->sc_kv.dc_addr += (dev->sc_tcnt - count); 267 acb->sc_kv.dc_count -= (dev->sc_tcnt - count); 268 acb->sc_pa.dc_addr += (dev->sc_tcnt - count); 269 acb->sc_pa.dc_count -= ((dev->sc_tcnt - count)>>1); 270 271 acb->sc_tcnt = dev->sc_tcnt = count; 272 #ifdef DEBUG 273 if(data_pointer_debug) 274 printf(" at (%p,%x):%x\n", 275 dev->sc_cur->dc_addr, dev->sc_cur->dc_count,count); 276 sbicdma_saves++; 277 #endif 278 splx(s); 279 SBIC_TRACE(dev); 280 } 281 282 283 /* 284 * DOES NOT RESTART DMA!!! 285 */ 286 void sbic_load_ptrs(dev, regs, target, lun) 287 struct sbic_softc *dev; 288 sbic_regmap_t regs; 289 int target, lun; 290 { 291 int s, count; 292 char* vaddr, * paddr; 293 struct sbic_acb *acb; 294 295 SBIC_TRACE(dev); 296 acb = dev->sc_nexus; 297 if( !acb->sc_kv.dc_count ) { 298 /* No data to xfer */ 299 SBIC_TRACE(dev); 300 return; 301 } 302 303 s = splbio(); 304 305 dev->sc_last = dev->sc_cur = &acb->sc_pa; 306 dev->sc_tcnt = acb->sc_tcnt; 307 dev->sc_dmacmd = acb->sc_dmacmd; 308 309 #ifdef DEBUG 310 sbicdma_ops++; 311 #endif 312 if( !dev->sc_tcnt ) { 313 /* sc_tcnt == 0 implies end of segment */ 314 315 /* do kvm to pa mappings */ 316 paddr = acb->sc_pa.dc_addr = 317 (char *) kvtop(acb->sc_kv.dc_addr); 318 319 vaddr = acb->sc_kv.dc_addr; 320 count = acb->sc_kv.dc_count; 321 for(count = (NBPG - ((int)vaddr & PGOFSET)); 322 count < acb->sc_kv.dc_count 323 && (char*)kvtop(vaddr + count + 4) == paddr + count + 4; 324 count += NBPG); 325 /* If it's all contiguous... */ 326 if(count > acb->sc_kv.dc_count ) { 327 count = acb->sc_kv.dc_count; 328 #ifdef DEBUG 329 sbicdma_hits++; 330 #endif 331 } else { 332 #ifdef DEBUG 333 sbicdma_misses++; 334 #endif 335 } 336 acb->sc_tcnt = count; 337 acb->sc_pa.dc_count = count >> 1; 338 339 #ifdef DEBUG 340 if(data_pointer_debug) 341 printf("DMA recalc:kv(%p,%x)pa(%p,%lx)\n", 342 acb->sc_kv.dc_addr, 343 acb->sc_kv.dc_count, 344 acb->sc_pa.dc_addr, 345 acb->sc_tcnt); 346 #endif 347 } 348 splx(s); 349 #ifdef DEBUG 350 if(data_pointer_debug) 351 printf("SBIC restoring target %d data pointers at (%p,%x)%x\n", 352 target, dev->sc_cur->dc_addr, dev->sc_cur->dc_count, 353 dev->sc_dmacmd); 354 #endif 355 SBIC_TRACE(dev); 356 } 357 358 /* 359 * used by specific sbic controller 360 * 361 * it appears that the higher level code does nothing with LUN's 362 * so I will too. I could plug it in, however so could they 363 * in scsi_scsipi_cmd(). 364 */ 365 void 366 sbic_scsipi_request(chan, req, arg) 367 struct scsipi_channel *chan; 368 scsipi_adapter_req_t req; 369 void *arg; 370 { 371 struct scsipi_xfer *xs; 372 struct scsipi_periph *periph; 373 struct sbic_acb *acb; 374 struct sbic_softc *dev = (void *)chan->chan_adapter->adapt_dev; 375 int flags, s, stat; 376 377 switch (req) { 378 case ADAPTER_REQ_RUN_XFER: 379 xs = arg; 380 periph = xs->xs_periph; 381 382 SBIC_TRACE(dev); 383 flags = xs->xs_control; 384 385 if (flags & XS_CTL_DATA_UIO) 386 panic("sbic: scsi data uio requested"); 387 388 if (dev->sc_nexus && flags & XS_CTL_POLL) 389 panic("sbic_scsipi_request: busy"); 390 391 s = splbio(); 392 acb = dev->free_list.tqh_first; 393 if (acb) 394 TAILQ_REMOVE(&dev->free_list, acb, chain); 395 splx(s); 396 397 #ifdef DIAGNOSTIC 398 if (acb == NULL) { 399 scsipi_printaddr(periph); 400 printf("unable to allocate acb\n"); 401 panic("sbic_scsipi_request"); 402 } 403 #endif 404 acb->flags = ACB_ACTIVE; 405 if (flags & XS_CTL_DATA_IN) 406 acb->flags |= ACB_DATAIN; 407 acb->xs = xs; 408 bcopy(xs->cmd, &acb->cmd, xs->cmdlen); 409 acb->clen = xs->cmdlen; 410 acb->sc_kv.dc_addr = xs->data; 411 acb->sc_kv.dc_count = xs->datalen; 412 acb->pa_addr = xs->data ? (char *)kvtop(xs->data) : 0; /* XXXX check */ 413 414 if (flags & XS_CTL_POLL) { 415 s = splbio(); 416 /* 417 * This has major side effects - it locks up the machine 418 */ 419 420 dev->sc_flags |= SBICF_ICMD; 421 do { 422 while(dev->sc_nexus) 423 sbicpoll(dev); 424 dev->sc_nexus = acb; 425 dev->sc_stat[0] = -1; 426 dev->sc_xs = xs; 427 dev->target = periph->periph_target; 428 dev->lun = periph->periph_lun; 429 stat = sbicicmd(dev, dev->target, dev->lun, 430 &acb->cmd, acb->clen, 431 acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 432 } while (dev->sc_nexus != acb); 433 sbic_scsidone(acb, stat); 434 435 splx(s); 436 SBIC_TRACE(dev); 437 return; 438 } 439 440 s = splbio(); 441 TAILQ_INSERT_TAIL(&dev->ready_list, acb, chain); 442 443 if (dev->sc_nexus) { 444 splx(s); 445 SBIC_TRACE(dev); 446 return; 447 } 448 449 /* 450 * nothing is active, try to start it now. 451 */ 452 sbic_sched(dev); 453 splx(s); 454 455 SBIC_TRACE(dev); 456 /* TODO: add sbic_poll to do XS_CTL_POLL operations */ 457 #if 0 458 if (flags & XS_CTL_POLL) 459 return(COMPLETE); 460 #endif 461 return; 462 463 case ADAPTER_REQ_GROW_RESOURCES: 464 return; 465 466 case ADAPTER_REQ_SET_XFER_MODE: 467 return; 468 } 469 } 470 471 /* 472 * attempt to start the next available command 473 */ 474 void 475 sbic_sched(dev) 476 struct sbic_softc *dev; 477 { 478 struct scsipi_xfer *xs; 479 struct scsipi_periph *periph; 480 struct sbic_acb *acb; 481 int flags, /*phase,*/ stat, i; 482 483 SBIC_TRACE(dev); 484 if (dev->sc_nexus) 485 return; /* a command is current active */ 486 487 SBIC_TRACE(dev); 488 for (acb = dev->ready_list.tqh_first; acb; acb = acb->chain.tqe_next) { 489 periph = acb->xs->xs_periph; 490 i = periph->periph_target; 491 if (!(dev->sc_tinfo[i].lubusy & (1 << periph->periph_lun))) { 492 struct sbic_tinfo *ti = &dev->sc_tinfo[i]; 493 494 TAILQ_REMOVE(&dev->ready_list, acb, chain); 495 dev->sc_nexus = acb; 496 ti = &dev->sc_tinfo[periph->periph_target]; 497 ti->lubusy |= (1 << periph->periph_lun); 498 acb->sc_pa.dc_addr = acb->pa_addr; /* XXXX check */ 499 break; 500 } 501 } 502 503 SBIC_TRACE(dev); 504 if (acb == NULL) 505 return; /* did not find an available command */ 506 507 dev->sc_xs = xs = acb->xs; 508 periph = xs->xs_periph; 509 flags = xs->xs_control; 510 511 if (flags & XS_CTL_RESET) 512 sbicreset(dev); 513 514 #ifdef DEBUG 515 if( data_pointer_debug > 1 ) 516 printf("sbic_sched(%d,%d)\n", periph->periph_target, 517 periph->periph_lun); 518 #endif 519 dev->sc_stat[0] = -1; 520 dev->target = periph->periph_target; 521 dev->lun = periph->periph_lun; 522 if ( flags & XS_CTL_POLL || ( !sbic_parallel_operations 523 && (sbicdmaok(dev, xs) == 0))) 524 stat = sbicicmd(dev, periph->periph_target, 525 periph->periph_lun, &acb->cmd, 526 acb->clen, acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 527 else if (sbicgo(dev, xs) == 0 && xs->error != XS_SELTIMEOUT) { 528 SBIC_TRACE(dev); 529 return; 530 } else 531 stat = dev->sc_stat[0]; 532 533 sbic_scsidone(acb, stat); 534 SBIC_TRACE(dev); 535 } 536 537 void 538 sbic_scsidone(acb, stat) 539 struct sbic_acb *acb; 540 int stat; 541 { 542 struct scsipi_xfer *xs; 543 struct scsipi_periph *periph; 544 struct sbic_softc *dev; 545 int dosched = 0; 546 547 xs = acb->xs; 548 periph = xs->xs_periph; 549 dev = (void *)periph->periph_channel->chan_adapter->adapt_dev; 550 SBIC_TRACE(dev); 551 #ifdef DIAGNOSTIC 552 if (acb == NULL || xs == NULL) { 553 printf("sbic_scsidone -- (%d,%d) no scsi_xfer\n", 554 dev->target, dev->lun); 555 #ifdef DDB 556 Debugger(); 557 #endif 558 return; 559 } 560 #endif 561 562 xs->status = stat; 563 xs->resid = 0; /* XXXX */ 564 #ifdef DEBUG 565 if( data_pointer_debug > 1 ) 566 printf("scsidone: (%d,%d)->(%d,%d)%02x\n", 567 periph->periph_target, periph->periph_lun, 568 dev->target, dev->lun, stat); 569 if( periph->periph_target == 570 periph->periph_channel->chan_id) 571 panic("target == hostid"); 572 #endif 573 574 if (xs->error == XS_NOERROR) { 575 if (stat == SCSI_CHECK || stat == SCSI_BUSY) 576 xs->error = XS_BUSY; 577 } 578 579 /* 580 * Remove the ACB from whatever queue it's on. We have to do a bit of 581 * a hack to figure out which queue it's on. Note that it is *not* 582 * necessary to cdr down the ready queue, but we must cdr down the 583 * nexus queue and see if it's there, so we can mark the unit as no 584 * longer busy. This code is sickening, but it works. 585 */ 586 if (acb == dev->sc_nexus) { 587 dev->sc_nexus = NULL; 588 dev->sc_xs = NULL; 589 dev->sc_tinfo[periph->periph_target].lubusy &= 590 ~(1<<periph->periph_lun); 591 if (dev->ready_list.tqh_first) 592 dosched = 1; /* start next command */ 593 } else if (dev->ready_list.tqh_last == &acb->chain.tqe_next) { 594 TAILQ_REMOVE(&dev->ready_list, acb, chain); 595 } else { 596 register struct sbic_acb *acb2; 597 for (acb2 = dev->nexus_list.tqh_first; acb2; 598 acb2 = acb2->chain.tqe_next) { 599 if (acb2 == acb) { 600 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 601 dev->sc_tinfo[periph->periph_target].lubusy 602 &= ~(1<<periph->periph_lun); 603 break; 604 } 605 } 606 if (acb2) 607 ; 608 else if (acb->chain.tqe_next) { 609 TAILQ_REMOVE(&dev->ready_list, acb, chain); 610 } else { 611 printf("%s: can't find matching acb\n", 612 dev->sc_dev.dv_xname); 613 #ifdef DDB 614 Debugger(); 615 #endif 616 } 617 } 618 /* Put it on the free list. */ 619 acb->flags = ACB_FREE; 620 TAILQ_INSERT_HEAD(&dev->free_list, acb, chain); 621 622 dev->sc_tinfo[periph->periph_target].cmds++; 623 624 scsipi_done(xs); 625 626 if (dosched) 627 sbic_sched(dev); 628 SBIC_TRACE(dev); 629 } 630 631 int 632 sbicdmaok(dev, xs) 633 struct sbic_softc *dev; 634 struct scsipi_xfer *xs; 635 { 636 if (sbic_no_dma || !xs->datalen || xs->datalen & 0x1 || 637 (u_int)xs->data & 0x3) 638 return(0); 639 /* 640 * controller supports dma to any addresses? 641 */ 642 else if ((dev->sc_flags & SBICF_BADDMA) == 0) 643 return(1); 644 /* 645 * this address is ok for dma? 646 */ 647 else if (sbiccheckdmap(xs->data, xs->datalen, dev->sc_dmamask) == 0) 648 return(1); 649 /* 650 * we have a bounce buffer? 651 */ 652 else if (dev->sc_tinfo[xs->xs_periph->periph_target].bounce) 653 return(1); 654 /* 655 * try to get one 656 */ 657 else if ((dev->sc_tinfo[xs->xs_periph->periph_target].bounce 658 = (char *)alloc_z2mem(MAXPHYS))) { 659 if (isztwomem(dev->sc_tinfo[xs->xs_periph->periph_target].bounce)) 660 printf("alloc ZII target %d bounce pa 0x%x\n", 661 xs->xs_periph->periph_target, 662 kvtop(dev->sc_tinfo[xs->xs_periph->periph_target].bounce)); 663 else if (dev->sc_tinfo[xs->xs_periph->periph_target].bounce) 664 printf("alloc CHIP target %d bounce pa 0x%p\n", 665 xs->xs_periph->periph_target, 666 PREP_DMA_MEM(dev->sc_tinfo[xs->xs_periph->periph_target].bounce)); 667 return(1); 668 } 669 670 return(0); 671 } 672 673 674 int 675 sbicwait(regs, until, timeo, line) 676 sbic_regmap_t regs; 677 char until; 678 int timeo; 679 int line; 680 { 681 u_char val; 682 int csr; 683 684 SBIC_TRACE((struct sbic_softc *)0); 685 if (timeo == 0) 686 timeo = 1000000; /* some large value.. */ 687 688 GET_SBIC_asr(regs,val); 689 while ((val & until) == 0) { 690 if (timeo-- == 0) { 691 GET_SBIC_csr(regs, csr); 692 printf("sbicwait TIMEO @%d with asr=x%x csr=x%x\n", 693 line, val, csr); 694 #if defined(DDB) && defined(DEBUG) 695 Debugger(); 696 #endif 697 return(val); /* Maybe I should abort */ 698 break; 699 } 700 DELAY(1); 701 GET_SBIC_asr(regs,val); 702 } 703 SBIC_TRACE((struct sbic_softc *)0); 704 return(val); 705 } 706 707 int 708 sbicabort(dev, regs, where) 709 struct sbic_softc *dev; 710 sbic_regmap_t regs; 711 char *where; 712 { 713 u_char csr, asr; 714 715 GET_SBIC_asr(regs, asr); 716 GET_SBIC_csr(regs, csr); 717 718 printf ("%s: abort %s: csr = 0x%02x, asr = 0x%02x\n", 719 dev->sc_dev.dv_xname, where, csr, asr); 720 721 722 #if 0 723 /* Clean up running command */ 724 if (dev->sc_nexus != NULL) { 725 dev->sc_nexus->xs->error = XS_DRIVER_STUFFUP; 726 sbic_scsidone(dev->sc_nexus, dev->sc_stat[0]); 727 } 728 while (acb = dev->nexus_list.tqh_first) { 729 acb->xs->error = XS_DRIVER_STUFFUP; 730 sbic_scsidone(acb, -1 /*acb->stat[0]*/); 731 } 732 #endif 733 734 /* Clean up chip itself */ 735 if (dev->sc_flags & SBICF_SELECTED) { 736 while( asr & SBIC_ASR_DBR ) { 737 /* sbic is jammed w/data. need to clear it */ 738 /* But we don't know what direction it needs to go */ 739 GET_SBIC_data(regs, asr); 740 printf("%s: abort %s: clearing data buffer 0x%02x\n", 741 dev->sc_dev.dv_xname, where, asr); 742 GET_SBIC_asr(regs, asr); 743 if( asr & SBIC_ASR_DBR ) /* Not the read direction, then */ 744 SET_SBIC_data(regs, asr); 745 GET_SBIC_asr(regs, asr); 746 } 747 WAIT_CIP(regs); 748 printf("%s: sbicabort - sending ABORT command\n", dev->sc_dev.dv_xname); 749 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 750 WAIT_CIP(regs); 751 752 GET_SBIC_asr(regs, asr); 753 if (asr & (SBIC_ASR_BSY|SBIC_ASR_LCI)) { 754 /* ok, get more drastic.. */ 755 756 printf("%s: sbicabort - asr %x, trying to reset\n", dev->sc_dev.dv_xname, asr); 757 sbicreset(dev); 758 dev->sc_flags &= ~SBICF_SELECTED; 759 return -1; 760 } 761 printf("%s: sbicabort - sending DISC command\n", dev->sc_dev.dv_xname); 762 SET_SBIC_cmd(regs, SBIC_CMD_DISC); 763 764 do { 765 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0); 766 GET_SBIC_csr (regs, csr); 767 CSR_TRACE('a',csr,asr,0); 768 } while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) 769 && (csr != SBIC_CSR_CMD_INVALID)); 770 771 /* lets just hope it worked.. */ 772 dev->sc_flags &= ~SBICF_SELECTED; 773 } 774 return -1; 775 } 776 777 778 /* 779 * Initialize driver-private structures 780 */ 781 782 void 783 sbicinit(dev) 784 struct sbic_softc *dev; 785 { 786 sbic_regmap_t regs; 787 u_int i; 788 struct sbic_acb *acb; 789 u_int inhibit_sync; 790 791 extern u_long scsi_nosync; 792 extern int shift_nosync; 793 794 regs = dev->sc_sbic; 795 796 if ((dev->sc_flags & SBICF_ALIVE) == 0) { 797 TAILQ_INIT(&dev->ready_list); 798 TAILQ_INIT(&dev->nexus_list); 799 TAILQ_INIT(&dev->free_list); 800 callout_init(&dev->sc_timo_ch); 801 dev->sc_nexus = NULL; 802 dev->sc_xs = NULL; 803 acb = dev->sc_acb; 804 bzero(acb, sizeof(dev->sc_acb)); 805 for (i = 0; i < sizeof(dev->sc_acb) / sizeof(*acb); i++) { 806 TAILQ_INSERT_TAIL(&dev->free_list, acb, chain); 807 acb++; 808 } 809 bzero(dev->sc_tinfo, sizeof(dev->sc_tinfo)); 810 #ifdef DEBUG 811 /* make sure timeout is really not needed */ 812 callout_reset(&dev->sc_timo_ch, 30 * hz, 813 (void *)sbictimeout, dev); 814 #endif 815 816 } else panic("sbic: reinitializing driver!"); 817 818 dev->sc_flags |= SBICF_ALIVE; 819 dev->sc_flags &= ~SBICF_SELECTED; 820 821 /* initialize inhibit array */ 822 if (scsi_nosync) { 823 inhibit_sync = (scsi_nosync >> shift_nosync) & 0xff; 824 shift_nosync += 8; 825 #ifdef DEBUG 826 if (inhibit_sync) 827 printf("%s: Inhibiting synchronous transfer %02x\n", 828 dev->sc_dev.dv_xname, inhibit_sync); 829 #endif 830 for (i = 0; i < 8; ++i) 831 if (inhibit_sync & (1 << i)) 832 sbic_inhibit_sync[i] = 1; 833 } 834 835 sbicreset(dev); 836 } 837 838 void 839 sbicreset(dev) 840 struct sbic_softc *dev; 841 { 842 sbic_regmap_t regs; 843 u_int my_id, s; 844 u_char csr; 845 #if 0 846 u_int i; 847 struct sbic_acb *acb; 848 #endif 849 850 regs = dev->sc_sbic; 851 #if 0 852 if (dev->sc_flags & SBICF_ALIVE) { 853 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 854 WAIT_CIP(regs); 855 } 856 #else 857 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 858 WAIT_CIP(regs); 859 #endif 860 s = splbio(); 861 my_id = dev->sc_channel.chan_id & SBIC_ID_MASK; 862 863 /* Enable advanced mode */ 864 my_id |= SBIC_ID_EAF /*| SBIC_ID_EHP*/ ; 865 SET_SBIC_myid(regs, my_id); 866 867 /* 868 * Disable interrupts (in dmainit) then reset the chip 869 */ 870 SET_SBIC_cmd(regs, SBIC_CMD_RESET); 871 DELAY(25); 872 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 873 GET_SBIC_csr(regs, csr); /* clears interrupt also */ 874 875 if (dev->sc_clkfreq < 110) 876 my_id |= SBIC_ID_FS_8_10; 877 else if (dev->sc_clkfreq < 160) 878 my_id |= SBIC_ID_FS_12_15; 879 else if (dev->sc_clkfreq < 210) 880 my_id |= SBIC_ID_FS_16_20; 881 882 SET_SBIC_myid(regs, my_id); 883 884 /* 885 * Set up various chip parameters 886 */ 887 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI /* | SBIC_CTL_HSP */ 888 | SBIC_MACHINE_DMA_MODE); 889 /* 890 * don't allow (re)selection (SBIC_RID_ES) 891 * until we can handle target mode!! 892 */ 893 SET_SBIC_rselid(regs, SBIC_RID_ER); 894 SET_SBIC_syn(regs, 0); /* asynch for now */ 895 896 /* 897 * anything else was zeroed by reset 898 */ 899 splx(s); 900 901 #if 0 902 if ((dev->sc_flags & SBICF_ALIVE) == 0) { 903 TAILQ_INIT(&dev->ready_list); 904 TAILQ_INIT(&dev->nexus_list); 905 TAILQ_INIT(&dev->free_list); 906 dev->sc_nexus = NULL; 907 dev->sc_xs = NULL; 908 acb = dev->sc_acb; 909 bzero(acb, sizeof(dev->sc_acb)); 910 for (i = 0; i < sizeof(dev->sc_acb) / sizeof(*acb); i++) { 911 TAILQ_INSERT_TAIL(&dev->free_list, acb, chain); 912 acb++; 913 } 914 bzero(dev->sc_tinfo, sizeof(dev->sc_tinfo)); 915 } else { 916 if (dev->sc_nexus != NULL) { 917 dev->sc_nexus->xs->error = XS_DRIVER_STUFFUP; 918 sbic_scsidone(dev->sc_nexus, dev->sc_stat[0]); 919 } 920 while (acb = dev->nexus_list.tqh_first) { 921 acb->xs->error = XS_DRIVER_STUFFUP; 922 sbic_scsidone(acb, -1 /*acb->stat[0]*/); 923 } 924 } 925 926 dev->sc_flags |= SBICF_ALIVE; 927 #endif 928 dev->sc_flags &= ~SBICF_SELECTED; 929 } 930 931 void 932 sbicerror(dev, regs, csr) 933 struct sbic_softc *dev; 934 sbic_regmap_t regs; 935 u_char csr; 936 { 937 struct scsipi_xfer *xs; 938 939 xs = dev->sc_xs; 940 941 #ifdef DIAGNOSTIC 942 if (xs == NULL) 943 panic("sbicerror"); 944 #endif 945 if (xs->xs_control & XS_CTL_SILENT) 946 return; 947 948 printf("%s: ", dev->sc_dev.dv_xname); 949 printf("csr == 0x%02x\n", csr); /* XXX */ 950 } 951 952 /* 953 * select the bus, return when selected or error. 954 */ 955 int 956 sbicselectbus(dev, regs, target, lun, our_addr) 957 struct sbic_softc *dev; 958 sbic_regmap_t regs; 959 u_char target, lun, our_addr; 960 { 961 u_char asr, csr, id; 962 963 SBIC_TRACE(dev); 964 QPRINTF(("sbicselectbus %d\n", target)); 965 966 /* 967 * if we're already selected, return (XXXX panic maybe?) 968 */ 969 if (dev->sc_flags & SBICF_SELECTED) { 970 SBIC_TRACE(dev); 971 return(1); 972 } 973 974 /* 975 * issue select 976 */ 977 SBIC_TC_PUT(regs, 0); 978 SET_SBIC_selid(regs, target); 979 SET_SBIC_timeo(regs, SBIC_TIMEOUT(250,dev->sc_clkfreq)); 980 981 /* 982 * set sync or async 983 */ 984 if (dev->sc_sync[target].state == SYNC_DONE) 985 SET_SBIC_syn(regs, SBIC_SYN (dev->sc_sync[target].offset, 986 dev->sc_sync[target].period)); 987 else 988 SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period)); 989 990 GET_SBIC_asr(regs, asr); 991 if( asr & (SBIC_ASR_INT|SBIC_ASR_BSY) ) { 992 /* This means we got ourselves reselected upon */ 993 /* printf("sbicselectbus: INT/BSY asr %02x\n", asr);*/ 994 #ifdef DDB 995 /* Debugger();*/ 996 #endif 997 SBIC_TRACE(dev); 998 return 1; 999 } 1000 1001 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN); 1002 1003 /* 1004 * wait for select (merged from separate function may need 1005 * cleanup) 1006 */ 1007 WAIT_CIP(regs); 1008 do { 1009 asr = SBIC_WAIT(regs, SBIC_ASR_INT | SBIC_ASR_LCI, 0); 1010 if (asr & SBIC_ASR_LCI) { 1011 #ifdef DEBUG 1012 if (reselect_debug) 1013 printf("sbicselectbus: late LCI asr %02x\n", asr); 1014 #endif 1015 SBIC_TRACE(dev); 1016 return 1; 1017 } 1018 GET_SBIC_csr (regs, csr); 1019 CSR_TRACE('s',csr,asr,target); 1020 QPRINTF(("%02x ", csr)); 1021 if( csr == SBIC_CSR_RSLT_NI || csr == SBIC_CSR_RSLT_IFY) { 1022 #ifdef DEBUG 1023 if(reselect_debug) 1024 printf("sbicselectbus: reselected asr %02x\n", asr); 1025 #endif 1026 /* We need to handle this now so we don't lock up later */ 1027 sbicnextstate(dev, csr, asr); 1028 SBIC_TRACE(dev); 1029 return 1; 1030 } 1031 if( csr == SBIC_CSR_SLT || csr == SBIC_CSR_SLT_ATN) { 1032 panic("sbicselectbus: target issued select!"); 1033 return 1; 1034 } 1035 } while (csr != (SBIC_CSR_MIS_2|MESG_OUT_PHASE) 1036 && csr != (SBIC_CSR_MIS_2|CMD_PHASE) && csr != SBIC_CSR_SEL_TIMEO); 1037 1038 /* Enable (or not) reselection */ 1039 if(!sbic_enable_reselect && dev->nexus_list.tqh_first == NULL) 1040 SET_SBIC_rselid (regs, 0); 1041 else 1042 SET_SBIC_rselid (regs, SBIC_RID_ER); 1043 1044 if (csr == (SBIC_CSR_MIS_2|CMD_PHASE)) { 1045 dev->sc_flags |= SBICF_SELECTED; /* device ignored ATN */ 1046 GET_SBIC_selid(regs, id); 1047 dev->target = id; 1048 GET_SBIC_tlun(regs,dev->lun); 1049 if( dev->lun & SBIC_TLUN_VALID ) 1050 dev->lun &= SBIC_TLUN_MASK; 1051 else 1052 dev->lun = lun; 1053 } else if (csr == (SBIC_CSR_MIS_2|MESG_OUT_PHASE)) { 1054 /* 1055 * Send identify message 1056 * (SCSI-2 requires an identify msg (?)) 1057 */ 1058 GET_SBIC_selid(regs, id); 1059 dev->target = id; 1060 GET_SBIC_tlun(regs,dev->lun); 1061 if( dev->lun & SBIC_TLUN_VALID ) 1062 dev->lun &= SBIC_TLUN_MASK; 1063 else 1064 dev->lun = lun; 1065 /* 1066 * handle drives that don't want to be asked 1067 * whether to go sync at all. 1068 */ 1069 if (sbic_inhibit_sync[id] 1070 && dev->sc_sync[id].state == SYNC_START) { 1071 #ifdef DEBUG 1072 if (sync_debug) 1073 printf("Forcing target %d asynchronous.\n", id); 1074 #endif 1075 dev->sc_sync[id].offset = 0; 1076 dev->sc_sync[id].period = sbic_min_period; 1077 dev->sc_sync[id].state = SYNC_DONE; 1078 } 1079 1080 1081 if (dev->sc_sync[id].state != SYNC_START){ 1082 if( dev->sc_xs->xs_control & XS_CTL_POLL 1083 || (dev->sc_flags & SBICF_ICMD) 1084 || !sbic_enable_reselect ) 1085 SEND_BYTE (regs, MSG_IDENTIFY | lun); 1086 else 1087 SEND_BYTE (regs, MSG_IDENTIFY_DR | lun); 1088 } else { 1089 /* 1090 * try to initiate a sync transfer. 1091 * So compose the sync message we're going 1092 * to send to the target 1093 */ 1094 1095 #ifdef DEBUG 1096 if (sync_debug) 1097 printf("Sending sync request to target %d ... ", 1098 id); 1099 #endif 1100 /* 1101 * setup scsi message sync message request 1102 */ 1103 dev->sc_msg[0] = MSG_IDENTIFY | lun; 1104 dev->sc_msg[1] = MSG_EXT_MESSAGE; 1105 dev->sc_msg[2] = 3; 1106 dev->sc_msg[3] = MSG_SYNC_REQ; 1107 dev->sc_msg[4] = sbictoscsiperiod(dev, regs, 1108 sbic_min_period); 1109 dev->sc_msg[5] = sbic_max_offset; 1110 1111 if (sbicxfstart(regs, 6, MESG_OUT_PHASE, sbic_cmd_wait)) 1112 sbicxfout(regs, 6, dev->sc_msg, MESG_OUT_PHASE); 1113 1114 dev->sc_sync[id].state = SYNC_SENT; 1115 #ifdef DEBUG 1116 if (sync_debug) 1117 printf ("sent\n"); 1118 #endif 1119 } 1120 1121 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0); 1122 GET_SBIC_csr (regs, csr); 1123 CSR_TRACE('y',csr,asr,target); 1124 QPRINTF(("[%02x]", csr)); 1125 #ifdef DEBUG 1126 if (sync_debug && dev->sc_sync[id].state == SYNC_SENT) 1127 printf("csr-result of last msgout: 0x%x\n", csr); 1128 #endif 1129 1130 if (csr != SBIC_CSR_SEL_TIMEO) 1131 dev->sc_flags |= SBICF_SELECTED; 1132 } 1133 if (csr == SBIC_CSR_SEL_TIMEO) 1134 dev->sc_xs->error = XS_SELTIMEOUT; 1135 1136 QPRINTF(("\n")); 1137 1138 SBIC_TRACE(dev); 1139 return(csr == SBIC_CSR_SEL_TIMEO); 1140 } 1141 1142 int 1143 sbicxfstart(regs, len, phase, wait) 1144 sbic_regmap_t regs; 1145 int len, wait; 1146 u_char phase; 1147 { 1148 u_char id; 1149 1150 switch (phase) { 1151 case DATA_IN_PHASE: 1152 case MESG_IN_PHASE: 1153 GET_SBIC_selid (regs, id); 1154 id |= SBIC_SID_FROM_SCSI; 1155 SET_SBIC_selid (regs, id); 1156 SBIC_TC_PUT (regs, (unsigned)len); 1157 break; 1158 case DATA_OUT_PHASE: 1159 case MESG_OUT_PHASE: 1160 case CMD_PHASE: 1161 GET_SBIC_selid (regs, id); 1162 id &= ~SBIC_SID_FROM_SCSI; 1163 SET_SBIC_selid (regs, id); 1164 SBIC_TC_PUT (regs, (unsigned)len); 1165 break; 1166 default: 1167 SBIC_TC_PUT (regs, 0); 1168 } 1169 QPRINTF(("sbicxfstart %d, %d, %d\n", len, phase, wait)); 1170 1171 return(1); 1172 } 1173 1174 int 1175 sbicxfout(regs, len, bp, phase) 1176 sbic_regmap_t regs; 1177 int len; 1178 void *bp; 1179 int phase; 1180 { 1181 u_char orig_csr, asr, *buf; 1182 int wait; 1183 1184 buf = bp; 1185 wait = sbic_data_wait; 1186 1187 QPRINTF(("sbicxfout {%d} %02x %02x %02x %02x %02x " 1188 "%02x %02x %02x %02x %02x\n", len, buf[0], buf[1], buf[2], 1189 buf[3], buf[4], buf[5], buf[6], buf[7], buf[8], buf[9])); 1190 1191 GET_SBIC_csr (regs, orig_csr); 1192 CSR_TRACE('>',orig_csr,0,0); 1193 1194 /* 1195 * sigh.. WD-PROTO strikes again.. sending the command in one go 1196 * causes the chip to lock up if talking to certain (misbehaving?) 1197 * targets. Anyway, this procedure should work for all targets, but 1198 * it's slightly slower due to the overhead 1199 */ 1200 WAIT_CIP (regs); 1201 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1202 for (;len > 0; len--) { 1203 GET_SBIC_asr (regs, asr); 1204 while ((asr & SBIC_ASR_DBR) == 0) { 1205 if ((asr & SBIC_ASR_INT) || --wait < 0) { 1206 #ifdef DEBUG 1207 if (sbic_debug) 1208 printf("sbicxfout fail: l%d i%x w%d\n", 1209 len, asr, wait); 1210 #endif 1211 return (len); 1212 } 1213 /* DELAY(1);*/ 1214 GET_SBIC_asr (regs, asr); 1215 } 1216 1217 SET_SBIC_data (regs, *buf); 1218 buf++; 1219 } 1220 SBIC_TC_GET(regs, len); 1221 QPRINTF(("sbicxfout done %d bytes\n", len)); 1222 /* 1223 * this leaves with one csr to be read 1224 */ 1225 return(0); 1226 } 1227 1228 /* returns # bytes left to read */ 1229 int 1230 sbicxfin(regs, len, bp) 1231 sbic_regmap_t regs; 1232 int len; 1233 void *bp; 1234 { 1235 int wait; 1236 u_char *obp, *buf; 1237 u_char orig_csr, csr, asr; 1238 1239 wait = sbic_data_wait; 1240 obp = bp; 1241 buf = bp; 1242 1243 GET_SBIC_csr (regs, orig_csr); 1244 CSR_TRACE('<',orig_csr,0,0); 1245 1246 QPRINTF(("sbicxfin %d, csr=%02x\n", len, orig_csr)); 1247 1248 WAIT_CIP (regs); 1249 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1250 for (;len > 0; len--) { 1251 GET_SBIC_asr (regs, asr); 1252 if((asr & SBIC_ASR_PE)) { 1253 #ifdef DEBUG 1254 printf("sbicxfin parity error: l%d i%x w%d\n", 1255 len, asr, wait); 1256 /* return ((unsigned long)buf - (unsigned long)bp); */ 1257 #ifdef DDB 1258 Debugger(); 1259 #endif 1260 #endif 1261 } 1262 while ((asr & SBIC_ASR_DBR) == 0) { 1263 if ((asr & SBIC_ASR_INT) || --wait < 0) { 1264 #ifdef DEBUG 1265 if (sbic_debug) { 1266 QPRINTF(("sbicxfin fail:{%d} %02x %02x %02x %02x %02x %02x " 1267 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1268 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1269 printf("sbicxfin fail: l%d i%x w%d\n", 1270 len, asr, wait); 1271 } 1272 #endif 1273 return len; 1274 } 1275 1276 if( ! asr & SBIC_ASR_BSY ) { 1277 GET_SBIC_csr(regs, csr); 1278 CSR_TRACE('<',csr,asr,len); 1279 QPRINTF(("[CSR%02xASR%02x]", csr, asr)); 1280 } 1281 1282 /* DELAY(1);*/ 1283 GET_SBIC_asr (regs, asr); 1284 } 1285 1286 GET_SBIC_data (regs, *buf); 1287 /* QPRINTF(("asr=%02x, csr=%02x, data=%02x\n", asr, csr, *buf));*/ 1288 buf++; 1289 } 1290 1291 QPRINTF(("sbicxfin {%d} %02x %02x %02x %02x %02x %02x " 1292 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1293 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1294 1295 /* this leaves with one csr to be read */ 1296 return len; 1297 } 1298 1299 /* 1300 * SCSI 'immediate' command: issue a command to some SCSI device 1301 * and get back an 'immediate' response (i.e., do programmed xfer 1302 * to get the response data). 'cbuf' is a buffer containing a scsi 1303 * command of length clen bytes. 'buf' is a buffer of length 'len' 1304 * bytes for data. The transfer direction is determined by the device 1305 * (i.e., by the scsi bus data xfer phase). If 'len' is zero, the 1306 * command must supply no data. 1307 */ 1308 int 1309 sbicicmd(dev, target, lun, cbuf, clen, buf, len) 1310 struct sbic_softc *dev; 1311 void *cbuf, *buf; 1312 int clen, len; 1313 { 1314 sbic_regmap_t regs; 1315 u_char phase, csr, asr; 1316 int wait, i; 1317 struct sbic_acb *acb; 1318 1319 #define CSR_LOG_BUF_SIZE 0 1320 #if CSR_LOG_BUF_SIZE 1321 int bufptr; 1322 int csrbuf[CSR_LOG_BUF_SIZE]; 1323 bufptr=0; 1324 #endif 1325 1326 SBIC_TRACE(dev); 1327 regs = dev->sc_sbic; 1328 acb = dev->sc_nexus; 1329 1330 /* Make sure pointers are OK */ 1331 dev->sc_last = dev->sc_cur = &acb->sc_pa; 1332 dev->sc_tcnt = acb->sc_tcnt = 0; 1333 acb->sc_pa.dc_count = 0; /* No DMA */ 1334 acb->sc_kv.dc_addr = buf; 1335 acb->sc_kv.dc_count = len; 1336 1337 #ifdef DEBUG 1338 routine = 3; 1339 debug_sbic_regs = regs; /* store this to allow debug calls */ 1340 if( data_pointer_debug > 1 ) 1341 printf("sbicicmd(%d,%d):%d\n", target, lun, 1342 acb->sc_kv.dc_count); 1343 #endif 1344 1345 /* 1346 * set the sbic into non-DMA mode 1347 */ 1348 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI /*| SBIC_CTL_HSP*/); 1349 1350 dev->sc_stat[0] = 0xff; 1351 dev->sc_msg[0] = 0xff; 1352 i = 1; /* pre-load */ 1353 1354 /* We're stealing the SCSI bus */ 1355 dev->sc_flags |= SBICF_ICMD; 1356 1357 do { 1358 /* 1359 * select the SCSI bus (it's an error if bus isn't free) 1360 */ 1361 if (!( dev->sc_flags & SBICF_SELECTED ) 1362 && sbicselectbus(dev, regs, target, lun, dev->sc_scsiaddr)) { 1363 /* printf("sbicicmd: trying to select busy bus!\n"); */ 1364 dev->sc_flags &= ~SBICF_ICMD; 1365 return(-1); 1366 } 1367 1368 /* 1369 * Wait for a phase change (or error) then let the device sequence 1370 * us through the various SCSI phases. 1371 */ 1372 1373 wait = sbic_cmd_wait; 1374 1375 asr = GET_SBIC_asr (regs, asr); 1376 GET_SBIC_csr (regs, csr); 1377 CSR_TRACE('I',csr,asr,target); 1378 QPRINTF((">ASR:%02xCSR:%02x<", asr, csr)); 1379 1380 #if CSR_LOG_BUF_SIZE 1381 csrbuf[bufptr++] = csr; 1382 #endif 1383 1384 1385 switch (csr) { 1386 case SBIC_CSR_S_XFERRED: 1387 case SBIC_CSR_DISC: 1388 case SBIC_CSR_DISC_1: 1389 dev->sc_flags &= ~SBICF_SELECTED; 1390 GET_SBIC_cmd_phase (regs, phase); 1391 if (phase == 0x60) { 1392 GET_SBIC_tlun (regs, dev->sc_stat[0]); 1393 i = 0; /* done */ 1394 /* break; */ /* Bypass all the state gobldygook */ 1395 } else { 1396 #ifdef DEBUG 1397 if(reselect_debug>1) 1398 printf("sbicicmd: handling disconnect\n"); 1399 #endif 1400 i = SBIC_STATE_DISCONNECT; 1401 } 1402 break; 1403 1404 case SBIC_CSR_XFERRED|CMD_PHASE: 1405 case SBIC_CSR_MIS|CMD_PHASE: 1406 case SBIC_CSR_MIS_1|CMD_PHASE: 1407 case SBIC_CSR_MIS_2|CMD_PHASE: 1408 if (sbicxfstart(regs, clen, CMD_PHASE, sbic_cmd_wait)) 1409 if (sbicxfout(regs, clen, 1410 cbuf, CMD_PHASE)) 1411 i = sbicabort(dev, regs,"icmd sending cmd"); 1412 #if 0 1413 GET_SBIC_csr(regs, csr); /* Lets us reload tcount */ 1414 WAIT_CIP(regs); 1415 GET_SBIC_asr(regs, asr); 1416 CSR_TRACE('I',csr,asr,target); 1417 if( asr & (SBIC_ASR_BSY|SBIC_ASR_LCI|SBIC_ASR_CIP) ) 1418 printf("next: cmd sent asr %02x, csr %02x\n", 1419 asr, csr); 1420 #endif 1421 break; 1422 1423 #if 0 1424 case SBIC_CSR_XFERRED|DATA_OUT_PHASE: 1425 case SBIC_CSR_XFERRED|DATA_IN_PHASE: 1426 case SBIC_CSR_MIS|DATA_OUT_PHASE: 1427 case SBIC_CSR_MIS|DATA_IN_PHASE: 1428 case SBIC_CSR_MIS_1|DATA_OUT_PHASE: 1429 case SBIC_CSR_MIS_1|DATA_IN_PHASE: 1430 case SBIC_CSR_MIS_2|DATA_OUT_PHASE: 1431 case SBIC_CSR_MIS_2|DATA_IN_PHASE: 1432 if (acb->sc_kv.dc_count <= 0) 1433 i = sbicabort(dev, regs, "icmd out of data"); 1434 else { 1435 wait = sbic_data_wait; 1436 if (sbicxfstart(regs, 1437 acb->sc_kv.dc_count, 1438 SBIC_PHASE(csr), wait)) 1439 if (csr & 0x01) 1440 /* data in? */ 1441 i=sbicxfin(regs, 1442 acb->sc_kv.dc_count, 1443 acb->sc_kv.dc_addr); 1444 else 1445 i=sbicxfout(regs, 1446 acb->sc_kv.dc_count, 1447 acb->sc_kv.dc_addr, 1448 SBIC_PHASE(csr)); 1449 acb->sc_kv.dc_addr += 1450 (acb->sc_kv.dc_count - i); 1451 acb->sc_kv.dc_count = i; 1452 i = 1; 1453 } 1454 break; 1455 1456 #endif 1457 case SBIC_CSR_XFERRED|STATUS_PHASE: 1458 case SBIC_CSR_MIS|STATUS_PHASE: 1459 case SBIC_CSR_MIS_1|STATUS_PHASE: 1460 case SBIC_CSR_MIS_2|STATUS_PHASE: 1461 /* 1462 * the sbic does the status/cmd-complete reading ok, 1463 * so do this with its hi-level commands. 1464 */ 1465 #ifdef DEBUG 1466 if(sbic_debug) 1467 printf("SBICICMD status phase\n"); 1468 #endif 1469 SBIC_TC_PUT(regs, 0); 1470 SET_SBIC_cmd_phase(regs, 0x46); 1471 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1472 break; 1473 1474 #if THIS_IS_A_RESERVED_STATE 1475 case BUS_FREE_PHASE: /* This is not legal */ 1476 if( dev->sc_stat[0] != 0xff ) 1477 goto out; 1478 break; 1479 #endif 1480 1481 default: 1482 i = sbicnextstate(dev, csr, asr); 1483 } 1484 1485 /* 1486 * make sure the last command was taken, 1487 * ie. we're not hunting after an ignored command.. 1488 */ 1489 GET_SBIC_asr(regs, asr); 1490 1491 /* tapes may take a loooong time.. */ 1492 while (asr & SBIC_ASR_BSY){ 1493 if(asr & SBIC_ASR_DBR) { 1494 printf("sbicicmd: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", 1495 csr,asr); 1496 #ifdef DDB 1497 Debugger(); 1498 #endif 1499 /* SBIC is jammed */ 1500 /* DUNNO which direction */ 1501 /* Try old direction */ 1502 GET_SBIC_data(regs,i); 1503 GET_SBIC_asr(regs, asr); 1504 if( asr & SBIC_ASR_DBR) /* Wants us to write */ 1505 SET_SBIC_data(regs,i); 1506 } 1507 GET_SBIC_asr(regs, asr); 1508 } 1509 1510 /* 1511 * wait for last command to complete 1512 */ 1513 if (asr & SBIC_ASR_LCI) { 1514 printf("sbicicmd: last command ignored\n"); 1515 } 1516 else if( i == 1 ) /* Bsy */ 1517 SBIC_WAIT (regs, SBIC_ASR_INT, wait); 1518 1519 /* 1520 * do it again 1521 */ 1522 } while ( i > 0 && dev->sc_stat[0] == 0xff); 1523 1524 /* Sometimes we need to do an extra read of the CSR */ 1525 GET_SBIC_csr(regs, csr); 1526 CSR_TRACE('I',csr,asr,0xff); 1527 1528 #if CSR_LOG_BUF_SIZE 1529 if(reselect_debug>1) 1530 for(i=0; i<bufptr; i++) 1531 printf("CSR:%02x", csrbuf[i]); 1532 #endif 1533 1534 #ifdef DEBUG 1535 if(data_pointer_debug > 1) 1536 printf("sbicicmd done(%d,%d):%d =%d=\n", 1537 dev->target, lun, 1538 acb->sc_kv.dc_count, 1539 dev->sc_stat[0]); 1540 #endif 1541 1542 QPRINTF(("=STS:%02x=", dev->sc_stat[0])); 1543 dev->sc_flags &= ~SBICF_ICMD; 1544 1545 SBIC_TRACE(dev); 1546 return(dev->sc_stat[0]); 1547 } 1548 1549 /* 1550 * Finish SCSI xfer command: After the completion interrupt from 1551 * a read/write operation, sequence through the final phases in 1552 * programmed i/o. This routine is a lot like sbicicmd except we 1553 * skip (and don't allow) the select, cmd out and data in/out phases. 1554 */ 1555 void 1556 sbicxfdone(dev, regs, target) 1557 struct sbic_softc *dev; 1558 sbic_regmap_t regs; 1559 int target; 1560 { 1561 u_char phase, asr, csr; 1562 int s; 1563 1564 SBIC_TRACE(dev); 1565 QPRINTF(("{")); 1566 s = splbio(); 1567 1568 /* 1569 * have the sbic complete on its own 1570 */ 1571 SBIC_TC_PUT(regs, 0); 1572 SET_SBIC_cmd_phase(regs, 0x46); 1573 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1574 1575 do { 1576 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0); 1577 GET_SBIC_csr (regs, csr); 1578 CSR_TRACE('f',csr,asr,target); 1579 QPRINTF(("%02x:", csr)); 1580 } while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) 1581 && (csr != SBIC_CSR_S_XFERRED)); 1582 1583 dev->sc_flags &= ~SBICF_SELECTED; 1584 1585 GET_SBIC_cmd_phase (regs, phase); 1586 QPRINTF(("}%02x", phase)); 1587 if (phase == 0x60) 1588 GET_SBIC_tlun(regs, dev->sc_stat[0]); 1589 else 1590 sbicerror(dev, regs, csr); 1591 1592 QPRINTF(("=STS:%02x=\n", dev->sc_stat[0])); 1593 splx(s); 1594 SBIC_TRACE(dev); 1595 } 1596 1597 /* 1598 * No DMA chains 1599 */ 1600 1601 int 1602 sbicgo(dev, xs) 1603 struct sbic_softc *dev; 1604 struct scsipi_xfer *xs; 1605 { 1606 int i, dmaflags, count, usedma; 1607 u_char csr, asr, *addr; 1608 sbic_regmap_t regs; 1609 struct sbic_acb *acb; 1610 1611 SBIC_TRACE(dev); 1612 dev->target = xs->xs_periph->periph_target; 1613 dev->lun = xs->xs_periph->periph_lun; 1614 acb = dev->sc_nexus; 1615 regs = dev->sc_sbic; 1616 1617 usedma = sbicdmaok(dev, xs); 1618 #ifdef DEBUG 1619 routine = 1; 1620 debug_sbic_regs = regs; /* store this to allow debug calls */ 1621 if( data_pointer_debug > 1 ) 1622 printf("sbicgo(%d,%d)\n", dev->target, dev->lun); 1623 #endif 1624 1625 /* 1626 * set the sbic into DMA mode 1627 */ 1628 if( usedma ) 1629 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI | 1630 SBIC_MACHINE_DMA_MODE); 1631 else 1632 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1633 1634 1635 /* 1636 * select the SCSI bus (it's an error if bus isn't free) 1637 */ 1638 if (sbicselectbus(dev, regs, dev->target, dev->lun, 1639 dev->sc_scsiaddr)) { 1640 /* printf("sbicgo: Trying to select busy bus!\n"); */ 1641 SBIC_TRACE(dev); 1642 return(0); /* Not done: needs to be rescheduled */ 1643 } 1644 dev->sc_stat[0] = 0xff; 1645 1646 /* 1647 * Calculate DMA chains now 1648 */ 1649 1650 dmaflags = 0; 1651 if (acb->flags & ACB_DATAIN) 1652 dmaflags |= DMAGO_READ; 1653 1654 1655 /* 1656 * Deal w/bounce buffers. 1657 */ 1658 1659 addr = acb->sc_kv.dc_addr; 1660 count = acb->sc_kv.dc_count; 1661 if (count && (char *)kvtop(addr) != acb->sc_pa.dc_addr) { /* XXXX check */ 1662 printf("sbic: DMA buffer mapping changed %p->%x\n", 1663 acb->sc_pa.dc_addr, kvtop(addr)); 1664 #ifdef DDB 1665 Debugger(); 1666 #endif 1667 } 1668 1669 #ifdef DEBUG 1670 ++sbicdma_ops; /* count total DMA operations */ 1671 #endif 1672 if (count && usedma && dev->sc_flags & SBICF_BADDMA && 1673 sbiccheckdmap(addr, count, dev->sc_dmamask)) { 1674 /* 1675 * need to bounce the dma. 1676 */ 1677 if (dmaflags & DMAGO_READ) { 1678 acb->flags |= ACB_BBUF; 1679 acb->sc_dmausrbuf = addr; 1680 acb->sc_dmausrlen = count; 1681 acb->sc_usrbufpa = (u_char *)kvtop(addr); 1682 if(!dev->sc_tinfo[dev->target].bounce) { 1683 printf("sbicgo: HELP! no bounce allocated for %d\n", 1684 dev->target); 1685 printf("xfer: (%p->%p,%lx)\n", acb->sc_dmausrbuf, 1686 acb->sc_usrbufpa, acb->sc_dmausrlen); 1687 dev->sc_tinfo[xs->xs_periph->periph_target].bounce 1688 = (char *)alloc_z2mem(MAXPHYS); 1689 if (isztwomem(dev->sc_tinfo[xs->xs_periph->periph_target].bounce)) 1690 printf("alloc ZII target %d bounce pa 0x%x\n", 1691 xs->xs_periph->periph_target, 1692 kvtop(dev->sc_tinfo[xs->xs_periph->periph_target].bounce)); 1693 else if (dev->sc_tinfo[xs->xs_periph->periph_target].bounce) 1694 printf("alloc CHIP target %d bounce pa 0x%p\n", 1695 xs->xs_periph->periph_target, 1696 PREP_DMA_MEM(dev->sc_tinfo[xs->xs_periph->periph_target].bounce)); 1697 1698 printf("Allocating %d bounce at %x\n", 1699 dev->target, 1700 kvtop(dev->sc_tinfo[dev->target].bounce)); 1701 } 1702 } else { /* write: copy to dma buffer */ 1703 #ifdef DEBUG 1704 if(data_pointer_debug) 1705 printf("sbicgo: copying %x bytes to target %d bounce %x\n", 1706 count, dev->target, 1707 kvtop(dev->sc_tinfo[dev->target].bounce)); 1708 #endif 1709 bcopy (addr, dev->sc_tinfo[dev->target].bounce, count); 1710 } 1711 addr = dev->sc_tinfo[dev->target].bounce;/* and use dma buffer */ 1712 acb->sc_kv.dc_addr = addr; 1713 #ifdef DEBUG 1714 ++sbicdma_bounces; /* count number of bounced */ 1715 #endif 1716 } 1717 1718 /* 1719 * Allocate the DMA chain 1720 */ 1721 1722 /* Set start KVM addresses */ 1723 #if 0 1724 acb->sc_kv.dc_addr = addr; 1725 acb->sc_kv.dc_count = count; 1726 #endif 1727 1728 /* Mark end of segment */ 1729 acb->sc_tcnt = dev->sc_tcnt = 0; 1730 acb->sc_pa.dc_count = 0; 1731 1732 sbic_load_ptrs(dev, regs, dev->target, dev->lun); 1733 SBIC_TRACE(dev); 1734 /* Enable interrupts but don't do any DMA */ 1735 dev->sc_enintr(dev); 1736 if (usedma) { 1737 dev->sc_tcnt = dev->sc_dmago(dev, acb->sc_pa.dc_addr, 1738 acb->sc_pa.dc_count, 1739 dmaflags); 1740 #ifdef DEBUG 1741 dev->sc_dmatimo = dev->sc_tcnt ? 1 : 0; 1742 #endif 1743 } else 1744 dev->sc_dmacmd = 0; /* Don't use DMA */ 1745 dev->sc_flags |= SBICF_INDMA; 1746 /* SBIC_TC_PUT(regs, dev->sc_tcnt); */ /* XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX */ 1747 SBIC_TRACE(dev); 1748 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 1749 1750 /* 1751 * push the data cache ( I think this won't work (EH)) 1752 */ 1753 #if defined(M68040) || defined(M68060) 1754 if (mmutype == MMU_68040 && usedma && count) { 1755 dma_cachectl(addr, count); 1756 if (((u_int)addr & 0xF) || (((u_int)addr + count) & 0xF)) 1757 dev->sc_flags |= SBICF_DCFLUSH; 1758 } 1759 #endif 1760 1761 /* 1762 * enintr() also enables interrupts for the sbic 1763 */ 1764 #ifdef DEBUG 1765 if( data_pointer_debug > 1 ) 1766 printf("sbicgo dmago:%d(%p:%lx)\n", 1767 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 1768 #if 0 1769 /* 1770 * Hmm - this isn't right: asr and csr haven't been set yet. 1771 */ 1772 debug_asr = asr; 1773 debug_csr = csr; 1774 #endif 1775 #endif 1776 1777 /* 1778 * Lets cycle a while then let the interrupt handler take over 1779 */ 1780 1781 asr = GET_SBIC_asr(regs, asr); 1782 do { 1783 GET_SBIC_csr(regs, csr); 1784 CSR_TRACE('g',csr,asr,dev->target); 1785 #ifdef DEBUG 1786 debug_csr = csr; 1787 routine = 1; 1788 #endif 1789 QPRINTF(("go[0x%x]", csr)); 1790 1791 i = sbicnextstate(dev, csr, asr); 1792 1793 WAIT_CIP(regs); 1794 GET_SBIC_asr(regs, asr); 1795 #ifdef DEBUG 1796 debug_asr = asr; 1797 #endif 1798 if(asr & SBIC_ASR_LCI) printf("sbicgo: LCI asr:%02x csr:%02x\n", 1799 asr,csr); 1800 } while( i == SBIC_STATE_RUNNING 1801 && asr & (SBIC_ASR_INT|SBIC_ASR_LCI) ); 1802 1803 CSR_TRACE('g',csr,asr,i<<4); 1804 SBIC_TRACE(dev); 1805 if (i == SBIC_STATE_DONE && dev->sc_stat[0] == 0xff) printf("sbicgo: done & stat = 0xff\n"); 1806 if (i == SBIC_STATE_DONE && dev->sc_stat[0] != 0xff) { 1807 /* if( i == SBIC_STATE_DONE && dev->sc_stat[0] ) { */ 1808 /* Did we really finish that fast? */ 1809 return 1; 1810 } 1811 return 0; 1812 } 1813 1814 1815 int 1816 sbicintr(dev) 1817 struct sbic_softc *dev; 1818 { 1819 sbic_regmap_t regs; 1820 u_char asr, csr; 1821 int i; 1822 1823 regs = dev->sc_sbic; 1824 1825 /* 1826 * pending interrupt? 1827 */ 1828 GET_SBIC_asr (regs, asr); 1829 if ((asr & SBIC_ASR_INT) == 0) 1830 return(0); 1831 1832 SBIC_TRACE(dev); 1833 do { 1834 GET_SBIC_csr(regs, csr); 1835 CSR_TRACE('i',csr,asr,dev->target); 1836 #ifdef DEBUG 1837 debug_csr = csr; 1838 routine = 2; 1839 #endif 1840 QPRINTF(("intr[0x%x]", csr)); 1841 1842 i = sbicnextstate(dev, csr, asr); 1843 1844 WAIT_CIP(regs); 1845 GET_SBIC_asr(regs, asr); 1846 #ifdef DEBUG 1847 debug_asr = asr; 1848 #endif 1849 #if 0 1850 if(asr & SBIC_ASR_LCI) printf("sbicintr: LCI asr:%02x csr:%02x\n", 1851 asr,csr); 1852 #endif 1853 } while(i == SBIC_STATE_RUNNING && 1854 asr & (SBIC_ASR_INT|SBIC_ASR_LCI)); 1855 CSR_TRACE('i',csr,asr,i<<4); 1856 SBIC_TRACE(dev); 1857 return(1); 1858 } 1859 1860 /* 1861 * Run commands and wait for disconnect 1862 */ 1863 int 1864 sbicpoll(dev) 1865 struct sbic_softc *dev; 1866 { 1867 sbic_regmap_t regs; 1868 u_char asr, csr; 1869 int i; 1870 1871 SBIC_TRACE(dev); 1872 regs = dev->sc_sbic; 1873 1874 do { 1875 GET_SBIC_asr (regs, asr); 1876 #ifdef DEBUG 1877 debug_asr = asr; 1878 #endif 1879 GET_SBIC_csr(regs, csr); 1880 CSR_TRACE('p',csr,asr,dev->target); 1881 #ifdef DEBUG 1882 debug_csr = csr; 1883 routine = 2; 1884 #endif 1885 QPRINTF(("poll[0x%x]", csr)); 1886 1887 i = sbicnextstate(dev, csr, asr); 1888 1889 WAIT_CIP(regs); 1890 GET_SBIC_asr(regs, asr); 1891 /* tapes may take a loooong time.. */ 1892 while (asr & SBIC_ASR_BSY){ 1893 if(asr & SBIC_ASR_DBR) { 1894 printf("sbipoll: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", 1895 csr,asr); 1896 #ifdef DDB 1897 Debugger(); 1898 #endif 1899 /* SBIC is jammed */ 1900 /* DUNNO which direction */ 1901 /* Try old direction */ 1902 GET_SBIC_data(regs,i); 1903 GET_SBIC_asr(regs, asr); 1904 if( asr & SBIC_ASR_DBR) /* Wants us to write */ 1905 SET_SBIC_data(regs,i); 1906 } 1907 GET_SBIC_asr(regs, asr); 1908 } 1909 1910 if(asr & SBIC_ASR_LCI) printf("sbicpoll: LCI asr:%02x csr:%02x\n", 1911 asr,csr); 1912 else if( i == 1 ) /* BSY */ 1913 SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait); 1914 } while(i == SBIC_STATE_RUNNING); 1915 CSR_TRACE('p',csr,asr,i<<4); 1916 SBIC_TRACE(dev); 1917 return(1); 1918 } 1919 1920 /* 1921 * Handle a single msgin 1922 */ 1923 1924 int 1925 sbicmsgin(dev) 1926 struct sbic_softc *dev; 1927 { 1928 sbic_regmap_t regs; 1929 int recvlen; 1930 u_char asr, csr, *tmpaddr; 1931 1932 regs = dev->sc_sbic; 1933 1934 dev->sc_msg[0] = 0xff; 1935 dev->sc_msg[1] = 0xff; 1936 1937 GET_SBIC_asr(regs, asr); 1938 #ifdef DEBUG 1939 if(reselect_debug>1) 1940 printf("sbicmsgin asr=%02x\n", asr); 1941 #endif 1942 1943 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 1944 1945 GET_SBIC_selid (regs, csr); 1946 SET_SBIC_selid (regs, csr | SBIC_SID_FROM_SCSI); 1947 1948 SBIC_TC_PUT(regs, 0); 1949 tmpaddr = dev->sc_msg; 1950 recvlen = 1; 1951 do { 1952 while( recvlen-- ) { 1953 asr = GET_SBIC_asr(regs, asr); 1954 GET_SBIC_csr(regs, csr); 1955 QPRINTF(("sbicmsgin ready to go (csr,asr)=(%02x,%02x)\n", 1956 csr, asr)); 1957 1958 RECV_BYTE(regs, *tmpaddr); 1959 CSR_TRACE('m',csr,asr,*tmpaddr); 1960 #if 1 1961 /* 1962 * get the command completion interrupt, or we 1963 * can't send a new command (LCI) 1964 */ 1965 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1966 GET_SBIC_csr(regs, csr); 1967 CSR_TRACE('X',csr,asr,dev->target); 1968 #else 1969 WAIT_CIP(regs); 1970 do { 1971 GET_SBIC_asr(regs, asr); 1972 csr = 0xff; 1973 GET_SBIC_csr(regs, csr); 1974 CSR_TRACE('X',csr,asr,dev->target); 1975 if( csr == 0xff ) 1976 printf("sbicmsgin waiting: csr %02x asr %02x\n", csr, asr); 1977 } while( csr == 0xff ); 1978 #endif 1979 #ifdef DEBUG 1980 if(reselect_debug>1) 1981 printf("sbicmsgin: got %02x csr %02x asr %02x\n", 1982 *tmpaddr, csr, asr); 1983 #endif 1984 #if do_parity_check 1985 if( asr & SBIC_ASR_PE ) { 1986 printf ("Parity error"); 1987 /* This code simply does not work. */ 1988 WAIT_CIP(regs); 1989 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 1990 WAIT_CIP(regs); 1991 GET_SBIC_asr(regs, asr); 1992 WAIT_CIP(regs); 1993 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 1994 WAIT_CIP(regs); 1995 if( !(asr & SBIC_ASR_LCI) ) 1996 /* Target wants to send garbled msg*/ 1997 continue; 1998 printf("--fixing\n"); 1999 /* loop until a msgout phase occurs on target */ 2000 while(csr & 0x07 != MESG_OUT_PHASE) { 2001 while( asr & SBIC_ASR_BSY && 2002 !(asr & SBIC_ASR_DBR|SBIC_ASR_INT) ) 2003 GET_SBIC_asr(regs, asr); 2004 if( asr & SBIC_ASR_DBR ) 2005 panic("msgin: jammed again!\n"); 2006 GET_SBIC_csr(regs, csr); 2007 CSR_TRACE('e',csr,asr,dev->target); 2008 if( csr & 0x07 != MESG_OUT_PHASE ) { 2009 sbicnextstate(dev, csr, asr); 2010 sbic_save_ptrs(dev, regs, 2011 dev->target, 2012 dev->lun); 2013 } 2014 } 2015 /* Should be msg out by now */ 2016 SEND_BYTE(regs, MSG_PARITY_ERROR); 2017 } 2018 else 2019 #endif 2020 tmpaddr++; 2021 2022 if(recvlen) { 2023 /* Clear ACK */ 2024 WAIT_CIP(regs); 2025 GET_SBIC_asr(regs, asr); 2026 GET_SBIC_csr(regs, csr); 2027 CSR_TRACE('X',csr,asr,dev->target); 2028 QPRINTF(("sbicmsgin pre byte CLR_ACK (csr,asr)=(%02x,%02x)\n", 2029 csr, asr)); 2030 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2031 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2032 } 2033 2034 }; 2035 2036 if(dev->sc_msg[0] == 0xff) { 2037 printf("sbicmsgin: sbic swallowed our message\n"); 2038 break; 2039 } 2040 #ifdef DEBUG 2041 if (sync_debug) 2042 printf("msgin done csr 0x%x asr 0x%x msg 0x%x\n", 2043 csr, asr, dev->sc_msg[0]); 2044 #endif 2045 /* 2046 * test whether this is a reply to our sync 2047 * request 2048 */ 2049 if (MSG_ISIDENTIFY(dev->sc_msg[0])) { 2050 QPRINTF(("IFFY")); 2051 #if 0 2052 /* There is an implied load-ptrs here */ 2053 sbic_load_ptrs(dev, regs, dev->target, dev->lun); 2054 #endif 2055 /* Got IFFY msg -- ack it */ 2056 } else if (dev->sc_msg[0] == MSG_REJECT 2057 && dev->sc_sync[dev->target].state == SYNC_SENT) { 2058 QPRINTF(("REJECT of SYN")); 2059 #ifdef DEBUG 2060 if (sync_debug) 2061 printf("target %d rejected sync, going async\n", 2062 dev->target); 2063 #endif 2064 dev->sc_sync[dev->target].period = sbic_min_period; 2065 dev->sc_sync[dev->target].offset = 0; 2066 dev->sc_sync[dev->target].state = SYNC_DONE; 2067 SET_SBIC_syn(regs, 2068 SBIC_SYN(dev->sc_sync[dev->target].offset, 2069 dev->sc_sync[dev->target].period)); 2070 } else if ((dev->sc_msg[0] == MSG_REJECT)) { 2071 QPRINTF(("REJECT")); 2072 /* 2073 * we'll never REJECt a REJECT message.. 2074 */ 2075 } else if ((dev->sc_msg[0] == MSG_SAVE_DATA_PTR)) { 2076 QPRINTF(("MSG_SAVE_DATA_PTR")); 2077 /* 2078 * don't reject this either. 2079 */ 2080 } else if ((dev->sc_msg[0] == MSG_DISCONNECT)) { 2081 QPRINTF(("DISCONNECT")); 2082 #ifdef DEBUG 2083 if( reselect_debug>1 && dev->sc_msg[0] == MSG_DISCONNECT ) 2084 printf("sbicmsgin: got disconnect msg %s\n", 2085 (dev->sc_flags & SBICF_ICMD)?"rejecting":""); 2086 #endif 2087 if( dev->sc_flags & SBICF_ICMD ) { 2088 /* We're in immediate mode. Prevent disconnects. */ 2089 /* prepare to reject the message, NACK */ 2090 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2091 WAIT_CIP(regs); 2092 } 2093 } else if (dev->sc_msg[0] == MSG_CMD_COMPLETE ) { 2094 QPRINTF(("CMD_COMPLETE")); 2095 /* !! KLUDGE ALERT !! quite a few drives don't seem to 2096 * really like the current way of sending the 2097 * sync-handshake together with the ident-message, and 2098 * they react by sending command-complete and 2099 * disconnecting right after returning the valid sync 2100 * handshake. So, all I can do is reselect the drive, 2101 * and hope it won't disconnect again. I don't think 2102 * this is valid behavior, but I can't help fixing a 2103 * problem that apparently exists. 2104 * 2105 * Note: we should not get here on `normal' command 2106 * completion, as that condition is handled by the 2107 * high-level sel&xfer resume command used to walk 2108 * thru status/cc-phase. 2109 */ 2110 2111 #ifdef DEBUG 2112 if (sync_debug) 2113 printf ("GOT MSG %d! target %d acting weird.." 2114 " waiting for disconnect...\n", 2115 dev->sc_msg[0], dev->target); 2116 #endif 2117 /* Check to see if sbic is handling this */ 2118 GET_SBIC_asr(regs, asr); 2119 if(asr & SBIC_ASR_BSY) 2120 return SBIC_STATE_RUNNING; 2121 2122 /* Let's try this: Assume it works and set status to 00 */ 2123 dev->sc_stat[0] = 0; 2124 } else if (dev->sc_msg[0] == MSG_EXT_MESSAGE 2125 && tmpaddr == &dev->sc_msg[1]) { 2126 QPRINTF(("ExtMSG\n")); 2127 /* Read in whole extended message */ 2128 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2129 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2130 GET_SBIC_asr(regs, asr); 2131 GET_SBIC_csr(regs, csr); 2132 QPRINTF(("CLR ACK asr %02x, csr %02x\n", asr, csr)); 2133 RECV_BYTE(regs, *tmpaddr); 2134 CSR_TRACE('x',csr,asr,*tmpaddr); 2135 /* Wait for command completion IRQ */ 2136 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2137 recvlen = *tmpaddr++; 2138 QPRINTF(("Recving ext msg, asr %02x csr %02x len %02x\n", 2139 asr, csr, recvlen)); 2140 } else if (dev->sc_msg[0] == MSG_EXT_MESSAGE && dev->sc_msg[1] == 3 2141 && dev->sc_msg[2] == MSG_SYNC_REQ) { 2142 QPRINTF(("SYN")); 2143 dev->sc_sync[dev->target].period = 2144 sbicfromscsiperiod(dev, 2145 regs, dev->sc_msg[3]); 2146 dev->sc_sync[dev->target].offset = dev->sc_msg[4]; 2147 dev->sc_sync[dev->target].state = SYNC_DONE; 2148 SET_SBIC_syn(regs, 2149 SBIC_SYN(dev->sc_sync[dev->target].offset, 2150 dev->sc_sync[dev->target].period)); 2151 printf("%s: target %d now synchronous," 2152 " period=%dns, offset=%d.\n", 2153 dev->sc_dev.dv_xname, dev->target, 2154 dev->sc_msg[3] * 4, dev->sc_msg[4]); 2155 } else { 2156 #ifdef DEBUG 2157 if (sbic_debug || sync_debug) 2158 printf ("sbicmsgin: Rejecting message 0x%02x\n", 2159 dev->sc_msg[0]); 2160 #endif 2161 /* prepare to reject the message, NACK */ 2162 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2163 WAIT_CIP(regs); 2164 } 2165 /* Clear ACK */ 2166 WAIT_CIP(regs); 2167 GET_SBIC_asr(regs, asr); 2168 GET_SBIC_csr(regs, csr); 2169 CSR_TRACE('X',csr,asr,dev->target); 2170 QPRINTF(("sbicmsgin pre CLR_ACK (csr,asr)=(%02x,%02x)%d\n", 2171 csr, asr, recvlen)); 2172 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2173 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2174 } 2175 #if 0 2176 while((csr == SBIC_CSR_MSGIN_W_ACK) 2177 || (SBIC_PHASE(csr) == MESG_IN_PHASE)); 2178 #else 2179 while (recvlen>0); 2180 #endif 2181 2182 QPRINTF(("sbicmsgin finished: csr %02x, asr %02x\n",csr, asr)); 2183 2184 /* Should still have one CSR to read */ 2185 return SBIC_STATE_RUNNING; 2186 } 2187 2188 2189 /* 2190 * sbicnextstate() 2191 * return: 2192 * 0 == done 2193 * 1 == working 2194 * 2 == disconnected 2195 * -1 == error 2196 */ 2197 int 2198 sbicnextstate(dev, csr, asr) 2199 struct sbic_softc *dev; 2200 u_char csr, asr; 2201 { 2202 sbic_regmap_t regs; 2203 struct sbic_acb *acb; 2204 int i, newtarget, newlun, wait; 2205 #if 0 2206 unsigned tcnt; 2207 #endif 2208 2209 i = 0; 2210 SBIC_TRACE(dev); 2211 regs = dev->sc_sbic; 2212 acb = dev->sc_nexus; 2213 2214 QPRINTF(("next[%02x,%02x]",asr,csr)); 2215 2216 switch (csr) { 2217 case SBIC_CSR_XFERRED|CMD_PHASE: 2218 case SBIC_CSR_MIS|CMD_PHASE: 2219 case SBIC_CSR_MIS_1|CMD_PHASE: 2220 case SBIC_CSR_MIS_2|CMD_PHASE: 2221 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 2222 if (sbicxfstart(regs, acb->clen, CMD_PHASE, sbic_cmd_wait)) 2223 if (sbicxfout(regs, acb->clen, 2224 &acb->cmd, CMD_PHASE)) 2225 goto abort; 2226 break; 2227 2228 case SBIC_CSR_XFERRED|STATUS_PHASE: 2229 case SBIC_CSR_MIS|STATUS_PHASE: 2230 case SBIC_CSR_MIS_1|STATUS_PHASE: 2231 case SBIC_CSR_MIS_2|STATUS_PHASE: 2232 /* 2233 * this should be the normal i/o completion case. 2234 * get the status & cmd complete msg then let the 2235 * device driver look at what happened. 2236 */ 2237 sbicxfdone(dev,regs,dev->target); 2238 /* 2239 * check for overlapping cache line, flush if so 2240 */ 2241 #if defined(M68040) || defined(M68060) 2242 if (dev->sc_flags & SBICF_DCFLUSH) { 2243 #if 0 2244 printf("sbic: 68040/68060 DMA cache flush needs" 2245 "fixing? %x:%x\n", 2246 dev->sc_xs->data, dev->sc_xs->datalen); 2247 #endif 2248 } 2249 #endif 2250 #ifdef DEBUG 2251 if( data_pointer_debug > 1 ) 2252 printf("next dmastop: %d(%p:%lx)\n", 2253 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 2254 dev->sc_dmatimo = 0; 2255 #endif 2256 dev->sc_dmastop(dev); /* was dmafree */ 2257 if (acb->flags & ACB_BBUF) { 2258 if ((u_char *)kvtop(acb->sc_dmausrbuf) != acb->sc_usrbufpa) 2259 printf("%s: WARNING - buffer mapping changed %p->%x\n", 2260 dev->sc_dev.dv_xname, acb->sc_usrbufpa, 2261 kvtop(acb->sc_dmausrbuf)); 2262 #ifdef DEBUG 2263 if(data_pointer_debug) 2264 printf("sbicgo:copying %lx bytes from target %d bounce %x\n", 2265 acb->sc_dmausrlen, 2266 dev->target, 2267 kvtop(dev->sc_tinfo[dev->target].bounce)); 2268 #endif 2269 bcopy(dev->sc_tinfo[dev->target].bounce, 2270 acb->sc_dmausrbuf, 2271 acb->sc_dmausrlen); 2272 } 2273 dev->sc_flags &= ~(SBICF_INDMA | SBICF_DCFLUSH); 2274 sbic_scsidone(acb, dev->sc_stat[0]); 2275 SBIC_TRACE(dev); 2276 return SBIC_STATE_DONE; 2277 2278 case SBIC_CSR_XFERRED|DATA_OUT_PHASE: 2279 case SBIC_CSR_XFERRED|DATA_IN_PHASE: 2280 case SBIC_CSR_MIS|DATA_OUT_PHASE: 2281 case SBIC_CSR_MIS|DATA_IN_PHASE: 2282 case SBIC_CSR_MIS_1|DATA_OUT_PHASE: 2283 case SBIC_CSR_MIS_1|DATA_IN_PHASE: 2284 case SBIC_CSR_MIS_2|DATA_OUT_PHASE: 2285 case SBIC_CSR_MIS_2|DATA_IN_PHASE: 2286 if( dev->sc_xs->xs_control & XS_CTL_POLL || dev->sc_flags & SBICF_ICMD 2287 || acb->sc_dmacmd == 0 ) { 2288 /* Do PIO */ 2289 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2290 if (acb->sc_kv.dc_count <= 0) { 2291 printf("sbicnextstate:xfer count %d asr%x csr%x\n", 2292 acb->sc_kv.dc_count, asr, csr); 2293 goto abort; 2294 } 2295 wait = sbic_data_wait; 2296 if( sbicxfstart(regs, 2297 acb->sc_kv.dc_count, 2298 SBIC_PHASE(csr), wait)) { 2299 if( SBIC_PHASE(csr) == DATA_IN_PHASE ) 2300 /* data in? */ 2301 i=sbicxfin(regs, 2302 acb->sc_kv.dc_count, 2303 acb->sc_kv.dc_addr); 2304 else 2305 i=sbicxfout(regs, 2306 acb->sc_kv.dc_count, 2307 acb->sc_kv.dc_addr, 2308 SBIC_PHASE(csr)); 2309 } 2310 acb->sc_kv.dc_addr += 2311 (acb->sc_kv.dc_count - i); 2312 acb->sc_kv.dc_count = i; 2313 } else { 2314 if (acb->sc_kv.dc_count <= 0) { 2315 printf("sbicnextstate:xfer count %d asr%x csr%x\n", 2316 acb->sc_kv.dc_count, asr, csr); 2317 goto abort; 2318 } 2319 /* 2320 * do scatter-gather dma 2321 * hacking the controller chip, ouch.. 2322 */ 2323 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI | 2324 SBIC_MACHINE_DMA_MODE); 2325 /* 2326 * set next dma addr and dec count 2327 */ 2328 #if 0 2329 SBIC_TC_GET(regs, tcnt); 2330 dev->sc_cur->dc_count -= ((dev->sc_tcnt - tcnt) >> 1); 2331 dev->sc_cur->dc_addr += (dev->sc_tcnt - tcnt); 2332 dev->sc_tcnt = acb->sc_tcnt = tcnt; 2333 #else 2334 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 2335 sbic_load_ptrs(dev, regs, dev->target, dev->lun); 2336 #endif 2337 #ifdef DEBUG 2338 if( data_pointer_debug > 1 ) 2339 printf("next dmanext: %d(%p:%lx)\n", 2340 dev->target,dev->sc_cur->dc_addr, 2341 dev->sc_tcnt); 2342 dev->sc_dmatimo = 1; 2343 #endif 2344 dev->sc_tcnt = dev->sc_dmanext(dev); 2345 SBIC_TC_PUT(regs, (unsigned)dev->sc_tcnt); 2346 SET_SBIC_cmd(regs, SBIC_CMD_XFER_INFO); 2347 dev->sc_flags |= SBICF_INDMA; 2348 } 2349 break; 2350 2351 case SBIC_CSR_XFERRED|MESG_IN_PHASE: 2352 case SBIC_CSR_MIS|MESG_IN_PHASE: 2353 case SBIC_CSR_MIS_1|MESG_IN_PHASE: 2354 case SBIC_CSR_MIS_2|MESG_IN_PHASE: 2355 SBIC_TRACE(dev); 2356 return sbicmsgin(dev); 2357 2358 case SBIC_CSR_MSGIN_W_ACK: 2359 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); /* Dunno what I'm ACKing */ 2360 printf("Acking unknown msgin CSR:%02x",csr); 2361 break; 2362 2363 case SBIC_CSR_XFERRED|MESG_OUT_PHASE: 2364 case SBIC_CSR_MIS|MESG_OUT_PHASE: 2365 case SBIC_CSR_MIS_1|MESG_OUT_PHASE: 2366 case SBIC_CSR_MIS_2|MESG_OUT_PHASE: 2367 #ifdef DEBUG 2368 if (sync_debug) 2369 printf ("sending REJECT msg to last msg.\n"); 2370 #endif 2371 2372 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 2373 /* 2374 * should only get here on reject, 2375 * since it's always US that 2376 * initiate a sync transfer 2377 */ 2378 SEND_BYTE(regs, MSG_REJECT); 2379 WAIT_CIP(regs); 2380 if( asr & (SBIC_ASR_BSY|SBIC_ASR_LCI|SBIC_ASR_CIP) ) 2381 printf("next: REJECT sent asr %02x\n", asr); 2382 SBIC_TRACE(dev); 2383 return SBIC_STATE_RUNNING; 2384 2385 case SBIC_CSR_DISC: 2386 case SBIC_CSR_DISC_1: 2387 dev->sc_flags &= ~(SBICF_INDMA|SBICF_SELECTED); 2388 2389 /* Try to schedule another target */ 2390 #ifdef DEBUG 2391 if(reselect_debug>1) 2392 printf("sbicnext target %d disconnected\n", dev->target); 2393 #endif 2394 TAILQ_INSERT_HEAD(&dev->nexus_list, acb, chain); 2395 ++dev->sc_tinfo[dev->target].dconns; 2396 dev->sc_nexus = NULL; 2397 dev->sc_xs = NULL; 2398 2399 if( acb->xs->xs_control & XS_CTL_POLL 2400 || (dev->sc_flags & SBICF_ICMD) 2401 || !sbic_parallel_operations ) { 2402 SBIC_TRACE(dev); 2403 return SBIC_STATE_DISCONNECT; 2404 } 2405 sbic_sched(dev); 2406 SBIC_TRACE(dev); 2407 return SBIC_STATE_DISCONNECT; 2408 2409 case SBIC_CSR_RSLT_NI: 2410 case SBIC_CSR_RSLT_IFY: 2411 GET_SBIC_rselid(regs, newtarget); 2412 /* check SBIC_RID_SIV? */ 2413 newtarget &= SBIC_RID_MASK; 2414 if (csr == SBIC_CSR_RSLT_IFY) { 2415 /* Read IFY msg to avoid lockup */ 2416 GET_SBIC_data(regs, newlun); 2417 WAIT_CIP(regs); 2418 newlun &= SBIC_TLUN_MASK; 2419 CSR_TRACE('r',csr,asr,newtarget); 2420 } else { 2421 /* Need to get IFY message */ 2422 for (newlun = 256; newlun; --newlun) { 2423 GET_SBIC_asr(regs, asr); 2424 if (asr & SBIC_ASR_INT) 2425 break; 2426 delay(1); 2427 } 2428 newlun = 0; /* XXXX */ 2429 if ((asr & SBIC_ASR_INT) == 0) { 2430 #ifdef DEBUG 2431 if (reselect_debug) 2432 printf("RSLT_NI - no IFFY message? asr %x\n", asr); 2433 #endif 2434 } else { 2435 GET_SBIC_csr(regs,csr); 2436 CSR_TRACE('n',csr,asr,newtarget); 2437 if (csr == (SBIC_CSR_MIS | MESG_IN_PHASE) || 2438 csr == (SBIC_CSR_MIS_1 | MESG_IN_PHASE) || 2439 csr == (SBIC_CSR_MIS_2 | MESG_IN_PHASE)) { 2440 sbicmsgin(dev); 2441 newlun = dev->sc_msg[0] & 7; 2442 } else { 2443 printf("RSLT_NI - not MESG_IN_PHASE %x\n", 2444 csr); 2445 } 2446 } 2447 } 2448 #ifdef DEBUG 2449 if(reselect_debug>1 || (reselect_debug && csr==SBIC_CSR_RSLT_NI)) 2450 printf("sbicnext: reselect %s from targ %d lun %d\n", 2451 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", 2452 newtarget, newlun); 2453 #endif 2454 if (dev->sc_nexus) { 2455 #ifdef DEBUG 2456 if (reselect_debug > 1) 2457 printf("%s: reselect %s with active command\n", 2458 dev->sc_dev.dv_xname, 2459 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY"); 2460 #ifdef DDB 2461 /* Debugger();*/ 2462 #endif 2463 #endif 2464 TAILQ_INSERT_HEAD(&dev->ready_list, dev->sc_nexus, chain); 2465 dev->sc_tinfo[dev->target].lubusy &= ~(1 << dev->lun); 2466 dev->sc_nexus = NULL; 2467 dev->sc_xs = NULL; 2468 } 2469 /* Reload sync values for this target */ 2470 if (dev->sc_sync[newtarget].state == SYNC_DONE) 2471 SET_SBIC_syn(regs, SBIC_SYN (dev->sc_sync[newtarget].offset, 2472 dev->sc_sync[newtarget].period)); 2473 else 2474 SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period)); 2475 for (acb = dev->nexus_list.tqh_first; acb; 2476 acb = acb->chain.tqe_next) { 2477 if (acb->xs->xs_periph->periph_target != newtarget || 2478 acb->xs->xs_periph->periph_lun != newlun) 2479 continue; 2480 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 2481 dev->sc_nexus = acb; 2482 dev->sc_xs = acb->xs; 2483 dev->sc_flags |= SBICF_SELECTED; 2484 dev->target = newtarget; 2485 dev->lun = newlun; 2486 break; 2487 } 2488 if (acb == NULL) { 2489 printf("%s: reselect %s targ %d not in nexus_list %p\n", 2490 dev->sc_dev.dv_xname, 2491 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", newtarget, 2492 &dev->nexus_list.tqh_first); 2493 panic("bad reselect in sbic"); 2494 } 2495 if (csr == SBIC_CSR_RSLT_IFY) 2496 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2497 break; 2498 2499 default: 2500 abort: 2501 /* 2502 * Something unexpected happened -- deal with it. 2503 */ 2504 printf("sbicnextstate: aborting csr %02x asr %02x\n", csr, asr); 2505 #ifdef DDB 2506 Debugger(); 2507 #endif 2508 #ifdef DEBUG 2509 if( data_pointer_debug > 1 ) 2510 printf("next dmastop: %d(%p:%lx)\n", 2511 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 2512 dev->sc_dmatimo = 0; 2513 #endif 2514 dev->sc_dmastop(dev); 2515 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2516 sbicerror(dev, regs, csr); 2517 sbicabort(dev, regs, "next"); 2518 if (dev->sc_flags & SBICF_INDMA) { 2519 /* 2520 * check for overlapping cache line, flush if so 2521 */ 2522 #if defined(M68040) || defined(M68060) 2523 if (dev->sc_flags & SBICF_DCFLUSH) { 2524 #if 0 2525 printf("sbic: 68040/060 DMA cache flush needs" 2526 "fixing? %x:%x\n", 2527 dev->sc_xs->data, dev->sc_xs->datalen); 2528 #endif 2529 } 2530 #endif 2531 dev->sc_flags &= 2532 ~(SBICF_INDMA | SBICF_DCFLUSH); 2533 #ifdef DEBUG 2534 if( data_pointer_debug > 1 ) 2535 printf("next dmastop: %d(%p:%lx)\n", 2536 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 2537 dev->sc_dmatimo = 0; 2538 #endif 2539 dev->sc_dmastop(dev); 2540 sbic_scsidone(acb, -1); 2541 } 2542 SBIC_TRACE(dev); 2543 return SBIC_STATE_ERROR; 2544 } 2545 2546 SBIC_TRACE(dev); 2547 return(SBIC_STATE_RUNNING); 2548 } 2549 2550 2551 /* 2552 * Check if DMA can not be used with specified buffer 2553 */ 2554 2555 int 2556 sbiccheckdmap(bp, len, mask) 2557 void *bp; 2558 u_long len, mask; 2559 { 2560 u_char *buffer; 2561 u_long phy_buf; 2562 u_long phy_len; 2563 2564 buffer = bp; 2565 2566 if (len == 0) 2567 return(0); 2568 2569 while (len) { 2570 phy_buf = kvtop(buffer); 2571 if (len < (phy_len = NBPG - ((int) buffer & PGOFSET))) 2572 phy_len = len; 2573 if (phy_buf & mask) 2574 return(1); 2575 buffer += phy_len; 2576 len -= phy_len; 2577 } 2578 return(0); 2579 } 2580 2581 int 2582 sbictoscsiperiod(dev, regs, a) 2583 struct sbic_softc *dev; 2584 sbic_regmap_t regs; 2585 int a; 2586 { 2587 unsigned int fs; 2588 2589 /* 2590 * cycle = DIV / (2*CLK) 2591 * DIV = FS+2 2592 * best we can do is 200ns at 20Mhz, 2 cycles 2593 */ 2594 2595 GET_SBIC_myid(regs,fs); 2596 fs = (fs >>6) + 2; /* DIV */ 2597 fs = (fs * 10000) / (dev->sc_clkfreq<<1); /* Cycle, in ns */ 2598 if (a < 2) a = 8; /* map to Cycles */ 2599 return ((fs*a)>>2); /* in 4 ns units */ 2600 } 2601 2602 int 2603 sbicfromscsiperiod(dev, regs, p) 2604 struct sbic_softc *dev; 2605 sbic_regmap_t regs; 2606 int p; 2607 { 2608 register unsigned int fs, ret; 2609 2610 /* Just the inverse of the above */ 2611 2612 GET_SBIC_myid(regs,fs); 2613 fs = (fs >>6) + 2; /* DIV */ 2614 fs = (fs * 10000) / (dev->sc_clkfreq<<1); /* Cycle, in ns */ 2615 2616 ret = p << 2; /* in ns units */ 2617 ret = ret / fs; /* in Cycles */ 2618 if (ret < sbic_min_period) 2619 return(sbic_min_period); 2620 2621 /* verify rounding */ 2622 if (sbictoscsiperiod(dev, regs, ret) < p) 2623 ret++; 2624 return (ret >= 8) ? 0 : ret; 2625 } 2626 2627 #ifdef DEBUG 2628 2629 void 2630 sbicdumpstate() 2631 { 2632 u_char csr, asr; 2633 2634 GET_SBIC_asr(debug_sbic_regs,asr); 2635 GET_SBIC_csr(debug_sbic_regs,csr); 2636 printf("%s: asr:csr(%02x:%02x)->(%02x:%02x)\n", 2637 (routine==1)?"sbicgo": 2638 (routine==2)?"sbicintr": 2639 (routine==3)?"sbicicmd": 2640 (routine==4)?"sbicnext":"unknown", 2641 debug_asr, debug_csr, asr, csr); 2642 2643 } 2644 2645 void 2646 sbictimeout(dev) 2647 struct sbic_softc *dev; 2648 { 2649 int s, asr; 2650 2651 s = splbio(); 2652 if (dev->sc_dmatimo) { 2653 if (dev->sc_dmatimo > 1) { 2654 printf("%s: dma timeout #%d\n", 2655 dev->sc_dev.dv_xname, dev->sc_dmatimo - 1); 2656 GET_SBIC_asr(dev->sc_sbic, asr); 2657 if( asr & SBIC_ASR_INT ) { 2658 /* We need to service a missed IRQ */ 2659 printf("Servicing a missed int:(%02x,%02x)->(%02x,??)\n", 2660 debug_asr, debug_csr, asr); 2661 sbicintr(dev); 2662 } 2663 sbicdumpstate(); 2664 } 2665 dev->sc_dmatimo++; 2666 } 2667 splx(s); 2668 callout_reset(&dev->sc_timo_ch, 30 * hz, 2669 (void *)sbictimeout, dev); 2670 } 2671 2672 void 2673 sbic_dump_acb(acb) 2674 struct sbic_acb *acb; 2675 { 2676 u_char *b = (u_char *) &acb->cmd; 2677 int i; 2678 2679 printf("acb@%p ", acb); 2680 if (acb->xs == NULL) { 2681 printf("<unused>\n"); 2682 return; 2683 } 2684 printf("(%d:%d) flags %2x clen %2d cmd ", 2685 acb->xs->xs_periph->periph_target, 2686 acb->xs->xs_periph->periph_lun, acb->flags, acb->clen); 2687 for (i = acb->clen; i; --i) 2688 printf(" %02x", *b++); 2689 printf("\n"); 2690 printf(" xs: %8p data %8p:%04x ", acb->xs, acb->xs->data, 2691 acb->xs->datalen); 2692 printf("va %8p:%04x ", acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 2693 printf("pa %8p:%04x tcnt %lx\n", acb->sc_pa.dc_addr, acb->sc_pa.dc_count, 2694 acb->sc_tcnt); 2695 } 2696 2697 void 2698 sbic_dump(dev) 2699 struct sbic_softc *dev; 2700 { 2701 sbic_regmap_t regs; 2702 u_char csr, asr; 2703 struct sbic_acb *acb; 2704 int s; 2705 int i; 2706 2707 s = splbio(); 2708 regs = dev->sc_sbic; 2709 #if CSR_TRACE_SIZE 2710 printf("csr trace: "); 2711 i = csr_traceptr; 2712 do { 2713 printf("%c%02x%02x%02x ", csr_trace[i].whr, 2714 csr_trace[i].csr, csr_trace[i].asr, csr_trace[i].xtn); 2715 switch(csr_trace[i].whr) { 2716 case 'g': 2717 printf("go "); break; 2718 case 's': 2719 printf("select "); break; 2720 case 'y': 2721 printf("select+ "); break; 2722 case 'i': 2723 printf("intr "); break; 2724 case 'f': 2725 printf("finish "); break; 2726 case '>': 2727 printf("out "); break; 2728 case '<': 2729 printf("in "); break; 2730 case 'm': 2731 printf("msgin "); break; 2732 case 'x': 2733 printf("msginx "); break; 2734 case 'X': 2735 printf("msginX "); break; 2736 case 'r': 2737 printf("reselect "); break; 2738 case 'I': 2739 printf("icmd "); break; 2740 case 'a': 2741 printf("abort "); break; 2742 default: 2743 printf("? "); 2744 } 2745 switch(csr_trace[i].csr) { 2746 case 0x11: 2747 printf("INITIATOR"); break; 2748 case 0x16: 2749 printf("S_XFERRED"); break; 2750 case 0x20: 2751 printf("MSGIN_ACK"); break; 2752 case 0x41: 2753 printf("DISC"); break; 2754 case 0x42: 2755 printf("SEL_TIMEO"); break; 2756 case 0x80: 2757 printf("RSLT_NI"); break; 2758 case 0x81: 2759 printf("RSLT_IFY"); break; 2760 case 0x85: 2761 printf("DISC_1"); break; 2762 case 0x18: case 0x19: case 0x1a: 2763 case 0x1b: case 0x1e: case 0x1f: 2764 case 0x28: case 0x29: case 0x2a: 2765 case 0x2b: case 0x2e: case 0x2f: 2766 case 0x48: case 0x49: case 0x4a: 2767 case 0x4b: case 0x4e: case 0x4f: 2768 case 0x88: case 0x89: case 0x8a: 2769 case 0x8b: case 0x8e: case 0x8f: 2770 switch(csr_trace[i].csr & 0xf0) { 2771 case 0x10: 2772 printf("DONE_"); break; 2773 case 0x20: 2774 printf("STOP_"); break; 2775 case 0x40: 2776 printf("ERR_"); break; 2777 case 0x80: 2778 printf("REQ_"); break; 2779 } 2780 switch(csr_trace[i].csr & 7) { 2781 case 0: 2782 printf("DATA_OUT"); break; 2783 case 1: 2784 printf("DATA_IN"); break; 2785 case 2: 2786 printf("CMD"); break; 2787 case 3: 2788 printf("STATUS"); break; 2789 case 6: 2790 printf("MSG_OUT"); break; 2791 case 7: 2792 printf("MSG_IN"); break; 2793 default: 2794 printf("invld phs"); 2795 } 2796 break; 2797 default: printf("****"); break; 2798 } 2799 if (csr_trace[i].asr & SBIC_ASR_INT) 2800 printf(" ASR_INT"); 2801 if (csr_trace[i].asr & SBIC_ASR_LCI) 2802 printf(" ASR_LCI"); 2803 if (csr_trace[i].asr & SBIC_ASR_BSY) 2804 printf(" ASR_BSY"); 2805 if (csr_trace[i].asr & SBIC_ASR_CIP) 2806 printf(" ASR_CIP"); 2807 printf("\n"); 2808 i = (i + 1) & (CSR_TRACE_SIZE - 1); 2809 } while (i != csr_traceptr); 2810 #endif 2811 GET_SBIC_asr(regs, asr); 2812 if ((asr & SBIC_ASR_INT) == 0) 2813 GET_SBIC_csr(regs, csr); 2814 else 2815 csr = 0; 2816 printf("%s@%p regs %p/%p asr %x csr %x\n", dev->sc_dev.dv_xname, 2817 dev, regs.sbic_asr_p, regs.sbic_value_p, asr, csr); 2818 if ((acb = dev->free_list.tqh_first)) { 2819 printf("Free list:\n"); 2820 while (acb) { 2821 sbic_dump_acb(acb); 2822 acb = acb->chain.tqe_next; 2823 } 2824 } 2825 if ((acb = dev->ready_list.tqh_first)) { 2826 printf("Ready list:\n"); 2827 while (acb) { 2828 sbic_dump_acb(acb); 2829 acb = acb->chain.tqe_next; 2830 } 2831 } 2832 if ((acb = dev->nexus_list.tqh_first)) { 2833 printf("Nexus list:\n"); 2834 while (acb) { 2835 sbic_dump_acb(acb); 2836 acb = acb->chain.tqe_next; 2837 } 2838 } 2839 if (dev->sc_nexus) { 2840 printf("nexus:\n"); 2841 sbic_dump_acb(dev->sc_nexus); 2842 } 2843 printf("sc_xs %p targ %d lun %d flags %x tcnt %lx dmacmd %x mask %lx\n", 2844 dev->sc_xs, dev->target, dev->lun, dev->sc_flags, dev->sc_tcnt, 2845 dev->sc_dmacmd, dev->sc_dmamask); 2846 for (i = 0; i < 8; ++i) { 2847 if (dev->sc_tinfo[i].cmds > 2) { 2848 printf("tgt %d: cmds %d disc %d lubusy %x\n", 2849 i, dev->sc_tinfo[i].cmds, 2850 dev->sc_tinfo[i].dconns, 2851 dev->sc_tinfo[i].lubusy); 2852 } 2853 } 2854 splx(s); 2855 } 2856 2857 #endif 2858
Indexes created Fri Sep 26 20:09:58 GMT 2025