sbic.c revision 1.45
1 /* $NetBSD: sbic.c,v 1.45 2002/01/26 13:40:59 aymeric Exp $ */ 2 3 /* 4 * Copyright (c) 1994 Christian E. Hopps 5 * Copyright (c) 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * Van Jacobson of Lawrence Berkeley Laboratory. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the University of 22 * California, Berkeley and its contributors. 23 * 4. Neither the name of the University nor the names of its contributors 24 * may be used to endorse or promote products derived from this software 25 * without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 37 * SUCH DAMAGE. 38 * 39 * @(#)scsi.c 7.5 (Berkeley) 5/4/91 40 */ 41 42 /* 43 * AMIGA AMD 33C93 scsi adaptor driver 44 */ 45 46 #include "opt_ddb.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/device.h> 51 #include <sys/kernel.h> /* For hz */ 52 #include <sys/disklabel.h> 53 #include <sys/dkstat.h> 54 #include <sys/buf.h> 55 #include <dev/scsipi/scsi_all.h> 56 #include <dev/scsipi/scsipi_all.h> 57 #include <dev/scsipi/scsiconf.h> 58 #include <uvm/uvm_extern.h> 59 #include <machine/cpu.h> 60 #include <amiga/amiga/device.h> 61 #include <amiga/amiga/custom.h> 62 #include <amiga/amiga/isr.h> 63 #include <amiga/dev/dmavar.h> 64 #include <amiga/dev/sbicreg.h> 65 #include <amiga/dev/sbicvar.h> 66 67 /* These are for bounce buffers */ 68 #include <amiga/amiga/cc.h> 69 #include <amiga/dev/zbusvar.h> 70 71 /* Since I can't find this in any other header files */ 72 #define SCSI_PHASE(reg) (reg&0x07) 73 74 /* 75 * SCSI delays 76 * In u-seconds, primarily for state changes on the SPC. 77 */ 78 #define SBIC_CMD_WAIT 50000 /* wait per step of 'immediate' cmds */ 79 #define SBIC_DATA_WAIT 50000 /* wait per data in/out step */ 80 #define SBIC_INIT_WAIT 50000 /* wait per step (both) during init */ 81 82 #define SBIC_WAIT(regs, until, timeo) sbicwait(regs, until, timeo, __LINE__) 83 84 int sbicicmd(struct sbic_softc *, int, int, void *, int, void *, int); 85 int sbicgo(struct sbic_softc *, struct scsipi_xfer *); 86 int sbicdmaok(struct sbic_softc *, struct scsipi_xfer *); 87 int sbicwait(sbic_regmap_t, char, int , int); 88 int sbiccheckdmap(void *, u_long, u_long); 89 int sbicselectbus(struct sbic_softc *, sbic_regmap_t, u_char, u_char, u_char); 90 int sbicxfstart(sbic_regmap_t, int, u_char, int); 91 int sbicxfout(sbic_regmap_t regs, int, void *, int); 92 int sbicfromscsiperiod(struct sbic_softc *, sbic_regmap_t, int); 93 int sbictoscsiperiod(struct sbic_softc *, sbic_regmap_t, int); 94 int sbicpoll(struct sbic_softc *); 95 int sbicnextstate(struct sbic_softc *, u_char, u_char); 96 int sbicmsgin(struct sbic_softc *); 97 int sbicxfin(sbic_regmap_t regs, int, void *); 98 int sbicabort(struct sbic_softc *, sbic_regmap_t, char *); 99 void sbicxfdone(struct sbic_softc *, sbic_regmap_t, int); 100 void sbicerror(struct sbic_softc *, sbic_regmap_t, u_char); 101 void sbicstart(struct sbic_softc *); 102 void sbicreset(struct sbic_softc *); 103 void sbic_scsidone(struct sbic_acb *, int); 104 void sbic_sched(struct sbic_softc *); 105 void sbic_save_ptrs(struct sbic_softc *, sbic_regmap_t,int,int); 106 void sbic_load_ptrs(struct sbic_softc *, sbic_regmap_t,int,int); 107 #ifdef DEBUG 108 void sbicdumpstate(void); 109 void sbic_dump_acb(struct sbic_acb *); 110 #endif 111 112 /* 113 * Synch xfer parameters, and timing conversions 114 */ 115 int sbic_min_period = SBIC_SYN_MIN_PERIOD; /* in cycles = f(ICLK,FSn) */ 116 int sbic_max_offset = SBIC_SYN_MAX_OFFSET; /* pure number */ 117 118 int sbic_cmd_wait = SBIC_CMD_WAIT; 119 int sbic_data_wait = SBIC_DATA_WAIT; 120 int sbic_init_wait = SBIC_INIT_WAIT; 121 122 /* 123 * was broken before.. now if you want this you get it for all drives 124 * on sbic controllers. 125 */ 126 u_char sbic_inhibit_sync[8]; 127 int sbic_enable_reselect = 1; 128 int sbic_clock_override = 0; 129 int sbic_no_dma = 0; 130 int sbic_parallel_operations = 1; 131 132 #ifdef DEBUG 133 sbic_regmap_t debug_sbic_regs; 134 int sbicdma_ops = 0; /* total DMA operations */ 135 int sbicdma_bounces = 0; /* number operations using bounce buffer */ 136 int sbicdma_hits = 0; /* number of DMA chains that were contiguous */ 137 int sbicdma_misses = 0; /* number of DMA chains that were not contiguous */ 138 int sbicdma_saves = 0; 139 #define QPRINTF(a) if (sbic_debug > 1) printf a 140 int sbic_debug = 0; 141 int sync_debug = 0; 142 int sbic_dma_debug = 0; 143 int reselect_debug = 0; 144 int data_pointer_debug = 0; 145 u_char debug_asr, debug_csr, routine; 146 void sbictimeout(struct sbic_softc *dev); 147 148 #define CSR_TRACE_SIZE 32 149 #if CSR_TRACE_SIZE 150 #define CSR_TRACE(w,c,a,x) do { \ 151 int s = splbio(); \ 152 csr_trace[csr_traceptr].whr = (w); csr_trace[csr_traceptr].csr = (c); \ 153 csr_trace[csr_traceptr].asr = (a); csr_trace[csr_traceptr].xtn = (x); \ 154 dma_cachectl((caddr_t)&csr_trace[csr_traceptr], sizeof(csr_trace[0])); \ 155 csr_traceptr = (csr_traceptr + 1) & (CSR_TRACE_SIZE - 1); \ 156 /* dma_cachectl((caddr_t)&csr_traceptr, sizeof(csr_traceptr));*/ \ 157 splx(s); \ 158 } while (0) 159 int csr_traceptr; 160 int csr_tracesize = CSR_TRACE_SIZE; 161 struct { 162 u_char whr; 163 u_char csr; 164 u_char asr; 165 u_char xtn; 166 } csr_trace[CSR_TRACE_SIZE]; 167 #else 168 #define CSR_TRACE(w,c,a,x) 169 #endif 170 171 #define SBIC_TRACE_SIZE 0 172 #if SBIC_TRACE_SIZE 173 #define SBIC_TRACE(dev) do { \ 174 int s = splbio(); \ 175 sbic_trace[sbic_traceptr].sp = &s; \ 176 sbic_trace[sbic_traceptr].line = __LINE__; \ 177 sbic_trace[sbic_traceptr].sr = s; \ 178 sbic_trace[sbic_traceptr].csr = csr_traceptr; \ 179 dma_cachectl(&sbic_trace[sbic_traceptr], sizeof(sbic_trace[0])); \ 180 sbic_traceptr = (sbic_traceptr + 1) & (SBIC_TRACE_SIZE - 1); \ 181 dma_cachectl(&sbic_traceptr, sizeof(sbic_traceptr)); \ 182 if (dev) dma_cachectl(dev, sizeof(*dev)); \ 183 splx(s); \ 184 } while (0) 185 int sbic_traceptr; 186 int sbic_tracesize = SBIC_TRACE_SIZE; 187 struct { 188 void *sp; 189 u_short line; 190 u_short sr; 191 int csr; 192 } sbic_trace[SBIC_TRACE_SIZE]; 193 #else 194 #define SBIC_TRACE(dev) 195 #endif 196 197 #else /* DEBUG */ 198 #define QPRINTF(a) 199 #define CSR_TRACE(w,c,a,x) 200 #define SBIC_TRACE(dev) 201 #endif /* DEBUG */ 202 203 /* 204 * default minphys routine for sbic based controllers 205 */ 206 void 207 sbic_minphys(struct buf *bp) 208 { 209 210 /* 211 * No max transfer at this level. 212 */ 213 minphys(bp); 214 } 215 216 /* 217 * Save DMA pointers. Take into account partial transfer. Shut down DMA. 218 */ 219 void 220 sbic_save_ptrs(struct sbic_softc *dev, sbic_regmap_t regs, int target, int lun) 221 { 222 int count, asr, s; 223 struct sbic_acb* acb; 224 225 SBIC_TRACE(dev); 226 if( !dev->sc_cur ) return; 227 if( !(dev->sc_flags & SBICF_INDMA) ) return; /* DMA not active */ 228 229 s = splbio(); 230 231 acb = dev->sc_nexus; 232 count = -1; 233 do { 234 GET_SBIC_asr(regs, asr); 235 if( asr & SBIC_ASR_DBR ) { 236 printf("sbic_save_ptrs: asr %02x canceled!\n", asr); 237 splx(s); 238 SBIC_TRACE(dev); 239 return; 240 } 241 } while( asr & (SBIC_ASR_BSY|SBIC_ASR_CIP) ); 242 243 /* Save important state */ 244 /* must be done before dmastop */ 245 acb->sc_dmacmd = dev->sc_dmacmd; 246 SBIC_TC_GET(regs, count); 247 248 /* Shut down DMA ====CAREFUL==== */ 249 dev->sc_dmastop(dev); 250 dev->sc_flags &= ~SBICF_INDMA; 251 SBIC_TC_PUT(regs, 0); 252 253 #ifdef DEBUG 254 if(!count && sbic_debug) printf("%dcount0",target); 255 if(data_pointer_debug == -1) 256 printf("SBIC saving target %d data pointers from (%p,%x)%xASR:%02x", 257 target, dev->sc_cur->dc_addr, dev->sc_cur->dc_count, 258 acb->sc_dmacmd, asr); 259 #endif 260 261 /* Fixup partial xfers */ 262 acb->sc_kv.dc_addr += (dev->sc_tcnt - count); 263 acb->sc_kv.dc_count -= (dev->sc_tcnt - count); 264 acb->sc_pa.dc_addr += (dev->sc_tcnt - count); 265 acb->sc_pa.dc_count -= ((dev->sc_tcnt - count)>>1); 266 267 acb->sc_tcnt = dev->sc_tcnt = count; 268 #ifdef DEBUG 269 if(data_pointer_debug) 270 printf(" at (%p,%x):%x\n", 271 dev->sc_cur->dc_addr, dev->sc_cur->dc_count,count); 272 sbicdma_saves++; 273 #endif 274 splx(s); 275 SBIC_TRACE(dev); 276 } 277 278 279 /* 280 * DOES NOT RESTART DMA!!! 281 */ 282 void 283 sbic_load_ptrs(struct sbic_softc *dev, sbic_regmap_t regs, int target, int lun) 284 { 285 int s, count; 286 char* vaddr, * paddr; 287 struct sbic_acb *acb; 288 289 SBIC_TRACE(dev); 290 acb = dev->sc_nexus; 291 if( !acb->sc_kv.dc_count ) { 292 /* No data to xfer */ 293 SBIC_TRACE(dev); 294 return; 295 } 296 297 s = splbio(); 298 299 dev->sc_last = dev->sc_cur = &acb->sc_pa; 300 dev->sc_tcnt = acb->sc_tcnt; 301 dev->sc_dmacmd = acb->sc_dmacmd; 302 303 #ifdef DEBUG 304 sbicdma_ops++; 305 #endif 306 if( !dev->sc_tcnt ) { 307 /* sc_tcnt == 0 implies end of segment */ 308 309 /* do kvm to pa mappings */ 310 paddr = acb->sc_pa.dc_addr = 311 (char *) kvtop(acb->sc_kv.dc_addr); 312 313 vaddr = acb->sc_kv.dc_addr; 314 count = acb->sc_kv.dc_count; 315 for(count = (NBPG - ((int)vaddr & PGOFSET)); 316 count < acb->sc_kv.dc_count 317 && (char*)kvtop(vaddr + count + 4) == paddr + count + 4; 318 count += NBPG); 319 /* If it's all contiguous... */ 320 if(count > acb->sc_kv.dc_count ) { 321 count = acb->sc_kv.dc_count; 322 #ifdef DEBUG 323 sbicdma_hits++; 324 #endif 325 } else { 326 #ifdef DEBUG 327 sbicdma_misses++; 328 #endif 329 } 330 acb->sc_tcnt = count; 331 acb->sc_pa.dc_count = count >> 1; 332 333 #ifdef DEBUG 334 if(data_pointer_debug) 335 printf("DMA recalc:kv(%p,%x)pa(%p,%lx)\n", 336 acb->sc_kv.dc_addr, 337 acb->sc_kv.dc_count, 338 acb->sc_pa.dc_addr, 339 acb->sc_tcnt); 340 #endif 341 } 342 splx(s); 343 #ifdef DEBUG 344 if(data_pointer_debug) 345 printf("SBIC restoring target %d data pointers at (%p,%x)%x\n", 346 target, dev->sc_cur->dc_addr, dev->sc_cur->dc_count, 347 dev->sc_dmacmd); 348 #endif 349 SBIC_TRACE(dev); 350 } 351 352 /* 353 * used by specific sbic controller 354 * 355 * it appears that the higher level code does nothing with LUN's 356 * so I will too. I could plug it in, however so could they 357 * in scsi_scsipi_cmd(). 358 */ 359 void 360 sbic_scsipi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req, 361 void *arg) 362 { 363 struct scsipi_xfer *xs; 364 struct scsipi_periph *periph; 365 struct sbic_acb *acb; 366 struct sbic_softc *dev = (void *)chan->chan_adapter->adapt_dev; 367 int flags, s, stat; 368 369 switch (req) { 370 case ADAPTER_REQ_RUN_XFER: 371 xs = arg; 372 periph = xs->xs_periph; 373 374 SBIC_TRACE(dev); 375 flags = xs->xs_control; 376 377 if (flags & XS_CTL_DATA_UIO) 378 panic("sbic: scsi data uio requested"); 379 380 if (dev->sc_nexus && flags & XS_CTL_POLL) 381 panic("sbic_scsipi_request: busy"); 382 383 s = splbio(); 384 acb = dev->free_list.tqh_first; 385 if (acb) 386 TAILQ_REMOVE(&dev->free_list, acb, chain); 387 splx(s); 388 389 #ifdef DIAGNOSTIC 390 if (acb == NULL) { 391 scsipi_printaddr(periph); 392 printf("unable to allocate acb\n"); 393 panic("sbic_scsipi_request"); 394 } 395 #endif 396 acb->flags = ACB_ACTIVE; 397 if (flags & XS_CTL_DATA_IN) 398 acb->flags |= ACB_DATAIN; 399 acb->xs = xs; 400 bcopy(xs->cmd, &acb->cmd, xs->cmdlen); 401 acb->clen = xs->cmdlen; 402 acb->sc_kv.dc_addr = xs->data; 403 acb->sc_kv.dc_count = xs->datalen; 404 acb->pa_addr = xs->data ? (char *)kvtop(xs->data) : 0; /* XXXX check */ 405 406 if (flags & XS_CTL_POLL) { 407 s = splbio(); 408 /* 409 * This has major side effects - it locks up the machine 410 */ 411 412 dev->sc_flags |= SBICF_ICMD; 413 do { 414 while(dev->sc_nexus) 415 sbicpoll(dev); 416 dev->sc_nexus = acb; 417 dev->sc_stat[0] = -1; 418 dev->sc_xs = xs; 419 dev->target = periph->periph_target; 420 dev->lun = periph->periph_lun; 421 stat = sbicicmd(dev, dev->target, dev->lun, 422 &acb->cmd, acb->clen, 423 acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 424 } while (dev->sc_nexus != acb); 425 sbic_scsidone(acb, stat); 426 427 splx(s); 428 SBIC_TRACE(dev); 429 return; 430 } 431 432 s = splbio(); 433 TAILQ_INSERT_TAIL(&dev->ready_list, acb, chain); 434 435 if (dev->sc_nexus) { 436 splx(s); 437 SBIC_TRACE(dev); 438 return; 439 } 440 441 /* 442 * nothing is active, try to start it now. 443 */ 444 sbic_sched(dev); 445 splx(s); 446 447 SBIC_TRACE(dev); 448 /* TODO: add sbic_poll to do XS_CTL_POLL operations */ 449 #if 0 450 if (flags & XS_CTL_POLL) 451 return(COMPLETE); 452 #endif 453 return; 454 455 case ADAPTER_REQ_GROW_RESOURCES: 456 return; 457 458 case ADAPTER_REQ_SET_XFER_MODE: 459 return; 460 } 461 } 462 463 /* 464 * attempt to start the next available command 465 */ 466 void 467 sbic_sched(struct sbic_softc *dev) 468 { 469 struct scsipi_xfer *xs; 470 struct scsipi_periph *periph; 471 struct sbic_acb *acb; 472 int flags, /*phase,*/ stat, i; 473 474 SBIC_TRACE(dev); 475 if (dev->sc_nexus) 476 return; /* a command is current active */ 477 478 SBIC_TRACE(dev); 479 for (acb = dev->ready_list.tqh_first; acb; acb = acb->chain.tqe_next) { 480 periph = acb->xs->xs_periph; 481 i = periph->periph_target; 482 if (!(dev->sc_tinfo[i].lubusy & (1 << periph->periph_lun))) { 483 struct sbic_tinfo *ti = &dev->sc_tinfo[i]; 484 485 TAILQ_REMOVE(&dev->ready_list, acb, chain); 486 dev->sc_nexus = acb; 487 ti = &dev->sc_tinfo[periph->periph_target]; 488 ti->lubusy |= (1 << periph->periph_lun); 489 acb->sc_pa.dc_addr = acb->pa_addr; /* XXXX check */ 490 break; 491 } 492 } 493 494 SBIC_TRACE(dev); 495 if (acb == NULL) 496 return; /* did not find an available command */ 497 498 dev->sc_xs = xs = acb->xs; 499 periph = xs->xs_periph; 500 flags = xs->xs_control; 501 502 if (flags & XS_CTL_RESET) 503 sbicreset(dev); 504 505 #ifdef DEBUG 506 if( data_pointer_debug > 1 ) 507 printf("sbic_sched(%d,%d)\n", periph->periph_target, 508 periph->periph_lun); 509 #endif 510 dev->sc_stat[0] = -1; 511 dev->target = periph->periph_target; 512 dev->lun = periph->periph_lun; 513 if ( flags & XS_CTL_POLL || ( !sbic_parallel_operations 514 && (sbicdmaok(dev, xs) == 0))) 515 stat = sbicicmd(dev, periph->periph_target, 516 periph->periph_lun, &acb->cmd, 517 acb->clen, acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 518 else if (sbicgo(dev, xs) == 0 && xs->error != XS_SELTIMEOUT) { 519 SBIC_TRACE(dev); 520 return; 521 } else 522 stat = dev->sc_stat[0]; 523 524 sbic_scsidone(acb, stat); 525 SBIC_TRACE(dev); 526 } 527 528 void 529 sbic_scsidone(struct sbic_acb *acb, int stat) 530 { 531 struct scsipi_xfer *xs; 532 struct scsipi_periph *periph; 533 struct sbic_softc *dev; 534 int dosched = 0; 535 536 xs = acb->xs; 537 periph = xs->xs_periph; 538 dev = (void *)periph->periph_channel->chan_adapter->adapt_dev; 539 SBIC_TRACE(dev); 540 #ifdef DIAGNOSTIC 541 if (acb == NULL || xs == NULL) { 542 printf("sbic_scsidone -- (%d,%d) no scsi_xfer\n", 543 dev->target, dev->lun); 544 #ifdef DDB 545 Debugger(); 546 #endif 547 return; 548 } 549 #endif 550 551 xs->status = stat; 552 xs->resid = 0; /* XXXX */ 553 #ifdef DEBUG 554 if( data_pointer_debug > 1 ) 555 printf("scsidone: (%d,%d)->(%d,%d)%02x\n", 556 periph->periph_target, periph->periph_lun, 557 dev->target, dev->lun, stat); 558 if( periph->periph_target == 559 periph->periph_channel->chan_id) 560 panic("target == hostid"); 561 #endif 562 563 if (xs->error == XS_NOERROR) { 564 if (stat == SCSI_CHECK || stat == SCSI_BUSY) 565 xs->error = XS_BUSY; 566 } 567 568 /* 569 * Remove the ACB from whatever queue it's on. We have to do a bit of 570 * a hack to figure out which queue it's on. Note that it is *not* 571 * necessary to cdr down the ready queue, but we must cdr down the 572 * nexus queue and see if it's there, so we can mark the unit as no 573 * longer busy. This code is sickening, but it works. 574 */ 575 if (acb == dev->sc_nexus) { 576 dev->sc_nexus = NULL; 577 dev->sc_xs = NULL; 578 dev->sc_tinfo[periph->periph_target].lubusy &= 579 ~(1<<periph->periph_lun); 580 if (dev->ready_list.tqh_first) 581 dosched = 1; /* start next command */ 582 } else if (dev->ready_list.tqh_last == &acb->chain.tqe_next) { 583 TAILQ_REMOVE(&dev->ready_list, acb, chain); 584 } else { 585 register struct sbic_acb *acb2; 586 for (acb2 = dev->nexus_list.tqh_first; acb2; 587 acb2 = acb2->chain.tqe_next) { 588 if (acb2 == acb) { 589 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 590 dev->sc_tinfo[periph->periph_target].lubusy 591 &= ~(1<<periph->periph_lun); 592 break; 593 } 594 } 595 if (acb2) 596 ; 597 else if (acb->chain.tqe_next) { 598 TAILQ_REMOVE(&dev->ready_list, acb, chain); 599 } else { 600 printf("%s: can't find matching acb\n", 601 dev->sc_dev.dv_xname); 602 #ifdef DDB 603 Debugger(); 604 #endif 605 } 606 } 607 /* Put it on the free list. */ 608 acb->flags = ACB_FREE; 609 TAILQ_INSERT_HEAD(&dev->free_list, acb, chain); 610 611 dev->sc_tinfo[periph->periph_target].cmds++; 612 613 scsipi_done(xs); 614 615 if (dosched) 616 sbic_sched(dev); 617 SBIC_TRACE(dev); 618 } 619 620 int 621 sbicdmaok(struct sbic_softc *dev, struct scsipi_xfer *xs) 622 { 623 if (sbic_no_dma || !xs->datalen || xs->datalen & 0x1 || 624 (u_int)xs->data & 0x3) 625 return(0); 626 /* 627 * controller supports dma to any addresses? 628 */ 629 else if ((dev->sc_flags & SBICF_BADDMA) == 0) 630 return(1); 631 /* 632 * this address is ok for dma? 633 */ 634 else if (sbiccheckdmap(xs->data, xs->datalen, dev->sc_dmamask) == 0) 635 return(1); 636 /* 637 * we have a bounce buffer? 638 */ 639 else if (dev->sc_tinfo[xs->xs_periph->periph_target].bounce) 640 return(1); 641 /* 642 * try to get one 643 */ 644 else if ((dev->sc_tinfo[xs->xs_periph->periph_target].bounce 645 = (char *)alloc_z2mem(MAXPHYS))) { 646 if (isztwomem(dev->sc_tinfo[xs->xs_periph->periph_target].bounce)) 647 printf("alloc ZII target %d bounce pa 0x%x\n", 648 xs->xs_periph->periph_target, 649 kvtop(dev->sc_tinfo[xs->xs_periph->periph_target].bounce)); 650 else if (dev->sc_tinfo[xs->xs_periph->periph_target].bounce) 651 printf("alloc CHIP target %d bounce pa 0x%p\n", 652 xs->xs_periph->periph_target, 653 PREP_DMA_MEM(dev->sc_tinfo[xs->xs_periph->periph_target].bounce)); 654 return(1); 655 } 656 657 return(0); 658 } 659 660 661 int 662 sbicwait(sbic_regmap_t regs, char until, int timeo, int line) 663 { 664 u_char val; 665 int csr; 666 667 SBIC_TRACE((struct sbic_softc *)0); 668 if (timeo == 0) 669 timeo = 1000000; /* some large value.. */ 670 671 GET_SBIC_asr(regs,val); 672 while ((val & until) == 0) { 673 if (timeo-- == 0) { 674 GET_SBIC_csr(regs, csr); 675 printf("sbicwait TIMEO @%d with asr=x%x csr=x%x\n", 676 line, val, csr); 677 #if defined(DDB) && defined(DEBUG) 678 Debugger(); 679 #endif 680 return(val); /* Maybe I should abort */ 681 break; 682 } 683 DELAY(1); 684 GET_SBIC_asr(regs,val); 685 } 686 SBIC_TRACE((struct sbic_softc *)0); 687 return(val); 688 } 689 690 int 691 sbicabort(struct sbic_softc *dev, sbic_regmap_t regs, char *where) 692 { 693 u_char csr, asr; 694 695 GET_SBIC_asr(regs, asr); 696 GET_SBIC_csr(regs, csr); 697 698 printf ("%s: abort %s: csr = 0x%02x, asr = 0x%02x\n", 699 dev->sc_dev.dv_xname, where, csr, asr); 700 701 702 #if 0 703 /* Clean up running command */ 704 if (dev->sc_nexus != NULL) { 705 dev->sc_nexus->xs->error = XS_DRIVER_STUFFUP; 706 sbic_scsidone(dev->sc_nexus, dev->sc_stat[0]); 707 } 708 while (acb = dev->nexus_list.tqh_first) { 709 acb->xs->error = XS_DRIVER_STUFFUP; 710 sbic_scsidone(acb, -1 /*acb->stat[0]*/); 711 } 712 #endif 713 714 /* Clean up chip itself */ 715 if (dev->sc_flags & SBICF_SELECTED) { 716 while( asr & SBIC_ASR_DBR ) { 717 /* sbic is jammed w/data. need to clear it */ 718 /* But we don't know what direction it needs to go */ 719 GET_SBIC_data(regs, asr); 720 printf("%s: abort %s: clearing data buffer 0x%02x\n", 721 dev->sc_dev.dv_xname, where, asr); 722 GET_SBIC_asr(regs, asr); 723 if( asr & SBIC_ASR_DBR ) /* Not the read direction, then */ 724 SET_SBIC_data(regs, asr); 725 GET_SBIC_asr(regs, asr); 726 } 727 WAIT_CIP(regs); 728 printf("%s: sbicabort - sending ABORT command\n", dev->sc_dev.dv_xname); 729 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 730 WAIT_CIP(regs); 731 732 GET_SBIC_asr(regs, asr); 733 if (asr & (SBIC_ASR_BSY|SBIC_ASR_LCI)) { 734 /* ok, get more drastic.. */ 735 736 printf("%s: sbicabort - asr %x, trying to reset\n", dev->sc_dev.dv_xname, asr); 737 sbicreset(dev); 738 dev->sc_flags &= ~SBICF_SELECTED; 739 return -1; 740 } 741 printf("%s: sbicabort - sending DISC command\n", dev->sc_dev.dv_xname); 742 SET_SBIC_cmd(regs, SBIC_CMD_DISC); 743 744 do { 745 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0); 746 GET_SBIC_csr (regs, csr); 747 CSR_TRACE('a',csr,asr,0); 748 } while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) 749 && (csr != SBIC_CSR_CMD_INVALID)); 750 751 /* lets just hope it worked.. */ 752 dev->sc_flags &= ~SBICF_SELECTED; 753 } 754 return -1; 755 } 756 757 758 /* 759 * Initialize driver-private structures 760 */ 761 762 void 763 sbicinit(struct sbic_softc *dev) 764 { 765 sbic_regmap_t regs; 766 u_int i; 767 struct sbic_acb *acb; 768 u_int inhibit_sync; 769 770 extern u_long scsi_nosync; 771 extern int shift_nosync; 772 773 regs = dev->sc_sbic; 774 775 if ((dev->sc_flags & SBICF_ALIVE) == 0) { 776 TAILQ_INIT(&dev->ready_list); 777 TAILQ_INIT(&dev->nexus_list); 778 TAILQ_INIT(&dev->free_list); 779 callout_init(&dev->sc_timo_ch); 780 dev->sc_nexus = NULL; 781 dev->sc_xs = NULL; 782 acb = dev->sc_acb; 783 bzero(acb, sizeof(dev->sc_acb)); 784 for (i = 0; i < sizeof(dev->sc_acb) / sizeof(*acb); i++) { 785 TAILQ_INSERT_TAIL(&dev->free_list, acb, chain); 786 acb++; 787 } 788 bzero(dev->sc_tinfo, sizeof(dev->sc_tinfo)); 789 #ifdef DEBUG 790 /* make sure timeout is really not needed */ 791 callout_reset(&dev->sc_timo_ch, 30 * hz, 792 (void *)sbictimeout, dev); 793 #endif 794 795 } else panic("sbic: reinitializing driver!"); 796 797 dev->sc_flags |= SBICF_ALIVE; 798 dev->sc_flags &= ~SBICF_SELECTED; 799 800 /* initialize inhibit array */ 801 if (scsi_nosync) { 802 inhibit_sync = (scsi_nosync >> shift_nosync) & 0xff; 803 shift_nosync += 8; 804 #ifdef DEBUG 805 if (inhibit_sync) 806 printf("%s: Inhibiting synchronous transfer %02x\n", 807 dev->sc_dev.dv_xname, inhibit_sync); 808 #endif 809 for (i = 0; i < 8; ++i) 810 if (inhibit_sync & (1 << i)) 811 sbic_inhibit_sync[i] = 1; 812 } 813 814 sbicreset(dev); 815 } 816 817 void 818 sbicreset(struct sbic_softc *dev) 819 { 820 sbic_regmap_t regs; 821 u_int my_id, s; 822 u_char csr; 823 #if 0 824 u_int i; 825 struct sbic_acb *acb; 826 #endif 827 828 regs = dev->sc_sbic; 829 #if 0 830 if (dev->sc_flags & SBICF_ALIVE) { 831 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 832 WAIT_CIP(regs); 833 } 834 #else 835 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 836 WAIT_CIP(regs); 837 #endif 838 s = splbio(); 839 my_id = dev->sc_channel.chan_id & SBIC_ID_MASK; 840 841 /* Enable advanced mode */ 842 my_id |= SBIC_ID_EAF /*| SBIC_ID_EHP*/ ; 843 SET_SBIC_myid(regs, my_id); 844 845 /* 846 * Disable interrupts (in dmainit) then reset the chip 847 */ 848 SET_SBIC_cmd(regs, SBIC_CMD_RESET); 849 DELAY(25); 850 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 851 GET_SBIC_csr(regs, csr); /* clears interrupt also */ 852 853 if (dev->sc_clkfreq < 110) 854 my_id |= SBIC_ID_FS_8_10; 855 else if (dev->sc_clkfreq < 160) 856 my_id |= SBIC_ID_FS_12_15; 857 else if (dev->sc_clkfreq < 210) 858 my_id |= SBIC_ID_FS_16_20; 859 860 SET_SBIC_myid(regs, my_id); 861 862 /* 863 * Set up various chip parameters 864 */ 865 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI /* | SBIC_CTL_HSP */ 866 | SBIC_MACHINE_DMA_MODE); 867 /* 868 * don't allow (re)selection (SBIC_RID_ES) 869 * until we can handle target mode!! 870 */ 871 SET_SBIC_rselid(regs, SBIC_RID_ER); 872 SET_SBIC_syn(regs, 0); /* asynch for now */ 873 874 /* 875 * anything else was zeroed by reset 876 */ 877 splx(s); 878 879 #if 0 880 if ((dev->sc_flags & SBICF_ALIVE) == 0) { 881 TAILQ_INIT(&dev->ready_list); 882 TAILQ_INIT(&dev->nexus_list); 883 TAILQ_INIT(&dev->free_list); 884 dev->sc_nexus = NULL; 885 dev->sc_xs = NULL; 886 acb = dev->sc_acb; 887 bzero(acb, sizeof(dev->sc_acb)); 888 for (i = 0; i < sizeof(dev->sc_acb) / sizeof(*acb); i++) { 889 TAILQ_INSERT_TAIL(&dev->free_list, acb, chain); 890 acb++; 891 } 892 bzero(dev->sc_tinfo, sizeof(dev->sc_tinfo)); 893 } else { 894 if (dev->sc_nexus != NULL) { 895 dev->sc_nexus->xs->error = XS_DRIVER_STUFFUP; 896 sbic_scsidone(dev->sc_nexus, dev->sc_stat[0]); 897 } 898 while (acb = dev->nexus_list.tqh_first) { 899 acb->xs->error = XS_DRIVER_STUFFUP; 900 sbic_scsidone(acb, -1 /*acb->stat[0]*/); 901 } 902 } 903 904 dev->sc_flags |= SBICF_ALIVE; 905 #endif 906 dev->sc_flags &= ~SBICF_SELECTED; 907 } 908 909 void 910 sbicerror(struct sbic_softc *dev, sbic_regmap_t regs, u_char csr) 911 { 912 struct scsipi_xfer *xs; 913 914 xs = dev->sc_xs; 915 916 #ifdef DIAGNOSTIC 917 if (xs == NULL) 918 panic("sbicerror"); 919 #endif 920 if (xs->xs_control & XS_CTL_SILENT) 921 return; 922 923 printf("%s: ", dev->sc_dev.dv_xname); 924 printf("csr == 0x%02x\n", csr); /* XXX */ 925 } 926 927 /* 928 * select the bus, return when selected or error. 929 */ 930 int 931 sbicselectbus(struct sbic_softc *dev, sbic_regmap_t regs, u_char target, 932 u_char lun, u_char our_addr) 933 { 934 u_char asr, csr, id; 935 936 SBIC_TRACE(dev); 937 QPRINTF(("sbicselectbus %d\n", target)); 938 939 /* 940 * if we're already selected, return (XXXX panic maybe?) 941 */ 942 if (dev->sc_flags & SBICF_SELECTED) { 943 SBIC_TRACE(dev); 944 return(1); 945 } 946 947 /* 948 * issue select 949 */ 950 SBIC_TC_PUT(regs, 0); 951 SET_SBIC_selid(regs, target); 952 SET_SBIC_timeo(regs, SBIC_TIMEOUT(250,dev->sc_clkfreq)); 953 954 /* 955 * set sync or async 956 */ 957 if (dev->sc_sync[target].state == SYNC_DONE) 958 SET_SBIC_syn(regs, SBIC_SYN (dev->sc_sync[target].offset, 959 dev->sc_sync[target].period)); 960 else 961 SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period)); 962 963 GET_SBIC_asr(regs, asr); 964 if( asr & (SBIC_ASR_INT|SBIC_ASR_BSY) ) { 965 /* This means we got ourselves reselected upon */ 966 /* printf("sbicselectbus: INT/BSY asr %02x\n", asr);*/ 967 #ifdef DDB 968 /* Debugger();*/ 969 #endif 970 SBIC_TRACE(dev); 971 return 1; 972 } 973 974 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN); 975 976 /* 977 * wait for select (merged from separate function may need 978 * cleanup) 979 */ 980 WAIT_CIP(regs); 981 do { 982 asr = SBIC_WAIT(regs, SBIC_ASR_INT | SBIC_ASR_LCI, 0); 983 if (asr & SBIC_ASR_LCI) { 984 #ifdef DEBUG 985 if (reselect_debug) 986 printf("sbicselectbus: late LCI asr %02x\n", asr); 987 #endif 988 SBIC_TRACE(dev); 989 return 1; 990 } 991 GET_SBIC_csr (regs, csr); 992 CSR_TRACE('s',csr,asr,target); 993 QPRINTF(("%02x ", csr)); 994 if( csr == SBIC_CSR_RSLT_NI || csr == SBIC_CSR_RSLT_IFY) { 995 #ifdef DEBUG 996 if(reselect_debug) 997 printf("sbicselectbus: reselected asr %02x\n", asr); 998 #endif 999 /* We need to handle this now so we don't lock up later */ 1000 sbicnextstate(dev, csr, asr); 1001 SBIC_TRACE(dev); 1002 return 1; 1003 } 1004 if( csr == SBIC_CSR_SLT || csr == SBIC_CSR_SLT_ATN) { 1005 panic("sbicselectbus: target issued select!"); 1006 return 1; 1007 } 1008 } while (csr != (SBIC_CSR_MIS_2|MESG_OUT_PHASE) 1009 && csr != (SBIC_CSR_MIS_2|CMD_PHASE) && csr != SBIC_CSR_SEL_TIMEO); 1010 1011 /* Enable (or not) reselection */ 1012 if(!sbic_enable_reselect && dev->nexus_list.tqh_first == NULL) 1013 SET_SBIC_rselid (regs, 0); 1014 else 1015 SET_SBIC_rselid (regs, SBIC_RID_ER); 1016 1017 if (csr == (SBIC_CSR_MIS_2|CMD_PHASE)) { 1018 dev->sc_flags |= SBICF_SELECTED; /* device ignored ATN */ 1019 GET_SBIC_selid(regs, id); 1020 dev->target = id; 1021 GET_SBIC_tlun(regs,dev->lun); 1022 if( dev->lun & SBIC_TLUN_VALID ) 1023 dev->lun &= SBIC_TLUN_MASK; 1024 else 1025 dev->lun = lun; 1026 } else if (csr == (SBIC_CSR_MIS_2|MESG_OUT_PHASE)) { 1027 /* 1028 * Send identify message 1029 * (SCSI-2 requires an identify msg (?)) 1030 */ 1031 GET_SBIC_selid(regs, id); 1032 dev->target = id; 1033 GET_SBIC_tlun(regs,dev->lun); 1034 if( dev->lun & SBIC_TLUN_VALID ) 1035 dev->lun &= SBIC_TLUN_MASK; 1036 else 1037 dev->lun = lun; 1038 /* 1039 * handle drives that don't want to be asked 1040 * whether to go sync at all. 1041 */ 1042 if (sbic_inhibit_sync[id] 1043 && dev->sc_sync[id].state == SYNC_START) { 1044 #ifdef DEBUG 1045 if (sync_debug) 1046 printf("Forcing target %d asynchronous.\n", id); 1047 #endif 1048 dev->sc_sync[id].offset = 0; 1049 dev->sc_sync[id].period = sbic_min_period; 1050 dev->sc_sync[id].state = SYNC_DONE; 1051 } 1052 1053 1054 if (dev->sc_sync[id].state != SYNC_START){ 1055 if( dev->sc_xs->xs_control & XS_CTL_POLL 1056 || (dev->sc_flags & SBICF_ICMD) 1057 || !sbic_enable_reselect ) 1058 SEND_BYTE (regs, MSG_IDENTIFY | lun); 1059 else 1060 SEND_BYTE (regs, MSG_IDENTIFY_DR | lun); 1061 } else { 1062 /* 1063 * try to initiate a sync transfer. 1064 * So compose the sync message we're going 1065 * to send to the target 1066 */ 1067 1068 #ifdef DEBUG 1069 if (sync_debug) 1070 printf("Sending sync request to target %d ... ", 1071 id); 1072 #endif 1073 /* 1074 * setup scsi message sync message request 1075 */ 1076 dev->sc_msg[0] = MSG_IDENTIFY | lun; 1077 dev->sc_msg[1] = MSG_EXT_MESSAGE; 1078 dev->sc_msg[2] = 3; 1079 dev->sc_msg[3] = MSG_SYNC_REQ; 1080 dev->sc_msg[4] = sbictoscsiperiod(dev, regs, 1081 sbic_min_period); 1082 dev->sc_msg[5] = sbic_max_offset; 1083 1084 if (sbicxfstart(regs, 6, MESG_OUT_PHASE, sbic_cmd_wait)) 1085 sbicxfout(regs, 6, dev->sc_msg, MESG_OUT_PHASE); 1086 1087 dev->sc_sync[id].state = SYNC_SENT; 1088 #ifdef DEBUG 1089 if (sync_debug) 1090 printf ("sent\n"); 1091 #endif 1092 } 1093 1094 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0); 1095 GET_SBIC_csr (regs, csr); 1096 CSR_TRACE('y',csr,asr,target); 1097 QPRINTF(("[%02x]", csr)); 1098 #ifdef DEBUG 1099 if (sync_debug && dev->sc_sync[id].state == SYNC_SENT) 1100 printf("csr-result of last msgout: 0x%x\n", csr); 1101 #endif 1102 1103 if (csr != SBIC_CSR_SEL_TIMEO) 1104 dev->sc_flags |= SBICF_SELECTED; 1105 } 1106 if (csr == SBIC_CSR_SEL_TIMEO) 1107 dev->sc_xs->error = XS_SELTIMEOUT; 1108 1109 QPRINTF(("\n")); 1110 1111 SBIC_TRACE(dev); 1112 return(csr == SBIC_CSR_SEL_TIMEO); 1113 } 1114 1115 int 1116 sbicxfstart(sbic_regmap_t regs, int len, u_char phase, int wait) 1117 { 1118 u_char id; 1119 1120 switch (phase) { 1121 case DATA_IN_PHASE: 1122 case MESG_IN_PHASE: 1123 GET_SBIC_selid (regs, id); 1124 id |= SBIC_SID_FROM_SCSI; 1125 SET_SBIC_selid (regs, id); 1126 SBIC_TC_PUT (regs, (unsigned)len); 1127 break; 1128 case DATA_OUT_PHASE: 1129 case MESG_OUT_PHASE: 1130 case CMD_PHASE: 1131 GET_SBIC_selid (regs, id); 1132 id &= ~SBIC_SID_FROM_SCSI; 1133 SET_SBIC_selid (regs, id); 1134 SBIC_TC_PUT (regs, (unsigned)len); 1135 break; 1136 default: 1137 SBIC_TC_PUT (regs, 0); 1138 } 1139 QPRINTF(("sbicxfstart %d, %d, %d\n", len, phase, wait)); 1140 1141 return(1); 1142 } 1143 1144 int 1145 sbicxfout(sbic_regmap_t regs, int len, void *bp, int phase) 1146 { 1147 u_char orig_csr, asr, *buf; 1148 int wait; 1149 1150 buf = bp; 1151 wait = sbic_data_wait; 1152 1153 QPRINTF(("sbicxfout {%d} %02x %02x %02x %02x %02x " 1154 "%02x %02x %02x %02x %02x\n", len, buf[0], buf[1], buf[2], 1155 buf[3], buf[4], buf[5], buf[6], buf[7], buf[8], buf[9])); 1156 1157 GET_SBIC_csr (regs, orig_csr); 1158 CSR_TRACE('>',orig_csr,0,0); 1159 1160 /* 1161 * sigh.. WD-PROTO strikes again.. sending the command in one go 1162 * causes the chip to lock up if talking to certain (misbehaving?) 1163 * targets. Anyway, this procedure should work for all targets, but 1164 * it's slightly slower due to the overhead 1165 */ 1166 WAIT_CIP (regs); 1167 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1168 for (;len > 0; len--) { 1169 GET_SBIC_asr (regs, asr); 1170 while ((asr & SBIC_ASR_DBR) == 0) { 1171 if ((asr & SBIC_ASR_INT) || --wait < 0) { 1172 #ifdef DEBUG 1173 if (sbic_debug) 1174 printf("sbicxfout fail: l%d i%x w%d\n", 1175 len, asr, wait); 1176 #endif 1177 return (len); 1178 } 1179 /* DELAY(1);*/ 1180 GET_SBIC_asr (regs, asr); 1181 } 1182 1183 SET_SBIC_data (regs, *buf); 1184 buf++; 1185 } 1186 SBIC_TC_GET(regs, len); 1187 QPRINTF(("sbicxfout done %d bytes\n", len)); 1188 /* 1189 * this leaves with one csr to be read 1190 */ 1191 return(0); 1192 } 1193 1194 /* returns # bytes left to read */ 1195 int 1196 sbicxfin(sbic_regmap_t regs, int len, void *bp) 1197 { 1198 int wait; 1199 u_char *obp, *buf; 1200 u_char orig_csr, csr, asr; 1201 1202 wait = sbic_data_wait; 1203 obp = bp; 1204 buf = bp; 1205 1206 GET_SBIC_csr (regs, orig_csr); 1207 CSR_TRACE('<',orig_csr,0,0); 1208 1209 QPRINTF(("sbicxfin %d, csr=%02x\n", len, orig_csr)); 1210 1211 WAIT_CIP (regs); 1212 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1213 for (;len > 0; len--) { 1214 GET_SBIC_asr (regs, asr); 1215 if((asr & SBIC_ASR_PE)) { 1216 #ifdef DEBUG 1217 printf("sbicxfin parity error: l%d i%x w%d\n", 1218 len, asr, wait); 1219 /* return ((unsigned long)buf - (unsigned long)bp); */ 1220 #ifdef DDB 1221 Debugger(); 1222 #endif 1223 #endif 1224 } 1225 while ((asr & SBIC_ASR_DBR) == 0) { 1226 if ((asr & SBIC_ASR_INT) || --wait < 0) { 1227 #ifdef DEBUG 1228 if (sbic_debug) { 1229 QPRINTF(("sbicxfin fail:{%d} %02x %02x %02x %02x %02x %02x " 1230 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1231 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1232 printf("sbicxfin fail: l%d i%x w%d\n", 1233 len, asr, wait); 1234 } 1235 #endif 1236 return len; 1237 } 1238 1239 if( ! asr & SBIC_ASR_BSY ) { 1240 GET_SBIC_csr(regs, csr); 1241 CSR_TRACE('<',csr,asr,len); 1242 QPRINTF(("[CSR%02xASR%02x]", csr, asr)); 1243 } 1244 1245 /* DELAY(1);*/ 1246 GET_SBIC_asr (regs, asr); 1247 } 1248 1249 GET_SBIC_data (regs, *buf); 1250 /* QPRINTF(("asr=%02x, csr=%02x, data=%02x\n", asr, csr, *buf));*/ 1251 buf++; 1252 } 1253 1254 QPRINTF(("sbicxfin {%d} %02x %02x %02x %02x %02x %02x " 1255 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1256 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1257 1258 /* this leaves with one csr to be read */ 1259 return len; 1260 } 1261 1262 /* 1263 * SCSI 'immediate' command: issue a command to some SCSI device 1264 * and get back an 'immediate' response (i.e., do programmed xfer 1265 * to get the response data). 'cbuf' is a buffer containing a scsi 1266 * command of length clen bytes. 'buf' is a buffer of length 'len' 1267 * bytes for data. The transfer direction is determined by the device 1268 * (i.e., by the scsi bus data xfer phase). If 'len' is zero, the 1269 * command must supply no data. 1270 */ 1271 int 1272 sbicicmd(struct sbic_softc *dev, int target, int lun, void *cbuf, int clen, 1273 void *buf, int len) 1274 { 1275 sbic_regmap_t regs; 1276 u_char phase, csr, asr; 1277 int wait, i; 1278 struct sbic_acb *acb; 1279 1280 #define CSR_LOG_BUF_SIZE 0 1281 #if CSR_LOG_BUF_SIZE 1282 int bufptr; 1283 int csrbuf[CSR_LOG_BUF_SIZE]; 1284 bufptr=0; 1285 #endif 1286 1287 SBIC_TRACE(dev); 1288 regs = dev->sc_sbic; 1289 acb = dev->sc_nexus; 1290 1291 /* Make sure pointers are OK */ 1292 dev->sc_last = dev->sc_cur = &acb->sc_pa; 1293 dev->sc_tcnt = acb->sc_tcnt = 0; 1294 acb->sc_pa.dc_count = 0; /* No DMA */ 1295 acb->sc_kv.dc_addr = buf; 1296 acb->sc_kv.dc_count = len; 1297 1298 #ifdef DEBUG 1299 routine = 3; 1300 debug_sbic_regs = regs; /* store this to allow debug calls */ 1301 if( data_pointer_debug > 1 ) 1302 printf("sbicicmd(%d,%d):%d\n", target, lun, 1303 acb->sc_kv.dc_count); 1304 #endif 1305 1306 /* 1307 * set the sbic into non-DMA mode 1308 */ 1309 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI /*| SBIC_CTL_HSP*/); 1310 1311 dev->sc_stat[0] = 0xff; 1312 dev->sc_msg[0] = 0xff; 1313 i = 1; /* pre-load */ 1314 1315 /* We're stealing the SCSI bus */ 1316 dev->sc_flags |= SBICF_ICMD; 1317 1318 do { 1319 /* 1320 * select the SCSI bus (it's an error if bus isn't free) 1321 */ 1322 if (!( dev->sc_flags & SBICF_SELECTED ) 1323 && sbicselectbus(dev, regs, target, lun, dev->sc_scsiaddr)) { 1324 /* printf("sbicicmd: trying to select busy bus!\n"); */ 1325 dev->sc_flags &= ~SBICF_ICMD; 1326 return(-1); 1327 } 1328 1329 /* 1330 * Wait for a phase change (or error) then let the device sequence 1331 * us through the various SCSI phases. 1332 */ 1333 1334 wait = sbic_cmd_wait; 1335 1336 asr = GET_SBIC_asr (regs, asr); 1337 GET_SBIC_csr (regs, csr); 1338 CSR_TRACE('I',csr,asr,target); 1339 QPRINTF((">ASR:%02xCSR:%02x<", asr, csr)); 1340 1341 #if CSR_LOG_BUF_SIZE 1342 csrbuf[bufptr++] = csr; 1343 #endif 1344 1345 1346 switch (csr) { 1347 case SBIC_CSR_S_XFERRED: 1348 case SBIC_CSR_DISC: 1349 case SBIC_CSR_DISC_1: 1350 dev->sc_flags &= ~SBICF_SELECTED; 1351 GET_SBIC_cmd_phase (regs, phase); 1352 if (phase == 0x60) { 1353 GET_SBIC_tlun (regs, dev->sc_stat[0]); 1354 i = 0; /* done */ 1355 /* break; */ /* Bypass all the state gobldygook */ 1356 } else { 1357 #ifdef DEBUG 1358 if(reselect_debug>1) 1359 printf("sbicicmd: handling disconnect\n"); 1360 #endif 1361 i = SBIC_STATE_DISCONNECT; 1362 } 1363 break; 1364 1365 case SBIC_CSR_XFERRED|CMD_PHASE: 1366 case SBIC_CSR_MIS|CMD_PHASE: 1367 case SBIC_CSR_MIS_1|CMD_PHASE: 1368 case SBIC_CSR_MIS_2|CMD_PHASE: 1369 if (sbicxfstart(regs, clen, CMD_PHASE, sbic_cmd_wait)) 1370 if (sbicxfout(regs, clen, 1371 cbuf, CMD_PHASE)) 1372 i = sbicabort(dev, regs,"icmd sending cmd"); 1373 #if 0 1374 GET_SBIC_csr(regs, csr); /* Lets us reload tcount */ 1375 WAIT_CIP(regs); 1376 GET_SBIC_asr(regs, asr); 1377 CSR_TRACE('I',csr,asr,target); 1378 if( asr & (SBIC_ASR_BSY|SBIC_ASR_LCI|SBIC_ASR_CIP) ) 1379 printf("next: cmd sent asr %02x, csr %02x\n", 1380 asr, csr); 1381 #endif 1382 break; 1383 1384 #if 0 1385 case SBIC_CSR_XFERRED|DATA_OUT_PHASE: 1386 case SBIC_CSR_XFERRED|DATA_IN_PHASE: 1387 case SBIC_CSR_MIS|DATA_OUT_PHASE: 1388 case SBIC_CSR_MIS|DATA_IN_PHASE: 1389 case SBIC_CSR_MIS_1|DATA_OUT_PHASE: 1390 case SBIC_CSR_MIS_1|DATA_IN_PHASE: 1391 case SBIC_CSR_MIS_2|DATA_OUT_PHASE: 1392 case SBIC_CSR_MIS_2|DATA_IN_PHASE: 1393 if (acb->sc_kv.dc_count <= 0) 1394 i = sbicabort(dev, regs, "icmd out of data"); 1395 else { 1396 wait = sbic_data_wait; 1397 if (sbicxfstart(regs, 1398 acb->sc_kv.dc_count, 1399 SBIC_PHASE(csr), wait)) 1400 if (csr & 0x01) 1401 /* data in? */ 1402 i=sbicxfin(regs, 1403 acb->sc_kv.dc_count, 1404 acb->sc_kv.dc_addr); 1405 else 1406 i=sbicxfout(regs, 1407 acb->sc_kv.dc_count, 1408 acb->sc_kv.dc_addr, 1409 SBIC_PHASE(csr)); 1410 acb->sc_kv.dc_addr += 1411 (acb->sc_kv.dc_count - i); 1412 acb->sc_kv.dc_count = i; 1413 i = 1; 1414 } 1415 break; 1416 1417 #endif 1418 case SBIC_CSR_XFERRED|STATUS_PHASE: 1419 case SBIC_CSR_MIS|STATUS_PHASE: 1420 case SBIC_CSR_MIS_1|STATUS_PHASE: 1421 case SBIC_CSR_MIS_2|STATUS_PHASE: 1422 /* 1423 * the sbic does the status/cmd-complete reading ok, 1424 * so do this with its hi-level commands. 1425 */ 1426 #ifdef DEBUG 1427 if(sbic_debug) 1428 printf("SBICICMD status phase\n"); 1429 #endif 1430 SBIC_TC_PUT(regs, 0); 1431 SET_SBIC_cmd_phase(regs, 0x46); 1432 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1433 break; 1434 1435 #if THIS_IS_A_RESERVED_STATE 1436 case BUS_FREE_PHASE: /* This is not legal */ 1437 if( dev->sc_stat[0] != 0xff ) 1438 goto out; 1439 break; 1440 #endif 1441 1442 default: 1443 i = sbicnextstate(dev, csr, asr); 1444 } 1445 1446 /* 1447 * make sure the last command was taken, 1448 * ie. we're not hunting after an ignored command.. 1449 */ 1450 GET_SBIC_asr(regs, asr); 1451 1452 /* tapes may take a loooong time.. */ 1453 while (asr & SBIC_ASR_BSY){ 1454 if(asr & SBIC_ASR_DBR) { 1455 printf("sbicicmd: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", 1456 csr,asr); 1457 #ifdef DDB 1458 Debugger(); 1459 #endif 1460 /* SBIC is jammed */ 1461 /* DUNNO which direction */ 1462 /* Try old direction */ 1463 GET_SBIC_data(regs,i); 1464 GET_SBIC_asr(regs, asr); 1465 if( asr & SBIC_ASR_DBR) /* Wants us to write */ 1466 SET_SBIC_data(regs,i); 1467 } 1468 GET_SBIC_asr(regs, asr); 1469 } 1470 1471 /* 1472 * wait for last command to complete 1473 */ 1474 if (asr & SBIC_ASR_LCI) { 1475 printf("sbicicmd: last command ignored\n"); 1476 } 1477 else if( i == 1 ) /* Bsy */ 1478 SBIC_WAIT (regs, SBIC_ASR_INT, wait); 1479 1480 /* 1481 * do it again 1482 */ 1483 } while ( i > 0 && dev->sc_stat[0] == 0xff); 1484 1485 /* Sometimes we need to do an extra read of the CSR */ 1486 GET_SBIC_csr(regs, csr); 1487 CSR_TRACE('I',csr,asr,0xff); 1488 1489 #if CSR_LOG_BUF_SIZE 1490 if(reselect_debug>1) 1491 for(i=0; i<bufptr; i++) 1492 printf("CSR:%02x", csrbuf[i]); 1493 #endif 1494 1495 #ifdef DEBUG 1496 if(data_pointer_debug > 1) 1497 printf("sbicicmd done(%d,%d):%d =%d=\n", 1498 dev->target, lun, 1499 acb->sc_kv.dc_count, 1500 dev->sc_stat[0]); 1501 #endif 1502 1503 QPRINTF(("=STS:%02x=", dev->sc_stat[0])); 1504 dev->sc_flags &= ~SBICF_ICMD; 1505 1506 SBIC_TRACE(dev); 1507 return(dev->sc_stat[0]); 1508 } 1509 1510 /* 1511 * Finish SCSI xfer command: After the completion interrupt from 1512 * a read/write operation, sequence through the final phases in 1513 * programmed i/o. This routine is a lot like sbicicmd except we 1514 * skip (and don't allow) the select, cmd out and data in/out phases. 1515 */ 1516 void 1517 sbicxfdone(struct sbic_softc *dev, sbic_regmap_t regs, int target) 1518 { 1519 u_char phase, asr, csr; 1520 int s; 1521 1522 SBIC_TRACE(dev); 1523 QPRINTF(("{")); 1524 s = splbio(); 1525 1526 /* 1527 * have the sbic complete on its own 1528 */ 1529 SBIC_TC_PUT(regs, 0); 1530 SET_SBIC_cmd_phase(regs, 0x46); 1531 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1532 1533 do { 1534 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0); 1535 GET_SBIC_csr (regs, csr); 1536 CSR_TRACE('f',csr,asr,target); 1537 QPRINTF(("%02x:", csr)); 1538 } while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) 1539 && (csr != SBIC_CSR_S_XFERRED)); 1540 1541 dev->sc_flags &= ~SBICF_SELECTED; 1542 1543 GET_SBIC_cmd_phase (regs, phase); 1544 QPRINTF(("}%02x", phase)); 1545 if (phase == 0x60) 1546 GET_SBIC_tlun(regs, dev->sc_stat[0]); 1547 else 1548 sbicerror(dev, regs, csr); 1549 1550 QPRINTF(("=STS:%02x=\n", dev->sc_stat[0])); 1551 splx(s); 1552 SBIC_TRACE(dev); 1553 } 1554 1555 /* 1556 * No DMA chains 1557 */ 1558 1559 int 1560 sbicgo(struct sbic_softc *dev, struct scsipi_xfer *xs) 1561 { 1562 int i, dmaflags, count, usedma; 1563 u_char csr, asr, *addr; 1564 sbic_regmap_t regs; 1565 struct sbic_acb *acb; 1566 1567 SBIC_TRACE(dev); 1568 dev->target = xs->xs_periph->periph_target; 1569 dev->lun = xs->xs_periph->periph_lun; 1570 acb = dev->sc_nexus; 1571 regs = dev->sc_sbic; 1572 1573 usedma = sbicdmaok(dev, xs); 1574 #ifdef DEBUG 1575 routine = 1; 1576 debug_sbic_regs = regs; /* store this to allow debug calls */ 1577 if( data_pointer_debug > 1 ) 1578 printf("sbicgo(%d,%d)\n", dev->target, dev->lun); 1579 #endif 1580 1581 /* 1582 * set the sbic into DMA mode 1583 */ 1584 if( usedma ) 1585 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI | 1586 SBIC_MACHINE_DMA_MODE); 1587 else 1588 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1589 1590 1591 /* 1592 * select the SCSI bus (it's an error if bus isn't free) 1593 */ 1594 if (sbicselectbus(dev, regs, dev->target, dev->lun, 1595 dev->sc_scsiaddr)) { 1596 /* printf("sbicgo: Trying to select busy bus!\n"); */ 1597 SBIC_TRACE(dev); 1598 return(0); /* Not done: needs to be rescheduled */ 1599 } 1600 dev->sc_stat[0] = 0xff; 1601 1602 /* 1603 * Calculate DMA chains now 1604 */ 1605 1606 dmaflags = 0; 1607 if (acb->flags & ACB_DATAIN) 1608 dmaflags |= DMAGO_READ; 1609 1610 1611 /* 1612 * Deal w/bounce buffers. 1613 */ 1614 1615 addr = acb->sc_kv.dc_addr; 1616 count = acb->sc_kv.dc_count; 1617 if (count && (char *)kvtop(addr) != acb->sc_pa.dc_addr) { /* XXXX check */ 1618 printf("sbic: DMA buffer mapping changed %p->%x\n", 1619 acb->sc_pa.dc_addr, kvtop(addr)); 1620 #ifdef DDB 1621 Debugger(); 1622 #endif 1623 } 1624 1625 #ifdef DEBUG 1626 ++sbicdma_ops; /* count total DMA operations */ 1627 #endif 1628 if (count && usedma && dev->sc_flags & SBICF_BADDMA && 1629 sbiccheckdmap(addr, count, dev->sc_dmamask)) { 1630 /* 1631 * need to bounce the dma. 1632 */ 1633 if (dmaflags & DMAGO_READ) { 1634 acb->flags |= ACB_BBUF; 1635 acb->sc_dmausrbuf = addr; 1636 acb->sc_dmausrlen = count; 1637 acb->sc_usrbufpa = (u_char *)kvtop(addr); 1638 if(!dev->sc_tinfo[dev->target].bounce) { 1639 printf("sbicgo: HELP! no bounce allocated for %d\n", 1640 dev->target); 1641 printf("xfer: (%p->%p,%lx)\n", acb->sc_dmausrbuf, 1642 acb->sc_usrbufpa, acb->sc_dmausrlen); 1643 dev->sc_tinfo[xs->xs_periph->periph_target].bounce 1644 = (char *)alloc_z2mem(MAXPHYS); 1645 if (isztwomem(dev->sc_tinfo[xs->xs_periph->periph_target].bounce)) 1646 printf("alloc ZII target %d bounce pa 0x%x\n", 1647 xs->xs_periph->periph_target, 1648 kvtop(dev->sc_tinfo[xs->xs_periph->periph_target].bounce)); 1649 else if (dev->sc_tinfo[xs->xs_periph->periph_target].bounce) 1650 printf("alloc CHIP target %d bounce pa 0x%p\n", 1651 xs->xs_periph->periph_target, 1652 PREP_DMA_MEM(dev->sc_tinfo[xs->xs_periph->periph_target].bounce)); 1653 1654 printf("Allocating %d bounce at %x\n", 1655 dev->target, 1656 kvtop(dev->sc_tinfo[dev->target].bounce)); 1657 } 1658 } else { /* write: copy to dma buffer */ 1659 #ifdef DEBUG 1660 if(data_pointer_debug) 1661 printf("sbicgo: copying %x bytes to target %d bounce %x\n", 1662 count, dev->target, 1663 kvtop(dev->sc_tinfo[dev->target].bounce)); 1664 #endif 1665 bcopy (addr, dev->sc_tinfo[dev->target].bounce, count); 1666 } 1667 addr = dev->sc_tinfo[dev->target].bounce;/* and use dma buffer */ 1668 acb->sc_kv.dc_addr = addr; 1669 #ifdef DEBUG 1670 ++sbicdma_bounces; /* count number of bounced */ 1671 #endif 1672 } 1673 1674 /* 1675 * Allocate the DMA chain 1676 */ 1677 1678 /* Set start KVM addresses */ 1679 #if 0 1680 acb->sc_kv.dc_addr = addr; 1681 acb->sc_kv.dc_count = count; 1682 #endif 1683 1684 /* Mark end of segment */ 1685 acb->sc_tcnt = dev->sc_tcnt = 0; 1686 acb->sc_pa.dc_count = 0; 1687 1688 sbic_load_ptrs(dev, regs, dev->target, dev->lun); 1689 SBIC_TRACE(dev); 1690 /* Enable interrupts but don't do any DMA */ 1691 dev->sc_enintr(dev); 1692 if (usedma) { 1693 dev->sc_tcnt = dev->sc_dmago(dev, acb->sc_pa.dc_addr, 1694 acb->sc_pa.dc_count, 1695 dmaflags); 1696 #ifdef DEBUG 1697 dev->sc_dmatimo = dev->sc_tcnt ? 1 : 0; 1698 #endif 1699 } else 1700 dev->sc_dmacmd = 0; /* Don't use DMA */ 1701 dev->sc_flags |= SBICF_INDMA; 1702 /* SBIC_TC_PUT(regs, dev->sc_tcnt); */ /* XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX */ 1703 SBIC_TRACE(dev); 1704 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 1705 1706 /* 1707 * push the data cache ( I think this won't work (EH)) 1708 */ 1709 #if defined(M68040) || defined(M68060) 1710 if (mmutype == MMU_68040 && usedma && count) { 1711 dma_cachectl(addr, count); 1712 if (((u_int)addr & 0xF) || (((u_int)addr + count) & 0xF)) 1713 dev->sc_flags |= SBICF_DCFLUSH; 1714 } 1715 #endif 1716 1717 /* 1718 * enintr() also enables interrupts for the sbic 1719 */ 1720 #ifdef DEBUG 1721 if( data_pointer_debug > 1 ) 1722 printf("sbicgo dmago:%d(%p:%lx)\n", 1723 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 1724 #if 0 1725 /* 1726 * Hmm - this isn't right: asr and csr haven't been set yet. 1727 */ 1728 debug_asr = asr; 1729 debug_csr = csr; 1730 #endif 1731 #endif 1732 1733 /* 1734 * Lets cycle a while then let the interrupt handler take over 1735 */ 1736 1737 asr = GET_SBIC_asr(regs, asr); 1738 do { 1739 GET_SBIC_csr(regs, csr); 1740 CSR_TRACE('g',csr,asr,dev->target); 1741 #ifdef DEBUG 1742 debug_csr = csr; 1743 routine = 1; 1744 #endif 1745 QPRINTF(("go[0x%x]", csr)); 1746 1747 i = sbicnextstate(dev, csr, asr); 1748 1749 WAIT_CIP(regs); 1750 GET_SBIC_asr(regs, asr); 1751 #ifdef DEBUG 1752 debug_asr = asr; 1753 #endif 1754 if(asr & SBIC_ASR_LCI) printf("sbicgo: LCI asr:%02x csr:%02x\n", 1755 asr,csr); 1756 } while( i == SBIC_STATE_RUNNING 1757 && asr & (SBIC_ASR_INT|SBIC_ASR_LCI) ); 1758 1759 CSR_TRACE('g',csr,asr,i<<4); 1760 SBIC_TRACE(dev); 1761 if (i == SBIC_STATE_DONE && dev->sc_stat[0] == 0xff) printf("sbicgo: done & stat = 0xff\n"); 1762 if (i == SBIC_STATE_DONE && dev->sc_stat[0] != 0xff) { 1763 /* if( i == SBIC_STATE_DONE && dev->sc_stat[0] ) { */ 1764 /* Did we really finish that fast? */ 1765 return 1; 1766 } 1767 return 0; 1768 } 1769 1770 1771 int 1772 sbicintr(struct sbic_softc *dev) 1773 { 1774 sbic_regmap_t regs; 1775 u_char asr, csr; 1776 int i; 1777 1778 regs = dev->sc_sbic; 1779 1780 /* 1781 * pending interrupt? 1782 */ 1783 GET_SBIC_asr (regs, asr); 1784 if ((asr & SBIC_ASR_INT) == 0) 1785 return(0); 1786 1787 SBIC_TRACE(dev); 1788 do { 1789 GET_SBIC_csr(regs, csr); 1790 CSR_TRACE('i',csr,asr,dev->target); 1791 #ifdef DEBUG 1792 debug_csr = csr; 1793 routine = 2; 1794 #endif 1795 QPRINTF(("intr[0x%x]", csr)); 1796 1797 i = sbicnextstate(dev, csr, asr); 1798 1799 WAIT_CIP(regs); 1800 GET_SBIC_asr(regs, asr); 1801 #ifdef DEBUG 1802 debug_asr = asr; 1803 #endif 1804 #if 0 1805 if(asr & SBIC_ASR_LCI) printf("sbicintr: LCI asr:%02x csr:%02x\n", 1806 asr,csr); 1807 #endif 1808 } while(i == SBIC_STATE_RUNNING && 1809 asr & (SBIC_ASR_INT|SBIC_ASR_LCI)); 1810 CSR_TRACE('i',csr,asr,i<<4); 1811 SBIC_TRACE(dev); 1812 return(1); 1813 } 1814 1815 /* 1816 * Run commands and wait for disconnect 1817 */ 1818 int 1819 sbicpoll(struct sbic_softc *dev) 1820 { 1821 sbic_regmap_t regs; 1822 u_char asr, csr; 1823 int i; 1824 1825 SBIC_TRACE(dev); 1826 regs = dev->sc_sbic; 1827 1828 do { 1829 GET_SBIC_asr (regs, asr); 1830 #ifdef DEBUG 1831 debug_asr = asr; 1832 #endif 1833 GET_SBIC_csr(regs, csr); 1834 CSR_TRACE('p',csr,asr,dev->target); 1835 #ifdef DEBUG 1836 debug_csr = csr; 1837 routine = 2; 1838 #endif 1839 QPRINTF(("poll[0x%x]", csr)); 1840 1841 i = sbicnextstate(dev, csr, asr); 1842 1843 WAIT_CIP(regs); 1844 GET_SBIC_asr(regs, asr); 1845 /* tapes may take a loooong time.. */ 1846 while (asr & SBIC_ASR_BSY){ 1847 if(asr & SBIC_ASR_DBR) { 1848 printf("sbipoll: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", 1849 csr,asr); 1850 #ifdef DDB 1851 Debugger(); 1852 #endif 1853 /* SBIC is jammed */ 1854 /* DUNNO which direction */ 1855 /* Try old direction */ 1856 GET_SBIC_data(regs,i); 1857 GET_SBIC_asr(regs, asr); 1858 if( asr & SBIC_ASR_DBR) /* Wants us to write */ 1859 SET_SBIC_data(regs,i); 1860 } 1861 GET_SBIC_asr(regs, asr); 1862 } 1863 1864 if(asr & SBIC_ASR_LCI) printf("sbicpoll: LCI asr:%02x csr:%02x\n", 1865 asr,csr); 1866 else if( i == 1 ) /* BSY */ 1867 SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait); 1868 } while(i == SBIC_STATE_RUNNING); 1869 CSR_TRACE('p',csr,asr,i<<4); 1870 SBIC_TRACE(dev); 1871 return(1); 1872 } 1873 1874 /* 1875 * Handle a single msgin 1876 */ 1877 1878 int 1879 sbicmsgin(struct sbic_softc *dev) 1880 { 1881 sbic_regmap_t regs; 1882 int recvlen; 1883 u_char asr, csr, *tmpaddr; 1884 1885 regs = dev->sc_sbic; 1886 1887 dev->sc_msg[0] = 0xff; 1888 dev->sc_msg[1] = 0xff; 1889 1890 GET_SBIC_asr(regs, asr); 1891 #ifdef DEBUG 1892 if(reselect_debug>1) 1893 printf("sbicmsgin asr=%02x\n", asr); 1894 #endif 1895 1896 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 1897 1898 GET_SBIC_selid (regs, csr); 1899 SET_SBIC_selid (regs, csr | SBIC_SID_FROM_SCSI); 1900 1901 SBIC_TC_PUT(regs, 0); 1902 tmpaddr = dev->sc_msg; 1903 recvlen = 1; 1904 do { 1905 while( recvlen-- ) { 1906 asr = GET_SBIC_asr(regs, asr); 1907 GET_SBIC_csr(regs, csr); 1908 QPRINTF(("sbicmsgin ready to go (csr,asr)=(%02x,%02x)\n", 1909 csr, asr)); 1910 1911 RECV_BYTE(regs, *tmpaddr); 1912 CSR_TRACE('m',csr,asr,*tmpaddr); 1913 #if 1 1914 /* 1915 * get the command completion interrupt, or we 1916 * can't send a new command (LCI) 1917 */ 1918 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1919 GET_SBIC_csr(regs, csr); 1920 CSR_TRACE('X',csr,asr,dev->target); 1921 #else 1922 WAIT_CIP(regs); 1923 do { 1924 GET_SBIC_asr(regs, asr); 1925 csr = 0xff; 1926 GET_SBIC_csr(regs, csr); 1927 CSR_TRACE('X',csr,asr,dev->target); 1928 if( csr == 0xff ) 1929 printf("sbicmsgin waiting: csr %02x asr %02x\n", csr, asr); 1930 } while( csr == 0xff ); 1931 #endif 1932 #ifdef DEBUG 1933 if(reselect_debug>1) 1934 printf("sbicmsgin: got %02x csr %02x asr %02x\n", 1935 *tmpaddr, csr, asr); 1936 #endif 1937 #if do_parity_check 1938 if( asr & SBIC_ASR_PE ) { 1939 printf ("Parity error"); 1940 /* This code simply does not work. */ 1941 WAIT_CIP(regs); 1942 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 1943 WAIT_CIP(regs); 1944 GET_SBIC_asr(regs, asr); 1945 WAIT_CIP(regs); 1946 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 1947 WAIT_CIP(regs); 1948 if( !(asr & SBIC_ASR_LCI) ) 1949 /* Target wants to send garbled msg*/ 1950 continue; 1951 printf("--fixing\n"); 1952 /* loop until a msgout phase occurs on target */ 1953 while(csr & 0x07 != MESG_OUT_PHASE) { 1954 while( asr & SBIC_ASR_BSY && 1955 !(asr & SBIC_ASR_DBR|SBIC_ASR_INT) ) 1956 GET_SBIC_asr(regs, asr); 1957 if( asr & SBIC_ASR_DBR ) 1958 panic("msgin: jammed again!\n"); 1959 GET_SBIC_csr(regs, csr); 1960 CSR_TRACE('e',csr,asr,dev->target); 1961 if( csr & 0x07 != MESG_OUT_PHASE ) { 1962 sbicnextstate(dev, csr, asr); 1963 sbic_save_ptrs(dev, regs, 1964 dev->target, 1965 dev->lun); 1966 } 1967 } 1968 /* Should be msg out by now */ 1969 SEND_BYTE(regs, MSG_PARITY_ERROR); 1970 } 1971 else 1972 #endif 1973 tmpaddr++; 1974 1975 if(recvlen) { 1976 /* Clear ACK */ 1977 WAIT_CIP(regs); 1978 GET_SBIC_asr(regs, asr); 1979 GET_SBIC_csr(regs, csr); 1980 CSR_TRACE('X',csr,asr,dev->target); 1981 QPRINTF(("sbicmsgin pre byte CLR_ACK (csr,asr)=(%02x,%02x)\n", 1982 csr, asr)); 1983 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 1984 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1985 } 1986 1987 }; 1988 1989 if(dev->sc_msg[0] == 0xff) { 1990 printf("sbicmsgin: sbic swallowed our message\n"); 1991 break; 1992 } 1993 #ifdef DEBUG 1994 if (sync_debug) 1995 printf("msgin done csr 0x%x asr 0x%x msg 0x%x\n", 1996 csr, asr, dev->sc_msg[0]); 1997 #endif 1998 /* 1999 * test whether this is a reply to our sync 2000 * request 2001 */ 2002 if (MSG_ISIDENTIFY(dev->sc_msg[0])) { 2003 QPRINTF(("IFFY")); 2004 #if 0 2005 /* There is an implied load-ptrs here */ 2006 sbic_load_ptrs(dev, regs, dev->target, dev->lun); 2007 #endif 2008 /* Got IFFY msg -- ack it */ 2009 } else if (dev->sc_msg[0] == MSG_REJECT 2010 && dev->sc_sync[dev->target].state == SYNC_SENT) { 2011 QPRINTF(("REJECT of SYN")); 2012 #ifdef DEBUG 2013 if (sync_debug) 2014 printf("target %d rejected sync, going async\n", 2015 dev->target); 2016 #endif 2017 dev->sc_sync[dev->target].period = sbic_min_period; 2018 dev->sc_sync[dev->target].offset = 0; 2019 dev->sc_sync[dev->target].state = SYNC_DONE; 2020 SET_SBIC_syn(regs, 2021 SBIC_SYN(dev->sc_sync[dev->target].offset, 2022 dev->sc_sync[dev->target].period)); 2023 } else if ((dev->sc_msg[0] == MSG_REJECT)) { 2024 QPRINTF(("REJECT")); 2025 /* 2026 * we'll never REJECt a REJECT message.. 2027 */ 2028 } else if ((dev->sc_msg[0] == MSG_SAVE_DATA_PTR)) { 2029 QPRINTF(("MSG_SAVE_DATA_PTR")); 2030 /* 2031 * don't reject this either. 2032 */ 2033 } else if ((dev->sc_msg[0] == MSG_DISCONNECT)) { 2034 QPRINTF(("DISCONNECT")); 2035 #ifdef DEBUG 2036 if( reselect_debug>1 && dev->sc_msg[0] == MSG_DISCONNECT ) 2037 printf("sbicmsgin: got disconnect msg %s\n", 2038 (dev->sc_flags & SBICF_ICMD)?"rejecting":""); 2039 #endif 2040 if( dev->sc_flags & SBICF_ICMD ) { 2041 /* We're in immediate mode. Prevent disconnects. */ 2042 /* prepare to reject the message, NACK */ 2043 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2044 WAIT_CIP(regs); 2045 } 2046 } else if (dev->sc_msg[0] == MSG_CMD_COMPLETE ) { 2047 QPRINTF(("CMD_COMPLETE")); 2048 /* !! KLUDGE ALERT !! quite a few drives don't seem to 2049 * really like the current way of sending the 2050 * sync-handshake together with the ident-message, and 2051 * they react by sending command-complete and 2052 * disconnecting right after returning the valid sync 2053 * handshake. So, all I can do is reselect the drive, 2054 * and hope it won't disconnect again. I don't think 2055 * this is valid behavior, but I can't help fixing a 2056 * problem that apparently exists. 2057 * 2058 * Note: we should not get here on `normal' command 2059 * completion, as that condition is handled by the 2060 * high-level sel&xfer resume command used to walk 2061 * thru status/cc-phase. 2062 */ 2063 2064 #ifdef DEBUG 2065 if (sync_debug) 2066 printf ("GOT MSG %d! target %d acting weird.." 2067 " waiting for disconnect...\n", 2068 dev->sc_msg[0], dev->target); 2069 #endif 2070 /* Check to see if sbic is handling this */ 2071 GET_SBIC_asr(regs, asr); 2072 if(asr & SBIC_ASR_BSY) 2073 return SBIC_STATE_RUNNING; 2074 2075 /* Let's try this: Assume it works and set status to 00 */ 2076 dev->sc_stat[0] = 0; 2077 } else if (dev->sc_msg[0] == MSG_EXT_MESSAGE 2078 && tmpaddr == &dev->sc_msg[1]) { 2079 QPRINTF(("ExtMSG\n")); 2080 /* Read in whole extended message */ 2081 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2082 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2083 GET_SBIC_asr(regs, asr); 2084 GET_SBIC_csr(regs, csr); 2085 QPRINTF(("CLR ACK asr %02x, csr %02x\n", asr, csr)); 2086 RECV_BYTE(regs, *tmpaddr); 2087 CSR_TRACE('x',csr,asr,*tmpaddr); 2088 /* Wait for command completion IRQ */ 2089 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2090 recvlen = *tmpaddr++; 2091 QPRINTF(("Recving ext msg, asr %02x csr %02x len %02x\n", 2092 asr, csr, recvlen)); 2093 } else if (dev->sc_msg[0] == MSG_EXT_MESSAGE && dev->sc_msg[1] == 3 2094 && dev->sc_msg[2] == MSG_SYNC_REQ) { 2095 QPRINTF(("SYN")); 2096 dev->sc_sync[dev->target].period = 2097 sbicfromscsiperiod(dev, 2098 regs, dev->sc_msg[3]); 2099 dev->sc_sync[dev->target].offset = dev->sc_msg[4]; 2100 dev->sc_sync[dev->target].state = SYNC_DONE; 2101 SET_SBIC_syn(regs, 2102 SBIC_SYN(dev->sc_sync[dev->target].offset, 2103 dev->sc_sync[dev->target].period)); 2104 printf("%s: target %d now synchronous," 2105 " period=%dns, offset=%d.\n", 2106 dev->sc_dev.dv_xname, dev->target, 2107 dev->sc_msg[3] * 4, dev->sc_msg[4]); 2108 } else { 2109 #ifdef DEBUG 2110 if (sbic_debug || sync_debug) 2111 printf ("sbicmsgin: Rejecting message 0x%02x\n", 2112 dev->sc_msg[0]); 2113 #endif 2114 /* prepare to reject the message, NACK */ 2115 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2116 WAIT_CIP(regs); 2117 } 2118 /* Clear ACK */ 2119 WAIT_CIP(regs); 2120 GET_SBIC_asr(regs, asr); 2121 GET_SBIC_csr(regs, csr); 2122 CSR_TRACE('X',csr,asr,dev->target); 2123 QPRINTF(("sbicmsgin pre CLR_ACK (csr,asr)=(%02x,%02x)%d\n", 2124 csr, asr, recvlen)); 2125 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2126 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2127 } 2128 #if 0 2129 while((csr == SBIC_CSR_MSGIN_W_ACK) 2130 || (SBIC_PHASE(csr) == MESG_IN_PHASE)); 2131 #else 2132 while (recvlen>0); 2133 #endif 2134 2135 QPRINTF(("sbicmsgin finished: csr %02x, asr %02x\n",csr, asr)); 2136 2137 /* Should still have one CSR to read */ 2138 return SBIC_STATE_RUNNING; 2139 } 2140 2141 2142 /* 2143 * sbicnextstate() 2144 * return: 2145 * 0 == done 2146 * 1 == working 2147 * 2 == disconnected 2148 * -1 == error 2149 */ 2150 int 2151 sbicnextstate(struct sbic_softc *dev, u_char csr, u_char asr) 2152 { 2153 sbic_regmap_t regs; 2154 struct sbic_acb *acb; 2155 int i, newtarget, newlun, wait; 2156 #if 0 2157 unsigned tcnt; 2158 #endif 2159 2160 i = 0; 2161 SBIC_TRACE(dev); 2162 regs = dev->sc_sbic; 2163 acb = dev->sc_nexus; 2164 2165 QPRINTF(("next[%02x,%02x]",asr,csr)); 2166 2167 switch (csr) { 2168 case SBIC_CSR_XFERRED|CMD_PHASE: 2169 case SBIC_CSR_MIS|CMD_PHASE: 2170 case SBIC_CSR_MIS_1|CMD_PHASE: 2171 case SBIC_CSR_MIS_2|CMD_PHASE: 2172 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 2173 if (sbicxfstart(regs, acb->clen, CMD_PHASE, sbic_cmd_wait)) 2174 if (sbicxfout(regs, acb->clen, 2175 &acb->cmd, CMD_PHASE)) 2176 goto abort; 2177 break; 2178 2179 case SBIC_CSR_XFERRED|STATUS_PHASE: 2180 case SBIC_CSR_MIS|STATUS_PHASE: 2181 case SBIC_CSR_MIS_1|STATUS_PHASE: 2182 case SBIC_CSR_MIS_2|STATUS_PHASE: 2183 /* 2184 * this should be the normal i/o completion case. 2185 * get the status & cmd complete msg then let the 2186 * device driver look at what happened. 2187 */ 2188 sbicxfdone(dev,regs,dev->target); 2189 /* 2190 * check for overlapping cache line, flush if so 2191 */ 2192 #if defined(M68040) || defined(M68060) 2193 if (dev->sc_flags & SBICF_DCFLUSH) { 2194 #if 0 2195 printf("sbic: 68040/68060 DMA cache flush needs" 2196 "fixing? %x:%x\n", 2197 dev->sc_xs->data, dev->sc_xs->datalen); 2198 #endif 2199 } 2200 #endif 2201 #ifdef DEBUG 2202 if( data_pointer_debug > 1 ) 2203 printf("next dmastop: %d(%p:%lx)\n", 2204 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 2205 dev->sc_dmatimo = 0; 2206 #endif 2207 dev->sc_dmastop(dev); /* was dmafree */ 2208 if (acb->flags & ACB_BBUF) { 2209 if ((u_char *)kvtop(acb->sc_dmausrbuf) != acb->sc_usrbufpa) 2210 printf("%s: WARNING - buffer mapping changed %p->%x\n", 2211 dev->sc_dev.dv_xname, acb->sc_usrbufpa, 2212 kvtop(acb->sc_dmausrbuf)); 2213 #ifdef DEBUG 2214 if(data_pointer_debug) 2215 printf("sbicgo:copying %lx bytes from target %d bounce %x\n", 2216 acb->sc_dmausrlen, 2217 dev->target, 2218 kvtop(dev->sc_tinfo[dev->target].bounce)); 2219 #endif 2220 bcopy(dev->sc_tinfo[dev->target].bounce, 2221 acb->sc_dmausrbuf, 2222 acb->sc_dmausrlen); 2223 } 2224 dev->sc_flags &= ~(SBICF_INDMA | SBICF_DCFLUSH); 2225 sbic_scsidone(acb, dev->sc_stat[0]); 2226 SBIC_TRACE(dev); 2227 return SBIC_STATE_DONE; 2228 2229 case SBIC_CSR_XFERRED|DATA_OUT_PHASE: 2230 case SBIC_CSR_XFERRED|DATA_IN_PHASE: 2231 case SBIC_CSR_MIS|DATA_OUT_PHASE: 2232 case SBIC_CSR_MIS|DATA_IN_PHASE: 2233 case SBIC_CSR_MIS_1|DATA_OUT_PHASE: 2234 case SBIC_CSR_MIS_1|DATA_IN_PHASE: 2235 case SBIC_CSR_MIS_2|DATA_OUT_PHASE: 2236 case SBIC_CSR_MIS_2|DATA_IN_PHASE: 2237 if( dev->sc_xs->xs_control & XS_CTL_POLL || dev->sc_flags & SBICF_ICMD 2238 || acb->sc_dmacmd == 0 ) { 2239 /* Do PIO */ 2240 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2241 if (acb->sc_kv.dc_count <= 0) { 2242 printf("sbicnextstate:xfer count %d asr%x csr%x\n", 2243 acb->sc_kv.dc_count, asr, csr); 2244 goto abort; 2245 } 2246 wait = sbic_data_wait; 2247 if( sbicxfstart(regs, 2248 acb->sc_kv.dc_count, 2249 SBIC_PHASE(csr), wait)) { 2250 if( SBIC_PHASE(csr) == DATA_IN_PHASE ) 2251 /* data in? */ 2252 i=sbicxfin(regs, 2253 acb->sc_kv.dc_count, 2254 acb->sc_kv.dc_addr); 2255 else 2256 i=sbicxfout(regs, 2257 acb->sc_kv.dc_count, 2258 acb->sc_kv.dc_addr, 2259 SBIC_PHASE(csr)); 2260 } 2261 acb->sc_kv.dc_addr += 2262 (acb->sc_kv.dc_count - i); 2263 acb->sc_kv.dc_count = i; 2264 } else { 2265 if (acb->sc_kv.dc_count <= 0) { 2266 printf("sbicnextstate:xfer count %d asr%x csr%x\n", 2267 acb->sc_kv.dc_count, asr, csr); 2268 goto abort; 2269 } 2270 /* 2271 * do scatter-gather dma 2272 * hacking the controller chip, ouch.. 2273 */ 2274 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI | 2275 SBIC_MACHINE_DMA_MODE); 2276 /* 2277 * set next dma addr and dec count 2278 */ 2279 #if 0 2280 SBIC_TC_GET(regs, tcnt); 2281 dev->sc_cur->dc_count -= ((dev->sc_tcnt - tcnt) >> 1); 2282 dev->sc_cur->dc_addr += (dev->sc_tcnt - tcnt); 2283 dev->sc_tcnt = acb->sc_tcnt = tcnt; 2284 #else 2285 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 2286 sbic_load_ptrs(dev, regs, dev->target, dev->lun); 2287 #endif 2288 #ifdef DEBUG 2289 if( data_pointer_debug > 1 ) 2290 printf("next dmanext: %d(%p:%lx)\n", 2291 dev->target,dev->sc_cur->dc_addr, 2292 dev->sc_tcnt); 2293 dev->sc_dmatimo = 1; 2294 #endif 2295 dev->sc_tcnt = dev->sc_dmanext(dev); 2296 SBIC_TC_PUT(regs, (unsigned)dev->sc_tcnt); 2297 SET_SBIC_cmd(regs, SBIC_CMD_XFER_INFO); 2298 dev->sc_flags |= SBICF_INDMA; 2299 } 2300 break; 2301 2302 case SBIC_CSR_XFERRED|MESG_IN_PHASE: 2303 case SBIC_CSR_MIS|MESG_IN_PHASE: 2304 case SBIC_CSR_MIS_1|MESG_IN_PHASE: 2305 case SBIC_CSR_MIS_2|MESG_IN_PHASE: 2306 SBIC_TRACE(dev); 2307 return sbicmsgin(dev); 2308 2309 case SBIC_CSR_MSGIN_W_ACK: 2310 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); /* Dunno what I'm ACKing */ 2311 printf("Acking unknown msgin CSR:%02x",csr); 2312 break; 2313 2314 case SBIC_CSR_XFERRED|MESG_OUT_PHASE: 2315 case SBIC_CSR_MIS|MESG_OUT_PHASE: 2316 case SBIC_CSR_MIS_1|MESG_OUT_PHASE: 2317 case SBIC_CSR_MIS_2|MESG_OUT_PHASE: 2318 #ifdef DEBUG 2319 if (sync_debug) 2320 printf ("sending REJECT msg to last msg.\n"); 2321 #endif 2322 2323 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 2324 /* 2325 * should only get here on reject, 2326 * since it's always US that 2327 * initiate a sync transfer 2328 */ 2329 SEND_BYTE(regs, MSG_REJECT); 2330 WAIT_CIP(regs); 2331 if( asr & (SBIC_ASR_BSY|SBIC_ASR_LCI|SBIC_ASR_CIP) ) 2332 printf("next: REJECT sent asr %02x\n", asr); 2333 SBIC_TRACE(dev); 2334 return SBIC_STATE_RUNNING; 2335 2336 case SBIC_CSR_DISC: 2337 case SBIC_CSR_DISC_1: 2338 dev->sc_flags &= ~(SBICF_INDMA|SBICF_SELECTED); 2339 2340 /* Try to schedule another target */ 2341 #ifdef DEBUG 2342 if(reselect_debug>1) 2343 printf("sbicnext target %d disconnected\n", dev->target); 2344 #endif 2345 TAILQ_INSERT_HEAD(&dev->nexus_list, acb, chain); 2346 ++dev->sc_tinfo[dev->target].dconns; 2347 dev->sc_nexus = NULL; 2348 dev->sc_xs = NULL; 2349 2350 if( acb->xs->xs_control & XS_CTL_POLL 2351 || (dev->sc_flags & SBICF_ICMD) 2352 || !sbic_parallel_operations ) { 2353 SBIC_TRACE(dev); 2354 return SBIC_STATE_DISCONNECT; 2355 } 2356 sbic_sched(dev); 2357 SBIC_TRACE(dev); 2358 return SBIC_STATE_DISCONNECT; 2359 2360 case SBIC_CSR_RSLT_NI: 2361 case SBIC_CSR_RSLT_IFY: 2362 GET_SBIC_rselid(regs, newtarget); 2363 /* check SBIC_RID_SIV? */ 2364 newtarget &= SBIC_RID_MASK; 2365 if (csr == SBIC_CSR_RSLT_IFY) { 2366 /* Read IFY msg to avoid lockup */ 2367 GET_SBIC_data(regs, newlun); 2368 WAIT_CIP(regs); 2369 newlun &= SBIC_TLUN_MASK; 2370 CSR_TRACE('r',csr,asr,newtarget); 2371 } else { 2372 /* Need to get IFY message */ 2373 for (newlun = 256; newlun; --newlun) { 2374 GET_SBIC_asr(regs, asr); 2375 if (asr & SBIC_ASR_INT) 2376 break; 2377 delay(1); 2378 } 2379 newlun = 0; /* XXXX */ 2380 if ((asr & SBIC_ASR_INT) == 0) { 2381 #ifdef DEBUG 2382 if (reselect_debug) 2383 printf("RSLT_NI - no IFFY message? asr %x\n", asr); 2384 #endif 2385 } else { 2386 GET_SBIC_csr(regs,csr); 2387 CSR_TRACE('n',csr,asr,newtarget); 2388 if (csr == (SBIC_CSR_MIS | MESG_IN_PHASE) || 2389 csr == (SBIC_CSR_MIS_1 | MESG_IN_PHASE) || 2390 csr == (SBIC_CSR_MIS_2 | MESG_IN_PHASE)) { 2391 sbicmsgin(dev); 2392 newlun = dev->sc_msg[0] & 7; 2393 } else { 2394 printf("RSLT_NI - not MESG_IN_PHASE %x\n", 2395 csr); 2396 } 2397 } 2398 } 2399 #ifdef DEBUG 2400 if(reselect_debug>1 || (reselect_debug && csr==SBIC_CSR_RSLT_NI)) 2401 printf("sbicnext: reselect %s from targ %d lun %d\n", 2402 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", 2403 newtarget, newlun); 2404 #endif 2405 if (dev->sc_nexus) { 2406 #ifdef DEBUG 2407 if (reselect_debug > 1) 2408 printf("%s: reselect %s with active command\n", 2409 dev->sc_dev.dv_xname, 2410 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY"); 2411 #ifdef DDB 2412 /* Debugger();*/ 2413 #endif 2414 #endif 2415 TAILQ_INSERT_HEAD(&dev->ready_list, dev->sc_nexus, chain); 2416 dev->sc_tinfo[dev->target].lubusy &= ~(1 << dev->lun); 2417 dev->sc_nexus = NULL; 2418 dev->sc_xs = NULL; 2419 } 2420 /* Reload sync values for this target */ 2421 if (dev->sc_sync[newtarget].state == SYNC_DONE) 2422 SET_SBIC_syn(regs, SBIC_SYN (dev->sc_sync[newtarget].offset, 2423 dev->sc_sync[newtarget].period)); 2424 else 2425 SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period)); 2426 for (acb = dev->nexus_list.tqh_first; acb; 2427 acb = acb->chain.tqe_next) { 2428 if (acb->xs->xs_periph->periph_target != newtarget || 2429 acb->xs->xs_periph->periph_lun != newlun) 2430 continue; 2431 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 2432 dev->sc_nexus = acb; 2433 dev->sc_xs = acb->xs; 2434 dev->sc_flags |= SBICF_SELECTED; 2435 dev->target = newtarget; 2436 dev->lun = newlun; 2437 break; 2438 } 2439 if (acb == NULL) { 2440 printf("%s: reselect %s targ %d not in nexus_list %p\n", 2441 dev->sc_dev.dv_xname, 2442 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", newtarget, 2443 &dev->nexus_list.tqh_first); 2444 panic("bad reselect in sbic"); 2445 } 2446 if (csr == SBIC_CSR_RSLT_IFY) 2447 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2448 break; 2449 2450 default: 2451 abort: 2452 /* 2453 * Something unexpected happened -- deal with it. 2454 */ 2455 printf("sbicnextstate: aborting csr %02x asr %02x\n", csr, asr); 2456 #ifdef DDB 2457 Debugger(); 2458 #endif 2459 #ifdef DEBUG 2460 if( data_pointer_debug > 1 ) 2461 printf("next dmastop: %d(%p:%lx)\n", 2462 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 2463 dev->sc_dmatimo = 0; 2464 #endif 2465 dev->sc_dmastop(dev); 2466 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2467 sbicerror(dev, regs, csr); 2468 sbicabort(dev, regs, "next"); 2469 if (dev->sc_flags & SBICF_INDMA) { 2470 /* 2471 * check for overlapping cache line, flush if so 2472 */ 2473 #if defined(M68040) || defined(M68060) 2474 if (dev->sc_flags & SBICF_DCFLUSH) { 2475 #if 0 2476 printf("sbic: 68040/060 DMA cache flush needs" 2477 "fixing? %x:%x\n", 2478 dev->sc_xs->data, dev->sc_xs->datalen); 2479 #endif 2480 } 2481 #endif 2482 dev->sc_flags &= 2483 ~(SBICF_INDMA | SBICF_DCFLUSH); 2484 #ifdef DEBUG 2485 if( data_pointer_debug > 1 ) 2486 printf("next dmastop: %d(%p:%lx)\n", 2487 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 2488 dev->sc_dmatimo = 0; 2489 #endif 2490 dev->sc_dmastop(dev); 2491 sbic_scsidone(acb, -1); 2492 } 2493 SBIC_TRACE(dev); 2494 return SBIC_STATE_ERROR; 2495 } 2496 2497 SBIC_TRACE(dev); 2498 return(SBIC_STATE_RUNNING); 2499 } 2500 2501 2502 /* 2503 * Check if DMA can not be used with specified buffer 2504 */ 2505 2506 int 2507 sbiccheckdmap(void *bp, u_long len, u_long mask) 2508 { 2509 u_char *buffer; 2510 u_long phy_buf; 2511 u_long phy_len; 2512 2513 buffer = bp; 2514 2515 if (len == 0) 2516 return(0); 2517 2518 while (len) { 2519 phy_buf = kvtop(buffer); 2520 if (len < (phy_len = NBPG - ((int) buffer & PGOFSET))) 2521 phy_len = len; 2522 if (phy_buf & mask) 2523 return(1); 2524 buffer += phy_len; 2525 len -= phy_len; 2526 } 2527 return(0); 2528 } 2529 2530 int 2531 sbictoscsiperiod(struct sbic_softc *dev, sbic_regmap_t regs, int a) 2532 { 2533 unsigned int fs; 2534 2535 /* 2536 * cycle = DIV / (2*CLK) 2537 * DIV = FS+2 2538 * best we can do is 200ns at 20Mhz, 2 cycles 2539 */ 2540 2541 GET_SBIC_myid(regs,fs); 2542 fs = (fs >>6) + 2; /* DIV */ 2543 fs = (fs * 10000) / (dev->sc_clkfreq<<1); /* Cycle, in ns */ 2544 if (a < 2) a = 8; /* map to Cycles */ 2545 return ((fs*a)>>2); /* in 4 ns units */ 2546 } 2547 2548 int 2549 sbicfromscsiperiod(struct sbic_softc *dev, sbic_regmap_t regs, int p) 2550 { 2551 register unsigned int fs, ret; 2552 2553 /* Just the inverse of the above */ 2554 2555 GET_SBIC_myid(regs,fs); 2556 fs = (fs >>6) + 2; /* DIV */ 2557 fs = (fs * 10000) / (dev->sc_clkfreq<<1); /* Cycle, in ns */ 2558 2559 ret = p << 2; /* in ns units */ 2560 ret = ret / fs; /* in Cycles */ 2561 if (ret < sbic_min_period) 2562 return(sbic_min_period); 2563 2564 /* verify rounding */ 2565 if (sbictoscsiperiod(dev, regs, ret) < p) 2566 ret++; 2567 return (ret >= 8) ? 0 : ret; 2568 } 2569 2570 #ifdef DEBUG 2571 2572 void 2573 sbicdumpstate(void) 2574 { 2575 u_char csr, asr; 2576 2577 GET_SBIC_asr(debug_sbic_regs,asr); 2578 GET_SBIC_csr(debug_sbic_regs,csr); 2579 printf("%s: asr:csr(%02x:%02x)->(%02x:%02x)\n", 2580 (routine==1)?"sbicgo": 2581 (routine==2)?"sbicintr": 2582 (routine==3)?"sbicicmd": 2583 (routine==4)?"sbicnext":"unknown", 2584 debug_asr, debug_csr, asr, csr); 2585 2586 } 2587 2588 void 2589 sbictimeout(struct sbic_softc *dev) 2590 { 2591 int s, asr; 2592 2593 s = splbio(); 2594 if (dev->sc_dmatimo) { 2595 if (dev->sc_dmatimo > 1) { 2596 printf("%s: dma timeout #%d\n", 2597 dev->sc_dev.dv_xname, dev->sc_dmatimo - 1); 2598 GET_SBIC_asr(dev->sc_sbic, asr); 2599 if( asr & SBIC_ASR_INT ) { 2600 /* We need to service a missed IRQ */ 2601 printf("Servicing a missed int:(%02x,%02x)->(%02x,??)\n", 2602 debug_asr, debug_csr, asr); 2603 sbicintr(dev); 2604 } 2605 sbicdumpstate(); 2606 } 2607 dev->sc_dmatimo++; 2608 } 2609 splx(s); 2610 callout_reset(&dev->sc_timo_ch, 30 * hz, 2611 (void *)sbictimeout, dev); 2612 } 2613 2614 void 2615 sbic_dump_acb(struct sbic_acb *acb) 2616 { 2617 u_char *b = (u_char *) &acb->cmd; 2618 int i; 2619 2620 printf("acb@%p ", acb); 2621 if (acb->xs == NULL) { 2622 printf("<unused>\n"); 2623 return; 2624 } 2625 printf("(%d:%d) flags %2x clen %2d cmd ", 2626 acb->xs->xs_periph->periph_target, 2627 acb->xs->xs_periph->periph_lun, acb->flags, acb->clen); 2628 for (i = acb->clen; i; --i) 2629 printf(" %02x", *b++); 2630 printf("\n"); 2631 printf(" xs: %8p data %8p:%04x ", acb->xs, acb->xs->data, 2632 acb->xs->datalen); 2633 printf("va %8p:%04x ", acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 2634 printf("pa %8p:%04x tcnt %lx\n", acb->sc_pa.dc_addr, acb->sc_pa.dc_count, 2635 acb->sc_tcnt); 2636 } 2637 2638 void 2639 sbic_dump(struct sbic_softc *dev) 2640 { 2641 sbic_regmap_t regs; 2642 u_char csr, asr; 2643 struct sbic_acb *acb; 2644 int s; 2645 int i; 2646 2647 s = splbio(); 2648 regs = dev->sc_sbic; 2649 #if CSR_TRACE_SIZE 2650 printf("csr trace: "); 2651 i = csr_traceptr; 2652 do { 2653 printf("%c%02x%02x%02x ", csr_trace[i].whr, 2654 csr_trace[i].csr, csr_trace[i].asr, csr_trace[i].xtn); 2655 switch(csr_trace[i].whr) { 2656 case 'g': 2657 printf("go "); break; 2658 case 's': 2659 printf("select "); break; 2660 case 'y': 2661 printf("select+ "); break; 2662 case 'i': 2663 printf("intr "); break; 2664 case 'f': 2665 printf("finish "); break; 2666 case '>': 2667 printf("out "); break; 2668 case '<': 2669 printf("in "); break; 2670 case 'm': 2671 printf("msgin "); break; 2672 case 'x': 2673 printf("msginx "); break; 2674 case 'X': 2675 printf("msginX "); break; 2676 case 'r': 2677 printf("reselect "); break; 2678 case 'I': 2679 printf("icmd "); break; 2680 case 'a': 2681 printf("abort "); break; 2682 default: 2683 printf("? "); 2684 } 2685 switch(csr_trace[i].csr) { 2686 case 0x11: 2687 printf("INITIATOR"); break; 2688 case 0x16: 2689 printf("S_XFERRED"); break; 2690 case 0x20: 2691 printf("MSGIN_ACK"); break; 2692 case 0x41: 2693 printf("DISC"); break; 2694 case 0x42: 2695 printf("SEL_TIMEO"); break; 2696 case 0x80: 2697 printf("RSLT_NI"); break; 2698 case 0x81: 2699 printf("RSLT_IFY"); break; 2700 case 0x85: 2701 printf("DISC_1"); break; 2702 case 0x18: case 0x19: case 0x1a: 2703 case 0x1b: case 0x1e: case 0x1f: 2704 case 0x28: case 0x29: case 0x2a: 2705 case 0x2b: case 0x2e: case 0x2f: 2706 case 0x48: case 0x49: case 0x4a: 2707 case 0x4b: case 0x4e: case 0x4f: 2708 case 0x88: case 0x89: case 0x8a: 2709 case 0x8b: case 0x8e: case 0x8f: 2710 switch(csr_trace[i].csr & 0xf0) { 2711 case 0x10: 2712 printf("DONE_"); break; 2713 case 0x20: 2714 printf("STOP_"); break; 2715 case 0x40: 2716 printf("ERR_"); break; 2717 case 0x80: 2718 printf("REQ_"); break; 2719 } 2720 switch(csr_trace[i].csr & 7) { 2721 case 0: 2722 printf("DATA_OUT"); break; 2723 case 1: 2724 printf("DATA_IN"); break; 2725 case 2: 2726 printf("CMD"); break; 2727 case 3: 2728 printf("STATUS"); break; 2729 case 6: 2730 printf("MSG_OUT"); break; 2731 case 7: 2732 printf("MSG_IN"); break; 2733 default: 2734 printf("invld phs"); 2735 } 2736 break; 2737 default: printf("****"); break; 2738 } 2739 if (csr_trace[i].asr & SBIC_ASR_INT) 2740 printf(" ASR_INT"); 2741 if (csr_trace[i].asr & SBIC_ASR_LCI) 2742 printf(" ASR_LCI"); 2743 if (csr_trace[i].asr & SBIC_ASR_BSY) 2744 printf(" ASR_BSY"); 2745 if (csr_trace[i].asr & SBIC_ASR_CIP) 2746 printf(" ASR_CIP"); 2747 printf("\n"); 2748 i = (i + 1) & (CSR_TRACE_SIZE - 1); 2749 } while (i != csr_traceptr); 2750 #endif 2751 GET_SBIC_asr(regs, asr); 2752 if ((asr & SBIC_ASR_INT) == 0) 2753 GET_SBIC_csr(regs, csr); 2754 else 2755 csr = 0; 2756 printf("%s@%p regs %p/%p asr %x csr %x\n", dev->sc_dev.dv_xname, 2757 dev, regs.sbic_asr_p, regs.sbic_value_p, asr, csr); 2758 if ((acb = dev->free_list.tqh_first)) { 2759 printf("Free list:\n"); 2760 while (acb) { 2761 sbic_dump_acb(acb); 2762 acb = acb->chain.tqe_next; 2763 } 2764 } 2765 if ((acb = dev->ready_list.tqh_first)) { 2766 printf("Ready list:\n"); 2767 while (acb) { 2768 sbic_dump_acb(acb); 2769 acb = acb->chain.tqe_next; 2770 } 2771 } 2772 if ((acb = dev->nexus_list.tqh_first)) { 2773 printf("Nexus list:\n"); 2774 while (acb) { 2775 sbic_dump_acb(acb); 2776 acb = acb->chain.tqe_next; 2777 } 2778 } 2779 if (dev->sc_nexus) { 2780 printf("nexus:\n"); 2781 sbic_dump_acb(dev->sc_nexus); 2782 } 2783 printf("sc_xs %p targ %d lun %d flags %x tcnt %lx dmacmd %x mask %lx\n", 2784 dev->sc_xs, dev->target, dev->lun, dev->sc_flags, dev->sc_tcnt, 2785 dev->sc_dmacmd, dev->sc_dmamask); 2786 for (i = 0; i < 8; ++i) { 2787 if (dev->sc_tinfo[i].cmds > 2) { 2788 printf("tgt %d: cmds %d disc %d lubusy %x\n", 2789 i, dev->sc_tinfo[i].cmds, 2790 dev->sc_tinfo[i].dconns, 2791 dev->sc_tinfo[i].lubusy); 2792 } 2793 } 2794 splx(s); 2795 } 2796 2797 #endif 2798
Indexes created Fri Sep 26 08:10:20 GMT 2025