sbic.c revision 1.46
1 /* $NetBSD: sbic.c,v 1.46 2002/01/28 09:57:02 aymeric Exp $ */ 2 3 /* 4 * Copyright (c) 1994 Christian E. Hopps 5 * Copyright (c) 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * Van Jacobson of Lawrence Berkeley Laboratory. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the University of 22 * California, Berkeley and its contributors. 23 * 4. Neither the name of the University nor the names of its contributors 24 * may be used to endorse or promote products derived from this software 25 * without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 37 * SUCH DAMAGE. 38 * 39 * @(#)scsi.c 7.5 (Berkeley) 5/4/91 40 */ 41 42 /* 43 * AMIGA AMD 33C93 scsi adaptor driver 44 */ 45 46 #include "opt_ddb.h" 47 48 #include <sys/cdefs.h> 49 __KERNEL_RCSID(0, "$NetBSD: sbic.c,v 1.46 2002/01/28 09:57:02 aymeric Exp $"); 50 51 #include <sys/param.h> 52 #include <sys/systm.h> 53 #include <sys/device.h> 54 #include <sys/kernel.h> /* For hz */ 55 #include <sys/disklabel.h> 56 #include <sys/dkstat.h> 57 #include <sys/buf.h> 58 #include <dev/scsipi/scsi_all.h> 59 #include <dev/scsipi/scsipi_all.h> 60 #include <dev/scsipi/scsiconf.h> 61 #include <uvm/uvm_extern.h> 62 #include <machine/cpu.h> 63 #include <amiga/amiga/device.h> 64 #include <amiga/amiga/custom.h> 65 #include <amiga/amiga/isr.h> 66 #include <amiga/dev/dmavar.h> 67 #include <amiga/dev/sbicreg.h> 68 #include <amiga/dev/sbicvar.h> 69 70 /* These are for bounce buffers */ 71 #include <amiga/amiga/cc.h> 72 #include <amiga/dev/zbusvar.h> 73 74 /* Since I can't find this in any other header files */ 75 #define SCSI_PHASE(reg) (reg&0x07) 76 77 /* 78 * SCSI delays 79 * In u-seconds, primarily for state changes on the SPC. 80 */ 81 #define SBIC_CMD_WAIT 50000 /* wait per step of 'immediate' cmds */ 82 #define SBIC_DATA_WAIT 50000 /* wait per data in/out step */ 83 #define SBIC_INIT_WAIT 50000 /* wait per step (both) during init */ 84 85 #define SBIC_WAIT(regs, until, timeo) sbicwait(regs, until, timeo, __LINE__) 86 87 int sbicicmd(struct sbic_softc *, int, int, void *, int, void *, int); 88 int sbicgo(struct sbic_softc *, struct scsipi_xfer *); 89 int sbicdmaok(struct sbic_softc *, struct scsipi_xfer *); 90 int sbicwait(sbic_regmap_t, char, int , int); 91 int sbiccheckdmap(void *, u_long, u_long); 92 int sbicselectbus(struct sbic_softc *, sbic_regmap_t, u_char, u_char, u_char); 93 int sbicxfstart(sbic_regmap_t, int, u_char, int); 94 int sbicxfout(sbic_regmap_t regs, int, void *, int); 95 int sbicfromscsiperiod(struct sbic_softc *, sbic_regmap_t, int); 96 int sbictoscsiperiod(struct sbic_softc *, sbic_regmap_t, int); 97 int sbicpoll(struct sbic_softc *); 98 int sbicnextstate(struct sbic_softc *, u_char, u_char); 99 int sbicmsgin(struct sbic_softc *); 100 int sbicxfin(sbic_regmap_t regs, int, void *); 101 int sbicabort(struct sbic_softc *, sbic_regmap_t, char *); 102 void sbicxfdone(struct sbic_softc *, sbic_regmap_t, int); 103 void sbicerror(struct sbic_softc *, sbic_regmap_t, u_char); 104 void sbicstart(struct sbic_softc *); 105 void sbicreset(struct sbic_softc *); 106 void sbic_scsidone(struct sbic_acb *, int); 107 void sbic_sched(struct sbic_softc *); 108 void sbic_save_ptrs(struct sbic_softc *, sbic_regmap_t,int,int); 109 void sbic_load_ptrs(struct sbic_softc *, sbic_regmap_t,int,int); 110 #ifdef DEBUG 111 void sbicdumpstate(void); 112 void sbic_dump_acb(struct sbic_acb *); 113 #endif 114 115 /* 116 * Synch xfer parameters, and timing conversions 117 */ 118 int sbic_min_period = SBIC_SYN_MIN_PERIOD; /* in cycles = f(ICLK,FSn) */ 119 int sbic_max_offset = SBIC_SYN_MAX_OFFSET; /* pure number */ 120 121 int sbic_cmd_wait = SBIC_CMD_WAIT; 122 int sbic_data_wait = SBIC_DATA_WAIT; 123 int sbic_init_wait = SBIC_INIT_WAIT; 124 125 /* 126 * was broken before.. now if you want this you get it for all drives 127 * on sbic controllers. 128 */ 129 u_char sbic_inhibit_sync[8]; 130 int sbic_enable_reselect = 1; 131 int sbic_clock_override = 0; 132 int sbic_no_dma = 0; 133 int sbic_parallel_operations = 1; 134 135 #ifdef DEBUG 136 sbic_regmap_t debug_sbic_regs; 137 int sbicdma_ops = 0; /* total DMA operations */ 138 int sbicdma_bounces = 0; /* number operations using bounce buffer */ 139 int sbicdma_hits = 0; /* number of DMA chains that were contiguous */ 140 int sbicdma_misses = 0; /* number of DMA chains that were not contiguous */ 141 int sbicdma_saves = 0; 142 #define QPRINTF(a) if (sbic_debug > 1) printf a 143 int sbic_debug = 0; 144 int sync_debug = 0; 145 int sbic_dma_debug = 0; 146 int reselect_debug = 0; 147 int data_pointer_debug = 0; 148 u_char debug_asr, debug_csr, routine; 149 void sbictimeout(struct sbic_softc *dev); 150 151 #define CSR_TRACE_SIZE 32 152 #if CSR_TRACE_SIZE 153 #define CSR_TRACE(w,c,a,x) do { \ 154 int s = splbio(); \ 155 csr_trace[csr_traceptr].whr = (w); csr_trace[csr_traceptr].csr = (c); \ 156 csr_trace[csr_traceptr].asr = (a); csr_trace[csr_traceptr].xtn = (x); \ 157 dma_cachectl((caddr_t)&csr_trace[csr_traceptr], sizeof(csr_trace[0])); \ 158 csr_traceptr = (csr_traceptr + 1) & (CSR_TRACE_SIZE - 1); \ 159 /* dma_cachectl((caddr_t)&csr_traceptr, sizeof(csr_traceptr));*/ \ 160 splx(s); \ 161 } while (0) 162 int csr_traceptr; 163 int csr_tracesize = CSR_TRACE_SIZE; 164 struct { 165 u_char whr; 166 u_char csr; 167 u_char asr; 168 u_char xtn; 169 } csr_trace[CSR_TRACE_SIZE]; 170 #else 171 #define CSR_TRACE(w,c,a,x) 172 #endif 173 174 #define SBIC_TRACE_SIZE 0 175 #if SBIC_TRACE_SIZE 176 #define SBIC_TRACE(dev) do { \ 177 int s = splbio(); \ 178 sbic_trace[sbic_traceptr].sp = &s; \ 179 sbic_trace[sbic_traceptr].line = __LINE__; \ 180 sbic_trace[sbic_traceptr].sr = s; \ 181 sbic_trace[sbic_traceptr].csr = csr_traceptr; \ 182 dma_cachectl(&sbic_trace[sbic_traceptr], sizeof(sbic_trace[0])); \ 183 sbic_traceptr = (sbic_traceptr + 1) & (SBIC_TRACE_SIZE - 1); \ 184 dma_cachectl(&sbic_traceptr, sizeof(sbic_traceptr)); \ 185 if (dev) dma_cachectl(dev, sizeof(*dev)); \ 186 splx(s); \ 187 } while (0) 188 int sbic_traceptr; 189 int sbic_tracesize = SBIC_TRACE_SIZE; 190 struct { 191 void *sp; 192 u_short line; 193 u_short sr; 194 int csr; 195 } sbic_trace[SBIC_TRACE_SIZE]; 196 #else 197 #define SBIC_TRACE(dev) 198 #endif 199 200 #else /* DEBUG */ 201 #define QPRINTF(a) 202 #define CSR_TRACE(w,c,a,x) 203 #define SBIC_TRACE(dev) 204 #endif /* DEBUG */ 205 206 /* 207 * default minphys routine for sbic based controllers 208 */ 209 void 210 sbic_minphys(struct buf *bp) 211 { 212 213 /* 214 * No max transfer at this level. 215 */ 216 minphys(bp); 217 } 218 219 /* 220 * Save DMA pointers. Take into account partial transfer. Shut down DMA. 221 */ 222 void 223 sbic_save_ptrs(struct sbic_softc *dev, sbic_regmap_t regs, int target, int lun) 224 { 225 int count, asr, s; 226 struct sbic_acb* acb; 227 228 SBIC_TRACE(dev); 229 if( !dev->sc_cur ) return; 230 if( !(dev->sc_flags & SBICF_INDMA) ) return; /* DMA not active */ 231 232 s = splbio(); 233 234 acb = dev->sc_nexus; 235 count = -1; 236 do { 237 GET_SBIC_asr(regs, asr); 238 if( asr & SBIC_ASR_DBR ) { 239 printf("sbic_save_ptrs: asr %02x canceled!\n", asr); 240 splx(s); 241 SBIC_TRACE(dev); 242 return; 243 } 244 } while( asr & (SBIC_ASR_BSY|SBIC_ASR_CIP) ); 245 246 /* Save important state */ 247 /* must be done before dmastop */ 248 acb->sc_dmacmd = dev->sc_dmacmd; 249 SBIC_TC_GET(regs, count); 250 251 /* Shut down DMA ====CAREFUL==== */ 252 dev->sc_dmastop(dev); 253 dev->sc_flags &= ~SBICF_INDMA; 254 SBIC_TC_PUT(regs, 0); 255 256 #ifdef DEBUG 257 if(!count && sbic_debug) printf("%dcount0",target); 258 if(data_pointer_debug == -1) 259 printf("SBIC saving target %d data pointers from (%p,%x)%xASR:%02x", 260 target, dev->sc_cur->dc_addr, dev->sc_cur->dc_count, 261 acb->sc_dmacmd, asr); 262 #endif 263 264 /* Fixup partial xfers */ 265 acb->sc_kv.dc_addr += (dev->sc_tcnt - count); 266 acb->sc_kv.dc_count -= (dev->sc_tcnt - count); 267 acb->sc_pa.dc_addr += (dev->sc_tcnt - count); 268 acb->sc_pa.dc_count -= ((dev->sc_tcnt - count)>>1); 269 270 acb->sc_tcnt = dev->sc_tcnt = count; 271 #ifdef DEBUG 272 if(data_pointer_debug) 273 printf(" at (%p,%x):%x\n", 274 dev->sc_cur->dc_addr, dev->sc_cur->dc_count,count); 275 sbicdma_saves++; 276 #endif 277 splx(s); 278 SBIC_TRACE(dev); 279 } 280 281 282 /* 283 * DOES NOT RESTART DMA!!! 284 */ 285 void 286 sbic_load_ptrs(struct sbic_softc *dev, sbic_regmap_t regs, int target, int lun) 287 { 288 int s, count; 289 char* vaddr, * paddr; 290 struct sbic_acb *acb; 291 292 SBIC_TRACE(dev); 293 acb = dev->sc_nexus; 294 if( !acb->sc_kv.dc_count ) { 295 /* No data to xfer */ 296 SBIC_TRACE(dev); 297 return; 298 } 299 300 s = splbio(); 301 302 dev->sc_last = dev->sc_cur = &acb->sc_pa; 303 dev->sc_tcnt = acb->sc_tcnt; 304 dev->sc_dmacmd = acb->sc_dmacmd; 305 306 #ifdef DEBUG 307 sbicdma_ops++; 308 #endif 309 if( !dev->sc_tcnt ) { 310 /* sc_tcnt == 0 implies end of segment */ 311 312 /* do kvm to pa mappings */ 313 paddr = acb->sc_pa.dc_addr = 314 (char *) kvtop(acb->sc_kv.dc_addr); 315 316 vaddr = acb->sc_kv.dc_addr; 317 count = acb->sc_kv.dc_count; 318 for(count = (NBPG - ((int)vaddr & PGOFSET)); 319 count < acb->sc_kv.dc_count 320 && (char*)kvtop(vaddr + count + 4) == paddr + count + 4; 321 count += NBPG); 322 /* If it's all contiguous... */ 323 if(count > acb->sc_kv.dc_count ) { 324 count = acb->sc_kv.dc_count; 325 #ifdef DEBUG 326 sbicdma_hits++; 327 #endif 328 } else { 329 #ifdef DEBUG 330 sbicdma_misses++; 331 #endif 332 } 333 acb->sc_tcnt = count; 334 acb->sc_pa.dc_count = count >> 1; 335 336 #ifdef DEBUG 337 if(data_pointer_debug) 338 printf("DMA recalc:kv(%p,%x)pa(%p,%lx)\n", 339 acb->sc_kv.dc_addr, 340 acb->sc_kv.dc_count, 341 acb->sc_pa.dc_addr, 342 acb->sc_tcnt); 343 #endif 344 } 345 splx(s); 346 #ifdef DEBUG 347 if(data_pointer_debug) 348 printf("SBIC restoring target %d data pointers at (%p,%x)%x\n", 349 target, dev->sc_cur->dc_addr, dev->sc_cur->dc_count, 350 dev->sc_dmacmd); 351 #endif 352 SBIC_TRACE(dev); 353 } 354 355 /* 356 * used by specific sbic controller 357 * 358 * it appears that the higher level code does nothing with LUN's 359 * so I will too. I could plug it in, however so could they 360 * in scsi_scsipi_cmd(). 361 */ 362 void 363 sbic_scsipi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req, 364 void *arg) 365 { 366 struct scsipi_xfer *xs; 367 struct scsipi_periph *periph; 368 struct sbic_acb *acb; 369 struct sbic_softc *dev = (void *)chan->chan_adapter->adapt_dev; 370 int flags, s, stat; 371 372 switch (req) { 373 case ADAPTER_REQ_RUN_XFER: 374 xs = arg; 375 periph = xs->xs_periph; 376 377 SBIC_TRACE(dev); 378 flags = xs->xs_control; 379 380 if (flags & XS_CTL_DATA_UIO) 381 panic("sbic: scsi data uio requested"); 382 383 if (dev->sc_nexus && flags & XS_CTL_POLL) 384 panic("sbic_scsipi_request: busy"); 385 386 s = splbio(); 387 acb = dev->free_list.tqh_first; 388 if (acb) 389 TAILQ_REMOVE(&dev->free_list, acb, chain); 390 splx(s); 391 392 #ifdef DIAGNOSTIC 393 if (acb == NULL) { 394 scsipi_printaddr(periph); 395 printf("unable to allocate acb\n"); 396 panic("sbic_scsipi_request"); 397 } 398 #endif 399 acb->flags = ACB_ACTIVE; 400 if (flags & XS_CTL_DATA_IN) 401 acb->flags |= ACB_DATAIN; 402 acb->xs = xs; 403 bcopy(xs->cmd, &acb->cmd, xs->cmdlen); 404 acb->clen = xs->cmdlen; 405 acb->sc_kv.dc_addr = xs->data; 406 acb->sc_kv.dc_count = xs->datalen; 407 acb->pa_addr = xs->data ? (char *)kvtop(xs->data) : 0; /* XXXX check */ 408 409 if (flags & XS_CTL_POLL) { 410 s = splbio(); 411 /* 412 * This has major side effects - it locks up the machine 413 */ 414 415 dev->sc_flags |= SBICF_ICMD; 416 do { 417 while(dev->sc_nexus) 418 sbicpoll(dev); 419 dev->sc_nexus = acb; 420 dev->sc_stat[0] = -1; 421 dev->sc_xs = xs; 422 dev->target = periph->periph_target; 423 dev->lun = periph->periph_lun; 424 stat = sbicicmd(dev, dev->target, dev->lun, 425 &acb->cmd, acb->clen, 426 acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 427 } while (dev->sc_nexus != acb); 428 sbic_scsidone(acb, stat); 429 430 splx(s); 431 SBIC_TRACE(dev); 432 return; 433 } 434 435 s = splbio(); 436 TAILQ_INSERT_TAIL(&dev->ready_list, acb, chain); 437 438 if (dev->sc_nexus) { 439 splx(s); 440 SBIC_TRACE(dev); 441 return; 442 } 443 444 /* 445 * nothing is active, try to start it now. 446 */ 447 sbic_sched(dev); 448 splx(s); 449 450 SBIC_TRACE(dev); 451 /* TODO: add sbic_poll to do XS_CTL_POLL operations */ 452 #if 0 453 if (flags & XS_CTL_POLL) 454 return(COMPLETE); 455 #endif 456 return; 457 458 case ADAPTER_REQ_GROW_RESOURCES: 459 return; 460 461 case ADAPTER_REQ_SET_XFER_MODE: 462 return; 463 } 464 } 465 466 /* 467 * attempt to start the next available command 468 */ 469 void 470 sbic_sched(struct sbic_softc *dev) 471 { 472 struct scsipi_xfer *xs; 473 struct scsipi_periph *periph; 474 struct sbic_acb *acb; 475 int flags, /*phase,*/ stat, i; 476 477 SBIC_TRACE(dev); 478 if (dev->sc_nexus) 479 return; /* a command is current active */ 480 481 SBIC_TRACE(dev); 482 for (acb = dev->ready_list.tqh_first; acb; acb = acb->chain.tqe_next) { 483 periph = acb->xs->xs_periph; 484 i = periph->periph_target; 485 if (!(dev->sc_tinfo[i].lubusy & (1 << periph->periph_lun))) { 486 struct sbic_tinfo *ti = &dev->sc_tinfo[i]; 487 488 TAILQ_REMOVE(&dev->ready_list, acb, chain); 489 dev->sc_nexus = acb; 490 ti = &dev->sc_tinfo[periph->periph_target]; 491 ti->lubusy |= (1 << periph->periph_lun); 492 acb->sc_pa.dc_addr = acb->pa_addr; /* XXXX check */ 493 break; 494 } 495 } 496 497 SBIC_TRACE(dev); 498 if (acb == NULL) 499 return; /* did not find an available command */ 500 501 dev->sc_xs = xs = acb->xs; 502 periph = xs->xs_periph; 503 flags = xs->xs_control; 504 505 if (flags & XS_CTL_RESET) 506 sbicreset(dev); 507 508 #ifdef DEBUG 509 if( data_pointer_debug > 1 ) 510 printf("sbic_sched(%d,%d)\n", periph->periph_target, 511 periph->periph_lun); 512 #endif 513 dev->sc_stat[0] = -1; 514 dev->target = periph->periph_target; 515 dev->lun = periph->periph_lun; 516 if ( flags & XS_CTL_POLL || ( !sbic_parallel_operations 517 && (sbicdmaok(dev, xs) == 0))) 518 stat = sbicicmd(dev, periph->periph_target, 519 periph->periph_lun, &acb->cmd, 520 acb->clen, acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 521 else if (sbicgo(dev, xs) == 0 && xs->error != XS_SELTIMEOUT) { 522 SBIC_TRACE(dev); 523 return; 524 } else 525 stat = dev->sc_stat[0]; 526 527 sbic_scsidone(acb, stat); 528 SBIC_TRACE(dev); 529 } 530 531 void 532 sbic_scsidone(struct sbic_acb *acb, int stat) 533 { 534 struct scsipi_xfer *xs; 535 struct scsipi_periph *periph; 536 struct sbic_softc *dev; 537 int dosched = 0; 538 539 xs = acb->xs; 540 periph = xs->xs_periph; 541 dev = (void *)periph->periph_channel->chan_adapter->adapt_dev; 542 SBIC_TRACE(dev); 543 #ifdef DIAGNOSTIC 544 if (acb == NULL || xs == NULL) { 545 printf("sbic_scsidone -- (%d,%d) no scsi_xfer\n", 546 dev->target, dev->lun); 547 #ifdef DDB 548 Debugger(); 549 #endif 550 return; 551 } 552 #endif 553 554 xs->status = stat; 555 xs->resid = 0; /* XXXX */ 556 #ifdef DEBUG 557 if( data_pointer_debug > 1 ) 558 printf("scsidone: (%d,%d)->(%d,%d)%02x\n", 559 periph->periph_target, periph->periph_lun, 560 dev->target, dev->lun, stat); 561 if( periph->periph_target == 562 periph->periph_channel->chan_id) 563 panic("target == hostid"); 564 #endif 565 566 if (xs->error == XS_NOERROR) { 567 if (stat == SCSI_CHECK || stat == SCSI_BUSY) 568 xs->error = XS_BUSY; 569 } 570 571 /* 572 * Remove the ACB from whatever queue it's on. We have to do a bit of 573 * a hack to figure out which queue it's on. Note that it is *not* 574 * necessary to cdr down the ready queue, but we must cdr down the 575 * nexus queue and see if it's there, so we can mark the unit as no 576 * longer busy. This code is sickening, but it works. 577 */ 578 if (acb == dev->sc_nexus) { 579 dev->sc_nexus = NULL; 580 dev->sc_xs = NULL; 581 dev->sc_tinfo[periph->periph_target].lubusy &= 582 ~(1<<periph->periph_lun); 583 if (dev->ready_list.tqh_first) 584 dosched = 1; /* start next command */ 585 } else if (dev->ready_list.tqh_last == &acb->chain.tqe_next) { 586 TAILQ_REMOVE(&dev->ready_list, acb, chain); 587 } else { 588 register struct sbic_acb *acb2; 589 for (acb2 = dev->nexus_list.tqh_first; acb2; 590 acb2 = acb2->chain.tqe_next) { 591 if (acb2 == acb) { 592 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 593 dev->sc_tinfo[periph->periph_target].lubusy 594 &= ~(1<<periph->periph_lun); 595 break; 596 } 597 } 598 if (acb2) 599 ; 600 else if (acb->chain.tqe_next) { 601 TAILQ_REMOVE(&dev->ready_list, acb, chain); 602 } else { 603 printf("%s: can't find matching acb\n", 604 dev->sc_dev.dv_xname); 605 #ifdef DDB 606 Debugger(); 607 #endif 608 } 609 } 610 /* Put it on the free list. */ 611 acb->flags = ACB_FREE; 612 TAILQ_INSERT_HEAD(&dev->free_list, acb, chain); 613 614 dev->sc_tinfo[periph->periph_target].cmds++; 615 616 scsipi_done(xs); 617 618 if (dosched) 619 sbic_sched(dev); 620 SBIC_TRACE(dev); 621 } 622 623 int 624 sbicdmaok(struct sbic_softc *dev, struct scsipi_xfer *xs) 625 { 626 if (sbic_no_dma || !xs->datalen || xs->datalen & 0x1 || 627 (u_int)xs->data & 0x3) 628 return(0); 629 /* 630 * controller supports dma to any addresses? 631 */ 632 else if ((dev->sc_flags & SBICF_BADDMA) == 0) 633 return(1); 634 /* 635 * this address is ok for dma? 636 */ 637 else if (sbiccheckdmap(xs->data, xs->datalen, dev->sc_dmamask) == 0) 638 return(1); 639 /* 640 * we have a bounce buffer? 641 */ 642 else if (dev->sc_tinfo[xs->xs_periph->periph_target].bounce) 643 return(1); 644 /* 645 * try to get one 646 */ 647 else if ((dev->sc_tinfo[xs->xs_periph->periph_target].bounce 648 = (char *)alloc_z2mem(MAXPHYS))) { 649 if (isztwomem(dev->sc_tinfo[xs->xs_periph->periph_target].bounce)) 650 printf("alloc ZII target %d bounce pa 0x%x\n", 651 xs->xs_periph->periph_target, 652 kvtop(dev->sc_tinfo[xs->xs_periph->periph_target].bounce)); 653 else if (dev->sc_tinfo[xs->xs_periph->periph_target].bounce) 654 printf("alloc CHIP target %d bounce pa 0x%p\n", 655 xs->xs_periph->periph_target, 656 PREP_DMA_MEM(dev->sc_tinfo[xs->xs_periph->periph_target].bounce)); 657 return(1); 658 } 659 660 return(0); 661 } 662 663 664 int 665 sbicwait(sbic_regmap_t regs, char until, int timeo, int line) 666 { 667 u_char val; 668 int csr; 669 670 SBIC_TRACE((struct sbic_softc *)0); 671 if (timeo == 0) 672 timeo = 1000000; /* some large value.. */ 673 674 GET_SBIC_asr(regs,val); 675 while ((val & until) == 0) { 676 if (timeo-- == 0) { 677 GET_SBIC_csr(regs, csr); 678 printf("sbicwait TIMEO @%d with asr=x%x csr=x%x\n", 679 line, val, csr); 680 #if defined(DDB) && defined(DEBUG) 681 Debugger(); 682 #endif 683 return(val); /* Maybe I should abort */ 684 break; 685 } 686 DELAY(1); 687 GET_SBIC_asr(regs,val); 688 } 689 SBIC_TRACE((struct sbic_softc *)0); 690 return(val); 691 } 692 693 int 694 sbicabort(struct sbic_softc *dev, sbic_regmap_t regs, char *where) 695 { 696 u_char csr, asr; 697 698 GET_SBIC_asr(regs, asr); 699 GET_SBIC_csr(regs, csr); 700 701 printf ("%s: abort %s: csr = 0x%02x, asr = 0x%02x\n", 702 dev->sc_dev.dv_xname, where, csr, asr); 703 704 705 #if 0 706 /* Clean up running command */ 707 if (dev->sc_nexus != NULL) { 708 dev->sc_nexus->xs->error = XS_DRIVER_STUFFUP; 709 sbic_scsidone(dev->sc_nexus, dev->sc_stat[0]); 710 } 711 while (acb = dev->nexus_list.tqh_first) { 712 acb->xs->error = XS_DRIVER_STUFFUP; 713 sbic_scsidone(acb, -1 /*acb->stat[0]*/); 714 } 715 #endif 716 717 /* Clean up chip itself */ 718 if (dev->sc_flags & SBICF_SELECTED) { 719 while( asr & SBIC_ASR_DBR ) { 720 /* sbic is jammed w/data. need to clear it */ 721 /* But we don't know what direction it needs to go */ 722 GET_SBIC_data(regs, asr); 723 printf("%s: abort %s: clearing data buffer 0x%02x\n", 724 dev->sc_dev.dv_xname, where, asr); 725 GET_SBIC_asr(regs, asr); 726 if( asr & SBIC_ASR_DBR ) /* Not the read direction, then */ 727 SET_SBIC_data(regs, asr); 728 GET_SBIC_asr(regs, asr); 729 } 730 WAIT_CIP(regs); 731 printf("%s: sbicabort - sending ABORT command\n", dev->sc_dev.dv_xname); 732 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 733 WAIT_CIP(regs); 734 735 GET_SBIC_asr(regs, asr); 736 if (asr & (SBIC_ASR_BSY|SBIC_ASR_LCI)) { 737 /* ok, get more drastic.. */ 738 739 printf("%s: sbicabort - asr %x, trying to reset\n", dev->sc_dev.dv_xname, asr); 740 sbicreset(dev); 741 dev->sc_flags &= ~SBICF_SELECTED; 742 return -1; 743 } 744 printf("%s: sbicabort - sending DISC command\n", dev->sc_dev.dv_xname); 745 SET_SBIC_cmd(regs, SBIC_CMD_DISC); 746 747 do { 748 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0); 749 GET_SBIC_csr (regs, csr); 750 CSR_TRACE('a',csr,asr,0); 751 } while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) 752 && (csr != SBIC_CSR_CMD_INVALID)); 753 754 /* lets just hope it worked.. */ 755 dev->sc_flags &= ~SBICF_SELECTED; 756 } 757 return -1; 758 } 759 760 761 /* 762 * Initialize driver-private structures 763 */ 764 765 void 766 sbicinit(struct sbic_softc *dev) 767 { 768 sbic_regmap_t regs; 769 u_int i; 770 struct sbic_acb *acb; 771 u_int inhibit_sync; 772 773 extern u_long scsi_nosync; 774 extern int shift_nosync; 775 776 regs = dev->sc_sbic; 777 778 if ((dev->sc_flags & SBICF_ALIVE) == 0) { 779 TAILQ_INIT(&dev->ready_list); 780 TAILQ_INIT(&dev->nexus_list); 781 TAILQ_INIT(&dev->free_list); 782 callout_init(&dev->sc_timo_ch); 783 dev->sc_nexus = NULL; 784 dev->sc_xs = NULL; 785 acb = dev->sc_acb; 786 bzero(acb, sizeof(dev->sc_acb)); 787 for (i = 0; i < sizeof(dev->sc_acb) / sizeof(*acb); i++) { 788 TAILQ_INSERT_TAIL(&dev->free_list, acb, chain); 789 acb++; 790 } 791 bzero(dev->sc_tinfo, sizeof(dev->sc_tinfo)); 792 #ifdef DEBUG 793 /* make sure timeout is really not needed */ 794 callout_reset(&dev->sc_timo_ch, 30 * hz, 795 (void *)sbictimeout, dev); 796 #endif 797 798 } else panic("sbic: reinitializing driver!"); 799 800 dev->sc_flags |= SBICF_ALIVE; 801 dev->sc_flags &= ~SBICF_SELECTED; 802 803 /* initialize inhibit array */ 804 if (scsi_nosync) { 805 inhibit_sync = (scsi_nosync >> shift_nosync) & 0xff; 806 shift_nosync += 8; 807 #ifdef DEBUG 808 if (inhibit_sync) 809 printf("%s: Inhibiting synchronous transfer %02x\n", 810 dev->sc_dev.dv_xname, inhibit_sync); 811 #endif 812 for (i = 0; i < 8; ++i) 813 if (inhibit_sync & (1 << i)) 814 sbic_inhibit_sync[i] = 1; 815 } 816 817 sbicreset(dev); 818 } 819 820 void 821 sbicreset(struct sbic_softc *dev) 822 { 823 sbic_regmap_t regs; 824 u_int my_id, s; 825 u_char csr; 826 #if 0 827 u_int i; 828 struct sbic_acb *acb; 829 #endif 830 831 regs = dev->sc_sbic; 832 #if 0 833 if (dev->sc_flags & SBICF_ALIVE) { 834 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 835 WAIT_CIP(regs); 836 } 837 #else 838 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 839 WAIT_CIP(regs); 840 #endif 841 s = splbio(); 842 my_id = dev->sc_channel.chan_id & SBIC_ID_MASK; 843 844 /* Enable advanced mode */ 845 my_id |= SBIC_ID_EAF /*| SBIC_ID_EHP*/ ; 846 SET_SBIC_myid(regs, my_id); 847 848 /* 849 * Disable interrupts (in dmainit) then reset the chip 850 */ 851 SET_SBIC_cmd(regs, SBIC_CMD_RESET); 852 DELAY(25); 853 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 854 GET_SBIC_csr(regs, csr); /* clears interrupt also */ 855 856 if (dev->sc_clkfreq < 110) 857 my_id |= SBIC_ID_FS_8_10; 858 else if (dev->sc_clkfreq < 160) 859 my_id |= SBIC_ID_FS_12_15; 860 else if (dev->sc_clkfreq < 210) 861 my_id |= SBIC_ID_FS_16_20; 862 863 SET_SBIC_myid(regs, my_id); 864 865 /* 866 * Set up various chip parameters 867 */ 868 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI /* | SBIC_CTL_HSP */ 869 | SBIC_MACHINE_DMA_MODE); 870 /* 871 * don't allow (re)selection (SBIC_RID_ES) 872 * until we can handle target mode!! 873 */ 874 SET_SBIC_rselid(regs, SBIC_RID_ER); 875 SET_SBIC_syn(regs, 0); /* asynch for now */ 876 877 /* 878 * anything else was zeroed by reset 879 */ 880 splx(s); 881 882 #if 0 883 if ((dev->sc_flags & SBICF_ALIVE) == 0) { 884 TAILQ_INIT(&dev->ready_list); 885 TAILQ_INIT(&dev->nexus_list); 886 TAILQ_INIT(&dev->free_list); 887 dev->sc_nexus = NULL; 888 dev->sc_xs = NULL; 889 acb = dev->sc_acb; 890 bzero(acb, sizeof(dev->sc_acb)); 891 for (i = 0; i < sizeof(dev->sc_acb) / sizeof(*acb); i++) { 892 TAILQ_INSERT_TAIL(&dev->free_list, acb, chain); 893 acb++; 894 } 895 bzero(dev->sc_tinfo, sizeof(dev->sc_tinfo)); 896 } else { 897 if (dev->sc_nexus != NULL) { 898 dev->sc_nexus->xs->error = XS_DRIVER_STUFFUP; 899 sbic_scsidone(dev->sc_nexus, dev->sc_stat[0]); 900 } 901 while (acb = dev->nexus_list.tqh_first) { 902 acb->xs->error = XS_DRIVER_STUFFUP; 903 sbic_scsidone(acb, -1 /*acb->stat[0]*/); 904 } 905 } 906 907 dev->sc_flags |= SBICF_ALIVE; 908 #endif 909 dev->sc_flags &= ~SBICF_SELECTED; 910 } 911 912 void 913 sbicerror(struct sbic_softc *dev, sbic_regmap_t regs, u_char csr) 914 { 915 struct scsipi_xfer *xs; 916 917 xs = dev->sc_xs; 918 919 #ifdef DIAGNOSTIC 920 if (xs == NULL) 921 panic("sbicerror"); 922 #endif 923 if (xs->xs_control & XS_CTL_SILENT) 924 return; 925 926 printf("%s: ", dev->sc_dev.dv_xname); 927 printf("csr == 0x%02x\n", csr); /* XXX */ 928 } 929 930 /* 931 * select the bus, return when selected or error. 932 */ 933 int 934 sbicselectbus(struct sbic_softc *dev, sbic_regmap_t regs, u_char target, 935 u_char lun, u_char our_addr) 936 { 937 u_char asr, csr, id; 938 939 SBIC_TRACE(dev); 940 QPRINTF(("sbicselectbus %d\n", target)); 941 942 /* 943 * if we're already selected, return (XXXX panic maybe?) 944 */ 945 if (dev->sc_flags & SBICF_SELECTED) { 946 SBIC_TRACE(dev); 947 return(1); 948 } 949 950 /* 951 * issue select 952 */ 953 SBIC_TC_PUT(regs, 0); 954 SET_SBIC_selid(regs, target); 955 SET_SBIC_timeo(regs, SBIC_TIMEOUT(250,dev->sc_clkfreq)); 956 957 /* 958 * set sync or async 959 */ 960 if (dev->sc_sync[target].state == SYNC_DONE) 961 SET_SBIC_syn(regs, SBIC_SYN (dev->sc_sync[target].offset, 962 dev->sc_sync[target].period)); 963 else 964 SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period)); 965 966 GET_SBIC_asr(regs, asr); 967 if( asr & (SBIC_ASR_INT|SBIC_ASR_BSY) ) { 968 /* This means we got ourselves reselected upon */ 969 /* printf("sbicselectbus: INT/BSY asr %02x\n", asr);*/ 970 #ifdef DDB 971 /* Debugger();*/ 972 #endif 973 SBIC_TRACE(dev); 974 return 1; 975 } 976 977 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN); 978 979 /* 980 * wait for select (merged from separate function may need 981 * cleanup) 982 */ 983 WAIT_CIP(regs); 984 do { 985 asr = SBIC_WAIT(regs, SBIC_ASR_INT | SBIC_ASR_LCI, 0); 986 if (asr & SBIC_ASR_LCI) { 987 #ifdef DEBUG 988 if (reselect_debug) 989 printf("sbicselectbus: late LCI asr %02x\n", asr); 990 #endif 991 SBIC_TRACE(dev); 992 return 1; 993 } 994 GET_SBIC_csr (regs, csr); 995 CSR_TRACE('s',csr,asr,target); 996 QPRINTF(("%02x ", csr)); 997 if( csr == SBIC_CSR_RSLT_NI || csr == SBIC_CSR_RSLT_IFY) { 998 #ifdef DEBUG 999 if(reselect_debug) 1000 printf("sbicselectbus: reselected asr %02x\n", asr); 1001 #endif 1002 /* We need to handle this now so we don't lock up later */ 1003 sbicnextstate(dev, csr, asr); 1004 SBIC_TRACE(dev); 1005 return 1; 1006 } 1007 if( csr == SBIC_CSR_SLT || csr == SBIC_CSR_SLT_ATN) { 1008 panic("sbicselectbus: target issued select!"); 1009 return 1; 1010 } 1011 } while (csr != (SBIC_CSR_MIS_2|MESG_OUT_PHASE) 1012 && csr != (SBIC_CSR_MIS_2|CMD_PHASE) && csr != SBIC_CSR_SEL_TIMEO); 1013 1014 /* Enable (or not) reselection */ 1015 if(!sbic_enable_reselect && dev->nexus_list.tqh_first == NULL) 1016 SET_SBIC_rselid (regs, 0); 1017 else 1018 SET_SBIC_rselid (regs, SBIC_RID_ER); 1019 1020 if (csr == (SBIC_CSR_MIS_2|CMD_PHASE)) { 1021 dev->sc_flags |= SBICF_SELECTED; /* device ignored ATN */ 1022 GET_SBIC_selid(regs, id); 1023 dev->target = id; 1024 GET_SBIC_tlun(regs,dev->lun); 1025 if( dev->lun & SBIC_TLUN_VALID ) 1026 dev->lun &= SBIC_TLUN_MASK; 1027 else 1028 dev->lun = lun; 1029 } else if (csr == (SBIC_CSR_MIS_2|MESG_OUT_PHASE)) { 1030 /* 1031 * Send identify message 1032 * (SCSI-2 requires an identify msg (?)) 1033 */ 1034 GET_SBIC_selid(regs, id); 1035 dev->target = id; 1036 GET_SBIC_tlun(regs,dev->lun); 1037 if( dev->lun & SBIC_TLUN_VALID ) 1038 dev->lun &= SBIC_TLUN_MASK; 1039 else 1040 dev->lun = lun; 1041 /* 1042 * handle drives that don't want to be asked 1043 * whether to go sync at all. 1044 */ 1045 if (sbic_inhibit_sync[id] 1046 && dev->sc_sync[id].state == SYNC_START) { 1047 #ifdef DEBUG 1048 if (sync_debug) 1049 printf("Forcing target %d asynchronous.\n", id); 1050 #endif 1051 dev->sc_sync[id].offset = 0; 1052 dev->sc_sync[id].period = sbic_min_period; 1053 dev->sc_sync[id].state = SYNC_DONE; 1054 } 1055 1056 1057 if (dev->sc_sync[id].state != SYNC_START){ 1058 if( dev->sc_xs->xs_control & XS_CTL_POLL 1059 || (dev->sc_flags & SBICF_ICMD) 1060 || !sbic_enable_reselect ) 1061 SEND_BYTE (regs, MSG_IDENTIFY | lun); 1062 else 1063 SEND_BYTE (regs, MSG_IDENTIFY_DR | lun); 1064 } else { 1065 /* 1066 * try to initiate a sync transfer. 1067 * So compose the sync message we're going 1068 * to send to the target 1069 */ 1070 1071 #ifdef DEBUG 1072 if (sync_debug) 1073 printf("Sending sync request to target %d ... ", 1074 id); 1075 #endif 1076 /* 1077 * setup scsi message sync message request 1078 */ 1079 dev->sc_msg[0] = MSG_IDENTIFY | lun; 1080 dev->sc_msg[1] = MSG_EXT_MESSAGE; 1081 dev->sc_msg[2] = 3; 1082 dev->sc_msg[3] = MSG_SYNC_REQ; 1083 dev->sc_msg[4] = sbictoscsiperiod(dev, regs, 1084 sbic_min_period); 1085 dev->sc_msg[5] = sbic_max_offset; 1086 1087 if (sbicxfstart(regs, 6, MESG_OUT_PHASE, sbic_cmd_wait)) 1088 sbicxfout(regs, 6, dev->sc_msg, MESG_OUT_PHASE); 1089 1090 dev->sc_sync[id].state = SYNC_SENT; 1091 #ifdef DEBUG 1092 if (sync_debug) 1093 printf ("sent\n"); 1094 #endif 1095 } 1096 1097 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0); 1098 GET_SBIC_csr (regs, csr); 1099 CSR_TRACE('y',csr,asr,target); 1100 QPRINTF(("[%02x]", csr)); 1101 #ifdef DEBUG 1102 if (sync_debug && dev->sc_sync[id].state == SYNC_SENT) 1103 printf("csr-result of last msgout: 0x%x\n", csr); 1104 #endif 1105 1106 if (csr != SBIC_CSR_SEL_TIMEO) 1107 dev->sc_flags |= SBICF_SELECTED; 1108 } 1109 if (csr == SBIC_CSR_SEL_TIMEO) 1110 dev->sc_xs->error = XS_SELTIMEOUT; 1111 1112 QPRINTF(("\n")); 1113 1114 SBIC_TRACE(dev); 1115 return(csr == SBIC_CSR_SEL_TIMEO); 1116 } 1117 1118 int 1119 sbicxfstart(sbic_regmap_t regs, int len, u_char phase, int wait) 1120 { 1121 u_char id; 1122 1123 switch (phase) { 1124 case DATA_IN_PHASE: 1125 case MESG_IN_PHASE: 1126 GET_SBIC_selid (regs, id); 1127 id |= SBIC_SID_FROM_SCSI; 1128 SET_SBIC_selid (regs, id); 1129 SBIC_TC_PUT (regs, (unsigned)len); 1130 break; 1131 case DATA_OUT_PHASE: 1132 case MESG_OUT_PHASE: 1133 case CMD_PHASE: 1134 GET_SBIC_selid (regs, id); 1135 id &= ~SBIC_SID_FROM_SCSI; 1136 SET_SBIC_selid (regs, id); 1137 SBIC_TC_PUT (regs, (unsigned)len); 1138 break; 1139 default: 1140 SBIC_TC_PUT (regs, 0); 1141 } 1142 QPRINTF(("sbicxfstart %d, %d, %d\n", len, phase, wait)); 1143 1144 return(1); 1145 } 1146 1147 int 1148 sbicxfout(sbic_regmap_t regs, int len, void *bp, int phase) 1149 { 1150 u_char orig_csr, asr, *buf; 1151 int wait; 1152 1153 buf = bp; 1154 wait = sbic_data_wait; 1155 1156 QPRINTF(("sbicxfout {%d} %02x %02x %02x %02x %02x " 1157 "%02x %02x %02x %02x %02x\n", len, buf[0], buf[1], buf[2], 1158 buf[3], buf[4], buf[5], buf[6], buf[7], buf[8], buf[9])); 1159 1160 GET_SBIC_csr (regs, orig_csr); 1161 CSR_TRACE('>',orig_csr,0,0); 1162 1163 /* 1164 * sigh.. WD-PROTO strikes again.. sending the command in one go 1165 * causes the chip to lock up if talking to certain (misbehaving?) 1166 * targets. Anyway, this procedure should work for all targets, but 1167 * it's slightly slower due to the overhead 1168 */ 1169 WAIT_CIP (regs); 1170 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1171 for (;len > 0; len--) { 1172 GET_SBIC_asr (regs, asr); 1173 while ((asr & SBIC_ASR_DBR) == 0) { 1174 if ((asr & SBIC_ASR_INT) || --wait < 0) { 1175 #ifdef DEBUG 1176 if (sbic_debug) 1177 printf("sbicxfout fail: l%d i%x w%d\n", 1178 len, asr, wait); 1179 #endif 1180 return (len); 1181 } 1182 /* DELAY(1);*/ 1183 GET_SBIC_asr (regs, asr); 1184 } 1185 1186 SET_SBIC_data (regs, *buf); 1187 buf++; 1188 } 1189 SBIC_TC_GET(regs, len); 1190 QPRINTF(("sbicxfout done %d bytes\n", len)); 1191 /* 1192 * this leaves with one csr to be read 1193 */ 1194 return(0); 1195 } 1196 1197 /* returns # bytes left to read */ 1198 int 1199 sbicxfin(sbic_regmap_t regs, int len, void *bp) 1200 { 1201 int wait; 1202 u_char *obp, *buf; 1203 u_char orig_csr, csr, asr; 1204 1205 wait = sbic_data_wait; 1206 obp = bp; 1207 buf = bp; 1208 1209 GET_SBIC_csr (regs, orig_csr); 1210 CSR_TRACE('<',orig_csr,0,0); 1211 1212 QPRINTF(("sbicxfin %d, csr=%02x\n", len, orig_csr)); 1213 1214 WAIT_CIP (regs); 1215 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1216 for (;len > 0; len--) { 1217 GET_SBIC_asr (regs, asr); 1218 if((asr & SBIC_ASR_PE)) { 1219 #ifdef DEBUG 1220 printf("sbicxfin parity error: l%d i%x w%d\n", 1221 len, asr, wait); 1222 /* return ((unsigned long)buf - (unsigned long)bp); */ 1223 #ifdef DDB 1224 Debugger(); 1225 #endif 1226 #endif 1227 } 1228 while ((asr & SBIC_ASR_DBR) == 0) { 1229 if ((asr & SBIC_ASR_INT) || --wait < 0) { 1230 #ifdef DEBUG 1231 if (sbic_debug) { 1232 QPRINTF(("sbicxfin fail:{%d} %02x %02x %02x %02x %02x %02x " 1233 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1234 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1235 printf("sbicxfin fail: l%d i%x w%d\n", 1236 len, asr, wait); 1237 } 1238 #endif 1239 return len; 1240 } 1241 1242 if( ! asr & SBIC_ASR_BSY ) { 1243 GET_SBIC_csr(regs, csr); 1244 CSR_TRACE('<',csr,asr,len); 1245 QPRINTF(("[CSR%02xASR%02x]", csr, asr)); 1246 } 1247 1248 /* DELAY(1);*/ 1249 GET_SBIC_asr (regs, asr); 1250 } 1251 1252 GET_SBIC_data (regs, *buf); 1253 /* QPRINTF(("asr=%02x, csr=%02x, data=%02x\n", asr, csr, *buf));*/ 1254 buf++; 1255 } 1256 1257 QPRINTF(("sbicxfin {%d} %02x %02x %02x %02x %02x %02x " 1258 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1259 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1260 1261 /* this leaves with one csr to be read */ 1262 return len; 1263 } 1264 1265 /* 1266 * SCSI 'immediate' command: issue a command to some SCSI device 1267 * and get back an 'immediate' response (i.e., do programmed xfer 1268 * to get the response data). 'cbuf' is a buffer containing a scsi 1269 * command of length clen bytes. 'buf' is a buffer of length 'len' 1270 * bytes for data. The transfer direction is determined by the device 1271 * (i.e., by the scsi bus data xfer phase). If 'len' is zero, the 1272 * command must supply no data. 1273 */ 1274 int 1275 sbicicmd(struct sbic_softc *dev, int target, int lun, void *cbuf, int clen, 1276 void *buf, int len) 1277 { 1278 sbic_regmap_t regs; 1279 u_char phase, csr, asr; 1280 int wait, i; 1281 struct sbic_acb *acb; 1282 1283 #define CSR_LOG_BUF_SIZE 0 1284 #if CSR_LOG_BUF_SIZE 1285 int bufptr; 1286 int csrbuf[CSR_LOG_BUF_SIZE]; 1287 bufptr=0; 1288 #endif 1289 1290 SBIC_TRACE(dev); 1291 regs = dev->sc_sbic; 1292 acb = dev->sc_nexus; 1293 1294 /* Make sure pointers are OK */ 1295 dev->sc_last = dev->sc_cur = &acb->sc_pa; 1296 dev->sc_tcnt = acb->sc_tcnt = 0; 1297 acb->sc_pa.dc_count = 0; /* No DMA */ 1298 acb->sc_kv.dc_addr = buf; 1299 acb->sc_kv.dc_count = len; 1300 1301 #ifdef DEBUG 1302 routine = 3; 1303 debug_sbic_regs = regs; /* store this to allow debug calls */ 1304 if( data_pointer_debug > 1 ) 1305 printf("sbicicmd(%d,%d):%d\n", target, lun, 1306 acb->sc_kv.dc_count); 1307 #endif 1308 1309 /* 1310 * set the sbic into non-DMA mode 1311 */ 1312 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI /*| SBIC_CTL_HSP*/); 1313 1314 dev->sc_stat[0] = 0xff; 1315 dev->sc_msg[0] = 0xff; 1316 i = 1; /* pre-load */ 1317 1318 /* We're stealing the SCSI bus */ 1319 dev->sc_flags |= SBICF_ICMD; 1320 1321 do { 1322 /* 1323 * select the SCSI bus (it's an error if bus isn't free) 1324 */ 1325 if (!( dev->sc_flags & SBICF_SELECTED ) 1326 && sbicselectbus(dev, regs, target, lun, dev->sc_scsiaddr)) { 1327 /* printf("sbicicmd: trying to select busy bus!\n"); */ 1328 dev->sc_flags &= ~SBICF_ICMD; 1329 return(-1); 1330 } 1331 1332 /* 1333 * Wait for a phase change (or error) then let the device sequence 1334 * us through the various SCSI phases. 1335 */ 1336 1337 wait = sbic_cmd_wait; 1338 1339 asr = GET_SBIC_asr (regs, asr); 1340 GET_SBIC_csr (regs, csr); 1341 CSR_TRACE('I',csr,asr,target); 1342 QPRINTF((">ASR:%02xCSR:%02x<", asr, csr)); 1343 1344 #if CSR_LOG_BUF_SIZE 1345 csrbuf[bufptr++] = csr; 1346 #endif 1347 1348 1349 switch (csr) { 1350 case SBIC_CSR_S_XFERRED: 1351 case SBIC_CSR_DISC: 1352 case SBIC_CSR_DISC_1: 1353 dev->sc_flags &= ~SBICF_SELECTED; 1354 GET_SBIC_cmd_phase (regs, phase); 1355 if (phase == 0x60) { 1356 GET_SBIC_tlun (regs, dev->sc_stat[0]); 1357 i = 0; /* done */ 1358 /* break; */ /* Bypass all the state gobldygook */ 1359 } else { 1360 #ifdef DEBUG 1361 if(reselect_debug>1) 1362 printf("sbicicmd: handling disconnect\n"); 1363 #endif 1364 i = SBIC_STATE_DISCONNECT; 1365 } 1366 break; 1367 1368 case SBIC_CSR_XFERRED|CMD_PHASE: 1369 case SBIC_CSR_MIS|CMD_PHASE: 1370 case SBIC_CSR_MIS_1|CMD_PHASE: 1371 case SBIC_CSR_MIS_2|CMD_PHASE: 1372 if (sbicxfstart(regs, clen, CMD_PHASE, sbic_cmd_wait)) 1373 if (sbicxfout(regs, clen, 1374 cbuf, CMD_PHASE)) 1375 i = sbicabort(dev, regs,"icmd sending cmd"); 1376 #if 0 1377 GET_SBIC_csr(regs, csr); /* Lets us reload tcount */ 1378 WAIT_CIP(regs); 1379 GET_SBIC_asr(regs, asr); 1380 CSR_TRACE('I',csr,asr,target); 1381 if( asr & (SBIC_ASR_BSY|SBIC_ASR_LCI|SBIC_ASR_CIP) ) 1382 printf("next: cmd sent asr %02x, csr %02x\n", 1383 asr, csr); 1384 #endif 1385 break; 1386 1387 #if 0 1388 case SBIC_CSR_XFERRED|DATA_OUT_PHASE: 1389 case SBIC_CSR_XFERRED|DATA_IN_PHASE: 1390 case SBIC_CSR_MIS|DATA_OUT_PHASE: 1391 case SBIC_CSR_MIS|DATA_IN_PHASE: 1392 case SBIC_CSR_MIS_1|DATA_OUT_PHASE: 1393 case SBIC_CSR_MIS_1|DATA_IN_PHASE: 1394 case SBIC_CSR_MIS_2|DATA_OUT_PHASE: 1395 case SBIC_CSR_MIS_2|DATA_IN_PHASE: 1396 if (acb->sc_kv.dc_count <= 0) 1397 i = sbicabort(dev, regs, "icmd out of data"); 1398 else { 1399 wait = sbic_data_wait; 1400 if (sbicxfstart(regs, 1401 acb->sc_kv.dc_count, 1402 SBIC_PHASE(csr), wait)) 1403 if (csr & 0x01) 1404 /* data in? */ 1405 i=sbicxfin(regs, 1406 acb->sc_kv.dc_count, 1407 acb->sc_kv.dc_addr); 1408 else 1409 i=sbicxfout(regs, 1410 acb->sc_kv.dc_count, 1411 acb->sc_kv.dc_addr, 1412 SBIC_PHASE(csr)); 1413 acb->sc_kv.dc_addr += 1414 (acb->sc_kv.dc_count - i); 1415 acb->sc_kv.dc_count = i; 1416 i = 1; 1417 } 1418 break; 1419 1420 #endif 1421 case SBIC_CSR_XFERRED|STATUS_PHASE: 1422 case SBIC_CSR_MIS|STATUS_PHASE: 1423 case SBIC_CSR_MIS_1|STATUS_PHASE: 1424 case SBIC_CSR_MIS_2|STATUS_PHASE: 1425 /* 1426 * the sbic does the status/cmd-complete reading ok, 1427 * so do this with its hi-level commands. 1428 */ 1429 #ifdef DEBUG 1430 if(sbic_debug) 1431 printf("SBICICMD status phase\n"); 1432 #endif 1433 SBIC_TC_PUT(regs, 0); 1434 SET_SBIC_cmd_phase(regs, 0x46); 1435 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1436 break; 1437 1438 #if THIS_IS_A_RESERVED_STATE 1439 case BUS_FREE_PHASE: /* This is not legal */ 1440 if( dev->sc_stat[0] != 0xff ) 1441 goto out; 1442 break; 1443 #endif 1444 1445 default: 1446 i = sbicnextstate(dev, csr, asr); 1447 } 1448 1449 /* 1450 * make sure the last command was taken, 1451 * ie. we're not hunting after an ignored command.. 1452 */ 1453 GET_SBIC_asr(regs, asr); 1454 1455 /* tapes may take a loooong time.. */ 1456 while (asr & SBIC_ASR_BSY){ 1457 if(asr & SBIC_ASR_DBR) { 1458 printf("sbicicmd: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", 1459 csr,asr); 1460 #ifdef DDB 1461 Debugger(); 1462 #endif 1463 /* SBIC is jammed */ 1464 /* DUNNO which direction */ 1465 /* Try old direction */ 1466 GET_SBIC_data(regs,i); 1467 GET_SBIC_asr(regs, asr); 1468 if( asr & SBIC_ASR_DBR) /* Wants us to write */ 1469 SET_SBIC_data(regs,i); 1470 } 1471 GET_SBIC_asr(regs, asr); 1472 } 1473 1474 /* 1475 * wait for last command to complete 1476 */ 1477 if (asr & SBIC_ASR_LCI) { 1478 printf("sbicicmd: last command ignored\n"); 1479 } 1480 else if( i == 1 ) /* Bsy */ 1481 SBIC_WAIT (regs, SBIC_ASR_INT, wait); 1482 1483 /* 1484 * do it again 1485 */ 1486 } while ( i > 0 && dev->sc_stat[0] == 0xff); 1487 1488 /* Sometimes we need to do an extra read of the CSR */ 1489 GET_SBIC_csr(regs, csr); 1490 CSR_TRACE('I',csr,asr,0xff); 1491 1492 #if CSR_LOG_BUF_SIZE 1493 if(reselect_debug>1) 1494 for(i=0; i<bufptr; i++) 1495 printf("CSR:%02x", csrbuf[i]); 1496 #endif 1497 1498 #ifdef DEBUG 1499 if(data_pointer_debug > 1) 1500 printf("sbicicmd done(%d,%d):%d =%d=\n", 1501 dev->target, lun, 1502 acb->sc_kv.dc_count, 1503 dev->sc_stat[0]); 1504 #endif 1505 1506 QPRINTF(("=STS:%02x=", dev->sc_stat[0])); 1507 dev->sc_flags &= ~SBICF_ICMD; 1508 1509 SBIC_TRACE(dev); 1510 return(dev->sc_stat[0]); 1511 } 1512 1513 /* 1514 * Finish SCSI xfer command: After the completion interrupt from 1515 * a read/write operation, sequence through the final phases in 1516 * programmed i/o. This routine is a lot like sbicicmd except we 1517 * skip (and don't allow) the select, cmd out and data in/out phases. 1518 */ 1519 void 1520 sbicxfdone(struct sbic_softc *dev, sbic_regmap_t regs, int target) 1521 { 1522 u_char phase, asr, csr; 1523 int s; 1524 1525 SBIC_TRACE(dev); 1526 QPRINTF(("{")); 1527 s = splbio(); 1528 1529 /* 1530 * have the sbic complete on its own 1531 */ 1532 SBIC_TC_PUT(regs, 0); 1533 SET_SBIC_cmd_phase(regs, 0x46); 1534 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1535 1536 do { 1537 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0); 1538 GET_SBIC_csr (regs, csr); 1539 CSR_TRACE('f',csr,asr,target); 1540 QPRINTF(("%02x:", csr)); 1541 } while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) 1542 && (csr != SBIC_CSR_S_XFERRED)); 1543 1544 dev->sc_flags &= ~SBICF_SELECTED; 1545 1546 GET_SBIC_cmd_phase (regs, phase); 1547 QPRINTF(("}%02x", phase)); 1548 if (phase == 0x60) 1549 GET_SBIC_tlun(regs, dev->sc_stat[0]); 1550 else 1551 sbicerror(dev, regs, csr); 1552 1553 QPRINTF(("=STS:%02x=\n", dev->sc_stat[0])); 1554 splx(s); 1555 SBIC_TRACE(dev); 1556 } 1557 1558 /* 1559 * No DMA chains 1560 */ 1561 1562 int 1563 sbicgo(struct sbic_softc *dev, struct scsipi_xfer *xs) 1564 { 1565 int i, dmaflags, count, usedma; 1566 u_char csr, asr, *addr; 1567 sbic_regmap_t regs; 1568 struct sbic_acb *acb; 1569 1570 SBIC_TRACE(dev); 1571 dev->target = xs->xs_periph->periph_target; 1572 dev->lun = xs->xs_periph->periph_lun; 1573 acb = dev->sc_nexus; 1574 regs = dev->sc_sbic; 1575 1576 usedma = sbicdmaok(dev, xs); 1577 #ifdef DEBUG 1578 routine = 1; 1579 debug_sbic_regs = regs; /* store this to allow debug calls */ 1580 if( data_pointer_debug > 1 ) 1581 printf("sbicgo(%d,%d)\n", dev->target, dev->lun); 1582 #endif 1583 1584 /* 1585 * set the sbic into DMA mode 1586 */ 1587 if( usedma ) 1588 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI | 1589 SBIC_MACHINE_DMA_MODE); 1590 else 1591 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1592 1593 1594 /* 1595 * select the SCSI bus (it's an error if bus isn't free) 1596 */ 1597 if (sbicselectbus(dev, regs, dev->target, dev->lun, 1598 dev->sc_scsiaddr)) { 1599 /* printf("sbicgo: Trying to select busy bus!\n"); */ 1600 SBIC_TRACE(dev); 1601 return(0); /* Not done: needs to be rescheduled */ 1602 } 1603 dev->sc_stat[0] = 0xff; 1604 1605 /* 1606 * Calculate DMA chains now 1607 */ 1608 1609 dmaflags = 0; 1610 if (acb->flags & ACB_DATAIN) 1611 dmaflags |= DMAGO_READ; 1612 1613 1614 /* 1615 * Deal w/bounce buffers. 1616 */ 1617 1618 addr = acb->sc_kv.dc_addr; 1619 count = acb->sc_kv.dc_count; 1620 if (count && (char *)kvtop(addr) != acb->sc_pa.dc_addr) { /* XXXX check */ 1621 printf("sbic: DMA buffer mapping changed %p->%x\n", 1622 acb->sc_pa.dc_addr, kvtop(addr)); 1623 #ifdef DDB 1624 Debugger(); 1625 #endif 1626 } 1627 1628 #ifdef DEBUG 1629 ++sbicdma_ops; /* count total DMA operations */ 1630 #endif 1631 if (count && usedma && dev->sc_flags & SBICF_BADDMA && 1632 sbiccheckdmap(addr, count, dev->sc_dmamask)) { 1633 /* 1634 * need to bounce the dma. 1635 */ 1636 if (dmaflags & DMAGO_READ) { 1637 acb->flags |= ACB_BBUF; 1638 acb->sc_dmausrbuf = addr; 1639 acb->sc_dmausrlen = count; 1640 acb->sc_usrbufpa = (u_char *)kvtop(addr); 1641 if(!dev->sc_tinfo[dev->target].bounce) { 1642 printf("sbicgo: HELP! no bounce allocated for %d\n", 1643 dev->target); 1644 printf("xfer: (%p->%p,%lx)\n", acb->sc_dmausrbuf, 1645 acb->sc_usrbufpa, acb->sc_dmausrlen); 1646 dev->sc_tinfo[xs->xs_periph->periph_target].bounce 1647 = (char *)alloc_z2mem(MAXPHYS); 1648 if (isztwomem(dev->sc_tinfo[xs->xs_periph->periph_target].bounce)) 1649 printf("alloc ZII target %d bounce pa 0x%x\n", 1650 xs->xs_periph->periph_target, 1651 kvtop(dev->sc_tinfo[xs->xs_periph->periph_target].bounce)); 1652 else if (dev->sc_tinfo[xs->xs_periph->periph_target].bounce) 1653 printf("alloc CHIP target %d bounce pa 0x%p\n", 1654 xs->xs_periph->periph_target, 1655 PREP_DMA_MEM(dev->sc_tinfo[xs->xs_periph->periph_target].bounce)); 1656 1657 printf("Allocating %d bounce at %x\n", 1658 dev->target, 1659 kvtop(dev->sc_tinfo[dev->target].bounce)); 1660 } 1661 } else { /* write: copy to dma buffer */ 1662 #ifdef DEBUG 1663 if(data_pointer_debug) 1664 printf("sbicgo: copying %x bytes to target %d bounce %x\n", 1665 count, dev->target, 1666 kvtop(dev->sc_tinfo[dev->target].bounce)); 1667 #endif 1668 bcopy (addr, dev->sc_tinfo[dev->target].bounce, count); 1669 } 1670 addr = dev->sc_tinfo[dev->target].bounce;/* and use dma buffer */ 1671 acb->sc_kv.dc_addr = addr; 1672 #ifdef DEBUG 1673 ++sbicdma_bounces; /* count number of bounced */ 1674 #endif 1675 } 1676 1677 /* 1678 * Allocate the DMA chain 1679 */ 1680 1681 /* Set start KVM addresses */ 1682 #if 0 1683 acb->sc_kv.dc_addr = addr; 1684 acb->sc_kv.dc_count = count; 1685 #endif 1686 1687 /* Mark end of segment */ 1688 acb->sc_tcnt = dev->sc_tcnt = 0; 1689 acb->sc_pa.dc_count = 0; 1690 1691 sbic_load_ptrs(dev, regs, dev->target, dev->lun); 1692 SBIC_TRACE(dev); 1693 /* Enable interrupts but don't do any DMA */ 1694 dev->sc_enintr(dev); 1695 if (usedma) { 1696 dev->sc_tcnt = dev->sc_dmago(dev, acb->sc_pa.dc_addr, 1697 acb->sc_pa.dc_count, 1698 dmaflags); 1699 #ifdef DEBUG 1700 dev->sc_dmatimo = dev->sc_tcnt ? 1 : 0; 1701 #endif 1702 } else 1703 dev->sc_dmacmd = 0; /* Don't use DMA */ 1704 dev->sc_flags |= SBICF_INDMA; 1705 /* SBIC_TC_PUT(regs, dev->sc_tcnt); */ /* XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX */ 1706 SBIC_TRACE(dev); 1707 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 1708 1709 /* 1710 * push the data cache ( I think this won't work (EH)) 1711 */ 1712 #if defined(M68040) || defined(M68060) 1713 if (mmutype == MMU_68040 && usedma && count) { 1714 dma_cachectl(addr, count); 1715 if (((u_int)addr & 0xF) || (((u_int)addr + count) & 0xF)) 1716 dev->sc_flags |= SBICF_DCFLUSH; 1717 } 1718 #endif 1719 1720 /* 1721 * enintr() also enables interrupts for the sbic 1722 */ 1723 #ifdef DEBUG 1724 if( data_pointer_debug > 1 ) 1725 printf("sbicgo dmago:%d(%p:%lx)\n", 1726 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 1727 #if 0 1728 /* 1729 * Hmm - this isn't right: asr and csr haven't been set yet. 1730 */ 1731 debug_asr = asr; 1732 debug_csr = csr; 1733 #endif 1734 #endif 1735 1736 /* 1737 * Lets cycle a while then let the interrupt handler take over 1738 */ 1739 1740 asr = GET_SBIC_asr(regs, asr); 1741 do { 1742 GET_SBIC_csr(regs, csr); 1743 CSR_TRACE('g',csr,asr,dev->target); 1744 #ifdef DEBUG 1745 debug_csr = csr; 1746 routine = 1; 1747 #endif 1748 QPRINTF(("go[0x%x]", csr)); 1749 1750 i = sbicnextstate(dev, csr, asr); 1751 1752 WAIT_CIP(regs); 1753 GET_SBIC_asr(regs, asr); 1754 #ifdef DEBUG 1755 debug_asr = asr; 1756 #endif 1757 if(asr & SBIC_ASR_LCI) printf("sbicgo: LCI asr:%02x csr:%02x\n", 1758 asr,csr); 1759 } while( i == SBIC_STATE_RUNNING 1760 && asr & (SBIC_ASR_INT|SBIC_ASR_LCI) ); 1761 1762 CSR_TRACE('g',csr,asr,i<<4); 1763 SBIC_TRACE(dev); 1764 if (i == SBIC_STATE_DONE && dev->sc_stat[0] == 0xff) printf("sbicgo: done & stat = 0xff\n"); 1765 if (i == SBIC_STATE_DONE && dev->sc_stat[0] != 0xff) { 1766 /* if( i == SBIC_STATE_DONE && dev->sc_stat[0] ) { */ 1767 /* Did we really finish that fast? */ 1768 return 1; 1769 } 1770 return 0; 1771 } 1772 1773 1774 int 1775 sbicintr(struct sbic_softc *dev) 1776 { 1777 sbic_regmap_t regs; 1778 u_char asr, csr; 1779 int i; 1780 1781 regs = dev->sc_sbic; 1782 1783 /* 1784 * pending interrupt? 1785 */ 1786 GET_SBIC_asr (regs, asr); 1787 if ((asr & SBIC_ASR_INT) == 0) 1788 return(0); 1789 1790 SBIC_TRACE(dev); 1791 do { 1792 GET_SBIC_csr(regs, csr); 1793 CSR_TRACE('i',csr,asr,dev->target); 1794 #ifdef DEBUG 1795 debug_csr = csr; 1796 routine = 2; 1797 #endif 1798 QPRINTF(("intr[0x%x]", csr)); 1799 1800 i = sbicnextstate(dev, csr, asr); 1801 1802 WAIT_CIP(regs); 1803 GET_SBIC_asr(regs, asr); 1804 #ifdef DEBUG 1805 debug_asr = asr; 1806 #endif 1807 #if 0 1808 if(asr & SBIC_ASR_LCI) printf("sbicintr: LCI asr:%02x csr:%02x\n", 1809 asr,csr); 1810 #endif 1811 } while(i == SBIC_STATE_RUNNING && 1812 asr & (SBIC_ASR_INT|SBIC_ASR_LCI)); 1813 CSR_TRACE('i',csr,asr,i<<4); 1814 SBIC_TRACE(dev); 1815 return(1); 1816 } 1817 1818 /* 1819 * Run commands and wait for disconnect 1820 */ 1821 int 1822 sbicpoll(struct sbic_softc *dev) 1823 { 1824 sbic_regmap_t regs; 1825 u_char asr, csr; 1826 int i; 1827 1828 SBIC_TRACE(dev); 1829 regs = dev->sc_sbic; 1830 1831 do { 1832 GET_SBIC_asr (regs, asr); 1833 #ifdef DEBUG 1834 debug_asr = asr; 1835 #endif 1836 GET_SBIC_csr(regs, csr); 1837 CSR_TRACE('p',csr,asr,dev->target); 1838 #ifdef DEBUG 1839 debug_csr = csr; 1840 routine = 2; 1841 #endif 1842 QPRINTF(("poll[0x%x]", csr)); 1843 1844 i = sbicnextstate(dev, csr, asr); 1845 1846 WAIT_CIP(regs); 1847 GET_SBIC_asr(regs, asr); 1848 /* tapes may take a loooong time.. */ 1849 while (asr & SBIC_ASR_BSY){ 1850 if(asr & SBIC_ASR_DBR) { 1851 printf("sbipoll: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", 1852 csr,asr); 1853 #ifdef DDB 1854 Debugger(); 1855 #endif 1856 /* SBIC is jammed */ 1857 /* DUNNO which direction */ 1858 /* Try old direction */ 1859 GET_SBIC_data(regs,i); 1860 GET_SBIC_asr(regs, asr); 1861 if( asr & SBIC_ASR_DBR) /* Wants us to write */ 1862 SET_SBIC_data(regs,i); 1863 } 1864 GET_SBIC_asr(regs, asr); 1865 } 1866 1867 if(asr & SBIC_ASR_LCI) printf("sbicpoll: LCI asr:%02x csr:%02x\n", 1868 asr,csr); 1869 else if( i == 1 ) /* BSY */ 1870 SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait); 1871 } while(i == SBIC_STATE_RUNNING); 1872 CSR_TRACE('p',csr,asr,i<<4); 1873 SBIC_TRACE(dev); 1874 return(1); 1875 } 1876 1877 /* 1878 * Handle a single msgin 1879 */ 1880 1881 int 1882 sbicmsgin(struct sbic_softc *dev) 1883 { 1884 sbic_regmap_t regs; 1885 int recvlen; 1886 u_char asr, csr, *tmpaddr; 1887 1888 regs = dev->sc_sbic; 1889 1890 dev->sc_msg[0] = 0xff; 1891 dev->sc_msg[1] = 0xff; 1892 1893 GET_SBIC_asr(regs, asr); 1894 #ifdef DEBUG 1895 if(reselect_debug>1) 1896 printf("sbicmsgin asr=%02x\n", asr); 1897 #endif 1898 1899 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 1900 1901 GET_SBIC_selid (regs, csr); 1902 SET_SBIC_selid (regs, csr | SBIC_SID_FROM_SCSI); 1903 1904 SBIC_TC_PUT(regs, 0); 1905 tmpaddr = dev->sc_msg; 1906 recvlen = 1; 1907 do { 1908 while( recvlen-- ) { 1909 asr = GET_SBIC_asr(regs, asr); 1910 GET_SBIC_csr(regs, csr); 1911 QPRINTF(("sbicmsgin ready to go (csr,asr)=(%02x,%02x)\n", 1912 csr, asr)); 1913 1914 RECV_BYTE(regs, *tmpaddr); 1915 CSR_TRACE('m',csr,asr,*tmpaddr); 1916 #if 1 1917 /* 1918 * get the command completion interrupt, or we 1919 * can't send a new command (LCI) 1920 */ 1921 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1922 GET_SBIC_csr(regs, csr); 1923 CSR_TRACE('X',csr,asr,dev->target); 1924 #else 1925 WAIT_CIP(regs); 1926 do { 1927 GET_SBIC_asr(regs, asr); 1928 csr = 0xff; 1929 GET_SBIC_csr(regs, csr); 1930 CSR_TRACE('X',csr,asr,dev->target); 1931 if( csr == 0xff ) 1932 printf("sbicmsgin waiting: csr %02x asr %02x\n", csr, asr); 1933 } while( csr == 0xff ); 1934 #endif 1935 #ifdef DEBUG 1936 if(reselect_debug>1) 1937 printf("sbicmsgin: got %02x csr %02x asr %02x\n", 1938 *tmpaddr, csr, asr); 1939 #endif 1940 #if do_parity_check 1941 if( asr & SBIC_ASR_PE ) { 1942 printf ("Parity error"); 1943 /* This code simply does not work. */ 1944 WAIT_CIP(regs); 1945 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 1946 WAIT_CIP(regs); 1947 GET_SBIC_asr(regs, asr); 1948 WAIT_CIP(regs); 1949 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 1950 WAIT_CIP(regs); 1951 if( !(asr & SBIC_ASR_LCI) ) 1952 /* Target wants to send garbled msg*/ 1953 continue; 1954 printf("--fixing\n"); 1955 /* loop until a msgout phase occurs on target */ 1956 while(csr & 0x07 != MESG_OUT_PHASE) { 1957 while( asr & SBIC_ASR_BSY && 1958 !(asr & SBIC_ASR_DBR|SBIC_ASR_INT) ) 1959 GET_SBIC_asr(regs, asr); 1960 if( asr & SBIC_ASR_DBR ) 1961 panic("msgin: jammed again!\n"); 1962 GET_SBIC_csr(regs, csr); 1963 CSR_TRACE('e',csr,asr,dev->target); 1964 if( csr & 0x07 != MESG_OUT_PHASE ) { 1965 sbicnextstate(dev, csr, asr); 1966 sbic_save_ptrs(dev, regs, 1967 dev->target, 1968 dev->lun); 1969 } 1970 } 1971 /* Should be msg out by now */ 1972 SEND_BYTE(regs, MSG_PARITY_ERROR); 1973 } 1974 else 1975 #endif 1976 tmpaddr++; 1977 1978 if(recvlen) { 1979 /* Clear ACK */ 1980 WAIT_CIP(regs); 1981 GET_SBIC_asr(regs, asr); 1982 GET_SBIC_csr(regs, csr); 1983 CSR_TRACE('X',csr,asr,dev->target); 1984 QPRINTF(("sbicmsgin pre byte CLR_ACK (csr,asr)=(%02x,%02x)\n", 1985 csr, asr)); 1986 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 1987 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1988 } 1989 1990 }; 1991 1992 if(dev->sc_msg[0] == 0xff) { 1993 printf("sbicmsgin: sbic swallowed our message\n"); 1994 break; 1995 } 1996 #ifdef DEBUG 1997 if (sync_debug) 1998 printf("msgin done csr 0x%x asr 0x%x msg 0x%x\n", 1999 csr, asr, dev->sc_msg[0]); 2000 #endif 2001 /* 2002 * test whether this is a reply to our sync 2003 * request 2004 */ 2005 if (MSG_ISIDENTIFY(dev->sc_msg[0])) { 2006 QPRINTF(("IFFY")); 2007 #if 0 2008 /* There is an implied load-ptrs here */ 2009 sbic_load_ptrs(dev, regs, dev->target, dev->lun); 2010 #endif 2011 /* Got IFFY msg -- ack it */ 2012 } else if (dev->sc_msg[0] == MSG_REJECT 2013 && dev->sc_sync[dev->target].state == SYNC_SENT) { 2014 QPRINTF(("REJECT of SYN")); 2015 #ifdef DEBUG 2016 if (sync_debug) 2017 printf("target %d rejected sync, going async\n", 2018 dev->target); 2019 #endif 2020 dev->sc_sync[dev->target].period = sbic_min_period; 2021 dev->sc_sync[dev->target].offset = 0; 2022 dev->sc_sync[dev->target].state = SYNC_DONE; 2023 SET_SBIC_syn(regs, 2024 SBIC_SYN(dev->sc_sync[dev->target].offset, 2025 dev->sc_sync[dev->target].period)); 2026 } else if ((dev->sc_msg[0] == MSG_REJECT)) { 2027 QPRINTF(("REJECT")); 2028 /* 2029 * we'll never REJECt a REJECT message.. 2030 */ 2031 } else if ((dev->sc_msg[0] == MSG_SAVE_DATA_PTR)) { 2032 QPRINTF(("MSG_SAVE_DATA_PTR")); 2033 /* 2034 * don't reject this either. 2035 */ 2036 } else if ((dev->sc_msg[0] == MSG_DISCONNECT)) { 2037 QPRINTF(("DISCONNECT")); 2038 #ifdef DEBUG 2039 if( reselect_debug>1 && dev->sc_msg[0] == MSG_DISCONNECT ) 2040 printf("sbicmsgin: got disconnect msg %s\n", 2041 (dev->sc_flags & SBICF_ICMD)?"rejecting":""); 2042 #endif 2043 if( dev->sc_flags & SBICF_ICMD ) { 2044 /* We're in immediate mode. Prevent disconnects. */ 2045 /* prepare to reject the message, NACK */ 2046 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2047 WAIT_CIP(regs); 2048 } 2049 } else if (dev->sc_msg[0] == MSG_CMD_COMPLETE ) { 2050 QPRINTF(("CMD_COMPLETE")); 2051 /* !! KLUDGE ALERT !! quite a few drives don't seem to 2052 * really like the current way of sending the 2053 * sync-handshake together with the ident-message, and 2054 * they react by sending command-complete and 2055 * disconnecting right after returning the valid sync 2056 * handshake. So, all I can do is reselect the drive, 2057 * and hope it won't disconnect again. I don't think 2058 * this is valid behavior, but I can't help fixing a 2059 * problem that apparently exists. 2060 * 2061 * Note: we should not get here on `normal' command 2062 * completion, as that condition is handled by the 2063 * high-level sel&xfer resume command used to walk 2064 * thru status/cc-phase. 2065 */ 2066 2067 #ifdef DEBUG 2068 if (sync_debug) 2069 printf ("GOT MSG %d! target %d acting weird.." 2070 " waiting for disconnect...\n", 2071 dev->sc_msg[0], dev->target); 2072 #endif 2073 /* Check to see if sbic is handling this */ 2074 GET_SBIC_asr(regs, asr); 2075 if(asr & SBIC_ASR_BSY) 2076 return SBIC_STATE_RUNNING; 2077 2078 /* Let's try this: Assume it works and set status to 00 */ 2079 dev->sc_stat[0] = 0; 2080 } else if (dev->sc_msg[0] == MSG_EXT_MESSAGE 2081 && tmpaddr == &dev->sc_msg[1]) { 2082 QPRINTF(("ExtMSG\n")); 2083 /* Read in whole extended message */ 2084 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2085 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2086 GET_SBIC_asr(regs, asr); 2087 GET_SBIC_csr(regs, csr); 2088 QPRINTF(("CLR ACK asr %02x, csr %02x\n", asr, csr)); 2089 RECV_BYTE(regs, *tmpaddr); 2090 CSR_TRACE('x',csr,asr,*tmpaddr); 2091 /* Wait for command completion IRQ */ 2092 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2093 recvlen = *tmpaddr++; 2094 QPRINTF(("Recving ext msg, asr %02x csr %02x len %02x\n", 2095 asr, csr, recvlen)); 2096 } else if (dev->sc_msg[0] == MSG_EXT_MESSAGE && dev->sc_msg[1] == 3 2097 && dev->sc_msg[2] == MSG_SYNC_REQ) { 2098 QPRINTF(("SYN")); 2099 dev->sc_sync[dev->target].period = 2100 sbicfromscsiperiod(dev, 2101 regs, dev->sc_msg[3]); 2102 dev->sc_sync[dev->target].offset = dev->sc_msg[4]; 2103 dev->sc_sync[dev->target].state = SYNC_DONE; 2104 SET_SBIC_syn(regs, 2105 SBIC_SYN(dev->sc_sync[dev->target].offset, 2106 dev->sc_sync[dev->target].period)); 2107 printf("%s: target %d now synchronous," 2108 " period=%dns, offset=%d.\n", 2109 dev->sc_dev.dv_xname, dev->target, 2110 dev->sc_msg[3] * 4, dev->sc_msg[4]); 2111 } else { 2112 #ifdef DEBUG 2113 if (sbic_debug || sync_debug) 2114 printf ("sbicmsgin: Rejecting message 0x%02x\n", 2115 dev->sc_msg[0]); 2116 #endif 2117 /* prepare to reject the message, NACK */ 2118 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2119 WAIT_CIP(regs); 2120 } 2121 /* Clear ACK */ 2122 WAIT_CIP(regs); 2123 GET_SBIC_asr(regs, asr); 2124 GET_SBIC_csr(regs, csr); 2125 CSR_TRACE('X',csr,asr,dev->target); 2126 QPRINTF(("sbicmsgin pre CLR_ACK (csr,asr)=(%02x,%02x)%d\n", 2127 csr, asr, recvlen)); 2128 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2129 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2130 } 2131 #if 0 2132 while((csr == SBIC_CSR_MSGIN_W_ACK) 2133 || (SBIC_PHASE(csr) == MESG_IN_PHASE)); 2134 #else 2135 while (recvlen>0); 2136 #endif 2137 2138 QPRINTF(("sbicmsgin finished: csr %02x, asr %02x\n",csr, asr)); 2139 2140 /* Should still have one CSR to read */ 2141 return SBIC_STATE_RUNNING; 2142 } 2143 2144 2145 /* 2146 * sbicnextstate() 2147 * return: 2148 * 0 == done 2149 * 1 == working 2150 * 2 == disconnected 2151 * -1 == error 2152 */ 2153 int 2154 sbicnextstate(struct sbic_softc *dev, u_char csr, u_char asr) 2155 { 2156 sbic_regmap_t regs; 2157 struct sbic_acb *acb; 2158 int i, newtarget, newlun, wait; 2159 #if 0 2160 unsigned tcnt; 2161 #endif 2162 2163 i = 0; 2164 SBIC_TRACE(dev); 2165 regs = dev->sc_sbic; 2166 acb = dev->sc_nexus; 2167 2168 QPRINTF(("next[%02x,%02x]",asr,csr)); 2169 2170 switch (csr) { 2171 case SBIC_CSR_XFERRED|CMD_PHASE: 2172 case SBIC_CSR_MIS|CMD_PHASE: 2173 case SBIC_CSR_MIS_1|CMD_PHASE: 2174 case SBIC_CSR_MIS_2|CMD_PHASE: 2175 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 2176 if (sbicxfstart(regs, acb->clen, CMD_PHASE, sbic_cmd_wait)) 2177 if (sbicxfout(regs, acb->clen, 2178 &acb->cmd, CMD_PHASE)) 2179 goto abort; 2180 break; 2181 2182 case SBIC_CSR_XFERRED|STATUS_PHASE: 2183 case SBIC_CSR_MIS|STATUS_PHASE: 2184 case SBIC_CSR_MIS_1|STATUS_PHASE: 2185 case SBIC_CSR_MIS_2|STATUS_PHASE: 2186 /* 2187 * this should be the normal i/o completion case. 2188 * get the status & cmd complete msg then let the 2189 * device driver look at what happened. 2190 */ 2191 sbicxfdone(dev,regs,dev->target); 2192 /* 2193 * check for overlapping cache line, flush if so 2194 */ 2195 #if defined(M68040) || defined(M68060) 2196 if (dev->sc_flags & SBICF_DCFLUSH) { 2197 #if 0 2198 printf("sbic: 68040/68060 DMA cache flush needs" 2199 "fixing? %x:%x\n", 2200 dev->sc_xs->data, dev->sc_xs->datalen); 2201 #endif 2202 } 2203 #endif 2204 #ifdef DEBUG 2205 if( data_pointer_debug > 1 ) 2206 printf("next dmastop: %d(%p:%lx)\n", 2207 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 2208 dev->sc_dmatimo = 0; 2209 #endif 2210 dev->sc_dmastop(dev); /* was dmafree */ 2211 if (acb->flags & ACB_BBUF) { 2212 if ((u_char *)kvtop(acb->sc_dmausrbuf) != acb->sc_usrbufpa) 2213 printf("%s: WARNING - buffer mapping changed %p->%x\n", 2214 dev->sc_dev.dv_xname, acb->sc_usrbufpa, 2215 kvtop(acb->sc_dmausrbuf)); 2216 #ifdef DEBUG 2217 if(data_pointer_debug) 2218 printf("sbicgo:copying %lx bytes from target %d bounce %x\n", 2219 acb->sc_dmausrlen, 2220 dev->target, 2221 kvtop(dev->sc_tinfo[dev->target].bounce)); 2222 #endif 2223 bcopy(dev->sc_tinfo[dev->target].bounce, 2224 acb->sc_dmausrbuf, 2225 acb->sc_dmausrlen); 2226 } 2227 dev->sc_flags &= ~(SBICF_INDMA | SBICF_DCFLUSH); 2228 sbic_scsidone(acb, dev->sc_stat[0]); 2229 SBIC_TRACE(dev); 2230 return SBIC_STATE_DONE; 2231 2232 case SBIC_CSR_XFERRED|DATA_OUT_PHASE: 2233 case SBIC_CSR_XFERRED|DATA_IN_PHASE: 2234 case SBIC_CSR_MIS|DATA_OUT_PHASE: 2235 case SBIC_CSR_MIS|DATA_IN_PHASE: 2236 case SBIC_CSR_MIS_1|DATA_OUT_PHASE: 2237 case SBIC_CSR_MIS_1|DATA_IN_PHASE: 2238 case SBIC_CSR_MIS_2|DATA_OUT_PHASE: 2239 case SBIC_CSR_MIS_2|DATA_IN_PHASE: 2240 if( dev->sc_xs->xs_control & XS_CTL_POLL || dev->sc_flags & SBICF_ICMD 2241 || acb->sc_dmacmd == 0 ) { 2242 /* Do PIO */ 2243 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2244 if (acb->sc_kv.dc_count <= 0) { 2245 printf("sbicnextstate:xfer count %d asr%x csr%x\n", 2246 acb->sc_kv.dc_count, asr, csr); 2247 goto abort; 2248 } 2249 wait = sbic_data_wait; 2250 if( sbicxfstart(regs, 2251 acb->sc_kv.dc_count, 2252 SBIC_PHASE(csr), wait)) { 2253 if( SBIC_PHASE(csr) == DATA_IN_PHASE ) 2254 /* data in? */ 2255 i=sbicxfin(regs, 2256 acb->sc_kv.dc_count, 2257 acb->sc_kv.dc_addr); 2258 else 2259 i=sbicxfout(regs, 2260 acb->sc_kv.dc_count, 2261 acb->sc_kv.dc_addr, 2262 SBIC_PHASE(csr)); 2263 } 2264 acb->sc_kv.dc_addr += 2265 (acb->sc_kv.dc_count - i); 2266 acb->sc_kv.dc_count = i; 2267 } else { 2268 if (acb->sc_kv.dc_count <= 0) { 2269 printf("sbicnextstate:xfer count %d asr%x csr%x\n", 2270 acb->sc_kv.dc_count, asr, csr); 2271 goto abort; 2272 } 2273 /* 2274 * do scatter-gather dma 2275 * hacking the controller chip, ouch.. 2276 */ 2277 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI | 2278 SBIC_MACHINE_DMA_MODE); 2279 /* 2280 * set next dma addr and dec count 2281 */ 2282 #if 0 2283 SBIC_TC_GET(regs, tcnt); 2284 dev->sc_cur->dc_count -= ((dev->sc_tcnt - tcnt) >> 1); 2285 dev->sc_cur->dc_addr += (dev->sc_tcnt - tcnt); 2286 dev->sc_tcnt = acb->sc_tcnt = tcnt; 2287 #else 2288 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 2289 sbic_load_ptrs(dev, regs, dev->target, dev->lun); 2290 #endif 2291 #ifdef DEBUG 2292 if( data_pointer_debug > 1 ) 2293 printf("next dmanext: %d(%p:%lx)\n", 2294 dev->target,dev->sc_cur->dc_addr, 2295 dev->sc_tcnt); 2296 dev->sc_dmatimo = 1; 2297 #endif 2298 dev->sc_tcnt = dev->sc_dmanext(dev); 2299 SBIC_TC_PUT(regs, (unsigned)dev->sc_tcnt); 2300 SET_SBIC_cmd(regs, SBIC_CMD_XFER_INFO); 2301 dev->sc_flags |= SBICF_INDMA; 2302 } 2303 break; 2304 2305 case SBIC_CSR_XFERRED|MESG_IN_PHASE: 2306 case SBIC_CSR_MIS|MESG_IN_PHASE: 2307 case SBIC_CSR_MIS_1|MESG_IN_PHASE: 2308 case SBIC_CSR_MIS_2|MESG_IN_PHASE: 2309 SBIC_TRACE(dev); 2310 return sbicmsgin(dev); 2311 2312 case SBIC_CSR_MSGIN_W_ACK: 2313 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); /* Dunno what I'm ACKing */ 2314 printf("Acking unknown msgin CSR:%02x",csr); 2315 break; 2316 2317 case SBIC_CSR_XFERRED|MESG_OUT_PHASE: 2318 case SBIC_CSR_MIS|MESG_OUT_PHASE: 2319 case SBIC_CSR_MIS_1|MESG_OUT_PHASE: 2320 case SBIC_CSR_MIS_2|MESG_OUT_PHASE: 2321 #ifdef DEBUG 2322 if (sync_debug) 2323 printf ("sending REJECT msg to last msg.\n"); 2324 #endif 2325 2326 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 2327 /* 2328 * should only get here on reject, 2329 * since it's always US that 2330 * initiate a sync transfer 2331 */ 2332 SEND_BYTE(regs, MSG_REJECT); 2333 WAIT_CIP(regs); 2334 if( asr & (SBIC_ASR_BSY|SBIC_ASR_LCI|SBIC_ASR_CIP) ) 2335 printf("next: REJECT sent asr %02x\n", asr); 2336 SBIC_TRACE(dev); 2337 return SBIC_STATE_RUNNING; 2338 2339 case SBIC_CSR_DISC: 2340 case SBIC_CSR_DISC_1: 2341 dev->sc_flags &= ~(SBICF_INDMA|SBICF_SELECTED); 2342 2343 /* Try to schedule another target */ 2344 #ifdef DEBUG 2345 if(reselect_debug>1) 2346 printf("sbicnext target %d disconnected\n", dev->target); 2347 #endif 2348 TAILQ_INSERT_HEAD(&dev->nexus_list, acb, chain); 2349 ++dev->sc_tinfo[dev->target].dconns; 2350 dev->sc_nexus = NULL; 2351 dev->sc_xs = NULL; 2352 2353 if( acb->xs->xs_control & XS_CTL_POLL 2354 || (dev->sc_flags & SBICF_ICMD) 2355 || !sbic_parallel_operations ) { 2356 SBIC_TRACE(dev); 2357 return SBIC_STATE_DISCONNECT; 2358 } 2359 sbic_sched(dev); 2360 SBIC_TRACE(dev); 2361 return SBIC_STATE_DISCONNECT; 2362 2363 case SBIC_CSR_RSLT_NI: 2364 case SBIC_CSR_RSLT_IFY: 2365 GET_SBIC_rselid(regs, newtarget); 2366 /* check SBIC_RID_SIV? */ 2367 newtarget &= SBIC_RID_MASK; 2368 if (csr == SBIC_CSR_RSLT_IFY) { 2369 /* Read IFY msg to avoid lockup */ 2370 GET_SBIC_data(regs, newlun); 2371 WAIT_CIP(regs); 2372 newlun &= SBIC_TLUN_MASK; 2373 CSR_TRACE('r',csr,asr,newtarget); 2374 } else { 2375 /* Need to get IFY message */ 2376 for (newlun = 256; newlun; --newlun) { 2377 GET_SBIC_asr(regs, asr); 2378 if (asr & SBIC_ASR_INT) 2379 break; 2380 delay(1); 2381 } 2382 newlun = 0; /* XXXX */ 2383 if ((asr & SBIC_ASR_INT) == 0) { 2384 #ifdef DEBUG 2385 if (reselect_debug) 2386 printf("RSLT_NI - no IFFY message? asr %x\n", asr); 2387 #endif 2388 } else { 2389 GET_SBIC_csr(regs,csr); 2390 CSR_TRACE('n',csr,asr,newtarget); 2391 if (csr == (SBIC_CSR_MIS | MESG_IN_PHASE) || 2392 csr == (SBIC_CSR_MIS_1 | MESG_IN_PHASE) || 2393 csr == (SBIC_CSR_MIS_2 | MESG_IN_PHASE)) { 2394 sbicmsgin(dev); 2395 newlun = dev->sc_msg[0] & 7; 2396 } else { 2397 printf("RSLT_NI - not MESG_IN_PHASE %x\n", 2398 csr); 2399 } 2400 } 2401 } 2402 #ifdef DEBUG 2403 if(reselect_debug>1 || (reselect_debug && csr==SBIC_CSR_RSLT_NI)) 2404 printf("sbicnext: reselect %s from targ %d lun %d\n", 2405 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", 2406 newtarget, newlun); 2407 #endif 2408 if (dev->sc_nexus) { 2409 #ifdef DEBUG 2410 if (reselect_debug > 1) 2411 printf("%s: reselect %s with active command\n", 2412 dev->sc_dev.dv_xname, 2413 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY"); 2414 #ifdef DDB 2415 /* Debugger();*/ 2416 #endif 2417 #endif 2418 TAILQ_INSERT_HEAD(&dev->ready_list, dev->sc_nexus, chain); 2419 dev->sc_tinfo[dev->target].lubusy &= ~(1 << dev->lun); 2420 dev->sc_nexus = NULL; 2421 dev->sc_xs = NULL; 2422 } 2423 /* Reload sync values for this target */ 2424 if (dev->sc_sync[newtarget].state == SYNC_DONE) 2425 SET_SBIC_syn(regs, SBIC_SYN (dev->sc_sync[newtarget].offset, 2426 dev->sc_sync[newtarget].period)); 2427 else 2428 SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period)); 2429 for (acb = dev->nexus_list.tqh_first; acb; 2430 acb = acb->chain.tqe_next) { 2431 if (acb->xs->xs_periph->periph_target != newtarget || 2432 acb->xs->xs_periph->periph_lun != newlun) 2433 continue; 2434 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 2435 dev->sc_nexus = acb; 2436 dev->sc_xs = acb->xs; 2437 dev->sc_flags |= SBICF_SELECTED; 2438 dev->target = newtarget; 2439 dev->lun = newlun; 2440 break; 2441 } 2442 if (acb == NULL) { 2443 printf("%s: reselect %s targ %d not in nexus_list %p\n", 2444 dev->sc_dev.dv_xname, 2445 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", newtarget, 2446 &dev->nexus_list.tqh_first); 2447 panic("bad reselect in sbic"); 2448 } 2449 if (csr == SBIC_CSR_RSLT_IFY) 2450 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2451 break; 2452 2453 default: 2454 abort: 2455 /* 2456 * Something unexpected happened -- deal with it. 2457 */ 2458 printf("sbicnextstate: aborting csr %02x asr %02x\n", csr, asr); 2459 #ifdef DDB 2460 Debugger(); 2461 #endif 2462 #ifdef DEBUG 2463 if( data_pointer_debug > 1 ) 2464 printf("next dmastop: %d(%p:%lx)\n", 2465 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 2466 dev->sc_dmatimo = 0; 2467 #endif 2468 dev->sc_dmastop(dev); 2469 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2470 sbicerror(dev, regs, csr); 2471 sbicabort(dev, regs, "next"); 2472 if (dev->sc_flags & SBICF_INDMA) { 2473 /* 2474 * check for overlapping cache line, flush if so 2475 */ 2476 #if defined(M68040) || defined(M68060) 2477 if (dev->sc_flags & SBICF_DCFLUSH) { 2478 #if 0 2479 printf("sbic: 68040/060 DMA cache flush needs" 2480 "fixing? %x:%x\n", 2481 dev->sc_xs->data, dev->sc_xs->datalen); 2482 #endif 2483 } 2484 #endif 2485 dev->sc_flags &= 2486 ~(SBICF_INDMA | SBICF_DCFLUSH); 2487 #ifdef DEBUG 2488 if( data_pointer_debug > 1 ) 2489 printf("next dmastop: %d(%p:%lx)\n", 2490 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 2491 dev->sc_dmatimo = 0; 2492 #endif 2493 dev->sc_dmastop(dev); 2494 sbic_scsidone(acb, -1); 2495 } 2496 SBIC_TRACE(dev); 2497 return SBIC_STATE_ERROR; 2498 } 2499 2500 SBIC_TRACE(dev); 2501 return(SBIC_STATE_RUNNING); 2502 } 2503 2504 2505 /* 2506 * Check if DMA can not be used with specified buffer 2507 */ 2508 2509 int 2510 sbiccheckdmap(void *bp, u_long len, u_long mask) 2511 { 2512 u_char *buffer; 2513 u_long phy_buf; 2514 u_long phy_len; 2515 2516 buffer = bp; 2517 2518 if (len == 0) 2519 return(0); 2520 2521 while (len) { 2522 phy_buf = kvtop(buffer); 2523 if (len < (phy_len = NBPG - ((int) buffer & PGOFSET))) 2524 phy_len = len; 2525 if (phy_buf & mask) 2526 return(1); 2527 buffer += phy_len; 2528 len -= phy_len; 2529 } 2530 return(0); 2531 } 2532 2533 int 2534 sbictoscsiperiod(struct sbic_softc *dev, sbic_regmap_t regs, int a) 2535 { 2536 unsigned int fs; 2537 2538 /* 2539 * cycle = DIV / (2*CLK) 2540 * DIV = FS+2 2541 * best we can do is 200ns at 20Mhz, 2 cycles 2542 */ 2543 2544 GET_SBIC_myid(regs,fs); 2545 fs = (fs >>6) + 2; /* DIV */ 2546 fs = (fs * 10000) / (dev->sc_clkfreq<<1); /* Cycle, in ns */ 2547 if (a < 2) a = 8; /* map to Cycles */ 2548 return ((fs*a)>>2); /* in 4 ns units */ 2549 } 2550 2551 int 2552 sbicfromscsiperiod(struct sbic_softc *dev, sbic_regmap_t regs, int p) 2553 { 2554 register unsigned int fs, ret; 2555 2556 /* Just the inverse of the above */ 2557 2558 GET_SBIC_myid(regs,fs); 2559 fs = (fs >>6) + 2; /* DIV */ 2560 fs = (fs * 10000) / (dev->sc_clkfreq<<1); /* Cycle, in ns */ 2561 2562 ret = p << 2; /* in ns units */ 2563 ret = ret / fs; /* in Cycles */ 2564 if (ret < sbic_min_period) 2565 return(sbic_min_period); 2566 2567 /* verify rounding */ 2568 if (sbictoscsiperiod(dev, regs, ret) < p) 2569 ret++; 2570 return (ret >= 8) ? 0 : ret; 2571 } 2572 2573 #ifdef DEBUG 2574 2575 void 2576 sbicdumpstate(void) 2577 { 2578 u_char csr, asr; 2579 2580 GET_SBIC_asr(debug_sbic_regs,asr); 2581 GET_SBIC_csr(debug_sbic_regs,csr); 2582 printf("%s: asr:csr(%02x:%02x)->(%02x:%02x)\n", 2583 (routine==1)?"sbicgo": 2584 (routine==2)?"sbicintr": 2585 (routine==3)?"sbicicmd": 2586 (routine==4)?"sbicnext":"unknown", 2587 debug_asr, debug_csr, asr, csr); 2588 2589 } 2590 2591 void 2592 sbictimeout(struct sbic_softc *dev) 2593 { 2594 int s, asr; 2595 2596 s = splbio(); 2597 if (dev->sc_dmatimo) { 2598 if (dev->sc_dmatimo > 1) { 2599 printf("%s: dma timeout #%d\n", 2600 dev->sc_dev.dv_xname, dev->sc_dmatimo - 1); 2601 GET_SBIC_asr(dev->sc_sbic, asr); 2602 if( asr & SBIC_ASR_INT ) { 2603 /* We need to service a missed IRQ */ 2604 printf("Servicing a missed int:(%02x,%02x)->(%02x,??)\n", 2605 debug_asr, debug_csr, asr); 2606 sbicintr(dev); 2607 } 2608 sbicdumpstate(); 2609 } 2610 dev->sc_dmatimo++; 2611 } 2612 splx(s); 2613 callout_reset(&dev->sc_timo_ch, 30 * hz, 2614 (void *)sbictimeout, dev); 2615 } 2616 2617 void 2618 sbic_dump_acb(struct sbic_acb *acb) 2619 { 2620 u_char *b = (u_char *) &acb->cmd; 2621 int i; 2622 2623 printf("acb@%p ", acb); 2624 if (acb->xs == NULL) { 2625 printf("<unused>\n"); 2626 return; 2627 } 2628 printf("(%d:%d) flags %2x clen %2d cmd ", 2629 acb->xs->xs_periph->periph_target, 2630 acb->xs->xs_periph->periph_lun, acb->flags, acb->clen); 2631 for (i = acb->clen; i; --i) 2632 printf(" %02x", *b++); 2633 printf("\n"); 2634 printf(" xs: %8p data %8p:%04x ", acb->xs, acb->xs->data, 2635 acb->xs->datalen); 2636 printf("va %8p:%04x ", acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 2637 printf("pa %8p:%04x tcnt %lx\n", acb->sc_pa.dc_addr, acb->sc_pa.dc_count, 2638 acb->sc_tcnt); 2639 } 2640 2641 void 2642 sbic_dump(struct sbic_softc *dev) 2643 { 2644 sbic_regmap_t regs; 2645 u_char csr, asr; 2646 struct sbic_acb *acb; 2647 int s; 2648 int i; 2649 2650 s = splbio(); 2651 regs = dev->sc_sbic; 2652 #if CSR_TRACE_SIZE 2653 printf("csr trace: "); 2654 i = csr_traceptr; 2655 do { 2656 printf("%c%02x%02x%02x ", csr_trace[i].whr, 2657 csr_trace[i].csr, csr_trace[i].asr, csr_trace[i].xtn); 2658 switch(csr_trace[i].whr) { 2659 case 'g': 2660 printf("go "); break; 2661 case 's': 2662 printf("select "); break; 2663 case 'y': 2664 printf("select+ "); break; 2665 case 'i': 2666 printf("intr "); break; 2667 case 'f': 2668 printf("finish "); break; 2669 case '>': 2670 printf("out "); break; 2671 case '<': 2672 printf("in "); break; 2673 case 'm': 2674 printf("msgin "); break; 2675 case 'x': 2676 printf("msginx "); break; 2677 case 'X': 2678 printf("msginX "); break; 2679 case 'r': 2680 printf("reselect "); break; 2681 case 'I': 2682 printf("icmd "); break; 2683 case 'a': 2684 printf("abort "); break; 2685 default: 2686 printf("? "); 2687 } 2688 switch(csr_trace[i].csr) { 2689 case 0x11: 2690 printf("INITIATOR"); break; 2691 case 0x16: 2692 printf("S_XFERRED"); break; 2693 case 0x20: 2694 printf("MSGIN_ACK"); break; 2695 case 0x41: 2696 printf("DISC"); break; 2697 case 0x42: 2698 printf("SEL_TIMEO"); break; 2699 case 0x80: 2700 printf("RSLT_NI"); break; 2701 case 0x81: 2702 printf("RSLT_IFY"); break; 2703 case 0x85: 2704 printf("DISC_1"); break; 2705 case 0x18: case 0x19: case 0x1a: 2706 case 0x1b: case 0x1e: case 0x1f: 2707 case 0x28: case 0x29: case 0x2a: 2708 case 0x2b: case 0x2e: case 0x2f: 2709 case 0x48: case 0x49: case 0x4a: 2710 case 0x4b: case 0x4e: case 0x4f: 2711 case 0x88: case 0x89: case 0x8a: 2712 case 0x8b: case 0x8e: case 0x8f: 2713 switch(csr_trace[i].csr & 0xf0) { 2714 case 0x10: 2715 printf("DONE_"); break; 2716 case 0x20: 2717 printf("STOP_"); break; 2718 case 0x40: 2719 printf("ERR_"); break; 2720 case 0x80: 2721 printf("REQ_"); break; 2722 } 2723 switch(csr_trace[i].csr & 7) { 2724 case 0: 2725 printf("DATA_OUT"); break; 2726 case 1: 2727 printf("DATA_IN"); break; 2728 case 2: 2729 printf("CMD"); break; 2730 case 3: 2731 printf("STATUS"); break; 2732 case 6: 2733 printf("MSG_OUT"); break; 2734 case 7: 2735 printf("MSG_IN"); break; 2736 default: 2737 printf("invld phs"); 2738 } 2739 break; 2740 default: printf("****"); break; 2741 } 2742 if (csr_trace[i].asr & SBIC_ASR_INT) 2743 printf(" ASR_INT"); 2744 if (csr_trace[i].asr & SBIC_ASR_LCI) 2745 printf(" ASR_LCI"); 2746 if (csr_trace[i].asr & SBIC_ASR_BSY) 2747 printf(" ASR_BSY"); 2748 if (csr_trace[i].asr & SBIC_ASR_CIP) 2749 printf(" ASR_CIP"); 2750 printf("\n"); 2751 i = (i + 1) & (CSR_TRACE_SIZE - 1); 2752 } while (i != csr_traceptr); 2753 #endif 2754 GET_SBIC_asr(regs, asr); 2755 if ((asr & SBIC_ASR_INT) == 0) 2756 GET_SBIC_csr(regs, csr); 2757 else 2758 csr = 0; 2759 printf("%s@%p regs %p/%p asr %x csr %x\n", dev->sc_dev.dv_xname, 2760 dev, regs.sbic_asr_p, regs.sbic_value_p, asr, csr); 2761 if ((acb = dev->free_list.tqh_first)) { 2762 printf("Free list:\n"); 2763 while (acb) { 2764 sbic_dump_acb(acb); 2765 acb = acb->chain.tqe_next; 2766 } 2767 } 2768 if ((acb = dev->ready_list.tqh_first)) { 2769 printf("Ready list:\n"); 2770 while (acb) { 2771 sbic_dump_acb(acb); 2772 acb = acb->chain.tqe_next; 2773 } 2774 } 2775 if ((acb = dev->nexus_list.tqh_first)) { 2776 printf("Nexus list:\n"); 2777 while (acb) { 2778 sbic_dump_acb(acb); 2779 acb = acb->chain.tqe_next; 2780 } 2781 } 2782 if (dev->sc_nexus) { 2783 printf("nexus:\n"); 2784 sbic_dump_acb(dev->sc_nexus); 2785 } 2786 printf("sc_xs %p targ %d lun %d flags %x tcnt %lx dmacmd %x mask %lx\n", 2787 dev->sc_xs, dev->target, dev->lun, dev->sc_flags, dev->sc_tcnt, 2788 dev->sc_dmacmd, dev->sc_dmamask); 2789 for (i = 0; i < 8; ++i) { 2790 if (dev->sc_tinfo[i].cmds > 2) { 2791 printf("tgt %d: cmds %d disc %d lubusy %x\n", 2792 i, dev->sc_tinfo[i].cmds, 2793 dev->sc_tinfo[i].dconns, 2794 dev->sc_tinfo[i].lubusy); 2795 } 2796 } 2797 splx(s); 2798 } 2799 2800 #endif 2801
Indexes created Fri Sep 26 08:10:20 GMT 2025