sbic.c revision 1.52
1 /* $NetBSD: sbic.c,v 1.52 2003/06/18 08:58:35 drochner Exp $ */ 2 3 /* 4 * Copyright (c) 1994 Christian E. Hopps 5 * Copyright (c) 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * Van Jacobson of Lawrence Berkeley Laboratory. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the University of 22 * California, Berkeley and its contributors. 23 * 4. Neither the name of the University nor the names of its contributors 24 * may be used to endorse or promote products derived from this software 25 * without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 37 * SUCH DAMAGE. 38 * 39 * @(#)scsi.c 7.5 (Berkeley) 5/4/91 40 */ 41 42 /* 43 * AMIGA AMD 33C93 scsi adaptor driver 44 */ 45 46 #include "opt_ddb.h" 47 48 #include <sys/cdefs.h> 49 __KERNEL_RCSID(0, "$NetBSD: sbic.c,v 1.52 2003/06/18 08:58:35 drochner Exp $"); 50 51 #include <sys/param.h> 52 #include <sys/systm.h> 53 #include <sys/device.h> 54 #include <sys/kernel.h> /* For hz */ 55 #include <sys/disklabel.h> 56 #include <sys/buf.h> 57 #include <dev/scsipi/scsi_all.h> 58 #include <dev/scsipi/scsipi_all.h> 59 #include <dev/scsipi/scsiconf.h> 60 #include <uvm/uvm_extern.h> 61 #include <machine/cpu.h> 62 #include <amiga/amiga/device.h> 63 #include <amiga/amiga/custom.h> 64 #include <amiga/amiga/isr.h> 65 #include <amiga/dev/dmavar.h> 66 #include <amiga/dev/sbicreg.h> 67 #include <amiga/dev/sbicvar.h> 68 69 /* These are for bounce buffers */ 70 #include <amiga/amiga/cc.h> 71 #include <amiga/dev/zbusvar.h> 72 73 /* Since I can't find this in any other header files */ 74 #define SCSI_PHASE(reg) (reg&0x07) 75 76 /* 77 * SCSI delays 78 * In u-seconds, primarily for state changes on the SPC. 79 */ 80 #define SBIC_CMD_WAIT 50000 /* wait per step of 'immediate' cmds */ 81 #define SBIC_DATA_WAIT 50000 /* wait per data in/out step */ 82 #define SBIC_INIT_WAIT 50000 /* wait per step (both) during init */ 83 84 #define SBIC_WAIT(regs, until, timeo) sbicwait(regs, until, timeo, __LINE__) 85 86 int sbicicmd(struct sbic_softc *, int, int, void *, int, void *, int); 87 int sbicgo(struct sbic_softc *, struct scsipi_xfer *); 88 int sbicdmaok(struct sbic_softc *, struct scsipi_xfer *); 89 int sbicwait(sbic_regmap_t, char, int , int); 90 int sbiccheckdmap(void *, u_long, u_long); 91 int sbicselectbus(struct sbic_softc *, sbic_regmap_t, u_char, u_char, u_char); 92 int sbicxfstart(sbic_regmap_t, int, u_char, int); 93 int sbicxfout(sbic_regmap_t regs, int, void *, int); 94 int sbicfromscsiperiod(struct sbic_softc *, sbic_regmap_t, int); 95 int sbictoscsiperiod(struct sbic_softc *, sbic_regmap_t, int); 96 int sbicpoll(struct sbic_softc *); 97 int sbicnextstate(struct sbic_softc *, u_char, u_char); 98 int sbicmsgin(struct sbic_softc *); 99 int sbicxfin(sbic_regmap_t regs, int, void *); 100 int sbicabort(struct sbic_softc *, sbic_regmap_t, char *); 101 void sbicxfdone(struct sbic_softc *, sbic_regmap_t, int); 102 void sbicerror(struct sbic_softc *, sbic_regmap_t, u_char); 103 void sbicstart(struct sbic_softc *); 104 void sbicreset(struct sbic_softc *); 105 void sbic_scsidone(struct sbic_acb *, int); 106 void sbic_sched(struct sbic_softc *); 107 void sbic_save_ptrs(struct sbic_softc *, sbic_regmap_t,int,int); 108 void sbic_load_ptrs(struct sbic_softc *, sbic_regmap_t,int,int); 109 #ifdef DEBUG 110 void sbicdumpstate(void); 111 void sbic_dump_acb(struct sbic_acb *); 112 #endif 113 114 /* 115 * Synch xfer parameters, and timing conversions 116 */ 117 int sbic_min_period = SBIC_SYN_MIN_PERIOD; /* in cycles = f(ICLK,FSn) */ 118 int sbic_max_offset = SBIC_SYN_MAX_OFFSET; /* pure number */ 119 120 int sbic_cmd_wait = SBIC_CMD_WAIT; 121 int sbic_data_wait = SBIC_DATA_WAIT; 122 int sbic_init_wait = SBIC_INIT_WAIT; 123 124 /* 125 * was broken before.. now if you want this you get it for all drives 126 * on sbic controllers. 127 */ 128 u_char sbic_inhibit_sync[8]; 129 int sbic_enable_reselect = 1; 130 int sbic_clock_override = 0; 131 int sbic_no_dma = 0; 132 int sbic_parallel_operations = 1; 133 134 #ifdef DEBUG 135 sbic_regmap_t debug_sbic_regs; 136 int sbicdma_ops = 0; /* total DMA operations */ 137 int sbicdma_bounces = 0; /* number operations using bounce buffer */ 138 int sbicdma_hits = 0; /* number of DMA chains that were contiguous */ 139 int sbicdma_misses = 0; /* number of DMA chains that were not contiguous */ 140 int sbicdma_saves = 0; 141 #define QPRINTF(a) if (sbic_debug > 1) printf a 142 int sbic_debug = 0; 143 int sync_debug = 0; 144 int sbic_dma_debug = 0; 145 int reselect_debug = 0; 146 int data_pointer_debug = 0; 147 u_char debug_asr, debug_csr, routine; 148 void sbictimeout(struct sbic_softc *dev); 149 150 #define CSR_TRACE_SIZE 32 151 #if CSR_TRACE_SIZE 152 #define CSR_TRACE(w,c,a,x) do { \ 153 int s = splbio(); \ 154 csr_trace[csr_traceptr].whr = (w); csr_trace[csr_traceptr].csr = (c); \ 155 csr_trace[csr_traceptr].asr = (a); csr_trace[csr_traceptr].xtn = (x); \ 156 dma_cachectl((caddr_t)&csr_trace[csr_traceptr], sizeof(csr_trace[0])); \ 157 csr_traceptr = (csr_traceptr + 1) & (CSR_TRACE_SIZE - 1); \ 158 /* dma_cachectl((caddr_t)&csr_traceptr, sizeof(csr_traceptr));*/ \ 159 splx(s); \ 160 } while (0) 161 int csr_traceptr; 162 int csr_tracesize = CSR_TRACE_SIZE; 163 struct { 164 u_char whr; 165 u_char csr; 166 u_char asr; 167 u_char xtn; 168 } csr_trace[CSR_TRACE_SIZE]; 169 #else 170 #define CSR_TRACE(w,c,a,x) 171 #endif 172 173 #define SBIC_TRACE_SIZE 0 174 #if SBIC_TRACE_SIZE 175 #define SBIC_TRACE(dev) do { \ 176 int s = splbio(); \ 177 sbic_trace[sbic_traceptr].sp = &s; \ 178 sbic_trace[sbic_traceptr].line = __LINE__; \ 179 sbic_trace[sbic_traceptr].sr = s; \ 180 sbic_trace[sbic_traceptr].csr = csr_traceptr; \ 181 dma_cachectl(&sbic_trace[sbic_traceptr], sizeof(sbic_trace[0])); \ 182 sbic_traceptr = (sbic_traceptr + 1) & (SBIC_TRACE_SIZE - 1); \ 183 dma_cachectl(&sbic_traceptr, sizeof(sbic_traceptr)); \ 184 if (dev) dma_cachectl(dev, sizeof(*dev)); \ 185 splx(s); \ 186 } while (0) 187 int sbic_traceptr; 188 int sbic_tracesize = SBIC_TRACE_SIZE; 189 struct { 190 void *sp; 191 u_short line; 192 u_short sr; 193 int csr; 194 } sbic_trace[SBIC_TRACE_SIZE]; 195 #else 196 #define SBIC_TRACE(dev) 197 #endif 198 199 #else /* DEBUG */ 200 #define QPRINTF(a) 201 #define CSR_TRACE(w,c,a,x) 202 #define SBIC_TRACE(dev) 203 #endif /* DEBUG */ 204 205 /* 206 * default minphys routine for sbic based controllers 207 */ 208 void 209 sbic_minphys(struct buf *bp) 210 { 211 212 /* 213 * No max transfer at this level. 214 */ 215 minphys(bp); 216 } 217 218 /* 219 * Save DMA pointers. Take into account partial transfer. Shut down DMA. 220 */ 221 void 222 sbic_save_ptrs(struct sbic_softc *dev, sbic_regmap_t regs, int target, int lun) 223 { 224 int count, asr, s; 225 struct sbic_acb* acb; 226 227 SBIC_TRACE(dev); 228 if( !dev->sc_cur ) return; 229 if( !(dev->sc_flags & SBICF_INDMA) ) return; /* DMA not active */ 230 231 s = splbio(); 232 233 acb = dev->sc_nexus; 234 count = -1; 235 do { 236 GET_SBIC_asr(regs, asr); 237 if( asr & SBIC_ASR_DBR ) { 238 printf("sbic_save_ptrs: asr %02x canceled!\n", asr); 239 splx(s); 240 SBIC_TRACE(dev); 241 return; 242 } 243 } while( asr & (SBIC_ASR_BSY|SBIC_ASR_CIP) ); 244 245 /* Save important state */ 246 /* must be done before dmastop */ 247 acb->sc_dmacmd = dev->sc_dmacmd; 248 SBIC_TC_GET(regs, count); 249 250 /* Shut down DMA ====CAREFUL==== */ 251 dev->sc_dmastop(dev); 252 dev->sc_flags &= ~SBICF_INDMA; 253 SBIC_TC_PUT(regs, 0); 254 255 #ifdef DEBUG 256 if(!count && sbic_debug) printf("%dcount0",target); 257 if(data_pointer_debug == -1) 258 printf("SBIC saving target %d data pointers from (%p,%x)%xASR:%02x", 259 target, dev->sc_cur->dc_addr, dev->sc_cur->dc_count, 260 acb->sc_dmacmd, asr); 261 #endif 262 263 /* Fixup partial xfers */ 264 acb->sc_kv.dc_addr += (dev->sc_tcnt - count); 265 acb->sc_kv.dc_count -= (dev->sc_tcnt - count); 266 acb->sc_pa.dc_addr += (dev->sc_tcnt - count); 267 acb->sc_pa.dc_count -= ((dev->sc_tcnt - count)>>1); 268 269 acb->sc_tcnt = dev->sc_tcnt = count; 270 #ifdef DEBUG 271 if(data_pointer_debug) 272 printf(" at (%p,%x):%x\n", 273 dev->sc_cur->dc_addr, dev->sc_cur->dc_count,count); 274 sbicdma_saves++; 275 #endif 276 splx(s); 277 SBIC_TRACE(dev); 278 } 279 280 281 /* 282 * DOES NOT RESTART DMA!!! 283 */ 284 void 285 sbic_load_ptrs(struct sbic_softc *dev, sbic_regmap_t regs, int target, int lun) 286 { 287 int s, count; 288 char* vaddr, * paddr; 289 struct sbic_acb *acb; 290 291 SBIC_TRACE(dev); 292 acb = dev->sc_nexus; 293 if( !acb->sc_kv.dc_count ) { 294 /* No data to xfer */ 295 SBIC_TRACE(dev); 296 return; 297 } 298 299 s = splbio(); 300 301 dev->sc_last = dev->sc_cur = &acb->sc_pa; 302 dev->sc_tcnt = acb->sc_tcnt; 303 dev->sc_dmacmd = acb->sc_dmacmd; 304 305 #ifdef DEBUG 306 sbicdma_ops++; 307 #endif 308 if( !dev->sc_tcnt ) { 309 /* sc_tcnt == 0 implies end of segment */ 310 311 /* do kvm to pa mappings */ 312 paddr = acb->sc_pa.dc_addr = 313 (char *) kvtop(acb->sc_kv.dc_addr); 314 315 vaddr = acb->sc_kv.dc_addr; 316 count = acb->sc_kv.dc_count; 317 for(count = (PAGE_SIZE - ((int)vaddr & PGOFSET)); 318 count < acb->sc_kv.dc_count 319 && (char*)kvtop(vaddr + count + 4) == paddr + count + 4; 320 count += PAGE_SIZE); 321 /* If it's all contiguous... */ 322 if(count > acb->sc_kv.dc_count ) { 323 count = acb->sc_kv.dc_count; 324 #ifdef DEBUG 325 sbicdma_hits++; 326 #endif 327 } else { 328 #ifdef DEBUG 329 sbicdma_misses++; 330 #endif 331 } 332 acb->sc_tcnt = count; 333 acb->sc_pa.dc_count = count >> 1; 334 335 #ifdef DEBUG 336 if(data_pointer_debug) 337 printf("DMA recalc:kv(%p,%x)pa(%p,%lx)\n", 338 acb->sc_kv.dc_addr, 339 acb->sc_kv.dc_count, 340 acb->sc_pa.dc_addr, 341 acb->sc_tcnt); 342 #endif 343 } 344 splx(s); 345 #ifdef DEBUG 346 if(data_pointer_debug) 347 printf("SBIC restoring target %d data pointers at (%p,%x)%x\n", 348 target, dev->sc_cur->dc_addr, dev->sc_cur->dc_count, 349 dev->sc_dmacmd); 350 #endif 351 SBIC_TRACE(dev); 352 } 353 354 /* 355 * used by specific sbic controller 356 * 357 * it appears that the higher level code does nothing with LUN's 358 * so I will too. I could plug it in, however so could they 359 * in scsi_scsipi_cmd(). 360 */ 361 void 362 sbic_scsipi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req, 363 void *arg) 364 { 365 struct scsipi_xfer *xs; 366 struct scsipi_periph *periph; 367 struct sbic_acb *acb; 368 struct sbic_softc *dev = (void *)chan->chan_adapter->adapt_dev; 369 int flags, s, stat; 370 371 switch (req) { 372 case ADAPTER_REQ_RUN_XFER: 373 xs = arg; 374 periph = xs->xs_periph; 375 376 SBIC_TRACE(dev); 377 flags = xs->xs_control; 378 379 if (flags & XS_CTL_DATA_UIO) 380 panic("sbic: scsi data uio requested"); 381 382 if (dev->sc_nexus && flags & XS_CTL_POLL) 383 panic("sbic_scsipi_request: busy"); 384 385 s = splbio(); 386 acb = dev->free_list.tqh_first; 387 if (acb) 388 TAILQ_REMOVE(&dev->free_list, acb, chain); 389 splx(s); 390 391 #ifdef DIAGNOSTIC 392 if (acb == NULL) { 393 scsipi_printaddr(periph); 394 printf("unable to allocate acb\n"); 395 panic("sbic_scsipi_request"); 396 } 397 #endif 398 acb->flags = ACB_ACTIVE; 399 if (flags & XS_CTL_DATA_IN) 400 acb->flags |= ACB_DATAIN; 401 acb->xs = xs; 402 bcopy(xs->cmd, &acb->cmd, xs->cmdlen); 403 acb->clen = xs->cmdlen; 404 acb->sc_kv.dc_addr = xs->data; 405 acb->sc_kv.dc_count = xs->datalen; 406 acb->pa_addr = xs->data ? (char *)kvtop(xs->data) : 0; /* XXXX check */ 407 408 if (flags & XS_CTL_POLL) { 409 s = splbio(); 410 /* 411 * This has major side effects - it locks up the machine 412 */ 413 414 dev->sc_flags |= SBICF_ICMD; 415 do { 416 while(dev->sc_nexus) 417 sbicpoll(dev); 418 dev->sc_nexus = acb; 419 dev->sc_stat[0] = -1; 420 dev->sc_xs = xs; 421 dev->target = periph->periph_target; 422 dev->lun = periph->periph_lun; 423 stat = sbicicmd(dev, dev->target, dev->lun, 424 &acb->cmd, acb->clen, 425 acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 426 } while (dev->sc_nexus != acb); 427 sbic_scsidone(acb, stat); 428 429 splx(s); 430 SBIC_TRACE(dev); 431 return; 432 } 433 434 s = splbio(); 435 TAILQ_INSERT_TAIL(&dev->ready_list, acb, chain); 436 437 if (dev->sc_nexus) { 438 splx(s); 439 SBIC_TRACE(dev); 440 return; 441 } 442 443 /* 444 * nothing is active, try to start it now. 445 */ 446 sbic_sched(dev); 447 splx(s); 448 449 SBIC_TRACE(dev); 450 /* TODO: add sbic_poll to do XS_CTL_POLL operations */ 451 #if 0 452 if (flags & XS_CTL_POLL) 453 return(COMPLETE); 454 #endif 455 return; 456 457 case ADAPTER_REQ_GROW_RESOURCES: 458 return; 459 460 case ADAPTER_REQ_SET_XFER_MODE: 461 return; 462 } 463 } 464 465 /* 466 * attempt to start the next available command 467 */ 468 void 469 sbic_sched(struct sbic_softc *dev) 470 { 471 struct scsipi_xfer *xs; 472 struct scsipi_periph *periph; 473 struct sbic_acb *acb; 474 int flags, /*phase,*/ stat, i; 475 476 SBIC_TRACE(dev); 477 if (dev->sc_nexus) 478 return; /* a command is current active */ 479 480 SBIC_TRACE(dev); 481 for (acb = dev->ready_list.tqh_first; acb; acb = acb->chain.tqe_next) { 482 periph = acb->xs->xs_periph; 483 i = periph->periph_target; 484 if (!(dev->sc_tinfo[i].lubusy & (1 << periph->periph_lun))) { 485 struct sbic_tinfo *ti = &dev->sc_tinfo[i]; 486 487 TAILQ_REMOVE(&dev->ready_list, acb, chain); 488 dev->sc_nexus = acb; 489 ti = &dev->sc_tinfo[periph->periph_target]; 490 ti->lubusy |= (1 << periph->periph_lun); 491 acb->sc_pa.dc_addr = acb->pa_addr; /* XXXX check */ 492 break; 493 } 494 } 495 496 SBIC_TRACE(dev); 497 if (acb == NULL) 498 return; /* did not find an available command */ 499 500 dev->sc_xs = xs = acb->xs; 501 periph = xs->xs_periph; 502 flags = xs->xs_control; 503 504 if (flags & XS_CTL_RESET) 505 sbicreset(dev); 506 507 #ifdef DEBUG 508 if( data_pointer_debug > 1 ) 509 printf("sbic_sched(%d,%d)\n", periph->periph_target, 510 periph->periph_lun); 511 #endif 512 dev->sc_stat[0] = -1; 513 dev->target = periph->periph_target; 514 dev->lun = periph->periph_lun; 515 if ( flags & XS_CTL_POLL || ( !sbic_parallel_operations 516 && (sbicdmaok(dev, xs) == 0))) 517 stat = sbicicmd(dev, periph->periph_target, 518 periph->periph_lun, &acb->cmd, 519 acb->clen, acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 520 else if (sbicgo(dev, xs) == 0 && xs->error != XS_SELTIMEOUT) { 521 SBIC_TRACE(dev); 522 return; 523 } else 524 stat = dev->sc_stat[0]; 525 526 sbic_scsidone(acb, stat); 527 SBIC_TRACE(dev); 528 } 529 530 void 531 sbic_scsidone(struct sbic_acb *acb, int stat) 532 { 533 struct scsipi_xfer *xs; 534 struct scsipi_periph *periph; 535 struct sbic_softc *dev; 536 int dosched = 0; 537 538 xs = acb->xs; 539 periph = xs->xs_periph; 540 dev = (void *)periph->periph_channel->chan_adapter->adapt_dev; 541 SBIC_TRACE(dev); 542 #ifdef DIAGNOSTIC 543 if (acb == NULL || xs == NULL) { 544 printf("sbic_scsidone -- (%d,%d) no scsi_xfer\n", 545 dev->target, dev->lun); 546 #ifdef DDB 547 Debugger(); 548 #endif 549 return; 550 } 551 #endif 552 553 xs->status = stat; 554 xs->resid = 0; /* XXXX */ 555 #ifdef DEBUG 556 if( data_pointer_debug > 1 ) 557 printf("scsidone: (%d,%d)->(%d,%d)%02x\n", 558 periph->periph_target, periph->periph_lun, 559 dev->target, dev->lun, stat); 560 if( periph->periph_target == 561 periph->periph_channel->chan_id) 562 panic("target == hostid"); 563 #endif 564 565 if (xs->error == XS_NOERROR) { 566 if (stat == SCSI_CHECK || stat == SCSI_BUSY) 567 xs->error = XS_BUSY; 568 } 569 570 /* 571 * Remove the ACB from whatever queue it's on. We have to do a bit of 572 * a hack to figure out which queue it's on. Note that it is *not* 573 * necessary to cdr down the ready queue, but we must cdr down the 574 * nexus queue and see if it's there, so we can mark the unit as no 575 * longer busy. This code is sickening, but it works. 576 */ 577 if (acb == dev->sc_nexus) { 578 dev->sc_nexus = NULL; 579 dev->sc_xs = NULL; 580 dev->sc_tinfo[periph->periph_target].lubusy &= 581 ~(1<<periph->periph_lun); 582 if (dev->ready_list.tqh_first) 583 dosched = 1; /* start next command */ 584 } else if (dev->ready_list.tqh_last == &acb->chain.tqe_next) { 585 TAILQ_REMOVE(&dev->ready_list, acb, chain); 586 } else { 587 register struct sbic_acb *acb2; 588 for (acb2 = dev->nexus_list.tqh_first; acb2; 589 acb2 = acb2->chain.tqe_next) { 590 if (acb2 == acb) { 591 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 592 dev->sc_tinfo[periph->periph_target].lubusy 593 &= ~(1<<periph->periph_lun); 594 break; 595 } 596 } 597 if (acb2) 598 ; 599 else if (acb->chain.tqe_next) { 600 TAILQ_REMOVE(&dev->ready_list, acb, chain); 601 } else { 602 printf("%s: can't find matching acb\n", 603 dev->sc_dev.dv_xname); 604 #ifdef DDB 605 Debugger(); 606 #endif 607 } 608 } 609 /* Put it on the free list. */ 610 acb->flags = ACB_FREE; 611 TAILQ_INSERT_HEAD(&dev->free_list, acb, chain); 612 613 dev->sc_tinfo[periph->periph_target].cmds++; 614 615 scsipi_done(xs); 616 617 if (dosched) 618 sbic_sched(dev); 619 SBIC_TRACE(dev); 620 } 621 622 int 623 sbicdmaok(struct sbic_softc *dev, struct scsipi_xfer *xs) 624 { 625 if (sbic_no_dma || !xs->datalen || xs->datalen & 0x1 || 626 (u_int)xs->data & 0x3) 627 return(0); 628 /* 629 * controller supports dma to any addresses? 630 */ 631 else if ((dev->sc_flags & SBICF_BADDMA) == 0) 632 return(1); 633 /* 634 * this address is ok for DMA? 635 */ 636 else if (sbiccheckdmap(xs->data, xs->datalen, dev->sc_dmamask) == 0) 637 return(1); 638 /* 639 * we have a bounce buffer? 640 */ 641 else if (dev->sc_tinfo[xs->xs_periph->periph_target].bounce) 642 return(1); 643 /* 644 * try to get one 645 */ 646 else if ((dev->sc_tinfo[xs->xs_periph->periph_target].bounce 647 = (char *)alloc_z2mem(MAXPHYS))) { 648 if (isztwomem(dev->sc_tinfo[xs->xs_periph->periph_target].bounce)) 649 printf("alloc ZII target %d bounce pa 0x%x\n", 650 xs->xs_periph->periph_target, 651 kvtop(dev->sc_tinfo[xs->xs_periph->periph_target].bounce)); 652 else if (dev->sc_tinfo[xs->xs_periph->periph_target].bounce) 653 printf("alloc CHIP target %d bounce pa 0x%p\n", 654 xs->xs_periph->periph_target, 655 PREP_DMA_MEM(dev->sc_tinfo[xs->xs_periph->periph_target].bounce)); 656 return(1); 657 } 658 659 return(0); 660 } 661 662 663 int 664 sbicwait(sbic_regmap_t regs, char until, int timeo, int line) 665 { 666 u_char val; 667 int csr; 668 669 SBIC_TRACE((struct sbic_softc *)0); 670 if (timeo == 0) 671 timeo = 1000000; /* some large value.. */ 672 673 GET_SBIC_asr(regs,val); 674 while ((val & until) == 0) { 675 if (timeo-- == 0) { 676 GET_SBIC_csr(regs, csr); 677 printf("sbicwait TIMEO @%d with asr=x%x csr=x%x\n", 678 line, val, csr); 679 #if defined(DDB) && defined(DEBUG) 680 Debugger(); 681 #endif 682 return(val); /* Maybe I should abort */ 683 break; 684 } 685 DELAY(1); 686 GET_SBIC_asr(regs,val); 687 } 688 SBIC_TRACE((struct sbic_softc *)0); 689 return(val); 690 } 691 692 int 693 sbicabort(struct sbic_softc *dev, sbic_regmap_t regs, char *where) 694 { 695 u_char csr, asr; 696 697 GET_SBIC_asr(regs, asr); 698 GET_SBIC_csr(regs, csr); 699 700 printf ("%s: abort %s: csr = 0x%02x, asr = 0x%02x\n", 701 dev->sc_dev.dv_xname, where, csr, asr); 702 703 704 #if 0 705 /* Clean up running command */ 706 if (dev->sc_nexus != NULL) { 707 dev->sc_nexus->xs->error = XS_DRIVER_STUFFUP; 708 sbic_scsidone(dev->sc_nexus, dev->sc_stat[0]); 709 } 710 while (acb = dev->nexus_list.tqh_first) { 711 acb->xs->error = XS_DRIVER_STUFFUP; 712 sbic_scsidone(acb, -1 /*acb->stat[0]*/); 713 } 714 #endif 715 716 /* Clean up chip itself */ 717 if (dev->sc_flags & SBICF_SELECTED) { 718 while( asr & SBIC_ASR_DBR ) { 719 /* sbic is jammed w/data. need to clear it */ 720 /* But we don't know what direction it needs to go */ 721 GET_SBIC_data(regs, asr); 722 printf("%s: abort %s: clearing data buffer 0x%02x\n", 723 dev->sc_dev.dv_xname, where, asr); 724 GET_SBIC_asr(regs, asr); 725 if( asr & SBIC_ASR_DBR ) /* Not the read direction, then */ 726 SET_SBIC_data(regs, asr); 727 GET_SBIC_asr(regs, asr); 728 } 729 WAIT_CIP(regs); 730 printf("%s: sbicabort - sending ABORT command\n", dev->sc_dev.dv_xname); 731 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 732 WAIT_CIP(regs); 733 734 GET_SBIC_asr(regs, asr); 735 if (asr & (SBIC_ASR_BSY|SBIC_ASR_LCI)) { 736 /* ok, get more drastic.. */ 737 738 printf("%s: sbicabort - asr %x, trying to reset\n", dev->sc_dev.dv_xname, asr); 739 sbicreset(dev); 740 dev->sc_flags &= ~SBICF_SELECTED; 741 return -1; 742 } 743 printf("%s: sbicabort - sending DISC command\n", dev->sc_dev.dv_xname); 744 SET_SBIC_cmd(regs, SBIC_CMD_DISC); 745 746 do { 747 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0); 748 GET_SBIC_csr (regs, csr); 749 CSR_TRACE('a',csr,asr,0); 750 } while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) 751 && (csr != SBIC_CSR_CMD_INVALID)); 752 753 /* lets just hope it worked.. */ 754 dev->sc_flags &= ~SBICF_SELECTED; 755 } 756 return -1; 757 } 758 759 760 /* 761 * Initialize driver-private structures 762 */ 763 764 void 765 sbicinit(struct sbic_softc *dev) 766 { 767 sbic_regmap_t regs; 768 u_int i; 769 struct sbic_acb *acb; 770 u_int inhibit_sync; 771 772 extern u_long scsi_nosync; 773 extern int shift_nosync; 774 775 regs = dev->sc_sbic; 776 777 if ((dev->sc_flags & SBICF_ALIVE) == 0) { 778 TAILQ_INIT(&dev->ready_list); 779 TAILQ_INIT(&dev->nexus_list); 780 TAILQ_INIT(&dev->free_list); 781 callout_init(&dev->sc_timo_ch); 782 dev->sc_nexus = NULL; 783 dev->sc_xs = NULL; 784 acb = dev->sc_acb; 785 bzero(acb, sizeof(dev->sc_acb)); 786 for (i = 0; i < sizeof(dev->sc_acb) / sizeof(*acb); i++) { 787 TAILQ_INSERT_TAIL(&dev->free_list, acb, chain); 788 acb++; 789 } 790 bzero(dev->sc_tinfo, sizeof(dev->sc_tinfo)); 791 #ifdef DEBUG 792 /* make sure timeout is really not needed */ 793 callout_reset(&dev->sc_timo_ch, 30 * hz, 794 (void *)sbictimeout, dev); 795 #endif 796 797 } else panic("sbic: reinitializing driver!"); 798 799 dev->sc_flags |= SBICF_ALIVE; 800 dev->sc_flags &= ~SBICF_SELECTED; 801 802 /* initialize inhibit array */ 803 if (scsi_nosync) { 804 inhibit_sync = (scsi_nosync >> shift_nosync) & 0xff; 805 shift_nosync += 8; 806 #ifdef DEBUG 807 if (inhibit_sync) 808 printf("%s: Inhibiting synchronous transfer %02x\n", 809 dev->sc_dev.dv_xname, inhibit_sync); 810 #endif 811 for (i = 0; i < 8; ++i) 812 if (inhibit_sync & (1 << i)) 813 sbic_inhibit_sync[i] = 1; 814 } 815 816 sbicreset(dev); 817 } 818 819 void 820 sbicreset(struct sbic_softc *dev) 821 { 822 sbic_regmap_t regs; 823 u_int my_id, s; 824 u_char csr; 825 #if 0 826 u_int i; 827 struct sbic_acb *acb; 828 #endif 829 830 regs = dev->sc_sbic; 831 #if 0 832 if (dev->sc_flags & SBICF_ALIVE) { 833 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 834 WAIT_CIP(regs); 835 } 836 #else 837 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 838 WAIT_CIP(regs); 839 #endif 840 s = splbio(); 841 my_id = dev->sc_channel.chan_id & SBIC_ID_MASK; 842 843 /* Enable advanced mode */ 844 my_id |= SBIC_ID_EAF /*| SBIC_ID_EHP*/ ; 845 SET_SBIC_myid(regs, my_id); 846 847 /* 848 * Disable interrupts (in dmainit) then reset the chip 849 */ 850 SET_SBIC_cmd(regs, SBIC_CMD_RESET); 851 DELAY(25); 852 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 853 GET_SBIC_csr(regs, csr); /* clears interrupt also */ 854 855 if (dev->sc_clkfreq < 110) 856 my_id |= SBIC_ID_FS_8_10; 857 else if (dev->sc_clkfreq < 160) 858 my_id |= SBIC_ID_FS_12_15; 859 else if (dev->sc_clkfreq < 210) 860 my_id |= SBIC_ID_FS_16_20; 861 862 SET_SBIC_myid(regs, my_id); 863 864 /* 865 * Set up various chip parameters 866 */ 867 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI /* | SBIC_CTL_HSP */ 868 | SBIC_MACHINE_DMA_MODE); 869 /* 870 * don't allow (re)selection (SBIC_RID_ES) 871 * until we can handle target mode!! 872 */ 873 SET_SBIC_rselid(regs, SBIC_RID_ER); 874 SET_SBIC_syn(regs, 0); /* asynch for now */ 875 876 /* 877 * anything else was zeroed by reset 878 */ 879 splx(s); 880 881 #if 0 882 if ((dev->sc_flags & SBICF_ALIVE) == 0) { 883 TAILQ_INIT(&dev->ready_list); 884 TAILQ_INIT(&dev->nexus_list); 885 TAILQ_INIT(&dev->free_list); 886 dev->sc_nexus = NULL; 887 dev->sc_xs = NULL; 888 acb = dev->sc_acb; 889 bzero(acb, sizeof(dev->sc_acb)); 890 for (i = 0; i < sizeof(dev->sc_acb) / sizeof(*acb); i++) { 891 TAILQ_INSERT_TAIL(&dev->free_list, acb, chain); 892 acb++; 893 } 894 bzero(dev->sc_tinfo, sizeof(dev->sc_tinfo)); 895 } else { 896 if (dev->sc_nexus != NULL) { 897 dev->sc_nexus->xs->error = XS_DRIVER_STUFFUP; 898 sbic_scsidone(dev->sc_nexus, dev->sc_stat[0]); 899 } 900 while (acb = dev->nexus_list.tqh_first) { 901 acb->xs->error = XS_DRIVER_STUFFUP; 902 sbic_scsidone(acb, -1 /*acb->stat[0]*/); 903 } 904 } 905 906 dev->sc_flags |= SBICF_ALIVE; 907 #endif 908 dev->sc_flags &= ~SBICF_SELECTED; 909 } 910 911 void 912 sbicerror(struct sbic_softc *dev, sbic_regmap_t regs, u_char csr) 913 { 914 struct scsipi_xfer *xs; 915 916 xs = dev->sc_xs; 917 918 #ifdef DIAGNOSTIC 919 if (xs == NULL) 920 panic("sbicerror"); 921 #endif 922 if (xs->xs_control & XS_CTL_SILENT) 923 return; 924 925 printf("%s: ", dev->sc_dev.dv_xname); 926 printf("csr == 0x%02x\n", csr); /* XXX */ 927 } 928 929 /* 930 * select the bus, return when selected or error. 931 */ 932 int 933 sbicselectbus(struct sbic_softc *dev, sbic_regmap_t regs, u_char target, 934 u_char lun, u_char our_addr) 935 { 936 u_char asr, csr, id; 937 938 SBIC_TRACE(dev); 939 QPRINTF(("sbicselectbus %d\n", target)); 940 941 /* 942 * if we're already selected, return (XXXX panic maybe?) 943 */ 944 if (dev->sc_flags & SBICF_SELECTED) { 945 SBIC_TRACE(dev); 946 return(1); 947 } 948 949 /* 950 * issue select 951 */ 952 SBIC_TC_PUT(regs, 0); 953 SET_SBIC_selid(regs, target); 954 SET_SBIC_timeo(regs, SBIC_TIMEOUT(250,dev->sc_clkfreq)); 955 956 /* 957 * set sync or async 958 */ 959 if (dev->sc_sync[target].state == SYNC_DONE) 960 SET_SBIC_syn(regs, SBIC_SYN (dev->sc_sync[target].offset, 961 dev->sc_sync[target].period)); 962 else 963 SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period)); 964 965 GET_SBIC_asr(regs, asr); 966 if( asr & (SBIC_ASR_INT|SBIC_ASR_BSY) ) { 967 /* This means we got ourselves reselected upon */ 968 /* printf("sbicselectbus: INT/BSY asr %02x\n", asr);*/ 969 #ifdef DDB 970 /* Debugger();*/ 971 #endif 972 SBIC_TRACE(dev); 973 return 1; 974 } 975 976 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN); 977 978 /* 979 * wait for select (merged from separate function may need 980 * cleanup) 981 */ 982 WAIT_CIP(regs); 983 do { 984 asr = SBIC_WAIT(regs, SBIC_ASR_INT | SBIC_ASR_LCI, 0); 985 if (asr & SBIC_ASR_LCI) { 986 #ifdef DEBUG 987 if (reselect_debug) 988 printf("sbicselectbus: late LCI asr %02x\n", asr); 989 #endif 990 SBIC_TRACE(dev); 991 return 1; 992 } 993 GET_SBIC_csr (regs, csr); 994 CSR_TRACE('s',csr,asr,target); 995 QPRINTF(("%02x ", csr)); 996 if( csr == SBIC_CSR_RSLT_NI || csr == SBIC_CSR_RSLT_IFY) { 997 #ifdef DEBUG 998 if(reselect_debug) 999 printf("sbicselectbus: reselected asr %02x\n", asr); 1000 #endif 1001 /* We need to handle this now so we don't lock up later */ 1002 sbicnextstate(dev, csr, asr); 1003 SBIC_TRACE(dev); 1004 return 1; 1005 } 1006 if( csr == SBIC_CSR_SLT || csr == SBIC_CSR_SLT_ATN) { 1007 panic("sbicselectbus: target issued select!"); 1008 return 1; 1009 } 1010 } while (csr != (SBIC_CSR_MIS_2|MESG_OUT_PHASE) 1011 && csr != (SBIC_CSR_MIS_2|CMD_PHASE) && csr != SBIC_CSR_SEL_TIMEO); 1012 1013 /* Enable (or not) reselection */ 1014 if(!sbic_enable_reselect && dev->nexus_list.tqh_first == NULL) 1015 SET_SBIC_rselid (regs, 0); 1016 else 1017 SET_SBIC_rselid (regs, SBIC_RID_ER); 1018 1019 if (csr == (SBIC_CSR_MIS_2|CMD_PHASE)) { 1020 dev->sc_flags |= SBICF_SELECTED; /* device ignored ATN */ 1021 GET_SBIC_selid(regs, id); 1022 dev->target = id; 1023 GET_SBIC_tlun(regs,dev->lun); 1024 if( dev->lun & SBIC_TLUN_VALID ) 1025 dev->lun &= SBIC_TLUN_MASK; 1026 else 1027 dev->lun = lun; 1028 } else if (csr == (SBIC_CSR_MIS_2|MESG_OUT_PHASE)) { 1029 /* 1030 * Send identify message 1031 * (SCSI-2 requires an identify msg (?)) 1032 */ 1033 GET_SBIC_selid(regs, id); 1034 dev->target = id; 1035 GET_SBIC_tlun(regs,dev->lun); 1036 if( dev->lun & SBIC_TLUN_VALID ) 1037 dev->lun &= SBIC_TLUN_MASK; 1038 else 1039 dev->lun = lun; 1040 /* 1041 * handle drives that don't want to be asked 1042 * whether to go sync at all. 1043 */ 1044 if (sbic_inhibit_sync[id] 1045 && dev->sc_sync[id].state == SYNC_START) { 1046 #ifdef DEBUG 1047 if (sync_debug) 1048 printf("Forcing target %d asynchronous.\n", id); 1049 #endif 1050 dev->sc_sync[id].offset = 0; 1051 dev->sc_sync[id].period = sbic_min_period; 1052 dev->sc_sync[id].state = SYNC_DONE; 1053 } 1054 1055 1056 if (dev->sc_sync[id].state != SYNC_START){ 1057 if( dev->sc_xs->xs_control & XS_CTL_POLL 1058 || (dev->sc_flags & SBICF_ICMD) 1059 || !sbic_enable_reselect ) 1060 SEND_BYTE (regs, MSG_IDENTIFY | lun); 1061 else 1062 SEND_BYTE (regs, MSG_IDENTIFY_DR | lun); 1063 } else { 1064 /* 1065 * try to initiate a sync transfer. 1066 * So compose the sync message we're going 1067 * to send to the target 1068 */ 1069 1070 #ifdef DEBUG 1071 if (sync_debug) 1072 printf("Sending sync request to target %d ... ", 1073 id); 1074 #endif 1075 /* 1076 * setup scsi message sync message request 1077 */ 1078 dev->sc_msg[0] = MSG_IDENTIFY | lun; 1079 dev->sc_msg[1] = MSG_EXT_MESSAGE; 1080 dev->sc_msg[2] = 3; 1081 dev->sc_msg[3] = MSG_SYNC_REQ; 1082 dev->sc_msg[4] = sbictoscsiperiod(dev, regs, 1083 sbic_min_period); 1084 dev->sc_msg[5] = sbic_max_offset; 1085 1086 if (sbicxfstart(regs, 6, MESG_OUT_PHASE, sbic_cmd_wait)) 1087 sbicxfout(regs, 6, dev->sc_msg, MESG_OUT_PHASE); 1088 1089 dev->sc_sync[id].state = SYNC_SENT; 1090 #ifdef DEBUG 1091 if (sync_debug) 1092 printf ("sent\n"); 1093 #endif 1094 } 1095 1096 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0); 1097 GET_SBIC_csr (regs, csr); 1098 CSR_TRACE('y',csr,asr,target); 1099 QPRINTF(("[%02x]", csr)); 1100 #ifdef DEBUG 1101 if (sync_debug && dev->sc_sync[id].state == SYNC_SENT) 1102 printf("csr-result of last msgout: 0x%x\n", csr); 1103 #endif 1104 1105 if (csr != SBIC_CSR_SEL_TIMEO) 1106 dev->sc_flags |= SBICF_SELECTED; 1107 } 1108 if (csr == SBIC_CSR_SEL_TIMEO) 1109 dev->sc_xs->error = XS_SELTIMEOUT; 1110 1111 QPRINTF(("\n")); 1112 1113 SBIC_TRACE(dev); 1114 return(csr == SBIC_CSR_SEL_TIMEO); 1115 } 1116 1117 int 1118 sbicxfstart(sbic_regmap_t regs, int len, u_char phase, int wait) 1119 { 1120 u_char id; 1121 1122 switch (phase) { 1123 case DATA_IN_PHASE: 1124 case MESG_IN_PHASE: 1125 GET_SBIC_selid (regs, id); 1126 id |= SBIC_SID_FROM_SCSI; 1127 SET_SBIC_selid (regs, id); 1128 SBIC_TC_PUT (regs, (unsigned)len); 1129 break; 1130 case DATA_OUT_PHASE: 1131 case MESG_OUT_PHASE: 1132 case CMD_PHASE: 1133 GET_SBIC_selid (regs, id); 1134 id &= ~SBIC_SID_FROM_SCSI; 1135 SET_SBIC_selid (regs, id); 1136 SBIC_TC_PUT (regs, (unsigned)len); 1137 break; 1138 default: 1139 SBIC_TC_PUT (regs, 0); 1140 } 1141 QPRINTF(("sbicxfstart %d, %d, %d\n", len, phase, wait)); 1142 1143 return(1); 1144 } 1145 1146 int 1147 sbicxfout(sbic_regmap_t regs, int len, void *bp, int phase) 1148 { 1149 u_char orig_csr, asr, *buf; 1150 int wait; 1151 1152 buf = bp; 1153 wait = sbic_data_wait; 1154 1155 QPRINTF(("sbicxfout {%d} %02x %02x %02x %02x %02x " 1156 "%02x %02x %02x %02x %02x\n", len, buf[0], buf[1], buf[2], 1157 buf[3], buf[4], buf[5], buf[6], buf[7], buf[8], buf[9])); 1158 1159 GET_SBIC_csr (regs, orig_csr); 1160 CSR_TRACE('>',orig_csr,0,0); 1161 1162 /* 1163 * sigh.. WD-PROTO strikes again.. sending the command in one go 1164 * causes the chip to lock up if talking to certain (misbehaving?) 1165 * targets. Anyway, this procedure should work for all targets, but 1166 * it's slightly slower due to the overhead 1167 */ 1168 WAIT_CIP (regs); 1169 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1170 for (;len > 0; len--) { 1171 GET_SBIC_asr (regs, asr); 1172 while ((asr & SBIC_ASR_DBR) == 0) { 1173 if ((asr & SBIC_ASR_INT) || --wait < 0) { 1174 #ifdef DEBUG 1175 if (sbic_debug) 1176 printf("sbicxfout fail: l%d i%x w%d\n", 1177 len, asr, wait); 1178 #endif 1179 return (len); 1180 } 1181 /* DELAY(1);*/ 1182 GET_SBIC_asr (regs, asr); 1183 } 1184 1185 SET_SBIC_data (regs, *buf); 1186 buf++; 1187 } 1188 SBIC_TC_GET(regs, len); 1189 QPRINTF(("sbicxfout done %d bytes\n", len)); 1190 /* 1191 * this leaves with one csr to be read 1192 */ 1193 return(0); 1194 } 1195 1196 /* returns # bytes left to read */ 1197 int 1198 sbicxfin(sbic_regmap_t regs, int len, void *bp) 1199 { 1200 int wait; 1201 u_char *obp, *buf; 1202 u_char orig_csr, csr, asr; 1203 1204 wait = sbic_data_wait; 1205 obp = bp; 1206 buf = bp; 1207 1208 GET_SBIC_csr (regs, orig_csr); 1209 CSR_TRACE('<',orig_csr,0,0); 1210 1211 QPRINTF(("sbicxfin %d, csr=%02x\n", len, orig_csr)); 1212 1213 WAIT_CIP (regs); 1214 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1215 for (;len > 0; len--) { 1216 GET_SBIC_asr (regs, asr); 1217 if((asr & SBIC_ASR_PE)) { 1218 #ifdef DEBUG 1219 printf("sbicxfin parity error: l%d i%x w%d\n", 1220 len, asr, wait); 1221 /* return ((unsigned long)buf - (unsigned long)bp); */ 1222 #ifdef DDB 1223 Debugger(); 1224 #endif 1225 #endif 1226 } 1227 while ((asr & SBIC_ASR_DBR) == 0) { 1228 if ((asr & SBIC_ASR_INT) || --wait < 0) { 1229 #ifdef DEBUG 1230 if (sbic_debug) { 1231 QPRINTF(("sbicxfin fail:{%d} %02x %02x %02x %02x %02x %02x " 1232 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1233 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1234 printf("sbicxfin fail: l%d i%x w%d\n", 1235 len, asr, wait); 1236 } 1237 #endif 1238 return len; 1239 } 1240 1241 if( ! asr & SBIC_ASR_BSY ) { 1242 GET_SBIC_csr(regs, csr); 1243 CSR_TRACE('<',csr,asr,len); 1244 QPRINTF(("[CSR%02xASR%02x]", csr, asr)); 1245 } 1246 1247 /* DELAY(1);*/ 1248 GET_SBIC_asr (regs, asr); 1249 } 1250 1251 GET_SBIC_data (regs, *buf); 1252 /* QPRINTF(("asr=%02x, csr=%02x, data=%02x\n", asr, csr, *buf));*/ 1253 buf++; 1254 } 1255 1256 QPRINTF(("sbicxfin {%d} %02x %02x %02x %02x %02x %02x " 1257 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1258 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1259 1260 /* this leaves with one csr to be read */ 1261 return len; 1262 } 1263 1264 /* 1265 * SCSI 'immediate' command: issue a command to some SCSI device 1266 * and get back an 'immediate' response (i.e., do programmed xfer 1267 * to get the response data). 'cbuf' is a buffer containing a scsi 1268 * command of length clen bytes. 'buf' is a buffer of length 'len' 1269 * bytes for data. The transfer direction is determined by the device 1270 * (i.e., by the scsi bus data xfer phase). If 'len' is zero, the 1271 * command must supply no data. 1272 */ 1273 int 1274 sbicicmd(struct sbic_softc *dev, int target, int lun, void *cbuf, int clen, 1275 void *buf, int len) 1276 { 1277 sbic_regmap_t regs; 1278 u_char phase, csr, asr; 1279 int wait, i; 1280 struct sbic_acb *acb; 1281 1282 #define CSR_LOG_BUF_SIZE 0 1283 #if CSR_LOG_BUF_SIZE 1284 int bufptr; 1285 int csrbuf[CSR_LOG_BUF_SIZE]; 1286 bufptr=0; 1287 #endif 1288 1289 SBIC_TRACE(dev); 1290 regs = dev->sc_sbic; 1291 acb = dev->sc_nexus; 1292 1293 /* Make sure pointers are OK */ 1294 dev->sc_last = dev->sc_cur = &acb->sc_pa; 1295 dev->sc_tcnt = acb->sc_tcnt = 0; 1296 acb->sc_pa.dc_count = 0; /* No DMA */ 1297 acb->sc_kv.dc_addr = buf; 1298 acb->sc_kv.dc_count = len; 1299 1300 #ifdef DEBUG 1301 routine = 3; 1302 debug_sbic_regs = regs; /* store this to allow debug calls */ 1303 if( data_pointer_debug > 1 ) 1304 printf("sbicicmd(%d,%d):%d\n", target, lun, 1305 acb->sc_kv.dc_count); 1306 #endif 1307 1308 /* 1309 * set the sbic into non-DMA mode 1310 */ 1311 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI /*| SBIC_CTL_HSP*/); 1312 1313 dev->sc_stat[0] = 0xff; 1314 dev->sc_msg[0] = 0xff; 1315 i = 1; /* pre-load */ 1316 1317 /* We're stealing the SCSI bus */ 1318 dev->sc_flags |= SBICF_ICMD; 1319 1320 do { 1321 /* 1322 * select the SCSI bus (it's an error if bus isn't free) 1323 */ 1324 if (!( dev->sc_flags & SBICF_SELECTED ) 1325 && sbicselectbus(dev, regs, target, lun, dev->sc_scsiaddr)) { 1326 /* printf("sbicicmd: trying to select busy bus!\n"); */ 1327 dev->sc_flags &= ~SBICF_ICMD; 1328 return(-1); 1329 } 1330 1331 /* 1332 * Wait for a phase change (or error) then let the device sequence 1333 * us through the various SCSI phases. 1334 */ 1335 1336 wait = sbic_cmd_wait; 1337 1338 GET_SBIC_asr (regs, asr); 1339 GET_SBIC_csr (regs, csr); 1340 CSR_TRACE('I',csr,asr,target); 1341 QPRINTF((">ASR:%02xCSR:%02x<", asr, csr)); 1342 1343 #if CSR_LOG_BUF_SIZE 1344 csrbuf[bufptr++] = csr; 1345 #endif 1346 1347 1348 switch (csr) { 1349 case SBIC_CSR_S_XFERRED: 1350 case SBIC_CSR_DISC: 1351 case SBIC_CSR_DISC_1: 1352 dev->sc_flags &= ~SBICF_SELECTED; 1353 GET_SBIC_cmd_phase (regs, phase); 1354 if (phase == 0x60) { 1355 GET_SBIC_tlun (regs, dev->sc_stat[0]); 1356 i = 0; /* done */ 1357 /* break; */ /* Bypass all the state gobldygook */ 1358 } else { 1359 #ifdef DEBUG 1360 if(reselect_debug>1) 1361 printf("sbicicmd: handling disconnect\n"); 1362 #endif 1363 i = SBIC_STATE_DISCONNECT; 1364 } 1365 break; 1366 1367 case SBIC_CSR_XFERRED|CMD_PHASE: 1368 case SBIC_CSR_MIS|CMD_PHASE: 1369 case SBIC_CSR_MIS_1|CMD_PHASE: 1370 case SBIC_CSR_MIS_2|CMD_PHASE: 1371 if (sbicxfstart(regs, clen, CMD_PHASE, sbic_cmd_wait)) 1372 if (sbicxfout(regs, clen, 1373 cbuf, CMD_PHASE)) 1374 i = sbicabort(dev, regs,"icmd sending cmd"); 1375 #if 0 1376 GET_SBIC_csr(regs, csr); /* Lets us reload tcount */ 1377 WAIT_CIP(regs); 1378 GET_SBIC_asr(regs, asr); 1379 CSR_TRACE('I',csr,asr,target); 1380 if( asr & (SBIC_ASR_BSY|SBIC_ASR_LCI|SBIC_ASR_CIP) ) 1381 printf("next: cmd sent asr %02x, csr %02x\n", 1382 asr, csr); 1383 #endif 1384 break; 1385 1386 #if 0 1387 case SBIC_CSR_XFERRED|DATA_OUT_PHASE: 1388 case SBIC_CSR_XFERRED|DATA_IN_PHASE: 1389 case SBIC_CSR_MIS|DATA_OUT_PHASE: 1390 case SBIC_CSR_MIS|DATA_IN_PHASE: 1391 case SBIC_CSR_MIS_1|DATA_OUT_PHASE: 1392 case SBIC_CSR_MIS_1|DATA_IN_PHASE: 1393 case SBIC_CSR_MIS_2|DATA_OUT_PHASE: 1394 case SBIC_CSR_MIS_2|DATA_IN_PHASE: 1395 if (acb->sc_kv.dc_count <= 0) 1396 i = sbicabort(dev, regs, "icmd out of data"); 1397 else { 1398 wait = sbic_data_wait; 1399 if (sbicxfstart(regs, 1400 acb->sc_kv.dc_count, 1401 SBIC_PHASE(csr), wait)) 1402 if (csr & 0x01) 1403 /* data in? */ 1404 i=sbicxfin(regs, 1405 acb->sc_kv.dc_count, 1406 acb->sc_kv.dc_addr); 1407 else 1408 i=sbicxfout(regs, 1409 acb->sc_kv.dc_count, 1410 acb->sc_kv.dc_addr, 1411 SBIC_PHASE(csr)); 1412 acb->sc_kv.dc_addr += 1413 (acb->sc_kv.dc_count - i); 1414 acb->sc_kv.dc_count = i; 1415 i = 1; 1416 } 1417 break; 1418 1419 #endif 1420 case SBIC_CSR_XFERRED|STATUS_PHASE: 1421 case SBIC_CSR_MIS|STATUS_PHASE: 1422 case SBIC_CSR_MIS_1|STATUS_PHASE: 1423 case SBIC_CSR_MIS_2|STATUS_PHASE: 1424 /* 1425 * the sbic does the status/cmd-complete reading ok, 1426 * so do this with its hi-level commands. 1427 */ 1428 #ifdef DEBUG 1429 if(sbic_debug) 1430 printf("SBICICMD status phase\n"); 1431 #endif 1432 SBIC_TC_PUT(regs, 0); 1433 SET_SBIC_cmd_phase(regs, 0x46); 1434 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1435 break; 1436 1437 #if THIS_IS_A_RESERVED_STATE 1438 case BUS_FREE_PHASE: /* This is not legal */ 1439 if( dev->sc_stat[0] != 0xff ) 1440 goto out; 1441 break; 1442 #endif 1443 1444 default: 1445 i = sbicnextstate(dev, csr, asr); 1446 } 1447 1448 /* 1449 * make sure the last command was taken, 1450 * ie. we're not hunting after an ignored command.. 1451 */ 1452 GET_SBIC_asr(regs, asr); 1453 1454 /* tapes may take a loooong time.. */ 1455 while (asr & SBIC_ASR_BSY){ 1456 if(asr & SBIC_ASR_DBR) { 1457 printf("sbicicmd: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", 1458 csr,asr); 1459 #ifdef DDB 1460 Debugger(); 1461 #endif 1462 /* SBIC is jammed */ 1463 /* DUNNO which direction */ 1464 /* Try old direction */ 1465 GET_SBIC_data(regs,i); 1466 GET_SBIC_asr(regs, asr); 1467 if( asr & SBIC_ASR_DBR) /* Wants us to write */ 1468 SET_SBIC_data(regs,i); 1469 } 1470 GET_SBIC_asr(regs, asr); 1471 } 1472 1473 /* 1474 * wait for last command to complete 1475 */ 1476 if (asr & SBIC_ASR_LCI) { 1477 printf("sbicicmd: last command ignored\n"); 1478 } 1479 else if( i == 1 ) /* Bsy */ 1480 SBIC_WAIT (regs, SBIC_ASR_INT, wait); 1481 1482 /* 1483 * do it again 1484 */ 1485 } while ( i > 0 && dev->sc_stat[0] == 0xff); 1486 1487 /* Sometimes we need to do an extra read of the CSR */ 1488 GET_SBIC_csr(regs, csr); 1489 CSR_TRACE('I',csr,asr,0xff); 1490 1491 #if CSR_LOG_BUF_SIZE 1492 if(reselect_debug>1) 1493 for(i=0; i<bufptr; i++) 1494 printf("CSR:%02x", csrbuf[i]); 1495 #endif 1496 1497 #ifdef DEBUG 1498 if(data_pointer_debug > 1) 1499 printf("sbicicmd done(%d,%d):%d =%d=\n", 1500 dev->target, lun, 1501 acb->sc_kv.dc_count, 1502 dev->sc_stat[0]); 1503 #endif 1504 1505 QPRINTF(("=STS:%02x=", dev->sc_stat[0])); 1506 dev->sc_flags &= ~SBICF_ICMD; 1507 1508 SBIC_TRACE(dev); 1509 return(dev->sc_stat[0]); 1510 } 1511 1512 /* 1513 * Finish SCSI xfer command: After the completion interrupt from 1514 * a read/write operation, sequence through the final phases in 1515 * programmed i/o. This routine is a lot like sbicicmd except we 1516 * skip (and don't allow) the select, cmd out and data in/out phases. 1517 */ 1518 void 1519 sbicxfdone(struct sbic_softc *dev, sbic_regmap_t regs, int target) 1520 { 1521 u_char phase, asr, csr; 1522 int s; 1523 1524 SBIC_TRACE(dev); 1525 QPRINTF(("{")); 1526 s = splbio(); 1527 1528 /* 1529 * have the sbic complete on its own 1530 */ 1531 SBIC_TC_PUT(regs, 0); 1532 SET_SBIC_cmd_phase(regs, 0x46); 1533 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1534 1535 do { 1536 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0); 1537 GET_SBIC_csr (regs, csr); 1538 CSR_TRACE('f',csr,asr,target); 1539 QPRINTF(("%02x:", csr)); 1540 } while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) 1541 && (csr != SBIC_CSR_S_XFERRED)); 1542 1543 dev->sc_flags &= ~SBICF_SELECTED; 1544 1545 GET_SBIC_cmd_phase (regs, phase); 1546 QPRINTF(("}%02x", phase)); 1547 if (phase == 0x60) 1548 GET_SBIC_tlun(regs, dev->sc_stat[0]); 1549 else 1550 sbicerror(dev, regs, csr); 1551 1552 QPRINTF(("=STS:%02x=\n", dev->sc_stat[0])); 1553 splx(s); 1554 SBIC_TRACE(dev); 1555 } 1556 1557 /* 1558 * No DMA chains 1559 */ 1560 1561 int 1562 sbicgo(struct sbic_softc *dev, struct scsipi_xfer *xs) 1563 { 1564 int i, dmaflags, count, usedma; 1565 u_char csr, asr, *addr; 1566 sbic_regmap_t regs; 1567 struct sbic_acb *acb; 1568 1569 SBIC_TRACE(dev); 1570 dev->target = xs->xs_periph->periph_target; 1571 dev->lun = xs->xs_periph->periph_lun; 1572 acb = dev->sc_nexus; 1573 regs = dev->sc_sbic; 1574 1575 usedma = sbicdmaok(dev, xs); 1576 #ifdef DEBUG 1577 routine = 1; 1578 debug_sbic_regs = regs; /* store this to allow debug calls */ 1579 if( data_pointer_debug > 1 ) 1580 printf("sbicgo(%d,%d)\n", dev->target, dev->lun); 1581 #endif 1582 1583 /* 1584 * set the sbic into DMA mode 1585 */ 1586 if( usedma ) 1587 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI | 1588 SBIC_MACHINE_DMA_MODE); 1589 else 1590 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1591 1592 1593 /* 1594 * select the SCSI bus (it's an error if bus isn't free) 1595 */ 1596 if (sbicselectbus(dev, regs, dev->target, dev->lun, 1597 dev->sc_scsiaddr)) { 1598 /* printf("sbicgo: Trying to select busy bus!\n"); */ 1599 SBIC_TRACE(dev); 1600 return(0); /* Not done: needs to be rescheduled */ 1601 } 1602 dev->sc_stat[0] = 0xff; 1603 1604 /* 1605 * Calculate DMA chains now 1606 */ 1607 1608 dmaflags = 0; 1609 if (acb->flags & ACB_DATAIN) 1610 dmaflags |= DMAGO_READ; 1611 1612 1613 /* 1614 * Deal w/bounce buffers. 1615 */ 1616 1617 addr = acb->sc_kv.dc_addr; 1618 count = acb->sc_kv.dc_count; 1619 if (count && (char *)kvtop(addr) != acb->sc_pa.dc_addr) { /* XXXX check */ 1620 printf("sbic: DMA buffer mapping changed %p->%x\n", 1621 acb->sc_pa.dc_addr, kvtop(addr)); 1622 #ifdef DDB 1623 Debugger(); 1624 #endif 1625 } 1626 1627 #ifdef DEBUG 1628 ++sbicdma_ops; /* count total DMA operations */ 1629 #endif 1630 if (count && usedma && dev->sc_flags & SBICF_BADDMA && 1631 sbiccheckdmap(addr, count, dev->sc_dmamask)) { 1632 /* 1633 * need to bounce the DMA. 1634 */ 1635 if (dmaflags & DMAGO_READ) { 1636 acb->flags |= ACB_BBUF; 1637 acb->sc_dmausrbuf = addr; 1638 acb->sc_dmausrlen = count; 1639 acb->sc_usrbufpa = (u_char *)kvtop(addr); 1640 if(!dev->sc_tinfo[dev->target].bounce) { 1641 printf("sbicgo: HELP! no bounce allocated for %d\n", 1642 dev->target); 1643 printf("xfer: (%p->%p,%lx)\n", acb->sc_dmausrbuf, 1644 acb->sc_usrbufpa, acb->sc_dmausrlen); 1645 dev->sc_tinfo[xs->xs_periph->periph_target].bounce 1646 = (char *)alloc_z2mem(MAXPHYS); 1647 if (isztwomem(dev->sc_tinfo[xs->xs_periph->periph_target].bounce)) 1648 printf("alloc ZII target %d bounce pa 0x%x\n", 1649 xs->xs_periph->periph_target, 1650 kvtop(dev->sc_tinfo[xs->xs_periph->periph_target].bounce)); 1651 else if (dev->sc_tinfo[xs->xs_periph->periph_target].bounce) 1652 printf("alloc CHIP target %d bounce pa 0x%p\n", 1653 xs->xs_periph->periph_target, 1654 PREP_DMA_MEM(dev->sc_tinfo[xs->xs_periph->periph_target].bounce)); 1655 1656 printf("Allocating %d bounce at %x\n", 1657 dev->target, 1658 kvtop(dev->sc_tinfo[dev->target].bounce)); 1659 } 1660 } else { /* write: copy to DMA buffer */ 1661 #ifdef DEBUG 1662 if(data_pointer_debug) 1663 printf("sbicgo: copying %x bytes to target %d bounce %x\n", 1664 count, dev->target, 1665 kvtop(dev->sc_tinfo[dev->target].bounce)); 1666 #endif 1667 bcopy (addr, dev->sc_tinfo[dev->target].bounce, count); 1668 } 1669 addr = dev->sc_tinfo[dev->target].bounce;/* and use DMA buffer */ 1670 acb->sc_kv.dc_addr = addr; 1671 #ifdef DEBUG 1672 ++sbicdma_bounces; /* count number of bounced */ 1673 #endif 1674 } 1675 1676 /* 1677 * Allocate the DMA chain 1678 */ 1679 1680 /* Set start KVM addresses */ 1681 #if 0 1682 acb->sc_kv.dc_addr = addr; 1683 acb->sc_kv.dc_count = count; 1684 #endif 1685 1686 /* Mark end of segment */ 1687 acb->sc_tcnt = dev->sc_tcnt = 0; 1688 acb->sc_pa.dc_count = 0; 1689 1690 sbic_load_ptrs(dev, regs, dev->target, dev->lun); 1691 SBIC_TRACE(dev); 1692 /* Enable interrupts but don't do any DMA */ 1693 dev->sc_enintr(dev); 1694 if (usedma) { 1695 dev->sc_tcnt = dev->sc_dmago(dev, acb->sc_pa.dc_addr, 1696 acb->sc_pa.dc_count, 1697 dmaflags); 1698 #ifdef DEBUG 1699 dev->sc_dmatimo = dev->sc_tcnt ? 1 : 0; 1700 #endif 1701 } else 1702 dev->sc_dmacmd = 0; /* Don't use DMA */ 1703 dev->sc_flags |= SBICF_INDMA; 1704 /* SBIC_TC_PUT(regs, dev->sc_tcnt); */ /* XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX */ 1705 SBIC_TRACE(dev); 1706 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 1707 1708 /* 1709 * push the data cache ( I think this won't work (EH)) 1710 */ 1711 #if defined(M68040) || defined(M68060) 1712 if (mmutype == MMU_68040 && usedma && count) { 1713 dma_cachectl(addr, count); 1714 if (((u_int)addr & 0xF) || (((u_int)addr + count) & 0xF)) 1715 dev->sc_flags |= SBICF_DCFLUSH; 1716 } 1717 #endif 1718 1719 /* 1720 * enintr() also enables interrupts for the sbic 1721 */ 1722 #ifdef DEBUG 1723 if( data_pointer_debug > 1 ) 1724 printf("sbicgo dmago:%d(%p:%lx)\n", 1725 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 1726 #if 0 1727 /* 1728 * Hmm - this isn't right: asr and csr haven't been set yet. 1729 */ 1730 debug_asr = asr; 1731 debug_csr = csr; 1732 #endif 1733 #endif 1734 1735 /* 1736 * Lets cycle a while then let the interrupt handler take over 1737 */ 1738 1739 GET_SBIC_asr(regs, asr); 1740 do { 1741 GET_SBIC_csr(regs, csr); 1742 CSR_TRACE('g',csr,asr,dev->target); 1743 #ifdef DEBUG 1744 debug_csr = csr; 1745 routine = 1; 1746 #endif 1747 QPRINTF(("go[0x%x]", csr)); 1748 1749 i = sbicnextstate(dev, csr, asr); 1750 1751 WAIT_CIP(regs); 1752 GET_SBIC_asr(regs, asr); 1753 #ifdef DEBUG 1754 debug_asr = asr; 1755 #endif 1756 if(asr & SBIC_ASR_LCI) printf("sbicgo: LCI asr:%02x csr:%02x\n", 1757 asr,csr); 1758 } while( i == SBIC_STATE_RUNNING 1759 && asr & (SBIC_ASR_INT|SBIC_ASR_LCI) ); 1760 1761 CSR_TRACE('g',csr,asr,i<<4); 1762 SBIC_TRACE(dev); 1763 if (i == SBIC_STATE_DONE && dev->sc_stat[0] == 0xff) printf("sbicgo: done & stat = 0xff\n"); 1764 if (i == SBIC_STATE_DONE && dev->sc_stat[0] != 0xff) { 1765 /* if( i == SBIC_STATE_DONE && dev->sc_stat[0] ) { */ 1766 /* Did we really finish that fast? */ 1767 return 1; 1768 } 1769 return 0; 1770 } 1771 1772 1773 int 1774 sbicintr(struct sbic_softc *dev) 1775 { 1776 sbic_regmap_t regs; 1777 u_char asr, csr; 1778 int i; 1779 1780 regs = dev->sc_sbic; 1781 1782 /* 1783 * pending interrupt? 1784 */ 1785 GET_SBIC_asr (regs, asr); 1786 if ((asr & SBIC_ASR_INT) == 0) 1787 return(0); 1788 1789 SBIC_TRACE(dev); 1790 do { 1791 GET_SBIC_csr(regs, csr); 1792 CSR_TRACE('i',csr,asr,dev->target); 1793 #ifdef DEBUG 1794 debug_csr = csr; 1795 routine = 2; 1796 #endif 1797 QPRINTF(("intr[0x%x]", csr)); 1798 1799 i = sbicnextstate(dev, csr, asr); 1800 1801 WAIT_CIP(regs); 1802 GET_SBIC_asr(regs, asr); 1803 #ifdef DEBUG 1804 debug_asr = asr; 1805 #endif 1806 #if 0 1807 if(asr & SBIC_ASR_LCI) printf("sbicintr: LCI asr:%02x csr:%02x\n", 1808 asr,csr); 1809 #endif 1810 } while(i == SBIC_STATE_RUNNING && 1811 asr & (SBIC_ASR_INT|SBIC_ASR_LCI)); 1812 CSR_TRACE('i',csr,asr,i<<4); 1813 SBIC_TRACE(dev); 1814 return(1); 1815 } 1816 1817 /* 1818 * Run commands and wait for disconnect 1819 */ 1820 int 1821 sbicpoll(struct sbic_softc *dev) 1822 { 1823 sbic_regmap_t regs; 1824 u_char asr, csr; 1825 int i; 1826 1827 SBIC_TRACE(dev); 1828 regs = dev->sc_sbic; 1829 1830 do { 1831 GET_SBIC_asr (regs, asr); 1832 #ifdef DEBUG 1833 debug_asr = asr; 1834 #endif 1835 GET_SBIC_csr(regs, csr); 1836 CSR_TRACE('p',csr,asr,dev->target); 1837 #ifdef DEBUG 1838 debug_csr = csr; 1839 routine = 2; 1840 #endif 1841 QPRINTF(("poll[0x%x]", csr)); 1842 1843 i = sbicnextstate(dev, csr, asr); 1844 1845 WAIT_CIP(regs); 1846 GET_SBIC_asr(regs, asr); 1847 /* tapes may take a loooong time.. */ 1848 while (asr & SBIC_ASR_BSY){ 1849 if(asr & SBIC_ASR_DBR) { 1850 printf("sbipoll: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", 1851 csr,asr); 1852 #ifdef DDB 1853 Debugger(); 1854 #endif 1855 /* SBIC is jammed */ 1856 /* DUNNO which direction */ 1857 /* Try old direction */ 1858 GET_SBIC_data(regs,i); 1859 GET_SBIC_asr(regs, asr); 1860 if( asr & SBIC_ASR_DBR) /* Wants us to write */ 1861 SET_SBIC_data(regs,i); 1862 } 1863 GET_SBIC_asr(regs, asr); 1864 } 1865 1866 if(asr & SBIC_ASR_LCI) printf("sbicpoll: LCI asr:%02x csr:%02x\n", 1867 asr,csr); 1868 else if( i == 1 ) /* BSY */ 1869 SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait); 1870 } while(i == SBIC_STATE_RUNNING); 1871 CSR_TRACE('p',csr,asr,i<<4); 1872 SBIC_TRACE(dev); 1873 return(1); 1874 } 1875 1876 /* 1877 * Handle a single msgin 1878 */ 1879 1880 int 1881 sbicmsgin(struct sbic_softc *dev) 1882 { 1883 sbic_regmap_t regs; 1884 int recvlen; 1885 u_char asr, csr, *tmpaddr; 1886 1887 regs = dev->sc_sbic; 1888 1889 dev->sc_msg[0] = 0xff; 1890 dev->sc_msg[1] = 0xff; 1891 1892 GET_SBIC_asr(regs, asr); 1893 #ifdef DEBUG 1894 if(reselect_debug>1) 1895 printf("sbicmsgin asr=%02x\n", asr); 1896 #endif 1897 1898 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 1899 1900 GET_SBIC_selid (regs, csr); 1901 SET_SBIC_selid (regs, csr | SBIC_SID_FROM_SCSI); 1902 1903 SBIC_TC_PUT(regs, 0); 1904 tmpaddr = dev->sc_msg; 1905 recvlen = 1; 1906 do { 1907 while( recvlen-- ) { 1908 GET_SBIC_asr(regs, asr); 1909 GET_SBIC_csr(regs, csr); 1910 QPRINTF(("sbicmsgin ready to go (csr,asr)=(%02x,%02x)\n", 1911 csr, asr)); 1912 1913 RECV_BYTE(regs, *tmpaddr); 1914 CSR_TRACE('m',csr,asr,*tmpaddr); 1915 #if 1 1916 /* 1917 * get the command completion interrupt, or we 1918 * can't send a new command (LCI) 1919 */ 1920 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1921 GET_SBIC_csr(regs, csr); 1922 CSR_TRACE('X',csr,asr,dev->target); 1923 #else 1924 WAIT_CIP(regs); 1925 do { 1926 GET_SBIC_asr(regs, asr); 1927 csr = 0xff; 1928 GET_SBIC_csr(regs, csr); 1929 CSR_TRACE('X',csr,asr,dev->target); 1930 if( csr == 0xff ) 1931 printf("sbicmsgin waiting: csr %02x asr %02x\n", csr, asr); 1932 } while( csr == 0xff ); 1933 #endif 1934 #ifdef DEBUG 1935 if(reselect_debug>1) 1936 printf("sbicmsgin: got %02x csr %02x asr %02x\n", 1937 *tmpaddr, csr, asr); 1938 #endif 1939 #if do_parity_check 1940 if( asr & SBIC_ASR_PE ) { 1941 printf ("Parity error"); 1942 /* This code simply does not work. */ 1943 WAIT_CIP(regs); 1944 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 1945 WAIT_CIP(regs); 1946 GET_SBIC_asr(regs, asr); 1947 WAIT_CIP(regs); 1948 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 1949 WAIT_CIP(regs); 1950 if( !(asr & SBIC_ASR_LCI) ) 1951 /* Target wants to send garbled msg*/ 1952 continue; 1953 printf("--fixing\n"); 1954 /* loop until a msgout phase occurs on target */ 1955 while(csr & 0x07 != MESG_OUT_PHASE) { 1956 while( asr & SBIC_ASR_BSY && 1957 !(asr & SBIC_ASR_DBR|SBIC_ASR_INT) ) 1958 GET_SBIC_asr(regs, asr); 1959 if( asr & SBIC_ASR_DBR ) 1960 panic("msgin: jammed again!"); 1961 GET_SBIC_csr(regs, csr); 1962 CSR_TRACE('e',csr,asr,dev->target); 1963 if( csr & 0x07 != MESG_OUT_PHASE ) { 1964 sbicnextstate(dev, csr, asr); 1965 sbic_save_ptrs(dev, regs, 1966 dev->target, 1967 dev->lun); 1968 } 1969 } 1970 /* Should be msg out by now */ 1971 SEND_BYTE(regs, MSG_PARITY_ERROR); 1972 } 1973 else 1974 #endif 1975 tmpaddr++; 1976 1977 if(recvlen) { 1978 /* Clear ACK */ 1979 WAIT_CIP(regs); 1980 GET_SBIC_asr(regs, asr); 1981 GET_SBIC_csr(regs, csr); 1982 CSR_TRACE('X',csr,asr,dev->target); 1983 QPRINTF(("sbicmsgin pre byte CLR_ACK (csr,asr)=(%02x,%02x)\n", 1984 csr, asr)); 1985 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 1986 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1987 } 1988 1989 }; 1990 1991 if(dev->sc_msg[0] == 0xff) { 1992 printf("sbicmsgin: sbic swallowed our message\n"); 1993 break; 1994 } 1995 #ifdef DEBUG 1996 if (sync_debug) 1997 printf("msgin done csr 0x%x asr 0x%x msg 0x%x\n", 1998 csr, asr, dev->sc_msg[0]); 1999 #endif 2000 /* 2001 * test whether this is a reply to our sync 2002 * request 2003 */ 2004 if (MSG_ISIDENTIFY(dev->sc_msg[0])) { 2005 QPRINTF(("IFFY")); 2006 #if 0 2007 /* There is an implied load-ptrs here */ 2008 sbic_load_ptrs(dev, regs, dev->target, dev->lun); 2009 #endif 2010 /* Got IFFY msg -- ack it */ 2011 } else if (dev->sc_msg[0] == MSG_REJECT 2012 && dev->sc_sync[dev->target].state == SYNC_SENT) { 2013 QPRINTF(("REJECT of SYN")); 2014 #ifdef DEBUG 2015 if (sync_debug) 2016 printf("target %d rejected sync, going async\n", 2017 dev->target); 2018 #endif 2019 dev->sc_sync[dev->target].period = sbic_min_period; 2020 dev->sc_sync[dev->target].offset = 0; 2021 dev->sc_sync[dev->target].state = SYNC_DONE; 2022 SET_SBIC_syn(regs, 2023 SBIC_SYN(dev->sc_sync[dev->target].offset, 2024 dev->sc_sync[dev->target].period)); 2025 } else if ((dev->sc_msg[0] == MSG_REJECT)) { 2026 QPRINTF(("REJECT")); 2027 /* 2028 * we'll never REJECt a REJECT message.. 2029 */ 2030 } else if ((dev->sc_msg[0] == MSG_SAVE_DATA_PTR)) { 2031 QPRINTF(("MSG_SAVE_DATA_PTR")); 2032 /* 2033 * don't reject this either. 2034 */ 2035 } else if ((dev->sc_msg[0] == MSG_DISCONNECT)) { 2036 QPRINTF(("DISCONNECT")); 2037 #ifdef DEBUG 2038 if( reselect_debug>1 && dev->sc_msg[0] == MSG_DISCONNECT ) 2039 printf("sbicmsgin: got disconnect msg %s\n", 2040 (dev->sc_flags & SBICF_ICMD)?"rejecting":""); 2041 #endif 2042 if( dev->sc_flags & SBICF_ICMD ) { 2043 /* We're in immediate mode. Prevent disconnects. */ 2044 /* prepare to reject the message, NACK */ 2045 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2046 WAIT_CIP(regs); 2047 } 2048 } else if (dev->sc_msg[0] == MSG_CMD_COMPLETE ) { 2049 QPRINTF(("CMD_COMPLETE")); 2050 /* !! KLUDGE ALERT !! quite a few drives don't seem to 2051 * really like the current way of sending the 2052 * sync-handshake together with the ident-message, and 2053 * they react by sending command-complete and 2054 * disconnecting right after returning the valid sync 2055 * handshake. So, all I can do is reselect the drive, 2056 * and hope it won't disconnect again. I don't think 2057 * this is valid behavior, but I can't help fixing a 2058 * problem that apparently exists. 2059 * 2060 * Note: we should not get here on `normal' command 2061 * completion, as that condition is handled by the 2062 * high-level sel&xfer resume command used to walk 2063 * thru status/cc-phase. 2064 */ 2065 2066 #ifdef DEBUG 2067 if (sync_debug) 2068 printf ("GOT MSG %d! target %d acting weird.." 2069 " waiting for disconnect...\n", 2070 dev->sc_msg[0], dev->target); 2071 #endif 2072 /* Check to see if sbic is handling this */ 2073 GET_SBIC_asr(regs, asr); 2074 if(asr & SBIC_ASR_BSY) 2075 return SBIC_STATE_RUNNING; 2076 2077 /* Let's try this: Assume it works and set status to 00 */ 2078 dev->sc_stat[0] = 0; 2079 } else if (dev->sc_msg[0] == MSG_EXT_MESSAGE 2080 && tmpaddr == &dev->sc_msg[1]) { 2081 QPRINTF(("ExtMSG\n")); 2082 /* Read in whole extended message */ 2083 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2084 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2085 GET_SBIC_asr(regs, asr); 2086 GET_SBIC_csr(regs, csr); 2087 QPRINTF(("CLR ACK asr %02x, csr %02x\n", asr, csr)); 2088 RECV_BYTE(regs, *tmpaddr); 2089 CSR_TRACE('x',csr,asr,*tmpaddr); 2090 /* Wait for command completion IRQ */ 2091 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2092 recvlen = *tmpaddr++; 2093 QPRINTF(("Recving ext msg, asr %02x csr %02x len %02x\n", 2094 asr, csr, recvlen)); 2095 } else if (dev->sc_msg[0] == MSG_EXT_MESSAGE && dev->sc_msg[1] == 3 2096 && dev->sc_msg[2] == MSG_SYNC_REQ) { 2097 QPRINTF(("SYN")); 2098 dev->sc_sync[dev->target].period = 2099 sbicfromscsiperiod(dev, 2100 regs, dev->sc_msg[3]); 2101 dev->sc_sync[dev->target].offset = dev->sc_msg[4]; 2102 dev->sc_sync[dev->target].state = SYNC_DONE; 2103 SET_SBIC_syn(regs, 2104 SBIC_SYN(dev->sc_sync[dev->target].offset, 2105 dev->sc_sync[dev->target].period)); 2106 printf("%s: target %d now synchronous," 2107 " period=%dns, offset=%d.\n", 2108 dev->sc_dev.dv_xname, dev->target, 2109 dev->sc_msg[3] * 4, dev->sc_msg[4]); 2110 } else { 2111 #ifdef DEBUG 2112 if (sbic_debug || sync_debug) 2113 printf ("sbicmsgin: Rejecting message 0x%02x\n", 2114 dev->sc_msg[0]); 2115 #endif 2116 /* prepare to reject the message, NACK */ 2117 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2118 WAIT_CIP(regs); 2119 } 2120 /* Clear ACK */ 2121 WAIT_CIP(regs); 2122 GET_SBIC_asr(regs, asr); 2123 GET_SBIC_csr(regs, csr); 2124 CSR_TRACE('X',csr,asr,dev->target); 2125 QPRINTF(("sbicmsgin pre CLR_ACK (csr,asr)=(%02x,%02x)%d\n", 2126 csr, asr, recvlen)); 2127 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2128 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2129 } 2130 #if 0 2131 while((csr == SBIC_CSR_MSGIN_W_ACK) 2132 || (SBIC_PHASE(csr) == MESG_IN_PHASE)); 2133 #else 2134 while (recvlen>0); 2135 #endif 2136 2137 QPRINTF(("sbicmsgin finished: csr %02x, asr %02x\n",csr, asr)); 2138 2139 /* Should still have one CSR to read */ 2140 return SBIC_STATE_RUNNING; 2141 } 2142 2143 2144 /* 2145 * sbicnextstate() 2146 * return: 2147 * 0 == done 2148 * 1 == working 2149 * 2 == disconnected 2150 * -1 == error 2151 */ 2152 int 2153 sbicnextstate(struct sbic_softc *dev, u_char csr, u_char asr) 2154 { 2155 sbic_regmap_t regs; 2156 struct sbic_acb *acb; 2157 int i, newtarget, newlun, wait; 2158 #if 0 2159 unsigned tcnt; 2160 #endif 2161 2162 i = 0; 2163 SBIC_TRACE(dev); 2164 regs = dev->sc_sbic; 2165 acb = dev->sc_nexus; 2166 2167 QPRINTF(("next[%02x,%02x]",asr,csr)); 2168 2169 switch (csr) { 2170 case SBIC_CSR_XFERRED|CMD_PHASE: 2171 case SBIC_CSR_MIS|CMD_PHASE: 2172 case SBIC_CSR_MIS_1|CMD_PHASE: 2173 case SBIC_CSR_MIS_2|CMD_PHASE: 2174 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 2175 if (sbicxfstart(regs, acb->clen, CMD_PHASE, sbic_cmd_wait)) 2176 if (sbicxfout(regs, acb->clen, 2177 &acb->cmd, CMD_PHASE)) 2178 goto abort; 2179 break; 2180 2181 case SBIC_CSR_XFERRED|STATUS_PHASE: 2182 case SBIC_CSR_MIS|STATUS_PHASE: 2183 case SBIC_CSR_MIS_1|STATUS_PHASE: 2184 case SBIC_CSR_MIS_2|STATUS_PHASE: 2185 /* 2186 * this should be the normal i/o completion case. 2187 * get the status & cmd complete msg then let the 2188 * device driver look at what happened. 2189 */ 2190 sbicxfdone(dev,regs,dev->target); 2191 /* 2192 * check for overlapping cache line, flush if so 2193 */ 2194 #if defined(M68040) || defined(M68060) 2195 if (dev->sc_flags & SBICF_DCFLUSH) { 2196 #if 0 2197 printf("sbic: 68040/68060 DMA cache flush needs" 2198 "fixing? %x:%x\n", 2199 dev->sc_xs->data, dev->sc_xs->datalen); 2200 #endif 2201 } 2202 #endif 2203 #ifdef DEBUG 2204 if( data_pointer_debug > 1 ) 2205 printf("next dmastop: %d(%p:%lx)\n", 2206 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 2207 dev->sc_dmatimo = 0; 2208 #endif 2209 dev->sc_dmastop(dev); /* was dmafree */ 2210 if (acb->flags & ACB_BBUF) { 2211 if ((u_char *)kvtop(acb->sc_dmausrbuf) != acb->sc_usrbufpa) 2212 printf("%s: WARNING - buffer mapping changed %p->%x\n", 2213 dev->sc_dev.dv_xname, acb->sc_usrbufpa, 2214 kvtop(acb->sc_dmausrbuf)); 2215 #ifdef DEBUG 2216 if(data_pointer_debug) 2217 printf("sbicgo:copying %lx bytes from target %d bounce %x\n", 2218 acb->sc_dmausrlen, 2219 dev->target, 2220 kvtop(dev->sc_tinfo[dev->target].bounce)); 2221 #endif 2222 bcopy(dev->sc_tinfo[dev->target].bounce, 2223 acb->sc_dmausrbuf, 2224 acb->sc_dmausrlen); 2225 } 2226 dev->sc_flags &= ~(SBICF_INDMA | SBICF_DCFLUSH); 2227 sbic_scsidone(acb, dev->sc_stat[0]); 2228 SBIC_TRACE(dev); 2229 return SBIC_STATE_DONE; 2230 2231 case SBIC_CSR_XFERRED|DATA_OUT_PHASE: 2232 case SBIC_CSR_XFERRED|DATA_IN_PHASE: 2233 case SBIC_CSR_MIS|DATA_OUT_PHASE: 2234 case SBIC_CSR_MIS|DATA_IN_PHASE: 2235 case SBIC_CSR_MIS_1|DATA_OUT_PHASE: 2236 case SBIC_CSR_MIS_1|DATA_IN_PHASE: 2237 case SBIC_CSR_MIS_2|DATA_OUT_PHASE: 2238 case SBIC_CSR_MIS_2|DATA_IN_PHASE: 2239 if( dev->sc_xs->xs_control & XS_CTL_POLL || dev->sc_flags & SBICF_ICMD 2240 || acb->sc_dmacmd == 0 ) { 2241 /* Do PIO */ 2242 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2243 if (acb->sc_kv.dc_count <= 0) { 2244 printf("sbicnextstate:xfer count %d asr%x csr%x\n", 2245 acb->sc_kv.dc_count, asr, csr); 2246 goto abort; 2247 } 2248 wait = sbic_data_wait; 2249 if( sbicxfstart(regs, 2250 acb->sc_kv.dc_count, 2251 SBIC_PHASE(csr), wait)) { 2252 if( SBIC_PHASE(csr) == DATA_IN_PHASE ) 2253 /* data in? */ 2254 i=sbicxfin(regs, 2255 acb->sc_kv.dc_count, 2256 acb->sc_kv.dc_addr); 2257 else 2258 i=sbicxfout(regs, 2259 acb->sc_kv.dc_count, 2260 acb->sc_kv.dc_addr, 2261 SBIC_PHASE(csr)); 2262 } 2263 acb->sc_kv.dc_addr += 2264 (acb->sc_kv.dc_count - i); 2265 acb->sc_kv.dc_count = i; 2266 } else { 2267 if (acb->sc_kv.dc_count <= 0) { 2268 printf("sbicnextstate:xfer count %d asr%x csr%x\n", 2269 acb->sc_kv.dc_count, asr, csr); 2270 goto abort; 2271 } 2272 /* 2273 * do scatter-gather DMA 2274 * hacking the controller chip, ouch.. 2275 */ 2276 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI | 2277 SBIC_MACHINE_DMA_MODE); 2278 /* 2279 * set next DMA addr and dec count 2280 */ 2281 #if 0 2282 SBIC_TC_GET(regs, tcnt); 2283 dev->sc_cur->dc_count -= ((dev->sc_tcnt - tcnt) >> 1); 2284 dev->sc_cur->dc_addr += (dev->sc_tcnt - tcnt); 2285 dev->sc_tcnt = acb->sc_tcnt = tcnt; 2286 #else 2287 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 2288 sbic_load_ptrs(dev, regs, dev->target, dev->lun); 2289 #endif 2290 #ifdef DEBUG 2291 if( data_pointer_debug > 1 ) 2292 printf("next dmanext: %d(%p:%lx)\n", 2293 dev->target,dev->sc_cur->dc_addr, 2294 dev->sc_tcnt); 2295 dev->sc_dmatimo = 1; 2296 #endif 2297 dev->sc_tcnt = dev->sc_dmanext(dev); 2298 SBIC_TC_PUT(regs, (unsigned)dev->sc_tcnt); 2299 SET_SBIC_cmd(regs, SBIC_CMD_XFER_INFO); 2300 dev->sc_flags |= SBICF_INDMA; 2301 } 2302 break; 2303 2304 case SBIC_CSR_XFERRED|MESG_IN_PHASE: 2305 case SBIC_CSR_MIS|MESG_IN_PHASE: 2306 case SBIC_CSR_MIS_1|MESG_IN_PHASE: 2307 case SBIC_CSR_MIS_2|MESG_IN_PHASE: 2308 SBIC_TRACE(dev); 2309 return sbicmsgin(dev); 2310 2311 case SBIC_CSR_MSGIN_W_ACK: 2312 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); /* Dunno what I'm ACKing */ 2313 printf("Acking unknown msgin CSR:%02x",csr); 2314 break; 2315 2316 case SBIC_CSR_XFERRED|MESG_OUT_PHASE: 2317 case SBIC_CSR_MIS|MESG_OUT_PHASE: 2318 case SBIC_CSR_MIS_1|MESG_OUT_PHASE: 2319 case SBIC_CSR_MIS_2|MESG_OUT_PHASE: 2320 #ifdef DEBUG 2321 if (sync_debug) 2322 printf ("sending REJECT msg to last msg.\n"); 2323 #endif 2324 2325 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 2326 /* 2327 * should only get here on reject, 2328 * since it's always US that 2329 * initiate a sync transfer 2330 */ 2331 SEND_BYTE(regs, MSG_REJECT); 2332 WAIT_CIP(regs); 2333 if( asr & (SBIC_ASR_BSY|SBIC_ASR_LCI|SBIC_ASR_CIP) ) 2334 printf("next: REJECT sent asr %02x\n", asr); 2335 SBIC_TRACE(dev); 2336 return SBIC_STATE_RUNNING; 2337 2338 case SBIC_CSR_DISC: 2339 case SBIC_CSR_DISC_1: 2340 dev->sc_flags &= ~(SBICF_INDMA|SBICF_SELECTED); 2341 2342 /* Try to schedule another target */ 2343 #ifdef DEBUG 2344 if(reselect_debug>1) 2345 printf("sbicnext target %d disconnected\n", dev->target); 2346 #endif 2347 TAILQ_INSERT_HEAD(&dev->nexus_list, acb, chain); 2348 ++dev->sc_tinfo[dev->target].dconns; 2349 dev->sc_nexus = NULL; 2350 dev->sc_xs = NULL; 2351 2352 if( acb->xs->xs_control & XS_CTL_POLL 2353 || (dev->sc_flags & SBICF_ICMD) 2354 || !sbic_parallel_operations ) { 2355 SBIC_TRACE(dev); 2356 return SBIC_STATE_DISCONNECT; 2357 } 2358 sbic_sched(dev); 2359 SBIC_TRACE(dev); 2360 return SBIC_STATE_DISCONNECT; 2361 2362 case SBIC_CSR_RSLT_NI: 2363 case SBIC_CSR_RSLT_IFY: 2364 GET_SBIC_rselid(regs, newtarget); 2365 /* check SBIC_RID_SIV? */ 2366 newtarget &= SBIC_RID_MASK; 2367 if (csr == SBIC_CSR_RSLT_IFY) { 2368 /* Read IFY msg to avoid lockup */ 2369 GET_SBIC_data(regs, newlun); 2370 WAIT_CIP(regs); 2371 newlun &= SBIC_TLUN_MASK; 2372 CSR_TRACE('r',csr,asr,newtarget); 2373 } else { 2374 /* Need to get IFY message */ 2375 for (newlun = 256; newlun; --newlun) { 2376 GET_SBIC_asr(regs, asr); 2377 if (asr & SBIC_ASR_INT) 2378 break; 2379 delay(1); 2380 } 2381 newlun = 0; /* XXXX */ 2382 if ((asr & SBIC_ASR_INT) == 0) { 2383 #ifdef DEBUG 2384 if (reselect_debug) 2385 printf("RSLT_NI - no IFFY message? asr %x\n", asr); 2386 #endif 2387 } else { 2388 GET_SBIC_csr(regs,csr); 2389 CSR_TRACE('n',csr,asr,newtarget); 2390 if (csr == (SBIC_CSR_MIS | MESG_IN_PHASE) || 2391 csr == (SBIC_CSR_MIS_1 | MESG_IN_PHASE) || 2392 csr == (SBIC_CSR_MIS_2 | MESG_IN_PHASE)) { 2393 sbicmsgin(dev); 2394 newlun = dev->sc_msg[0] & 7; 2395 } else { 2396 printf("RSLT_NI - not MESG_IN_PHASE %x\n", 2397 csr); 2398 } 2399 } 2400 } 2401 #ifdef DEBUG 2402 if(reselect_debug>1 || (reselect_debug && csr==SBIC_CSR_RSLT_NI)) 2403 printf("sbicnext: reselect %s from targ %d lun %d\n", 2404 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", 2405 newtarget, newlun); 2406 #endif 2407 if (dev->sc_nexus) { 2408 #ifdef DEBUG 2409 if (reselect_debug > 1) 2410 printf("%s: reselect %s with active command\n", 2411 dev->sc_dev.dv_xname, 2412 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY"); 2413 #ifdef DDB 2414 /* Debugger();*/ 2415 #endif 2416 #endif 2417 TAILQ_INSERT_HEAD(&dev->ready_list, dev->sc_nexus, chain); 2418 dev->sc_tinfo[dev->target].lubusy &= ~(1 << dev->lun); 2419 dev->sc_nexus = NULL; 2420 dev->sc_xs = NULL; 2421 } 2422 /* Reload sync values for this target */ 2423 if (dev->sc_sync[newtarget].state == SYNC_DONE) 2424 SET_SBIC_syn(regs, SBIC_SYN (dev->sc_sync[newtarget].offset, 2425 dev->sc_sync[newtarget].period)); 2426 else 2427 SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period)); 2428 for (acb = dev->nexus_list.tqh_first; acb; 2429 acb = acb->chain.tqe_next) { 2430 if (acb->xs->xs_periph->periph_target != newtarget || 2431 acb->xs->xs_periph->periph_lun != newlun) 2432 continue; 2433 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 2434 dev->sc_nexus = acb; 2435 dev->sc_xs = acb->xs; 2436 dev->sc_flags |= SBICF_SELECTED; 2437 dev->target = newtarget; 2438 dev->lun = newlun; 2439 break; 2440 } 2441 if (acb == NULL) { 2442 printf("%s: reselect %s targ %d not in nexus_list %p\n", 2443 dev->sc_dev.dv_xname, 2444 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", newtarget, 2445 &dev->nexus_list.tqh_first); 2446 panic("bad reselect in sbic"); 2447 } 2448 if (csr == SBIC_CSR_RSLT_IFY) 2449 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2450 break; 2451 2452 default: 2453 abort: 2454 /* 2455 * Something unexpected happened -- deal with it. 2456 */ 2457 printf("sbicnextstate: aborting csr %02x asr %02x\n", csr, asr); 2458 #ifdef DDB 2459 Debugger(); 2460 #endif 2461 #ifdef DEBUG 2462 if( data_pointer_debug > 1 ) 2463 printf("next dmastop: %d(%p:%lx)\n", 2464 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 2465 dev->sc_dmatimo = 0; 2466 #endif 2467 dev->sc_dmastop(dev); 2468 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2469 sbicerror(dev, regs, csr); 2470 sbicabort(dev, regs, "next"); 2471 if (dev->sc_flags & SBICF_INDMA) { 2472 /* 2473 * check for overlapping cache line, flush if so 2474 */ 2475 #if defined(M68040) || defined(M68060) 2476 if (dev->sc_flags & SBICF_DCFLUSH) { 2477 #if 0 2478 printf("sbic: 68040/060 DMA cache flush needs" 2479 "fixing? %x:%x\n", 2480 dev->sc_xs->data, dev->sc_xs->datalen); 2481 #endif 2482 } 2483 #endif 2484 dev->sc_flags &= 2485 ~(SBICF_INDMA | SBICF_DCFLUSH); 2486 #ifdef DEBUG 2487 if( data_pointer_debug > 1 ) 2488 printf("next dmastop: %d(%p:%lx)\n", 2489 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 2490 dev->sc_dmatimo = 0; 2491 #endif 2492 dev->sc_dmastop(dev); 2493 sbic_scsidone(acb, -1); 2494 } 2495 SBIC_TRACE(dev); 2496 return SBIC_STATE_ERROR; 2497 } 2498 2499 SBIC_TRACE(dev); 2500 return(SBIC_STATE_RUNNING); 2501 } 2502 2503 2504 /* 2505 * Check if DMA can not be used with specified buffer 2506 */ 2507 2508 int 2509 sbiccheckdmap(void *bp, u_long len, u_long mask) 2510 { 2511 u_char *buffer; 2512 u_long phy_buf; 2513 u_long phy_len; 2514 2515 buffer = bp; 2516 2517 if (len == 0) 2518 return(0); 2519 2520 while (len) { 2521 phy_buf = kvtop(buffer); 2522 if (len < (phy_len = PAGE_SIZE - ((int) buffer & PGOFSET))) 2523 phy_len = len; 2524 if (phy_buf & mask) 2525 return(1); 2526 buffer += phy_len; 2527 len -= phy_len; 2528 } 2529 return(0); 2530 } 2531 2532 int 2533 sbictoscsiperiod(struct sbic_softc *dev, sbic_regmap_t regs, int a) 2534 { 2535 unsigned int fs; 2536 2537 /* 2538 * cycle = DIV / (2*CLK) 2539 * DIV = FS+2 2540 * best we can do is 200ns at 20Mhz, 2 cycles 2541 */ 2542 2543 GET_SBIC_myid(regs,fs); 2544 fs = (fs >>6) + 2; /* DIV */ 2545 fs = (fs * 10000) / (dev->sc_clkfreq<<1); /* Cycle, in ns */ 2546 if (a < 2) a = 8; /* map to Cycles */ 2547 return ((fs*a)>>2); /* in 4 ns units */ 2548 } 2549 2550 int 2551 sbicfromscsiperiod(struct sbic_softc *dev, sbic_regmap_t regs, int p) 2552 { 2553 register unsigned int fs, ret; 2554 2555 /* Just the inverse of the above */ 2556 2557 GET_SBIC_myid(regs,fs); 2558 fs = (fs >>6) + 2; /* DIV */ 2559 fs = (fs * 10000) / (dev->sc_clkfreq<<1); /* Cycle, in ns */ 2560 2561 ret = p << 2; /* in ns units */ 2562 ret = ret / fs; /* in Cycles */ 2563 if (ret < sbic_min_period) 2564 return(sbic_min_period); 2565 2566 /* verify rounding */ 2567 if (sbictoscsiperiod(dev, regs, ret) < p) 2568 ret++; 2569 return (ret >= 8) ? 0 : ret; 2570 } 2571 2572 #ifdef DEBUG 2573 2574 void 2575 sbicdumpstate(void) 2576 { 2577 u_char csr, asr; 2578 2579 GET_SBIC_asr(debug_sbic_regs,asr); 2580 GET_SBIC_csr(debug_sbic_regs,csr); 2581 printf("%s: asr:csr(%02x:%02x)->(%02x:%02x)\n", 2582 (routine==1)?"sbicgo": 2583 (routine==2)?"sbicintr": 2584 (routine==3)?"sbicicmd": 2585 (routine==4)?"sbicnext":"unknown", 2586 debug_asr, debug_csr, asr, csr); 2587 2588 } 2589 2590 void 2591 sbictimeout(struct sbic_softc *dev) 2592 { 2593 int s, asr; 2594 2595 s = splbio(); 2596 if (dev->sc_dmatimo) { 2597 if (dev->sc_dmatimo > 1) { 2598 printf("%s: DMA timeout #%d\n", 2599 dev->sc_dev.dv_xname, dev->sc_dmatimo - 1); 2600 GET_SBIC_asr(dev->sc_sbic, asr); 2601 if( asr & SBIC_ASR_INT ) { 2602 /* We need to service a missed IRQ */ 2603 printf("Servicing a missed int:(%02x,%02x)->(%02x,?)\n", 2604 debug_asr, debug_csr, asr); 2605 sbicintr(dev); 2606 } 2607 sbicdumpstate(); 2608 } 2609 dev->sc_dmatimo++; 2610 } 2611 splx(s); 2612 callout_reset(&dev->sc_timo_ch, 30 * hz, 2613 (void *)sbictimeout, dev); 2614 } 2615 2616 void 2617 sbic_dump_acb(struct sbic_acb *acb) 2618 { 2619 u_char *b = (u_char *) &acb->cmd; 2620 int i; 2621 2622 printf("acb@%p ", acb); 2623 if (acb->xs == NULL) { 2624 printf("<unused>\n"); 2625 return; 2626 } 2627 printf("(%d:%d) flags %2x clen %2d cmd ", 2628 acb->xs->xs_periph->periph_target, 2629 acb->xs->xs_periph->periph_lun, acb->flags, acb->clen); 2630 for (i = acb->clen; i; --i) 2631 printf(" %02x", *b++); 2632 printf("\n"); 2633 printf(" xs: %8p data %8p:%04x ", acb->xs, acb->xs->data, 2634 acb->xs->datalen); 2635 printf("va %8p:%04x ", acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 2636 printf("pa %8p:%04x tcnt %lx\n", acb->sc_pa.dc_addr, acb->sc_pa.dc_count, 2637 acb->sc_tcnt); 2638 } 2639 2640 void 2641 sbic_dump(struct sbic_softc *dev) 2642 { 2643 sbic_regmap_t regs; 2644 u_char csr, asr; 2645 struct sbic_acb *acb; 2646 int s; 2647 int i; 2648 2649 s = splbio(); 2650 regs = dev->sc_sbic; 2651 #if CSR_TRACE_SIZE 2652 printf("csr trace: "); 2653 i = csr_traceptr; 2654 do { 2655 printf("%c%02x%02x%02x ", csr_trace[i].whr, 2656 csr_trace[i].csr, csr_trace[i].asr, csr_trace[i].xtn); 2657 switch(csr_trace[i].whr) { 2658 case 'g': 2659 printf("go "); break; 2660 case 's': 2661 printf("select "); break; 2662 case 'y': 2663 printf("select+ "); break; 2664 case 'i': 2665 printf("intr "); break; 2666 case 'f': 2667 printf("finish "); break; 2668 case '>': 2669 printf("out "); break; 2670 case '<': 2671 printf("in "); break; 2672 case 'm': 2673 printf("msgin "); break; 2674 case 'x': 2675 printf("msginx "); break; 2676 case 'X': 2677 printf("msginX "); break; 2678 case 'r': 2679 printf("reselect "); break; 2680 case 'I': 2681 printf("icmd "); break; 2682 case 'a': 2683 printf("abort "); break; 2684 default: 2685 printf("? "); 2686 } 2687 switch(csr_trace[i].csr) { 2688 case 0x11: 2689 printf("INITIATOR"); break; 2690 case 0x16: 2691 printf("S_XFERRED"); break; 2692 case 0x20: 2693 printf("MSGIN_ACK"); break; 2694 case 0x41: 2695 printf("DISC"); break; 2696 case 0x42: 2697 printf("SEL_TIMEO"); break; 2698 case 0x80: 2699 printf("RSLT_NI"); break; 2700 case 0x81: 2701 printf("RSLT_IFY"); break; 2702 case 0x85: 2703 printf("DISC_1"); break; 2704 case 0x18: case 0x19: case 0x1a: 2705 case 0x1b: case 0x1e: case 0x1f: 2706 case 0x28: case 0x29: case 0x2a: 2707 case 0x2b: case 0x2e: case 0x2f: 2708 case 0x48: case 0x49: case 0x4a: 2709 case 0x4b: case 0x4e: case 0x4f: 2710 case 0x88: case 0x89: case 0x8a: 2711 case 0x8b: case 0x8e: case 0x8f: 2712 switch(csr_trace[i].csr & 0xf0) { 2713 case 0x10: 2714 printf("DONE_"); break; 2715 case 0x20: 2716 printf("STOP_"); break; 2717 case 0x40: 2718 printf("ERR_"); break; 2719 case 0x80: 2720 printf("REQ_"); break; 2721 } 2722 switch(csr_trace[i].csr & 7) { 2723 case 0: 2724 printf("DATA_OUT"); break; 2725 case 1: 2726 printf("DATA_IN"); break; 2727 case 2: 2728 printf("CMD"); break; 2729 case 3: 2730 printf("STATUS"); break; 2731 case 6: 2732 printf("MSG_OUT"); break; 2733 case 7: 2734 printf("MSG_IN"); break; 2735 default: 2736 printf("invld phs"); 2737 } 2738 break; 2739 default: printf("****"); break; 2740 } 2741 if (csr_trace[i].asr & SBIC_ASR_INT) 2742 printf(" ASR_INT"); 2743 if (csr_trace[i].asr & SBIC_ASR_LCI) 2744 printf(" ASR_LCI"); 2745 if (csr_trace[i].asr & SBIC_ASR_BSY) 2746 printf(" ASR_BSY"); 2747 if (csr_trace[i].asr & SBIC_ASR_CIP) 2748 printf(" ASR_CIP"); 2749 printf("\n"); 2750 i = (i + 1) & (CSR_TRACE_SIZE - 1); 2751 } while (i != csr_traceptr); 2752 #endif 2753 GET_SBIC_asr(regs, asr); 2754 if ((asr & SBIC_ASR_INT) == 0) 2755 GET_SBIC_csr(regs, csr); 2756 else 2757 csr = 0; 2758 printf("%s@%p regs %p/%p asr %x csr %x\n", dev->sc_dev.dv_xname, 2759 dev, regs.sbic_asr_p, regs.sbic_value_p, asr, csr); 2760 if ((acb = dev->free_list.tqh_first)) { 2761 printf("Free list:\n"); 2762 while (acb) { 2763 sbic_dump_acb(acb); 2764 acb = acb->chain.tqe_next; 2765 } 2766 } 2767 if ((acb = dev->ready_list.tqh_first)) { 2768 printf("Ready list:\n"); 2769 while (acb) { 2770 sbic_dump_acb(acb); 2771 acb = acb->chain.tqe_next; 2772 } 2773 } 2774 if ((acb = dev->nexus_list.tqh_first)) { 2775 printf("Nexus list:\n"); 2776 while (acb) { 2777 sbic_dump_acb(acb); 2778 acb = acb->chain.tqe_next; 2779 } 2780 } 2781 if (dev->sc_nexus) { 2782 printf("nexus:\n"); 2783 sbic_dump_acb(dev->sc_nexus); 2784 } 2785 printf("sc_xs %p targ %d lun %d flags %x tcnt %lx dmacmd %x mask %lx\n", 2786 dev->sc_xs, dev->target, dev->lun, dev->sc_flags, dev->sc_tcnt, 2787 dev->sc_dmacmd, dev->sc_dmamask); 2788 for (i = 0; i < 8; ++i) { 2789 if (dev->sc_tinfo[i].cmds > 2) { 2790 printf("tgt %d: cmds %d disc %d lubusy %x\n", 2791 i, dev->sc_tinfo[i].cmds, 2792 dev->sc_tinfo[i].dconns, 2793 dev->sc_tinfo[i].lubusy); 2794 } 2795 } 2796 splx(s); 2797 } 2798 2799 #endif 2800
Indexes created Thu Oct 02 14:10:14 GMT 2025