sbic.c revision 1.66.2.1
1 /* $NetBSD: sbic.c,v 1.66.2.1 2010/08/17 06:43:57 uebayasi Exp $ */ 2 3 /* 4 * Copyright (c) 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Van Jacobson of Lawrence Berkeley Laboratory. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)scsi.c 7.5 (Berkeley) 5/4/91 35 */ 36 37 /* 38 * Copyright (c) 1994 Christian E. Hopps 39 * 40 * This code is derived from software contributed to Berkeley by 41 * Van Jacobson of Lawrence Berkeley Laboratory. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed by the University of 54 * California, Berkeley and its contributors. 55 * 4. Neither the name of the University nor the names of its contributors 56 * may be used to endorse or promote products derived from this software 57 * without specific prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 61 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 62 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 63 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 64 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 65 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 67 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 68 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 69 * SUCH DAMAGE. 70 * 71 * @(#)scsi.c 7.5 (Berkeley) 5/4/91 72 */ 73 74 /* 75 * AMIGA AMD 33C93 scsi adaptor driver 76 */ 77 78 #include "opt_ddb.h" 79 #include "opt_m68k_arch.h" 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: sbic.c,v 1.66.2.1 2010/08/17 06:43:57 uebayasi Exp $"); 83 84 #include <sys/param.h> 85 #include <sys/systm.h> 86 #include <sys/device.h> 87 #include <sys/kernel.h> /* For hz */ 88 #include <sys/disklabel.h> 89 #include <sys/buf.h> 90 #include <dev/scsipi/scsi_all.h> 91 #include <dev/scsipi/scsipi_all.h> 92 #include <dev/scsipi/scsiconf.h> 93 #include <uvm/uvm_extern.h> 94 #include <machine/cpu.h> 95 #include <amiga/amiga/device.h> 96 #include <amiga/amiga/custom.h> 97 #include <amiga/amiga/isr.h> 98 #include <amiga/dev/dmavar.h> 99 #include <amiga/dev/sbicreg.h> 100 #include <amiga/dev/sbicvar.h> 101 102 /* These are for bounce buffers */ 103 #include <amiga/amiga/cc.h> 104 #include <amiga/dev/zbusvar.h> 105 106 /* Since I can't find this in any other header files */ 107 #define SCSI_PHASE(reg) (reg&0x07) 108 109 /* 110 * SCSI delays 111 * In u-seconds, primarily for state changes on the SPC. 112 */ 113 #define SBIC_CMD_WAIT 50000 /* wait per step of 'immediate' cmds */ 114 #define SBIC_DATA_WAIT 50000 /* wait per data in/out step */ 115 #define SBIC_INIT_WAIT 50000 /* wait per step (both) during init */ 116 117 #define SBIC_WAIT(regs, until, timeo) sbicwait(regs, until, timeo, __LINE__) 118 119 int sbicicmd(struct sbic_softc *, int, int, void *, int, void *, int); 120 int sbicgo(struct sbic_softc *, struct scsipi_xfer *); 121 int sbicdmaok(struct sbic_softc *, struct scsipi_xfer *); 122 int sbicwait(sbic_regmap_t, char, int , int); 123 int sbiccheckdmap(void *, u_long, u_long); 124 int sbicselectbus(struct sbic_softc *, sbic_regmap_t, u_char, u_char, u_char); 125 int sbicxfstart(sbic_regmap_t, int, u_char, int); 126 int sbicxfout(sbic_regmap_t regs, int, void *, int); 127 int sbicfromscsiperiod(struct sbic_softc *, sbic_regmap_t, int); 128 int sbictoscsiperiod(struct sbic_softc *, sbic_regmap_t, int); 129 int sbicpoll(struct sbic_softc *); 130 int sbicnextstate(struct sbic_softc *, u_char, u_char); 131 int sbicmsgin(struct sbic_softc *); 132 int sbicxfin(sbic_regmap_t regs, int, void *); 133 int sbicabort(struct sbic_softc *, sbic_regmap_t, const char *); 134 void sbicxfdone(struct sbic_softc *, sbic_regmap_t, int); 135 void sbicerror(struct sbic_softc *, sbic_regmap_t, u_char); 136 void sbicstart(struct sbic_softc *); 137 void sbicreset(struct sbic_softc *); 138 void sbic_scsidone(struct sbic_acb *, int); 139 void sbic_sched(struct sbic_softc *); 140 void sbic_save_ptrs(struct sbic_softc *, sbic_regmap_t,int,int); 141 void sbic_load_ptrs(struct sbic_softc *, sbic_regmap_t,int,int); 142 #ifdef DEBUG 143 void sbicdumpstate(void); 144 void sbic_dump_acb(struct sbic_acb *); 145 #endif 146 147 /* 148 * Synch xfer parameters, and timing conversions 149 */ 150 int sbic_min_period = SBIC_SYN_MIN_PERIOD; /* in cycles = f(ICLK,FSn) */ 151 int sbic_max_offset = SBIC_SYN_MAX_OFFSET; /* pure number */ 152 153 int sbic_cmd_wait = SBIC_CMD_WAIT; 154 int sbic_data_wait = SBIC_DATA_WAIT; 155 int sbic_init_wait = SBIC_INIT_WAIT; 156 157 /* 158 * was broken before.. now if you want this you get it for all drives 159 * on sbic controllers. 160 */ 161 u_char sbic_inhibit_sync[8]; 162 int sbic_enable_reselect = 1; 163 int sbic_clock_override = 0; 164 int sbic_no_dma = 0; 165 int sbic_parallel_operations = 1; 166 167 #ifdef DEBUG 168 sbic_regmap_t debug_sbic_regs; 169 int sbicdma_ops = 0; /* total DMA operations */ 170 int sbicdma_bounces = 0; /* number operations using bounce buffer */ 171 int sbicdma_hits = 0; /* number of DMA chains that were contiguous */ 172 int sbicdma_misses = 0; /* number of DMA chains that were not contiguous */ 173 int sbicdma_saves = 0; 174 #define QPRINTF(a) if (sbic_debug > 1) printf a 175 int sbic_debug = 0; 176 int sync_debug = 0; 177 int sbic_dma_debug = 0; 178 int reselect_debug = 0; 179 int data_pointer_debug = 0; 180 u_char debug_asr, debug_csr, routine; 181 void sbictimeout(struct sbic_softc *dev); 182 183 #define CSR_TRACE_SIZE 32 184 #if CSR_TRACE_SIZE 185 #define CSR_TRACE(w,c,a,x) do { \ 186 int s_csr_trace = splbio(); \ 187 csr_trace[csr_traceptr].whr = (w); csr_trace[csr_traceptr].csr = (c); \ 188 csr_trace[csr_traceptr].asr = (a); csr_trace[csr_traceptr].xtn = (x); \ 189 dma_cachectl((void *)&csr_trace[csr_traceptr], sizeof(csr_trace[0])); \ 190 csr_traceptr = (csr_traceptr + 1) & (CSR_TRACE_SIZE - 1); \ 191 /* dma_cachectl((void *)&csr_traceptr, sizeof(csr_traceptr));*/ \ 192 splx(s_csr_trace); \ 193 } while (0) 194 int csr_traceptr; 195 int csr_tracesize = CSR_TRACE_SIZE; 196 struct { 197 u_char whr; 198 u_char csr; 199 u_char asr; 200 u_char xtn; 201 } csr_trace[CSR_TRACE_SIZE]; 202 #else 203 #define CSR_TRACE(w,c,a,x) 204 #endif 205 206 #define SBIC_TRACE_SIZE 0 207 #if SBIC_TRACE_SIZE 208 #define SBIC_TRACE(dev) do { \ 209 int s = splbio(); \ 210 sbic_trace[sbic_traceptr].sp = &s; \ 211 sbic_trace[sbic_traceptr].line = __LINE__; \ 212 sbic_trace[sbic_traceptr].sr = s; \ 213 sbic_trace[sbic_traceptr].csr = csr_traceptr; \ 214 dma_cachectl(&sbic_trace[sbic_traceptr], sizeof(sbic_trace[0])); \ 215 sbic_traceptr = (sbic_traceptr + 1) & (SBIC_TRACE_SIZE - 1); \ 216 dma_cachectl(&sbic_traceptr, sizeof(sbic_traceptr)); \ 217 if (dev) dma_cachectl(dev, sizeof(*dev)); \ 218 splx(s); \ 219 } while (0) 220 int sbic_traceptr; 221 int sbic_tracesize = SBIC_TRACE_SIZE; 222 struct { 223 void *sp; 224 u_short line; 225 u_short sr; 226 int csr; 227 } sbic_trace[SBIC_TRACE_SIZE]; 228 #else 229 #define SBIC_TRACE(dev) 230 #endif 231 232 #else /* DEBUG */ 233 #define QPRINTF(a) 234 #define CSR_TRACE(w,c,a,x) 235 #define SBIC_TRACE(dev) 236 #endif /* DEBUG */ 237 238 /* 239 * default minphys routine for sbic based controllers 240 */ 241 void 242 sbic_minphys(struct buf *bp) 243 { 244 245 /* 246 * No max transfer at this level. 247 */ 248 minphys(bp); 249 } 250 251 /* 252 * Save DMA pointers. Take into account partial transfer. Shut down DMA. 253 */ 254 void 255 sbic_save_ptrs(struct sbic_softc *dev, sbic_regmap_t regs, int target, int lun) 256 { 257 int count, asr, s; 258 struct sbic_acb* acb; 259 260 SBIC_TRACE(dev); 261 if( !dev->sc_cur ) return; 262 if( !(dev->sc_flags & SBICF_INDMA) ) return; /* DMA not active */ 263 264 s = splbio(); 265 266 acb = dev->sc_nexus; 267 count = -1; 268 do { 269 GET_SBIC_asr(regs, asr); 270 if( asr & SBIC_ASR_DBR ) { 271 printf("sbic_save_ptrs: asr %02x canceled!\n", asr); 272 splx(s); 273 SBIC_TRACE(dev); 274 return; 275 } 276 } while( asr & (SBIC_ASR_BSY|SBIC_ASR_CIP) ); 277 278 /* Save important state */ 279 /* must be done before dmastop */ 280 acb->sc_dmacmd = dev->sc_dmacmd; 281 SBIC_TC_GET(regs, count); 282 283 /* Shut down DMA ====CAREFUL==== */ 284 dev->sc_dmastop(dev); 285 dev->sc_flags &= ~SBICF_INDMA; 286 SBIC_TC_PUT(regs, 0); 287 288 #ifdef DEBUG 289 if(!count && sbic_debug) printf("%dcount0",target); 290 if(data_pointer_debug == -1) 291 printf("SBIC saving target %d data pointers from (%p,%x)%xASR:%02x", 292 target, dev->sc_cur->dc_addr, dev->sc_cur->dc_count, 293 acb->sc_dmacmd, asr); 294 #endif 295 296 /* Fixup partial xfers */ 297 acb->sc_kv.dc_addr += (dev->sc_tcnt - count); 298 acb->sc_kv.dc_count -= (dev->sc_tcnt - count); 299 acb->sc_pa.dc_addr += (dev->sc_tcnt - count); 300 acb->sc_pa.dc_count -= ((dev->sc_tcnt - count)>>1); 301 302 acb->sc_tcnt = dev->sc_tcnt = count; 303 #ifdef DEBUG 304 if(data_pointer_debug) 305 printf(" at (%p,%x):%x\n", 306 dev->sc_cur->dc_addr, dev->sc_cur->dc_count,count); 307 sbicdma_saves++; 308 #endif 309 splx(s); 310 SBIC_TRACE(dev); 311 } 312 313 314 /* 315 * DOES NOT RESTART DMA!!! 316 */ 317 void 318 sbic_load_ptrs(struct sbic_softc *dev, sbic_regmap_t regs, int target, int lun) 319 { 320 int s, count; 321 char* vaddr, * paddr; 322 struct sbic_acb *acb; 323 324 SBIC_TRACE(dev); 325 acb = dev->sc_nexus; 326 if( !acb->sc_kv.dc_count ) { 327 /* No data to xfer */ 328 SBIC_TRACE(dev); 329 return; 330 } 331 332 s = splbio(); 333 334 dev->sc_last = dev->sc_cur = &acb->sc_pa; 335 dev->sc_tcnt = acb->sc_tcnt; 336 dev->sc_dmacmd = acb->sc_dmacmd; 337 338 #ifdef DEBUG 339 sbicdma_ops++; 340 #endif 341 if( !dev->sc_tcnt ) { 342 /* sc_tcnt == 0 implies end of segment */ 343 344 /* do kvm to pa mappings */ 345 paddr = acb->sc_pa.dc_addr = 346 (char *) kvtop(acb->sc_kv.dc_addr); 347 348 vaddr = acb->sc_kv.dc_addr; 349 count = acb->sc_kv.dc_count; 350 for(count = (PAGE_SIZE - ((int)vaddr & PGOFSET)); 351 count < acb->sc_kv.dc_count 352 && (char*)kvtop(vaddr + count + 4) == paddr + count + 4; 353 count += PAGE_SIZE); 354 /* If it's all contiguous... */ 355 if(count > acb->sc_kv.dc_count ) { 356 count = acb->sc_kv.dc_count; 357 #ifdef DEBUG 358 sbicdma_hits++; 359 #endif 360 } else { 361 #ifdef DEBUG 362 sbicdma_misses++; 363 #endif 364 } 365 acb->sc_tcnt = count; 366 acb->sc_pa.dc_count = count >> 1; 367 368 #ifdef DEBUG 369 if(data_pointer_debug) 370 printf("DMA recalc:kv(%p,%x)pa(%p,%lx)\n", 371 acb->sc_kv.dc_addr, 372 acb->sc_kv.dc_count, 373 acb->sc_pa.dc_addr, 374 acb->sc_tcnt); 375 #endif 376 } 377 splx(s); 378 #ifdef DEBUG 379 if(data_pointer_debug) 380 printf("SBIC restoring target %d data pointers at (%p,%x)%x\n", 381 target, dev->sc_cur->dc_addr, dev->sc_cur->dc_count, 382 dev->sc_dmacmd); 383 #endif 384 SBIC_TRACE(dev); 385 } 386 387 /* 388 * used by specific sbic controller 389 * 390 * it appears that the higher level code does nothing with LUN's 391 * so I will too. I could plug it in, however so could they 392 * in scsi_scsipi_cmd(). 393 */ 394 void 395 sbic_scsipi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req, 396 void *arg) 397 { 398 struct scsipi_xfer *xs; 399 struct scsipi_periph *periph; 400 struct sbic_acb *acb; 401 struct sbic_softc *dev = (void *)chan->chan_adapter->adapt_dev; 402 int flags, s, stat; 403 404 switch (req) { 405 case ADAPTER_REQ_RUN_XFER: 406 xs = arg; 407 periph = xs->xs_periph; 408 409 SBIC_TRACE(dev); 410 flags = xs->xs_control; 411 412 if (flags & XS_CTL_DATA_UIO) 413 panic("sbic: scsi data uio requested"); 414 415 if (dev->sc_nexus && flags & XS_CTL_POLL) 416 panic("sbic_scsipi_request: busy"); 417 418 s = splbio(); 419 acb = dev->free_list.tqh_first; 420 if (acb) 421 TAILQ_REMOVE(&dev->free_list, acb, chain); 422 splx(s); 423 424 #ifdef DIAGNOSTIC 425 if (acb == NULL) { 426 scsipi_printaddr(periph); 427 printf("unable to allocate acb\n"); 428 panic("sbic_scsipi_request"); 429 } 430 #endif 431 acb->flags = ACB_ACTIVE; 432 if (flags & XS_CTL_DATA_IN) 433 acb->flags |= ACB_DATAIN; 434 acb->xs = xs; 435 memcpy(&acb->cmd, xs->cmd, xs->cmdlen); 436 acb->clen = xs->cmdlen; 437 acb->sc_kv.dc_addr = xs->data; 438 acb->sc_kv.dc_count = xs->datalen; 439 acb->pa_addr = xs->data ? (char *)kvtop(xs->data) : 0; /* XXXX check */ 440 441 if (flags & XS_CTL_POLL) { 442 s = splbio(); 443 /* 444 * This has major side effects - it locks up the machine 445 */ 446 447 dev->sc_flags |= SBICF_ICMD; 448 do { 449 while(dev->sc_nexus) 450 sbicpoll(dev); 451 dev->sc_nexus = acb; 452 dev->sc_stat[0] = -1; 453 dev->sc_xs = xs; 454 dev->target = periph->periph_target; 455 dev->lun = periph->periph_lun; 456 stat = sbicicmd(dev, dev->target, dev->lun, 457 &acb->cmd, acb->clen, 458 acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 459 } while (dev->sc_nexus != acb); 460 sbic_scsidone(acb, stat); 461 462 splx(s); 463 SBIC_TRACE(dev); 464 return; 465 } 466 467 s = splbio(); 468 TAILQ_INSERT_TAIL(&dev->ready_list, acb, chain); 469 470 if (dev->sc_nexus) { 471 splx(s); 472 SBIC_TRACE(dev); 473 return; 474 } 475 476 /* 477 * nothing is active, try to start it now. 478 */ 479 sbic_sched(dev); 480 splx(s); 481 482 SBIC_TRACE(dev); 483 /* TODO: add sbic_poll to do XS_CTL_POLL operations */ 484 #if 0 485 if (flags & XS_CTL_POLL) 486 return(COMPLETE); 487 #endif 488 return; 489 490 case ADAPTER_REQ_GROW_RESOURCES: 491 return; 492 493 case ADAPTER_REQ_SET_XFER_MODE: 494 return; 495 } 496 } 497 498 /* 499 * attempt to start the next available command 500 */ 501 void 502 sbic_sched(struct sbic_softc *dev) 503 { 504 struct scsipi_xfer *xs; 505 struct scsipi_periph *periph; 506 struct sbic_acb *acb; 507 int flags, /*phase,*/ stat, i; 508 509 SBIC_TRACE(dev); 510 if (dev->sc_nexus) 511 return; /* a command is current active */ 512 513 SBIC_TRACE(dev); 514 for (acb = dev->ready_list.tqh_first; acb; acb = acb->chain.tqe_next) { 515 periph = acb->xs->xs_periph; 516 i = periph->periph_target; 517 if (!(dev->sc_tinfo[i].lubusy & (1 << periph->periph_lun))) { 518 struct sbic_tinfo *ti = &dev->sc_tinfo[i]; 519 520 TAILQ_REMOVE(&dev->ready_list, acb, chain); 521 dev->sc_nexus = acb; 522 ti = &dev->sc_tinfo[periph->periph_target]; 523 ti->lubusy |= (1 << periph->periph_lun); 524 acb->sc_pa.dc_addr = acb->pa_addr; /* XXXX check */ 525 break; 526 } 527 } 528 529 SBIC_TRACE(dev); 530 if (acb == NULL) 531 return; /* did not find an available command */ 532 533 dev->sc_xs = xs = acb->xs; 534 periph = xs->xs_periph; 535 flags = xs->xs_control; 536 537 if (flags & XS_CTL_RESET) 538 sbicreset(dev); 539 540 #ifdef DEBUG 541 if( data_pointer_debug > 1 ) 542 printf("sbic_sched(%d,%d)\n", periph->periph_target, 543 periph->periph_lun); 544 #endif 545 dev->sc_stat[0] = -1; 546 dev->target = periph->periph_target; 547 dev->lun = periph->periph_lun; 548 if ( flags & XS_CTL_POLL || ( !sbic_parallel_operations 549 && (sbicdmaok(dev, xs) == 0))) 550 stat = sbicicmd(dev, periph->periph_target, 551 periph->periph_lun, &acb->cmd, 552 acb->clen, acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 553 else if (sbicgo(dev, xs) == 0 && xs->error != XS_SELTIMEOUT) { 554 SBIC_TRACE(dev); 555 return; 556 } else 557 stat = dev->sc_stat[0]; 558 559 sbic_scsidone(acb, stat); 560 SBIC_TRACE(dev); 561 } 562 563 void 564 sbic_scsidone(struct sbic_acb *acb, int stat) 565 { 566 struct scsipi_xfer *xs; 567 struct scsipi_periph *periph; 568 struct sbic_softc *dev; 569 int dosched = 0; 570 571 xs = acb->xs; 572 periph = xs->xs_periph; 573 dev = (void *)periph->periph_channel->chan_adapter->adapt_dev; 574 SBIC_TRACE(dev); 575 #ifdef DIAGNOSTIC 576 if (acb == NULL || xs == NULL) { 577 printf("sbic_scsidone -- (%d,%d) no scsi_xfer\n", 578 dev->target, dev->lun); 579 #ifdef DDB 580 Debugger(); 581 #endif 582 return; 583 } 584 #endif 585 586 xs->status = stat; 587 xs->resid = 0; /* XXXX */ 588 #ifdef DEBUG 589 if( data_pointer_debug > 1 ) 590 printf("scsidone: (%d,%d)->(%d,%d)%02x\n", 591 periph->periph_target, periph->periph_lun, 592 dev->target, dev->lun, stat); 593 if( periph->periph_target == 594 periph->periph_channel->chan_id) 595 panic("target == hostid"); 596 #endif 597 598 if (xs->error == XS_NOERROR) { 599 if (stat == SCSI_CHECK || stat == SCSI_BUSY) 600 xs->error = XS_BUSY; 601 } 602 603 /* 604 * Remove the ACB from whatever queue it's on. We have to do a bit of 605 * a hack to figure out which queue it's on. Note that it is *not* 606 * necessary to cdr down the ready queue, but we must cdr down the 607 * nexus queue and see if it's there, so we can mark the unit as no 608 * longer busy. This code is sickening, but it works. 609 */ 610 if (acb == dev->sc_nexus) { 611 dev->sc_nexus = NULL; 612 dev->sc_xs = NULL; 613 dev->sc_tinfo[periph->periph_target].lubusy &= 614 ~(1<<periph->periph_lun); 615 if (dev->ready_list.tqh_first) 616 dosched = 1; /* start next command */ 617 } else if (dev->ready_list.tqh_last == &acb->chain.tqe_next) { 618 TAILQ_REMOVE(&dev->ready_list, acb, chain); 619 } else { 620 register struct sbic_acb *acb2; 621 for (acb2 = dev->nexus_list.tqh_first; acb2; 622 acb2 = acb2->chain.tqe_next) { 623 if (acb2 == acb) { 624 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 625 dev->sc_tinfo[periph->periph_target].lubusy 626 &= ~(1<<periph->periph_lun); 627 break; 628 } 629 } 630 if (acb2) 631 ; 632 else if (acb->chain.tqe_next) { 633 TAILQ_REMOVE(&dev->ready_list, acb, chain); 634 } else { 635 printf("%s: can't find matching acb\n", 636 dev->sc_dev.dv_xname); 637 #ifdef DDB 638 Debugger(); 639 #endif 640 } 641 } 642 /* Put it on the free list. */ 643 acb->flags = ACB_FREE; 644 TAILQ_INSERT_HEAD(&dev->free_list, acb, chain); 645 646 dev->sc_tinfo[periph->periph_target].cmds++; 647 648 scsipi_done(xs); 649 650 if (dosched) 651 sbic_sched(dev); 652 SBIC_TRACE(dev); 653 } 654 655 int 656 sbicdmaok(struct sbic_softc *dev, struct scsipi_xfer *xs) 657 { 658 if (sbic_no_dma || !xs->datalen || xs->datalen & 0x1 || 659 (u_int)xs->data & 0x3) 660 return(0); 661 /* 662 * controller supports dma to any addresses? 663 */ 664 else if ((dev->sc_flags & SBICF_BADDMA) == 0) 665 return(1); 666 /* 667 * this address is ok for DMA? 668 */ 669 else if (sbiccheckdmap(xs->data, xs->datalen, dev->sc_dmamask) == 0) 670 return(1); 671 /* 672 * we have a bounce buffer? 673 */ 674 else if (dev->sc_tinfo[xs->xs_periph->periph_target].bounce) 675 return(1); 676 /* 677 * try to get one 678 */ 679 else if ((dev->sc_tinfo[xs->xs_periph->periph_target].bounce 680 = (char *)alloc_z2mem(MAXPHYS))) { 681 if (isztwomem(dev->sc_tinfo[xs->xs_periph->periph_target].bounce)) 682 printf("alloc ZII target %d bounce pa 0x%x\n", 683 xs->xs_periph->periph_target, 684 (unsigned)kvtop(dev->sc_tinfo[xs->xs_periph->periph_target].bounce)); 685 else if (dev->sc_tinfo[xs->xs_periph->periph_target].bounce) 686 printf("alloc CHIP target %d bounce pa %p\n", 687 xs->xs_periph->periph_target, 688 PREP_DMA_MEM(dev->sc_tinfo[xs->xs_periph->periph_target].bounce)); 689 return(1); 690 } 691 692 return(0); 693 } 694 695 696 int 697 sbicwait(sbic_regmap_t regs, char until, int timeo, int line) 698 { 699 u_char val; 700 int csr; 701 702 SBIC_TRACE((struct sbic_softc *)0); 703 if (timeo == 0) 704 timeo = 1000000; /* some large value.. */ 705 706 GET_SBIC_asr(regs,val); 707 while ((val & until) == 0) { 708 if (timeo-- == 0) { 709 GET_SBIC_csr(regs, csr); 710 printf("sbicwait TIMEO @%d with asr=x%x csr=x%x\n", 711 line, val, csr); 712 #if defined(DDB) && defined(DEBUG) 713 Debugger(); 714 #endif 715 return(val); /* Maybe I should abort */ 716 break; 717 } 718 DELAY(1); 719 GET_SBIC_asr(regs,val); 720 } 721 SBIC_TRACE((struct sbic_softc *)0); 722 return(val); 723 } 724 725 int 726 sbicabort(struct sbic_softc *dev, sbic_regmap_t regs, const char *where) 727 { 728 u_char csr, asr; 729 730 GET_SBIC_asr(regs, asr); 731 GET_SBIC_csr(regs, csr); 732 733 printf ("%s: abort %s: csr = 0x%02x, asr = 0x%02x\n", 734 dev->sc_dev.dv_xname, where, csr, asr); 735 736 737 #if 0 738 /* Clean up running command */ 739 if (dev->sc_nexus != NULL) { 740 dev->sc_nexus->xs->error = XS_DRIVER_STUFFUP; 741 sbic_scsidone(dev->sc_nexus, dev->sc_stat[0]); 742 } 743 while (acb = dev->nexus_list.tqh_first) { 744 acb->xs->error = XS_DRIVER_STUFFUP; 745 sbic_scsidone(acb, -1 /*acb->stat[0]*/); 746 } 747 #endif 748 749 /* Clean up chip itself */ 750 if (dev->sc_flags & SBICF_SELECTED) { 751 while( asr & SBIC_ASR_DBR ) { 752 /* sbic is jammed w/data. need to clear it */ 753 /* But we don't know what direction it needs to go */ 754 GET_SBIC_data(regs, asr); 755 printf("%s: abort %s: clearing data buffer 0x%02x\n", 756 dev->sc_dev.dv_xname, where, asr); 757 GET_SBIC_asr(regs, asr); 758 if( asr & SBIC_ASR_DBR ) /* Not the read direction, then */ 759 SET_SBIC_data(regs, asr); 760 GET_SBIC_asr(regs, asr); 761 } 762 WAIT_CIP(regs); 763 printf("%s: sbicabort - sending ABORT command\n", dev->sc_dev.dv_xname); 764 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 765 WAIT_CIP(regs); 766 767 GET_SBIC_asr(regs, asr); 768 if (asr & (SBIC_ASR_BSY|SBIC_ASR_LCI)) { 769 /* ok, get more drastic.. */ 770 771 printf("%s: sbicabort - asr %x, trying to reset\n", dev->sc_dev.dv_xname, asr); 772 sbicreset(dev); 773 dev->sc_flags &= ~SBICF_SELECTED; 774 return -1; 775 } 776 printf("%s: sbicabort - sending DISC command\n", dev->sc_dev.dv_xname); 777 SET_SBIC_cmd(regs, SBIC_CMD_DISC); 778 779 do { 780 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0); 781 GET_SBIC_csr (regs, csr); 782 CSR_TRACE('a',csr,asr,0); 783 } while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) 784 && (csr != SBIC_CSR_CMD_INVALID)); 785 786 /* lets just hope it worked.. */ 787 dev->sc_flags &= ~SBICF_SELECTED; 788 } 789 return -1; 790 } 791 792 793 /* 794 * Initialize driver-private structures 795 */ 796 797 void 798 sbicinit(struct sbic_softc *dev) 799 { 800 sbic_regmap_t regs; 801 u_int i; 802 struct sbic_acb *acb; 803 u_int inhibit_sync; 804 805 extern u_long scsi_nosync; 806 extern int shift_nosync; 807 808 regs = dev->sc_sbic; 809 810 if ((dev->sc_flags & SBICF_ALIVE) == 0) { 811 TAILQ_INIT(&dev->ready_list); 812 TAILQ_INIT(&dev->nexus_list); 813 TAILQ_INIT(&dev->free_list); 814 callout_init(&dev->sc_timo_ch, 0); 815 dev->sc_nexus = NULL; 816 dev->sc_xs = NULL; 817 acb = dev->sc_acb; 818 memset(acb, 0, sizeof(dev->sc_acb)); 819 for (i = 0; i < sizeof(dev->sc_acb) / sizeof(*acb); i++) { 820 TAILQ_INSERT_TAIL(&dev->free_list, acb, chain); 821 acb++; 822 } 823 memset(dev->sc_tinfo, 0, sizeof(dev->sc_tinfo)); 824 #ifdef DEBUG 825 /* make sure timeout is really not needed */ 826 callout_reset(&dev->sc_timo_ch, 30 * hz, 827 (void *)sbictimeout, dev); 828 #endif 829 830 } else panic("sbic: reinitializing driver!"); 831 832 dev->sc_flags |= SBICF_ALIVE; 833 dev->sc_flags &= ~SBICF_SELECTED; 834 835 /* initialize inhibit array */ 836 if (scsi_nosync) { 837 inhibit_sync = (scsi_nosync >> shift_nosync) & 0xff; 838 shift_nosync += 8; 839 #ifdef DEBUG 840 if (inhibit_sync) 841 printf("%s: Inhibiting synchronous transfer %02x\n", 842 dev->sc_dev.dv_xname, inhibit_sync); 843 #endif 844 for (i = 0; i < 8; ++i) 845 if (inhibit_sync & (1 << i)) 846 sbic_inhibit_sync[i] = 1; 847 } 848 849 sbicreset(dev); 850 } 851 852 void 853 sbicreset(struct sbic_softc *dev) 854 { 855 sbic_regmap_t regs; 856 u_int my_id, s; 857 u_char csr; 858 #if 0 859 u_int i; 860 struct sbic_acb *acb; 861 #endif 862 863 regs = dev->sc_sbic; 864 #if 0 865 if (dev->sc_flags & SBICF_ALIVE) { 866 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 867 WAIT_CIP(regs); 868 } 869 #else 870 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 871 WAIT_CIP(regs); 872 #endif 873 s = splbio(); 874 my_id = dev->sc_channel.chan_id & SBIC_ID_MASK; 875 876 /* Enable advanced mode */ 877 my_id |= SBIC_ID_EAF /*| SBIC_ID_EHP*/ ; 878 SET_SBIC_myid(regs, my_id); 879 880 /* 881 * Disable interrupts (in dmainit) then reset the chip 882 */ 883 SET_SBIC_cmd(regs, SBIC_CMD_RESET); 884 DELAY(25); 885 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 886 GET_SBIC_csr(regs, csr); /* clears interrupt also */ 887 888 if (dev->sc_clkfreq < 110) 889 my_id |= SBIC_ID_FS_8_10; 890 else if (dev->sc_clkfreq < 160) 891 my_id |= SBIC_ID_FS_12_15; 892 else if (dev->sc_clkfreq < 210) 893 my_id |= SBIC_ID_FS_16_20; 894 895 SET_SBIC_myid(regs, my_id); 896 897 /* 898 * Set up various chip parameters 899 */ 900 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI /* | SBIC_CTL_HSP */ 901 | SBIC_MACHINE_DMA_MODE); 902 /* 903 * don't allow (re)selection (SBIC_RID_ES) 904 * until we can handle target mode!! 905 */ 906 SET_SBIC_rselid(regs, SBIC_RID_ER); 907 SET_SBIC_syn(regs, 0); /* asynch for now */ 908 909 /* 910 * anything else was zeroed by reset 911 */ 912 splx(s); 913 914 #if 0 915 if ((dev->sc_flags & SBICF_ALIVE) == 0) { 916 TAILQ_INIT(&dev->ready_list); 917 TAILQ_INIT(&dev->nexus_list); 918 TAILQ_INIT(&dev->free_list); 919 dev->sc_nexus = NULL; 920 dev->sc_xs = NULL; 921 acb = dev->sc_acb; 922 memset(acb, 0, sizeof(dev->sc_acb)); 923 for (i = 0; i < sizeof(dev->sc_acb) / sizeof(*acb); i++) { 924 TAILQ_INSERT_TAIL(&dev->free_list, acb, chain); 925 acb++; 926 } 927 memset(dev->sc_tinfo, 0, sizeof(dev->sc_tinfo)); 928 } else { 929 if (dev->sc_nexus != NULL) { 930 dev->sc_nexus->xs->error = XS_DRIVER_STUFFUP; 931 sbic_scsidone(dev->sc_nexus, dev->sc_stat[0]); 932 } 933 while (acb = dev->nexus_list.tqh_first) { 934 acb->xs->error = XS_DRIVER_STUFFUP; 935 sbic_scsidone(acb, -1 /*acb->stat[0]*/); 936 } 937 } 938 939 dev->sc_flags |= SBICF_ALIVE; 940 #endif 941 dev->sc_flags &= ~SBICF_SELECTED; 942 } 943 944 void 945 sbicerror(struct sbic_softc *dev, sbic_regmap_t regs, u_char csr) 946 { 947 struct scsipi_xfer *xs; 948 949 xs = dev->sc_xs; 950 951 #ifdef DIAGNOSTIC 952 if (xs == NULL) 953 panic("sbicerror"); 954 #endif 955 if (xs->xs_control & XS_CTL_SILENT) 956 return; 957 958 printf("%s: ", dev->sc_dev.dv_xname); 959 printf("csr == 0x%02x\n", csr); /* XXX */ 960 } 961 962 /* 963 * select the bus, return when selected or error. 964 */ 965 int 966 sbicselectbus(struct sbic_softc *dev, sbic_regmap_t regs, u_char target, 967 u_char lun, u_char our_addr) 968 { 969 u_char asr, csr, id; 970 971 SBIC_TRACE(dev); 972 QPRINTF(("sbicselectbus %d\n", target)); 973 974 /* 975 * if we're already selected, return (XXXX panic maybe?) 976 */ 977 if (dev->sc_flags & SBICF_SELECTED) { 978 SBIC_TRACE(dev); 979 return(1); 980 } 981 982 /* 983 * issue select 984 */ 985 SBIC_TC_PUT(regs, 0); 986 SET_SBIC_selid(regs, target); 987 SET_SBIC_timeo(regs, SBIC_TIMEOUT(250,dev->sc_clkfreq)); 988 989 /* 990 * set sync or async 991 */ 992 if (dev->sc_sync[target].state == SYNC_DONE) 993 SET_SBIC_syn(regs, SBIC_SYN (dev->sc_sync[target].offset, 994 dev->sc_sync[target].period)); 995 else 996 SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period)); 997 998 GET_SBIC_asr(regs, asr); 999 if( asr & (SBIC_ASR_INT|SBIC_ASR_BSY) ) { 1000 /* This means we got ourselves reselected upon */ 1001 /* printf("sbicselectbus: INT/BSY asr %02x\n", asr);*/ 1002 #ifdef DDB 1003 /* Debugger();*/ 1004 #endif 1005 SBIC_TRACE(dev); 1006 return 1; 1007 } 1008 1009 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN); 1010 1011 /* 1012 * wait for select (merged from separate function may need 1013 * cleanup) 1014 */ 1015 WAIT_CIP(regs); 1016 do { 1017 asr = SBIC_WAIT(regs, SBIC_ASR_INT | SBIC_ASR_LCI, 0); 1018 if (asr & SBIC_ASR_LCI) { 1019 #ifdef DEBUG 1020 if (reselect_debug) 1021 printf("sbicselectbus: late LCI asr %02x\n", asr); 1022 #endif 1023 SBIC_TRACE(dev); 1024 return 1; 1025 } 1026 GET_SBIC_csr (regs, csr); 1027 CSR_TRACE('s',csr,asr,target); 1028 QPRINTF(("%02x ", csr)); 1029 if( csr == SBIC_CSR_RSLT_NI || csr == SBIC_CSR_RSLT_IFY) { 1030 #ifdef DEBUG 1031 if(reselect_debug) 1032 printf("sbicselectbus: reselected asr %02x\n", asr); 1033 #endif 1034 /* We need to handle this now so we don't lock up later */ 1035 sbicnextstate(dev, csr, asr); 1036 SBIC_TRACE(dev); 1037 return 1; 1038 } 1039 if( csr == SBIC_CSR_SLT || csr == SBIC_CSR_SLT_ATN) { 1040 panic("sbicselectbus: target issued select!"); 1041 return 1; 1042 } 1043 } while (csr != (SBIC_CSR_MIS_2|MESG_OUT_PHASE) 1044 && csr != (SBIC_CSR_MIS_2|CMD_PHASE) && csr != SBIC_CSR_SEL_TIMEO); 1045 1046 /* Enable (or not) reselection */ 1047 if(!sbic_enable_reselect && dev->nexus_list.tqh_first == NULL) 1048 SET_SBIC_rselid (regs, 0); 1049 else 1050 SET_SBIC_rselid (regs, SBIC_RID_ER); 1051 1052 if (csr == (SBIC_CSR_MIS_2|CMD_PHASE)) { 1053 dev->sc_flags |= SBICF_SELECTED; /* device ignored ATN */ 1054 GET_SBIC_selid(regs, id); 1055 dev->target = id; 1056 GET_SBIC_tlun(regs,dev->lun); 1057 if( dev->lun & SBIC_TLUN_VALID ) 1058 dev->lun &= SBIC_TLUN_MASK; 1059 else 1060 dev->lun = lun; 1061 } else if (csr == (SBIC_CSR_MIS_2|MESG_OUT_PHASE)) { 1062 /* 1063 * Send identify message 1064 * (SCSI-2 requires an identify msg (?)) 1065 */ 1066 GET_SBIC_selid(regs, id); 1067 dev->target = id; 1068 GET_SBIC_tlun(regs,dev->lun); 1069 if( dev->lun & SBIC_TLUN_VALID ) 1070 dev->lun &= SBIC_TLUN_MASK; 1071 else 1072 dev->lun = lun; 1073 /* 1074 * handle drives that don't want to be asked 1075 * whether to go sync at all. 1076 */ 1077 if (sbic_inhibit_sync[id] 1078 && dev->sc_sync[id].state == SYNC_START) { 1079 #ifdef DEBUG 1080 if (sync_debug) 1081 printf("Forcing target %d asynchronous.\n", id); 1082 #endif 1083 dev->sc_sync[id].offset = 0; 1084 dev->sc_sync[id].period = sbic_min_period; 1085 dev->sc_sync[id].state = SYNC_DONE; 1086 } 1087 1088 1089 if (dev->sc_sync[id].state != SYNC_START){ 1090 if( dev->sc_xs->xs_control & XS_CTL_POLL 1091 || (dev->sc_flags & SBICF_ICMD) 1092 || !sbic_enable_reselect ) 1093 SEND_BYTE (regs, MSG_IDENTIFY | lun); 1094 else 1095 SEND_BYTE (regs, MSG_IDENTIFY_DR | lun); 1096 } else { 1097 /* 1098 * try to initiate a sync transfer. 1099 * So compose the sync message we're going 1100 * to send to the target 1101 */ 1102 1103 #ifdef DEBUG 1104 if (sync_debug) 1105 printf("Sending sync request to target %d ... ", 1106 id); 1107 #endif 1108 /* 1109 * setup scsi message sync message request 1110 */ 1111 dev->sc_msg[0] = MSG_IDENTIFY | lun; 1112 dev->sc_msg[1] = MSG_EXT_MESSAGE; 1113 dev->sc_msg[2] = 3; 1114 dev->sc_msg[3] = MSG_SYNC_REQ; 1115 dev->sc_msg[4] = sbictoscsiperiod(dev, regs, 1116 sbic_min_period); 1117 dev->sc_msg[5] = sbic_max_offset; 1118 1119 if (sbicxfstart(regs, 6, MESG_OUT_PHASE, sbic_cmd_wait)) 1120 sbicxfout(regs, 6, dev->sc_msg, MESG_OUT_PHASE); 1121 1122 dev->sc_sync[id].state = SYNC_SENT; 1123 #ifdef DEBUG 1124 if (sync_debug) 1125 printf ("sent\n"); 1126 #endif 1127 } 1128 1129 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0); 1130 GET_SBIC_csr (regs, csr); 1131 CSR_TRACE('y',csr,asr,target); 1132 QPRINTF(("[%02x]", csr)); 1133 #ifdef DEBUG 1134 if (sync_debug && dev->sc_sync[id].state == SYNC_SENT) 1135 printf("csr-result of last msgout: 0x%x\n", csr); 1136 #endif 1137 1138 if (csr != SBIC_CSR_SEL_TIMEO) 1139 dev->sc_flags |= SBICF_SELECTED; 1140 } 1141 if (csr == SBIC_CSR_SEL_TIMEO) 1142 dev->sc_xs->error = XS_SELTIMEOUT; 1143 1144 QPRINTF(("\n")); 1145 1146 SBIC_TRACE(dev); 1147 return(csr == SBIC_CSR_SEL_TIMEO); 1148 } 1149 1150 int 1151 sbicxfstart(sbic_regmap_t regs, int len, u_char phase, int wait) 1152 { 1153 u_char id; 1154 1155 switch (phase) { 1156 case DATA_IN_PHASE: 1157 case MESG_IN_PHASE: 1158 GET_SBIC_selid (regs, id); 1159 id |= SBIC_SID_FROM_SCSI; 1160 SET_SBIC_selid (regs, id); 1161 SBIC_TC_PUT (regs, (unsigned)len); 1162 break; 1163 case DATA_OUT_PHASE: 1164 case MESG_OUT_PHASE: 1165 case CMD_PHASE: 1166 GET_SBIC_selid (regs, id); 1167 id &= ~SBIC_SID_FROM_SCSI; 1168 SET_SBIC_selid (regs, id); 1169 SBIC_TC_PUT (regs, (unsigned)len); 1170 break; 1171 default: 1172 SBIC_TC_PUT (regs, 0); 1173 } 1174 QPRINTF(("sbicxfstart %d, %d, %d\n", len, phase, wait)); 1175 1176 return(1); 1177 } 1178 1179 int 1180 sbicxfout(sbic_regmap_t regs, int len, void *bp, int phase) 1181 { 1182 u_char orig_csr, asr, *buf; 1183 int wait; 1184 1185 buf = bp; 1186 wait = sbic_data_wait; 1187 1188 QPRINTF(("sbicxfout {%d} %02x %02x %02x %02x %02x " 1189 "%02x %02x %02x %02x %02x\n", len, buf[0], buf[1], buf[2], 1190 buf[3], buf[4], buf[5], buf[6], buf[7], buf[8], buf[9])); 1191 1192 GET_SBIC_csr (regs, orig_csr); 1193 CSR_TRACE('>',orig_csr,0,0); 1194 1195 /* 1196 * sigh.. WD-PROTO strikes again.. sending the command in one go 1197 * causes the chip to lock up if talking to certain (misbehaving?) 1198 * targets. Anyway, this procedure should work for all targets, but 1199 * it's slightly slower due to the overhead 1200 */ 1201 WAIT_CIP (regs); 1202 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1203 for (;len > 0; len--) { 1204 GET_SBIC_asr (regs, asr); 1205 while ((asr & SBIC_ASR_DBR) == 0) { 1206 if ((asr & SBIC_ASR_INT) || --wait < 0) { 1207 #ifdef DEBUG 1208 if (sbic_debug) 1209 printf("sbicxfout fail: l%d i%x w%d\n", 1210 len, asr, wait); 1211 #endif 1212 return (len); 1213 } 1214 /* DELAY(1);*/ 1215 GET_SBIC_asr (regs, asr); 1216 } 1217 1218 SET_SBIC_data (regs, *buf); 1219 buf++; 1220 } 1221 SBIC_TC_GET(regs, len); 1222 QPRINTF(("sbicxfout done %d bytes\n", len)); 1223 /* 1224 * this leaves with one csr to be read 1225 */ 1226 return(0); 1227 } 1228 1229 /* returns # bytes left to read */ 1230 int 1231 sbicxfin(sbic_regmap_t regs, int len, void *bp) 1232 { 1233 int wait; 1234 u_char *obp, *buf; 1235 u_char orig_csr, csr, asr; 1236 1237 wait = sbic_data_wait; 1238 obp = bp; 1239 buf = bp; 1240 1241 GET_SBIC_csr (regs, orig_csr); 1242 CSR_TRACE('<',orig_csr,0,0); 1243 1244 QPRINTF(("sbicxfin %d, csr=%02x\n", len, orig_csr)); 1245 1246 WAIT_CIP (regs); 1247 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1248 for (;len > 0; len--) { 1249 GET_SBIC_asr (regs, asr); 1250 if((asr & SBIC_ASR_PE)) { 1251 #ifdef DEBUG 1252 printf("sbicxfin parity error: l%d i%x w%d\n", 1253 len, asr, wait); 1254 /* return ((unsigned long)buf - (unsigned long)bp); */ 1255 #ifdef DDB 1256 Debugger(); 1257 #endif 1258 #endif 1259 } 1260 while ((asr & SBIC_ASR_DBR) == 0) { 1261 if ((asr & SBIC_ASR_INT) || --wait < 0) { 1262 #ifdef DEBUG 1263 if (sbic_debug) { 1264 QPRINTF(("sbicxfin fail:{%d} %02x %02x %02x %02x %02x %02x " 1265 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1266 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1267 printf("sbicxfin fail: l%d i%x w%d\n", 1268 len, asr, wait); 1269 } 1270 #endif 1271 return len; 1272 } 1273 1274 if( ! asr & SBIC_ASR_BSY ) { 1275 GET_SBIC_csr(regs, csr); 1276 CSR_TRACE('<',csr,asr,len); 1277 QPRINTF(("[CSR%02xASR%02x]", csr, asr)); 1278 } 1279 1280 /* DELAY(1);*/ 1281 GET_SBIC_asr (regs, asr); 1282 } 1283 1284 GET_SBIC_data (regs, *buf); 1285 /* QPRINTF(("asr=%02x, csr=%02x, data=%02x\n", asr, csr, *buf));*/ 1286 buf++; 1287 } 1288 1289 QPRINTF(("sbicxfin {%d} %02x %02x %02x %02x %02x %02x " 1290 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1291 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1292 1293 /* this leaves with one csr to be read */ 1294 return len; 1295 } 1296 1297 /* 1298 * SCSI 'immediate' command: issue a command to some SCSI device 1299 * and get back an 'immediate' response (i.e., do programmed xfer 1300 * to get the response data). 'cbuf' is a buffer containing a scsi 1301 * command of length clen bytes. 'buf' is a buffer of length 'len' 1302 * bytes for data. The transfer direction is determined by the device 1303 * (i.e., by the scsi bus data xfer phase). If 'len' is zero, the 1304 * command must supply no data. 1305 */ 1306 int 1307 sbicicmd(struct sbic_softc *dev, int target, int lun, void *cbuf, int clen, 1308 void *buf, int len) 1309 { 1310 sbic_regmap_t regs; 1311 u_char phase, csr, asr; 1312 int wait, i; 1313 struct sbic_acb *acb; 1314 1315 #define CSR_LOG_BUF_SIZE 0 1316 #if CSR_LOG_BUF_SIZE 1317 int bufptr; 1318 int csrbuf[CSR_LOG_BUF_SIZE]; 1319 bufptr=0; 1320 #endif 1321 1322 SBIC_TRACE(dev); 1323 regs = dev->sc_sbic; 1324 acb = dev->sc_nexus; 1325 1326 /* Make sure pointers are OK */ 1327 dev->sc_last = dev->sc_cur = &acb->sc_pa; 1328 dev->sc_tcnt = acb->sc_tcnt = 0; 1329 acb->sc_pa.dc_count = 0; /* No DMA */ 1330 acb->sc_kv.dc_addr = buf; 1331 acb->sc_kv.dc_count = len; 1332 1333 #ifdef DEBUG 1334 routine = 3; 1335 debug_sbic_regs = regs; /* store this to allow debug calls */ 1336 if( data_pointer_debug > 1 ) 1337 printf("sbicicmd(%d,%d):%d\n", target, lun, 1338 acb->sc_kv.dc_count); 1339 #endif 1340 1341 /* 1342 * set the sbic into non-DMA mode 1343 */ 1344 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI /*| SBIC_CTL_HSP*/); 1345 1346 dev->sc_stat[0] = 0xff; 1347 dev->sc_msg[0] = 0xff; 1348 i = 1; /* pre-load */ 1349 1350 /* We're stealing the SCSI bus */ 1351 dev->sc_flags |= SBICF_ICMD; 1352 1353 do { 1354 /* 1355 * select the SCSI bus (it's an error if bus isn't free) 1356 */ 1357 if (!( dev->sc_flags & SBICF_SELECTED ) 1358 && sbicselectbus(dev, regs, target, lun, dev->sc_scsiaddr)) { 1359 /* printf("sbicicmd: trying to select busy bus!\n"); */ 1360 dev->sc_flags &= ~SBICF_ICMD; 1361 return(-1); 1362 } 1363 1364 /* 1365 * Wait for a phase change (or error) then let the device sequence 1366 * us through the various SCSI phases. 1367 */ 1368 1369 wait = sbic_cmd_wait; 1370 1371 GET_SBIC_asr (regs, asr); 1372 GET_SBIC_csr (regs, csr); 1373 CSR_TRACE('I',csr,asr,target); 1374 QPRINTF((">ASR:%02xCSR:%02x<", asr, csr)); 1375 1376 #if CSR_LOG_BUF_SIZE 1377 csrbuf[bufptr++] = csr; 1378 #endif 1379 1380 1381 switch (csr) { 1382 case SBIC_CSR_S_XFERRED: 1383 case SBIC_CSR_DISC: 1384 case SBIC_CSR_DISC_1: 1385 dev->sc_flags &= ~SBICF_SELECTED; 1386 GET_SBIC_cmd_phase (regs, phase); 1387 if (phase == 0x60) { 1388 GET_SBIC_tlun (regs, dev->sc_stat[0]); 1389 i = 0; /* done */ 1390 /* break; */ /* Bypass all the state gobldygook */ 1391 } else { 1392 #ifdef DEBUG 1393 if(reselect_debug>1) 1394 printf("sbicicmd: handling disconnect\n"); 1395 #endif 1396 i = SBIC_STATE_DISCONNECT; 1397 } 1398 break; 1399 1400 case SBIC_CSR_XFERRED|CMD_PHASE: 1401 case SBIC_CSR_MIS|CMD_PHASE: 1402 case SBIC_CSR_MIS_1|CMD_PHASE: 1403 case SBIC_CSR_MIS_2|CMD_PHASE: 1404 if (sbicxfstart(regs, clen, CMD_PHASE, sbic_cmd_wait)) 1405 if (sbicxfout(regs, clen, 1406 cbuf, CMD_PHASE)) 1407 i = sbicabort(dev, regs, "icmd sending cmd"); 1408 #if 0 1409 GET_SBIC_csr(regs, csr); /* Lets us reload tcount */ 1410 WAIT_CIP(regs); 1411 GET_SBIC_asr(regs, asr); 1412 CSR_TRACE('I',csr,asr,target); 1413 if( asr & (SBIC_ASR_BSY|SBIC_ASR_LCI|SBIC_ASR_CIP) ) 1414 printf("next: cmd sent asr %02x, csr %02x\n", 1415 asr, csr); 1416 #endif 1417 break; 1418 1419 #if 0 1420 case SBIC_CSR_XFERRED|DATA_OUT_PHASE: 1421 case SBIC_CSR_XFERRED|DATA_IN_PHASE: 1422 case SBIC_CSR_MIS|DATA_OUT_PHASE: 1423 case SBIC_CSR_MIS|DATA_IN_PHASE: 1424 case SBIC_CSR_MIS_1|DATA_OUT_PHASE: 1425 case SBIC_CSR_MIS_1|DATA_IN_PHASE: 1426 case SBIC_CSR_MIS_2|DATA_OUT_PHASE: 1427 case SBIC_CSR_MIS_2|DATA_IN_PHASE: 1428 if (acb->sc_kv.dc_count <= 0) 1429 i = sbicabort(dev, regs, "icmd out of data"); 1430 else { 1431 wait = sbic_data_wait; 1432 if (sbicxfstart(regs, 1433 acb->sc_kv.dc_count, 1434 SBIC_PHASE(csr), wait)) 1435 if (csr & 0x01) 1436 /* data in? */ 1437 i=sbicxfin(regs, 1438 acb->sc_kv.dc_count, 1439 acb->sc_kv.dc_addr); 1440 else 1441 i=sbicxfout(regs, 1442 acb->sc_kv.dc_count, 1443 acb->sc_kv.dc_addr, 1444 SBIC_PHASE(csr)); 1445 acb->sc_kv.dc_addr += 1446 (acb->sc_kv.dc_count - i); 1447 acb->sc_kv.dc_count = i; 1448 i = 1; 1449 } 1450 break; 1451 1452 #endif 1453 case SBIC_CSR_XFERRED|STATUS_PHASE: 1454 case SBIC_CSR_MIS|STATUS_PHASE: 1455 case SBIC_CSR_MIS_1|STATUS_PHASE: 1456 case SBIC_CSR_MIS_2|STATUS_PHASE: 1457 /* 1458 * the sbic does the status/cmd-complete reading ok, 1459 * so do this with its hi-level commands. 1460 */ 1461 #ifdef DEBUG 1462 if(sbic_debug) 1463 printf("SBICICMD status phase\n"); 1464 #endif 1465 SBIC_TC_PUT(regs, 0); 1466 SET_SBIC_cmd_phase(regs, 0x46); 1467 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1468 break; 1469 1470 #if THIS_IS_A_RESERVED_STATE 1471 case BUS_FREE_PHASE: /* This is not legal */ 1472 if( dev->sc_stat[0] != 0xff ) 1473 goto out; 1474 break; 1475 #endif 1476 1477 default: 1478 i = sbicnextstate(dev, csr, asr); 1479 } 1480 1481 /* 1482 * make sure the last command was taken, 1483 * ie. we're not hunting after an ignored command.. 1484 */ 1485 GET_SBIC_asr(regs, asr); 1486 1487 /* tapes may take a loooong time.. */ 1488 while (asr & SBIC_ASR_BSY){ 1489 if(asr & SBIC_ASR_DBR) { 1490 printf("sbicicmd: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", 1491 csr,asr); 1492 #ifdef DDB 1493 Debugger(); 1494 #endif 1495 /* SBIC is jammed */ 1496 /* DUNNO which direction */ 1497 /* Try old direction */ 1498 GET_SBIC_data(regs,i); 1499 GET_SBIC_asr(regs, asr); 1500 if( asr & SBIC_ASR_DBR) /* Wants us to write */ 1501 SET_SBIC_data(regs,i); 1502 } 1503 GET_SBIC_asr(regs, asr); 1504 } 1505 1506 /* 1507 * wait for last command to complete 1508 */ 1509 if (asr & SBIC_ASR_LCI) { 1510 printf("sbicicmd: last command ignored\n"); 1511 } 1512 else if( i == 1 ) /* Bsy */ 1513 SBIC_WAIT (regs, SBIC_ASR_INT, wait); 1514 1515 /* 1516 * do it again 1517 */ 1518 } while ( i > 0 && dev->sc_stat[0] == 0xff); 1519 1520 /* Sometimes we need to do an extra read of the CSR */ 1521 GET_SBIC_csr(regs, csr); 1522 CSR_TRACE('I',csr,asr,0xff); 1523 1524 #if CSR_LOG_BUF_SIZE 1525 if(reselect_debug>1) 1526 for(i=0; i<bufptr; i++) 1527 printf("CSR:%02x", csrbuf[i]); 1528 #endif 1529 1530 #ifdef DEBUG 1531 if(data_pointer_debug > 1) 1532 printf("sbicicmd done(%d,%d):%d =%d=\n", 1533 dev->target, lun, 1534 acb->sc_kv.dc_count, 1535 dev->sc_stat[0]); 1536 #endif 1537 1538 QPRINTF(("=STS:%02x=", dev->sc_stat[0])); 1539 dev->sc_flags &= ~SBICF_ICMD; 1540 1541 SBIC_TRACE(dev); 1542 return(dev->sc_stat[0]); 1543 } 1544 1545 /* 1546 * Finish SCSI xfer command: After the completion interrupt from 1547 * a read/write operation, sequence through the final phases in 1548 * programmed i/o. This routine is a lot like sbicicmd except we 1549 * skip (and don't allow) the select, cmd out and data in/out phases. 1550 */ 1551 void 1552 sbicxfdone(struct sbic_softc *dev, sbic_regmap_t regs, int target) 1553 { 1554 u_char phase, asr, csr; 1555 int s; 1556 1557 SBIC_TRACE(dev); 1558 QPRINTF(("{")); 1559 s = splbio(); 1560 1561 /* 1562 * have the sbic complete on its own 1563 */ 1564 SBIC_TC_PUT(regs, 0); 1565 SET_SBIC_cmd_phase(regs, 0x46); 1566 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1567 1568 do { 1569 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0); 1570 GET_SBIC_csr (regs, csr); 1571 CSR_TRACE('f',csr,asr,target); 1572 QPRINTF(("%02x:", csr)); 1573 } while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) 1574 && (csr != SBIC_CSR_S_XFERRED)); 1575 1576 dev->sc_flags &= ~SBICF_SELECTED; 1577 1578 GET_SBIC_cmd_phase (regs, phase); 1579 QPRINTF(("}%02x", phase)); 1580 if (phase == 0x60) 1581 GET_SBIC_tlun(regs, dev->sc_stat[0]); 1582 else 1583 sbicerror(dev, regs, csr); 1584 1585 QPRINTF(("=STS:%02x=\n", dev->sc_stat[0])); 1586 splx(s); 1587 SBIC_TRACE(dev); 1588 } 1589 1590 /* 1591 * No DMA chains 1592 */ 1593 1594 int 1595 sbicgo(struct sbic_softc *dev, struct scsipi_xfer *xs) 1596 { 1597 int i, dmaflags, count, usedma; 1598 u_char csr, asr, *addr; 1599 sbic_regmap_t regs; 1600 struct sbic_acb *acb; 1601 1602 SBIC_TRACE(dev); 1603 dev->target = xs->xs_periph->periph_target; 1604 dev->lun = xs->xs_periph->periph_lun; 1605 acb = dev->sc_nexus; 1606 regs = dev->sc_sbic; 1607 1608 usedma = sbicdmaok(dev, xs); 1609 #ifdef DEBUG 1610 routine = 1; 1611 debug_sbic_regs = regs; /* store this to allow debug calls */ 1612 if( data_pointer_debug > 1 ) 1613 printf("sbicgo(%d,%d)\n", dev->target, dev->lun); 1614 #endif 1615 1616 /* 1617 * set the sbic into DMA mode 1618 */ 1619 if( usedma ) 1620 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI | 1621 SBIC_MACHINE_DMA_MODE); 1622 else 1623 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1624 1625 1626 /* 1627 * select the SCSI bus (it's an error if bus isn't free) 1628 */ 1629 if (sbicselectbus(dev, regs, dev->target, dev->lun, 1630 dev->sc_scsiaddr)) { 1631 /* printf("sbicgo: Trying to select busy bus!\n"); */ 1632 SBIC_TRACE(dev); 1633 return(0); /* Not done: needs to be rescheduled */ 1634 } 1635 dev->sc_stat[0] = 0xff; 1636 1637 /* 1638 * Calculate DMA chains now 1639 */ 1640 1641 dmaflags = 0; 1642 if (acb->flags & ACB_DATAIN) 1643 dmaflags |= DMAGO_READ; 1644 1645 1646 /* 1647 * Deal w/bounce buffers. 1648 */ 1649 1650 addr = acb->sc_kv.dc_addr; 1651 count = acb->sc_kv.dc_count; 1652 if (count && (char *)kvtop(addr) != acb->sc_pa.dc_addr) { /* XXXX check */ 1653 printf("sbic: DMA buffer mapping changed %p->%x\n", 1654 acb->sc_pa.dc_addr, (unsigned)kvtop(addr)); 1655 #ifdef DDB 1656 Debugger(); 1657 #endif 1658 } 1659 1660 #ifdef DEBUG 1661 ++sbicdma_ops; /* count total DMA operations */ 1662 #endif 1663 if (count && usedma && dev->sc_flags & SBICF_BADDMA && 1664 sbiccheckdmap(addr, count, dev->sc_dmamask)) { 1665 /* 1666 * need to bounce the DMA. 1667 */ 1668 if (dmaflags & DMAGO_READ) { 1669 acb->flags |= ACB_BBUF; 1670 acb->sc_dmausrbuf = addr; 1671 acb->sc_dmausrlen = count; 1672 acb->sc_usrbufpa = (u_char *)kvtop(addr); 1673 if(!dev->sc_tinfo[dev->target].bounce) { 1674 printf("sbicgo: HELP! no bounce allocated for %d\n", 1675 dev->target); 1676 printf("xfer: (%p->%p,%lx)\n", acb->sc_dmausrbuf, 1677 acb->sc_usrbufpa, acb->sc_dmausrlen); 1678 dev->sc_tinfo[xs->xs_periph->periph_target].bounce 1679 = (char *)alloc_z2mem(MAXPHYS); 1680 if (isztwomem(dev->sc_tinfo[xs->xs_periph->periph_target].bounce)) 1681 printf("alloc ZII target %d bounce pa 0x%x\n", 1682 xs->xs_periph->periph_target, 1683 (unsigned)kvtop(dev->sc_tinfo[xs->xs_periph->periph_target].bounce)); 1684 else if (dev->sc_tinfo[xs->xs_periph->periph_target].bounce) 1685 printf("alloc CHIP target %d bounce pa %p\n", 1686 xs->xs_periph->periph_target, 1687 PREP_DMA_MEM(dev->sc_tinfo[xs->xs_periph->periph_target].bounce)); 1688 1689 printf("Allocating %d bounce at %x\n", 1690 dev->target, 1691 (unsigned)kvtop(dev->sc_tinfo[dev->target].bounce)); 1692 } 1693 } else { /* write: copy to DMA buffer */ 1694 #ifdef DEBUG 1695 if(data_pointer_debug) 1696 printf("sbicgo: copying %x bytes to target %d bounce %x\n", 1697 count, dev->target, 1698 (unsigned)kvtop(dev->sc_tinfo[dev->target].bounce)); 1699 #endif 1700 bcopy (addr, dev->sc_tinfo[dev->target].bounce, count); 1701 } 1702 addr = dev->sc_tinfo[dev->target].bounce;/* and use DMA buffer */ 1703 acb->sc_kv.dc_addr = addr; 1704 #ifdef DEBUG 1705 ++sbicdma_bounces; /* count number of bounced */ 1706 #endif 1707 } 1708 1709 /* 1710 * Allocate the DMA chain 1711 */ 1712 1713 /* Set start KVM addresses */ 1714 #if 0 1715 acb->sc_kv.dc_addr = addr; 1716 acb->sc_kv.dc_count = count; 1717 #endif 1718 1719 /* Mark end of segment */ 1720 acb->sc_tcnt = dev->sc_tcnt = 0; 1721 acb->sc_pa.dc_count = 0; 1722 1723 sbic_load_ptrs(dev, regs, dev->target, dev->lun); 1724 SBIC_TRACE(dev); 1725 /* Enable interrupts but don't do any DMA */ 1726 dev->sc_enintr(dev); 1727 if (usedma) { 1728 dev->sc_tcnt = dev->sc_dmago(dev, acb->sc_pa.dc_addr, 1729 acb->sc_pa.dc_count, 1730 dmaflags); 1731 #ifdef DEBUG 1732 dev->sc_dmatimo = dev->sc_tcnt ? 1 : 0; 1733 #endif 1734 } else 1735 dev->sc_dmacmd = 0; /* Don't use DMA */ 1736 dev->sc_flags |= SBICF_INDMA; 1737 /* SBIC_TC_PUT(regs, dev->sc_tcnt); */ /* XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX */ 1738 SBIC_TRACE(dev); 1739 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 1740 1741 /* 1742 * push the data cache ( I think this won't work (EH)) 1743 */ 1744 #if defined(M68040) || defined(M68060) 1745 if (mmutype == MMU_68040 && usedma && count) { 1746 dma_cachectl(addr, count); 1747 if (((u_int)addr & 0xF) || (((u_int)addr + count) & 0xF)) 1748 dev->sc_flags |= SBICF_DCFLUSH; 1749 } 1750 #endif 1751 #ifdef __powerpc__ 1752 dma_cachectl(addr, count); 1753 #endif 1754 1755 /* 1756 * enintr() also enables interrupts for the sbic 1757 */ 1758 #ifdef DEBUG 1759 if( data_pointer_debug > 1 ) 1760 printf("sbicgo dmago:%d(%p:%lx)\n", 1761 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 1762 #if 0 1763 /* 1764 * Hmm - this isn't right: asr and csr haven't been set yet. 1765 */ 1766 debug_asr = asr; 1767 debug_csr = csr; 1768 #endif 1769 #endif 1770 1771 /* 1772 * Lets cycle a while then let the interrupt handler take over 1773 */ 1774 1775 GET_SBIC_asr(regs, asr); 1776 do { 1777 GET_SBIC_csr(regs, csr); 1778 CSR_TRACE('g',csr,asr,dev->target); 1779 #ifdef DEBUG 1780 debug_csr = csr; 1781 routine = 1; 1782 #endif 1783 QPRINTF(("go[0x%x]", csr)); 1784 1785 i = sbicnextstate(dev, csr, asr); 1786 1787 WAIT_CIP(regs); 1788 GET_SBIC_asr(regs, asr); 1789 #ifdef DEBUG 1790 debug_asr = asr; 1791 #endif 1792 if(asr & SBIC_ASR_LCI) printf("sbicgo: LCI asr:%02x csr:%02x\n", 1793 asr,csr); 1794 } while( i == SBIC_STATE_RUNNING 1795 && asr & (SBIC_ASR_INT|SBIC_ASR_LCI) ); 1796 1797 CSR_TRACE('g',csr,asr,i<<4); 1798 SBIC_TRACE(dev); 1799 if (i == SBIC_STATE_DONE && dev->sc_stat[0] == 0xff) printf("sbicgo: done & stat = 0xff\n"); 1800 if (i == SBIC_STATE_DONE && dev->sc_stat[0] != 0xff) { 1801 /* if( i == SBIC_STATE_DONE && dev->sc_stat[0] ) { */ 1802 /* Did we really finish that fast? */ 1803 return 1; 1804 } 1805 return 0; 1806 } 1807 1808 1809 int 1810 sbicintr(struct sbic_softc *dev) 1811 { 1812 sbic_regmap_t regs; 1813 u_char asr, csr; 1814 int i; 1815 1816 regs = dev->sc_sbic; 1817 1818 /* 1819 * pending interrupt? 1820 */ 1821 GET_SBIC_asr (regs, asr); 1822 if ((asr & SBIC_ASR_INT) == 0) 1823 return(0); 1824 1825 SBIC_TRACE(dev); 1826 do { 1827 GET_SBIC_csr(regs, csr); 1828 CSR_TRACE('i',csr,asr,dev->target); 1829 #ifdef DEBUG 1830 debug_csr = csr; 1831 routine = 2; 1832 #endif 1833 QPRINTF(("intr[0x%x]", csr)); 1834 1835 i = sbicnextstate(dev, csr, asr); 1836 1837 WAIT_CIP(regs); 1838 GET_SBIC_asr(regs, asr); 1839 #ifdef DEBUG 1840 debug_asr = asr; 1841 #endif 1842 #if 0 1843 if(asr & SBIC_ASR_LCI) printf("sbicintr: LCI asr:%02x csr:%02x\n", 1844 asr,csr); 1845 #endif 1846 } while(i == SBIC_STATE_RUNNING && 1847 asr & (SBIC_ASR_INT|SBIC_ASR_LCI)); 1848 CSR_TRACE('i',csr,asr,i<<4); 1849 SBIC_TRACE(dev); 1850 return(1); 1851 } 1852 1853 /* 1854 * Run commands and wait for disconnect 1855 */ 1856 int 1857 sbicpoll(struct sbic_softc *dev) 1858 { 1859 sbic_regmap_t regs; 1860 u_char asr, csr; 1861 int i; 1862 1863 SBIC_TRACE(dev); 1864 regs = dev->sc_sbic; 1865 1866 do { 1867 GET_SBIC_asr (regs, asr); 1868 #ifdef DEBUG 1869 debug_asr = asr; 1870 #endif 1871 GET_SBIC_csr(regs, csr); 1872 CSR_TRACE('p',csr,asr,dev->target); 1873 #ifdef DEBUG 1874 debug_csr = csr; 1875 routine = 2; 1876 #endif 1877 QPRINTF(("poll[0x%x]", csr)); 1878 1879 i = sbicnextstate(dev, csr, asr); 1880 1881 WAIT_CIP(regs); 1882 GET_SBIC_asr(regs, asr); 1883 /* tapes may take a loooong time.. */ 1884 while (asr & SBIC_ASR_BSY){ 1885 if(asr & SBIC_ASR_DBR) { 1886 printf("sbipoll: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", 1887 csr,asr); 1888 #ifdef DDB 1889 Debugger(); 1890 #endif 1891 /* SBIC is jammed */ 1892 /* DUNNO which direction */ 1893 /* Try old direction */ 1894 GET_SBIC_data(regs,i); 1895 GET_SBIC_asr(regs, asr); 1896 if( asr & SBIC_ASR_DBR) /* Wants us to write */ 1897 SET_SBIC_data(regs,i); 1898 } 1899 GET_SBIC_asr(regs, asr); 1900 } 1901 1902 if(asr & SBIC_ASR_LCI) printf("sbicpoll: LCI asr:%02x csr:%02x\n", 1903 asr,csr); 1904 else if( i == 1 ) /* BSY */ 1905 SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait); 1906 } while(i == SBIC_STATE_RUNNING); 1907 CSR_TRACE('p',csr,asr,i<<4); 1908 SBIC_TRACE(dev); 1909 return(1); 1910 } 1911 1912 /* 1913 * Handle a single msgin 1914 */ 1915 1916 int 1917 sbicmsgin(struct sbic_softc *dev) 1918 { 1919 sbic_regmap_t regs; 1920 int recvlen; 1921 u_char asr, csr, *tmpaddr; 1922 1923 regs = dev->sc_sbic; 1924 1925 dev->sc_msg[0] = 0xff; 1926 dev->sc_msg[1] = 0xff; 1927 1928 GET_SBIC_asr(regs, asr); 1929 #ifdef DEBUG 1930 if(reselect_debug>1) 1931 printf("sbicmsgin asr=%02x\n", asr); 1932 #endif 1933 1934 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 1935 1936 GET_SBIC_selid (regs, csr); 1937 SET_SBIC_selid (regs, csr | SBIC_SID_FROM_SCSI); 1938 1939 SBIC_TC_PUT(regs, 0); 1940 tmpaddr = dev->sc_msg; 1941 recvlen = 1; 1942 do { 1943 while( recvlen-- ) { 1944 GET_SBIC_asr(regs, asr); 1945 GET_SBIC_csr(regs, csr); 1946 QPRINTF(("sbicmsgin ready to go (csr,asr)=(%02x,%02x)\n", 1947 csr, asr)); 1948 1949 RECV_BYTE(regs, *tmpaddr); 1950 CSR_TRACE('m',csr,asr,*tmpaddr); 1951 #if 1 1952 /* 1953 * get the command completion interrupt, or we 1954 * can't send a new command (LCI) 1955 */ 1956 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1957 GET_SBIC_csr(regs, csr); 1958 CSR_TRACE('X',csr,asr,dev->target); 1959 #else 1960 WAIT_CIP(regs); 1961 do { 1962 GET_SBIC_asr(regs, asr); 1963 csr = 0xff; 1964 GET_SBIC_csr(regs, csr); 1965 CSR_TRACE('X',csr,asr,dev->target); 1966 if( csr == 0xff ) 1967 printf("sbicmsgin waiting: csr %02x asr %02x\n", csr, asr); 1968 } while( csr == 0xff ); 1969 #endif 1970 #ifdef DEBUG 1971 if(reselect_debug>1) 1972 printf("sbicmsgin: got %02x csr %02x asr %02x\n", 1973 *tmpaddr, csr, asr); 1974 #endif 1975 #if do_parity_check 1976 if( asr & SBIC_ASR_PE ) { 1977 printf ("Parity error"); 1978 /* This code simply does not work. */ 1979 WAIT_CIP(regs); 1980 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 1981 WAIT_CIP(regs); 1982 GET_SBIC_asr(regs, asr); 1983 WAIT_CIP(regs); 1984 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 1985 WAIT_CIP(regs); 1986 if( !(asr & SBIC_ASR_LCI) ) 1987 /* Target wants to send garbled msg*/ 1988 continue; 1989 printf("--fixing\n"); 1990 /* loop until a msgout phase occurs on target */ 1991 while(csr & 0x07 != MESG_OUT_PHASE) { 1992 while( asr & SBIC_ASR_BSY && 1993 !(asr & SBIC_ASR_DBR|SBIC_ASR_INT) ) 1994 GET_SBIC_asr(regs, asr); 1995 if( asr & SBIC_ASR_DBR ) 1996 panic("msgin: jammed again!"); 1997 GET_SBIC_csr(regs, csr); 1998 CSR_TRACE('e',csr,asr,dev->target); 1999 if( csr & 0x07 != MESG_OUT_PHASE ) { 2000 sbicnextstate(dev, csr, asr); 2001 sbic_save_ptrs(dev, regs, 2002 dev->target, 2003 dev->lun); 2004 } 2005 } 2006 /* Should be msg out by now */ 2007 SEND_BYTE(regs, MSG_PARITY_ERROR); 2008 } 2009 else 2010 #endif 2011 tmpaddr++; 2012 2013 if(recvlen) { 2014 /* Clear ACK */ 2015 WAIT_CIP(regs); 2016 GET_SBIC_asr(regs, asr); 2017 GET_SBIC_csr(regs, csr); 2018 CSR_TRACE('X',csr,asr,dev->target); 2019 QPRINTF(("sbicmsgin pre byte CLR_ACK (csr,asr)=(%02x,%02x)\n", 2020 csr, asr)); 2021 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2022 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2023 } 2024 2025 }; 2026 2027 if(dev->sc_msg[0] == 0xff) { 2028 printf("sbicmsgin: sbic swallowed our message\n"); 2029 break; 2030 } 2031 #ifdef DEBUG 2032 if (sync_debug) 2033 printf("msgin done csr 0x%x asr 0x%x msg 0x%x\n", 2034 csr, asr, dev->sc_msg[0]); 2035 #endif 2036 /* 2037 * test whether this is a reply to our sync 2038 * request 2039 */ 2040 if (MSG_ISIDENTIFY(dev->sc_msg[0])) { 2041 QPRINTF(("IFFY")); 2042 #if 0 2043 /* There is an implied load-ptrs here */ 2044 sbic_load_ptrs(dev, regs, dev->target, dev->lun); 2045 #endif 2046 /* Got IFFY msg -- ack it */ 2047 } else if (dev->sc_msg[0] == MSG_REJECT 2048 && dev->sc_sync[dev->target].state == SYNC_SENT) { 2049 QPRINTF(("REJECT of SYN")); 2050 #ifdef DEBUG 2051 if (sync_debug) 2052 printf("target %d rejected sync, going async\n", 2053 dev->target); 2054 #endif 2055 dev->sc_sync[dev->target].period = sbic_min_period; 2056 dev->sc_sync[dev->target].offset = 0; 2057 dev->sc_sync[dev->target].state = SYNC_DONE; 2058 SET_SBIC_syn(regs, 2059 SBIC_SYN(dev->sc_sync[dev->target].offset, 2060 dev->sc_sync[dev->target].period)); 2061 } else if ((dev->sc_msg[0] == MSG_REJECT)) { 2062 QPRINTF(("REJECT")); 2063 /* 2064 * we'll never REJECt a REJECT message.. 2065 */ 2066 } else if ((dev->sc_msg[0] == MSG_SAVE_DATA_PTR)) { 2067 QPRINTF(("MSG_SAVE_DATA_PTR")); 2068 /* 2069 * don't reject this either. 2070 */ 2071 } else if ((dev->sc_msg[0] == MSG_DISCONNECT)) { 2072 QPRINTF(("DISCONNECT")); 2073 #ifdef DEBUG 2074 if( reselect_debug>1 && dev->sc_msg[0] == MSG_DISCONNECT ) 2075 printf("sbicmsgin: got disconnect msg %s\n", 2076 (dev->sc_flags & SBICF_ICMD)?"rejecting":""); 2077 #endif 2078 if( dev->sc_flags & SBICF_ICMD ) { 2079 /* We're in immediate mode. Prevent disconnects. */ 2080 /* prepare to reject the message, NACK */ 2081 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2082 WAIT_CIP(regs); 2083 } 2084 } else if (dev->sc_msg[0] == MSG_CMD_COMPLETE ) { 2085 QPRINTF(("CMD_COMPLETE")); 2086 /* !! KLUDGE ALERT !! quite a few drives don't seem to 2087 * really like the current way of sending the 2088 * sync-handshake together with the ident-message, and 2089 * they react by sending command-complete and 2090 * disconnecting right after returning the valid sync 2091 * handshake. So, all I can do is reselect the drive, 2092 * and hope it won't disconnect again. I don't think 2093 * this is valid behavior, but I can't help fixing a 2094 * problem that apparently exists. 2095 * 2096 * Note: we should not get here on `normal' command 2097 * completion, as that condition is handled by the 2098 * high-level sel&xfer resume command used to walk 2099 * thru status/cc-phase. 2100 */ 2101 2102 #ifdef DEBUG 2103 if (sync_debug) 2104 printf ("GOT MSG %d! target %d acting weird.." 2105 " waiting for disconnect...\n", 2106 dev->sc_msg[0], dev->target); 2107 #endif 2108 /* Check to see if sbic is handling this */ 2109 GET_SBIC_asr(regs, asr); 2110 if(asr & SBIC_ASR_BSY) 2111 return SBIC_STATE_RUNNING; 2112 2113 /* Let's try this: Assume it works and set status to 00 */ 2114 dev->sc_stat[0] = 0; 2115 } else if (dev->sc_msg[0] == MSG_EXT_MESSAGE 2116 && tmpaddr == &dev->sc_msg[1]) { 2117 QPRINTF(("ExtMSG\n")); 2118 /* Read in whole extended message */ 2119 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2120 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2121 GET_SBIC_asr(regs, asr); 2122 GET_SBIC_csr(regs, csr); 2123 QPRINTF(("CLR ACK asr %02x, csr %02x\n", asr, csr)); 2124 RECV_BYTE(regs, *tmpaddr); 2125 CSR_TRACE('x',csr,asr,*tmpaddr); 2126 /* Wait for command completion IRQ */ 2127 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2128 recvlen = *tmpaddr++; 2129 QPRINTF(("Recving ext msg, asr %02x csr %02x len %02x\n", 2130 asr, csr, recvlen)); 2131 } else if (dev->sc_msg[0] == MSG_EXT_MESSAGE && dev->sc_msg[1] == 3 2132 && dev->sc_msg[2] == MSG_SYNC_REQ) { 2133 QPRINTF(("SYN")); 2134 dev->sc_sync[dev->target].period = 2135 sbicfromscsiperiod(dev, 2136 regs, dev->sc_msg[3]); 2137 dev->sc_sync[dev->target].offset = dev->sc_msg[4]; 2138 dev->sc_sync[dev->target].state = SYNC_DONE; 2139 SET_SBIC_syn(regs, 2140 SBIC_SYN(dev->sc_sync[dev->target].offset, 2141 dev->sc_sync[dev->target].period)); 2142 printf("%s: target %d now synchronous," 2143 " period=%dns, offset=%d.\n", 2144 dev->sc_dev.dv_xname, dev->target, 2145 dev->sc_msg[3] * 4, dev->sc_msg[4]); 2146 } else { 2147 #ifdef DEBUG 2148 if (sbic_debug || sync_debug) 2149 printf ("sbicmsgin: Rejecting message 0x%02x\n", 2150 dev->sc_msg[0]); 2151 #endif 2152 /* prepare to reject the message, NACK */ 2153 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2154 WAIT_CIP(regs); 2155 } 2156 /* Clear ACK */ 2157 WAIT_CIP(regs); 2158 GET_SBIC_asr(regs, asr); 2159 GET_SBIC_csr(regs, csr); 2160 CSR_TRACE('X',csr,asr,dev->target); 2161 QPRINTF(("sbicmsgin pre CLR_ACK (csr,asr)=(%02x,%02x)%d\n", 2162 csr, asr, recvlen)); 2163 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2164 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2165 } 2166 #if 0 2167 while((csr == SBIC_CSR_MSGIN_W_ACK) 2168 || (SBIC_PHASE(csr) == MESG_IN_PHASE)); 2169 #else 2170 while (recvlen>0); 2171 #endif 2172 2173 QPRINTF(("sbicmsgin finished: csr %02x, asr %02x\n",csr, asr)); 2174 2175 /* Should still have one CSR to read */ 2176 return SBIC_STATE_RUNNING; 2177 } 2178 2179 2180 /* 2181 * sbicnextstate() 2182 * return: 2183 * 0 == done 2184 * 1 == working 2185 * 2 == disconnected 2186 * -1 == error 2187 */ 2188 int 2189 sbicnextstate(struct sbic_softc *dev, u_char csr, u_char asr) 2190 { 2191 sbic_regmap_t regs; 2192 struct sbic_acb *acb; 2193 int i, newtarget, newlun, wait; 2194 #if 0 2195 unsigned tcnt; 2196 #endif 2197 2198 i = 0; 2199 SBIC_TRACE(dev); 2200 regs = dev->sc_sbic; 2201 acb = dev->sc_nexus; 2202 2203 QPRINTF(("next[%02x,%02x]",asr,csr)); 2204 2205 switch (csr) { 2206 case SBIC_CSR_XFERRED|CMD_PHASE: 2207 case SBIC_CSR_MIS|CMD_PHASE: 2208 case SBIC_CSR_MIS_1|CMD_PHASE: 2209 case SBIC_CSR_MIS_2|CMD_PHASE: 2210 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 2211 if (sbicxfstart(regs, acb->clen, CMD_PHASE, sbic_cmd_wait)) 2212 if (sbicxfout(regs, acb->clen, 2213 &acb->cmd, CMD_PHASE)) 2214 goto abort; 2215 break; 2216 2217 case SBIC_CSR_XFERRED|STATUS_PHASE: 2218 case SBIC_CSR_MIS|STATUS_PHASE: 2219 case SBIC_CSR_MIS_1|STATUS_PHASE: 2220 case SBIC_CSR_MIS_2|STATUS_PHASE: 2221 /* 2222 * this should be the normal i/o completion case. 2223 * get the status & cmd complete msg then let the 2224 * device driver look at what happened. 2225 */ 2226 sbicxfdone(dev,regs,dev->target); 2227 /* 2228 * check for overlapping cache line, flush if so 2229 */ 2230 #if defined(M68040) || defined(M68060) 2231 if (dev->sc_flags & SBICF_DCFLUSH) { 2232 #if 0 2233 printf("sbic: 68040/68060 DMA cache flush needs" 2234 "fixing? %x:%x\n", 2235 dev->sc_xs->data, dev->sc_xs->datalen); 2236 #endif 2237 } 2238 #endif 2239 #ifdef DEBUG 2240 if( data_pointer_debug > 1 ) 2241 printf("next dmastop: %d(%p:%lx)\n", 2242 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 2243 dev->sc_dmatimo = 0; 2244 #endif 2245 dev->sc_dmastop(dev); /* was dmafree */ 2246 if (acb->flags & ACB_BBUF) { 2247 if ((u_char *)kvtop(acb->sc_dmausrbuf) != acb->sc_usrbufpa) 2248 printf("%s: WARNING - buffer mapping changed %p->%x\n", 2249 dev->sc_dev.dv_xname, acb->sc_usrbufpa, 2250 (unsigned)kvtop(acb->sc_dmausrbuf)); 2251 #ifdef DEBUG 2252 if(data_pointer_debug) 2253 printf("sbicgo:copying %lx bytes from target %d bounce %x\n", 2254 acb->sc_dmausrlen, 2255 dev->target, 2256 (unsigned)kvtop(dev->sc_tinfo[dev->target].bounce)); 2257 #endif 2258 bcopy(dev->sc_tinfo[dev->target].bounce, 2259 acb->sc_dmausrbuf, 2260 acb->sc_dmausrlen); 2261 } 2262 dev->sc_flags &= ~(SBICF_INDMA | SBICF_DCFLUSH); 2263 sbic_scsidone(acb, dev->sc_stat[0]); 2264 SBIC_TRACE(dev); 2265 return SBIC_STATE_DONE; 2266 2267 case SBIC_CSR_XFERRED|DATA_OUT_PHASE: 2268 case SBIC_CSR_XFERRED|DATA_IN_PHASE: 2269 case SBIC_CSR_MIS|DATA_OUT_PHASE: 2270 case SBIC_CSR_MIS|DATA_IN_PHASE: 2271 case SBIC_CSR_MIS_1|DATA_OUT_PHASE: 2272 case SBIC_CSR_MIS_1|DATA_IN_PHASE: 2273 case SBIC_CSR_MIS_2|DATA_OUT_PHASE: 2274 case SBIC_CSR_MIS_2|DATA_IN_PHASE: 2275 if( dev->sc_xs->xs_control & XS_CTL_POLL || dev->sc_flags & SBICF_ICMD 2276 || acb->sc_dmacmd == 0 ) { 2277 /* Do PIO */ 2278 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2279 if (acb->sc_kv.dc_count <= 0) { 2280 printf("sbicnextstate:xfer count %d asr%x csr%x\n", 2281 acb->sc_kv.dc_count, asr, csr); 2282 goto abort; 2283 } 2284 wait = sbic_data_wait; 2285 if( sbicxfstart(regs, 2286 acb->sc_kv.dc_count, 2287 SBIC_PHASE(csr), wait)) { 2288 if( SBIC_PHASE(csr) == DATA_IN_PHASE ) 2289 /* data in? */ 2290 i=sbicxfin(regs, 2291 acb->sc_kv.dc_count, 2292 acb->sc_kv.dc_addr); 2293 else 2294 i=sbicxfout(regs, 2295 acb->sc_kv.dc_count, 2296 acb->sc_kv.dc_addr, 2297 SBIC_PHASE(csr)); 2298 } 2299 acb->sc_kv.dc_addr += 2300 (acb->sc_kv.dc_count - i); 2301 acb->sc_kv.dc_count = i; 2302 } else { 2303 if (acb->sc_kv.dc_count <= 0) { 2304 printf("sbicnextstate:xfer count %d asr%x csr%x\n", 2305 acb->sc_kv.dc_count, asr, csr); 2306 goto abort; 2307 } 2308 /* 2309 * do scatter-gather DMA 2310 * hacking the controller chip, ouch.. 2311 */ 2312 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI | 2313 SBIC_MACHINE_DMA_MODE); 2314 /* 2315 * set next DMA addr and dec count 2316 */ 2317 #if 0 2318 SBIC_TC_GET(regs, tcnt); 2319 dev->sc_cur->dc_count -= ((dev->sc_tcnt - tcnt) >> 1); 2320 dev->sc_cur->dc_addr += (dev->sc_tcnt - tcnt); 2321 dev->sc_tcnt = acb->sc_tcnt = tcnt; 2322 #else 2323 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 2324 sbic_load_ptrs(dev, regs, dev->target, dev->lun); 2325 #endif 2326 #ifdef DEBUG 2327 if( data_pointer_debug > 1 ) 2328 printf("next dmanext: %d(%p:%lx)\n", 2329 dev->target,dev->sc_cur->dc_addr, 2330 dev->sc_tcnt); 2331 dev->sc_dmatimo = 1; 2332 #endif 2333 dev->sc_tcnt = dev->sc_dmanext(dev); 2334 SBIC_TC_PUT(regs, (unsigned)dev->sc_tcnt); 2335 SET_SBIC_cmd(regs, SBIC_CMD_XFER_INFO); 2336 dev->sc_flags |= SBICF_INDMA; 2337 } 2338 break; 2339 2340 case SBIC_CSR_XFERRED|MESG_IN_PHASE: 2341 case SBIC_CSR_MIS|MESG_IN_PHASE: 2342 case SBIC_CSR_MIS_1|MESG_IN_PHASE: 2343 case SBIC_CSR_MIS_2|MESG_IN_PHASE: 2344 SBIC_TRACE(dev); 2345 return sbicmsgin(dev); 2346 2347 case SBIC_CSR_MSGIN_W_ACK: 2348 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); /* Dunno what I'm ACKing */ 2349 printf("Acking unknown msgin CSR:%02x",csr); 2350 break; 2351 2352 case SBIC_CSR_XFERRED|MESG_OUT_PHASE: 2353 case SBIC_CSR_MIS|MESG_OUT_PHASE: 2354 case SBIC_CSR_MIS_1|MESG_OUT_PHASE: 2355 case SBIC_CSR_MIS_2|MESG_OUT_PHASE: 2356 #ifdef DEBUG 2357 if (sync_debug) 2358 printf ("sending REJECT msg to last msg.\n"); 2359 #endif 2360 2361 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 2362 /* 2363 * should only get here on reject, 2364 * since it's always US that 2365 * initiate a sync transfer 2366 */ 2367 SEND_BYTE(regs, MSG_REJECT); 2368 WAIT_CIP(regs); 2369 if( asr & (SBIC_ASR_BSY|SBIC_ASR_LCI|SBIC_ASR_CIP) ) 2370 printf("next: REJECT sent asr %02x\n", asr); 2371 SBIC_TRACE(dev); 2372 return SBIC_STATE_RUNNING; 2373 2374 case SBIC_CSR_DISC: 2375 case SBIC_CSR_DISC_1: 2376 dev->sc_flags &= ~(SBICF_INDMA|SBICF_SELECTED); 2377 2378 /* Try to schedule another target */ 2379 #ifdef DEBUG 2380 if(reselect_debug>1) 2381 printf("sbicnext target %d disconnected\n", dev->target); 2382 #endif 2383 TAILQ_INSERT_HEAD(&dev->nexus_list, acb, chain); 2384 ++dev->sc_tinfo[dev->target].dconns; 2385 dev->sc_nexus = NULL; 2386 dev->sc_xs = NULL; 2387 2388 if( acb->xs->xs_control & XS_CTL_POLL 2389 || (dev->sc_flags & SBICF_ICMD) 2390 || !sbic_parallel_operations ) { 2391 SBIC_TRACE(dev); 2392 return SBIC_STATE_DISCONNECT; 2393 } 2394 sbic_sched(dev); 2395 SBIC_TRACE(dev); 2396 return SBIC_STATE_DISCONNECT; 2397 2398 case SBIC_CSR_RSLT_NI: 2399 case SBIC_CSR_RSLT_IFY: 2400 GET_SBIC_rselid(regs, newtarget); 2401 /* check SBIC_RID_SIV? */ 2402 newtarget &= SBIC_RID_MASK; 2403 if (csr == SBIC_CSR_RSLT_IFY) { 2404 /* Read IFY msg to avoid lockup */ 2405 GET_SBIC_data(regs, newlun); 2406 WAIT_CIP(regs); 2407 newlun &= SBIC_TLUN_MASK; 2408 CSR_TRACE('r',csr,asr,newtarget); 2409 } else { 2410 /* Need to get IFY message */ 2411 for (newlun = 256; newlun; --newlun) { 2412 GET_SBIC_asr(regs, asr); 2413 if (asr & SBIC_ASR_INT) 2414 break; 2415 delay(1); 2416 } 2417 newlun = 0; /* XXXX */ 2418 if ((asr & SBIC_ASR_INT) == 0) { 2419 #ifdef DEBUG 2420 if (reselect_debug) 2421 printf("RSLT_NI - no IFFY message? asr %x\n", asr); 2422 #endif 2423 } else { 2424 GET_SBIC_csr(regs,csr); 2425 CSR_TRACE('n',csr,asr,newtarget); 2426 if (csr == (SBIC_CSR_MIS | MESG_IN_PHASE) || 2427 csr == (SBIC_CSR_MIS_1 | MESG_IN_PHASE) || 2428 csr == (SBIC_CSR_MIS_2 | MESG_IN_PHASE)) { 2429 sbicmsgin(dev); 2430 newlun = dev->sc_msg[0] & 7; 2431 } else { 2432 printf("RSLT_NI - not MESG_IN_PHASE %x\n", 2433 csr); 2434 } 2435 } 2436 } 2437 #ifdef DEBUG 2438 if(reselect_debug>1 || (reselect_debug && csr==SBIC_CSR_RSLT_NI)) 2439 printf("sbicnext: reselect %s from targ %d lun %d\n", 2440 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", 2441 newtarget, newlun); 2442 #endif 2443 if (dev->sc_nexus) { 2444 #ifdef DEBUG 2445 if (reselect_debug > 1) 2446 printf("%s: reselect %s with active command\n", 2447 dev->sc_dev.dv_xname, 2448 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY"); 2449 #ifdef DDB 2450 /* Debugger();*/ 2451 #endif 2452 #endif 2453 TAILQ_INSERT_HEAD(&dev->ready_list, dev->sc_nexus, chain); 2454 dev->sc_tinfo[dev->target].lubusy &= ~(1 << dev->lun); 2455 dev->sc_nexus = NULL; 2456 dev->sc_xs = NULL; 2457 } 2458 /* Reload sync values for this target */ 2459 if (dev->sc_sync[newtarget].state == SYNC_DONE) 2460 SET_SBIC_syn(regs, SBIC_SYN (dev->sc_sync[newtarget].offset, 2461 dev->sc_sync[newtarget].period)); 2462 else 2463 SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period)); 2464 for (acb = dev->nexus_list.tqh_first; acb; 2465 acb = acb->chain.tqe_next) { 2466 if (acb->xs->xs_periph->periph_target != newtarget || 2467 acb->xs->xs_periph->periph_lun != newlun) 2468 continue; 2469 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 2470 dev->sc_nexus = acb; 2471 dev->sc_xs = acb->xs; 2472 dev->sc_flags |= SBICF_SELECTED; 2473 dev->target = newtarget; 2474 dev->lun = newlun; 2475 break; 2476 } 2477 if (acb == NULL) { 2478 printf("%s: reselect %s targ %d not in nexus_list %p\n", 2479 dev->sc_dev.dv_xname, 2480 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", newtarget, 2481 &dev->nexus_list.tqh_first); 2482 panic("bad reselect in sbic"); 2483 } 2484 if (csr == SBIC_CSR_RSLT_IFY) 2485 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2486 break; 2487 2488 default: 2489 abort: 2490 /* 2491 * Something unexpected happened -- deal with it. 2492 */ 2493 printf("sbicnextstate: aborting csr %02x asr %02x\n", csr, asr); 2494 #ifdef DDB 2495 Debugger(); 2496 #endif 2497 #ifdef DEBUG 2498 if( data_pointer_debug > 1 ) 2499 printf("next dmastop: %d(%p:%lx)\n", 2500 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 2501 dev->sc_dmatimo = 0; 2502 #endif 2503 dev->sc_dmastop(dev); 2504 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2505 sbicerror(dev, regs, csr); 2506 sbicabort(dev, regs, "next"); 2507 if (dev->sc_flags & SBICF_INDMA) { 2508 /* 2509 * check for overlapping cache line, flush if so 2510 */ 2511 #if defined(M68040) || defined(M68060) 2512 if (dev->sc_flags & SBICF_DCFLUSH) { 2513 #if 0 2514 printf("sbic: 68040/060 DMA cache flush needs" 2515 "fixing? %x:%x\n", 2516 dev->sc_xs->data, dev->sc_xs->datalen); 2517 #endif 2518 } 2519 #endif 2520 dev->sc_flags &= 2521 ~(SBICF_INDMA | SBICF_DCFLUSH); 2522 #ifdef DEBUG 2523 if( data_pointer_debug > 1 ) 2524 printf("next dmastop: %d(%p:%lx)\n", 2525 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 2526 dev->sc_dmatimo = 0; 2527 #endif 2528 dev->sc_dmastop(dev); 2529 sbic_scsidone(acb, -1); 2530 } 2531 SBIC_TRACE(dev); 2532 return SBIC_STATE_ERROR; 2533 } 2534 2535 SBIC_TRACE(dev); 2536 return(SBIC_STATE_RUNNING); 2537 } 2538 2539 2540 /* 2541 * Check if DMA can not be used with specified buffer 2542 */ 2543 2544 int 2545 sbiccheckdmap(void *bp, u_long len, u_long mask) 2546 { 2547 u_char *buffer; 2548 u_long phy_buf; 2549 u_long phy_len; 2550 2551 buffer = bp; 2552 2553 if (len == 0) 2554 return(0); 2555 2556 while (len) { 2557 phy_buf = kvtop(buffer); 2558 if (len < (phy_len = PAGE_SIZE - ((int) buffer & PGOFSET))) 2559 phy_len = len; 2560 if (phy_buf & mask) 2561 return(1); 2562 buffer += phy_len; 2563 len -= phy_len; 2564 } 2565 return(0); 2566 } 2567 2568 int 2569 sbictoscsiperiod(struct sbic_softc *dev, sbic_regmap_t regs, int a) 2570 { 2571 unsigned int fs; 2572 2573 /* 2574 * cycle = DIV / (2*CLK) 2575 * DIV = FS+2 2576 * best we can do is 200ns at 20 MHz, 2 cycles 2577 */ 2578 2579 GET_SBIC_myid(regs,fs); 2580 fs = (fs >>6) + 2; /* DIV */ 2581 fs = (fs * 10000) / (dev->sc_clkfreq<<1); /* Cycle, in ns */ 2582 if (a < 2) a = 8; /* map to Cycles */ 2583 return ((fs*a)>>2); /* in 4 ns units */ 2584 } 2585 2586 int 2587 sbicfromscsiperiod(struct sbic_softc *dev, sbic_regmap_t regs, int p) 2588 { 2589 register unsigned int fs, ret; 2590 2591 /* Just the inverse of the above */ 2592 2593 GET_SBIC_myid(regs,fs); 2594 fs = (fs >>6) + 2; /* DIV */ 2595 fs = (fs * 10000) / (dev->sc_clkfreq<<1); /* Cycle, in ns */ 2596 2597 ret = p << 2; /* in ns units */ 2598 ret = ret / fs; /* in Cycles */ 2599 if (ret < sbic_min_period) 2600 return(sbic_min_period); 2601 2602 /* verify rounding */ 2603 if (sbictoscsiperiod(dev, regs, ret) < p) 2604 ret++; 2605 return (ret >= 8) ? 0 : ret; 2606 } 2607 2608 #ifdef DEBUG 2609 2610 void 2611 sbicdumpstate(void) 2612 { 2613 u_char csr, asr; 2614 2615 GET_SBIC_asr(debug_sbic_regs,asr); 2616 GET_SBIC_csr(debug_sbic_regs,csr); 2617 printf("%s: asr:csr(%02x:%02x)->(%02x:%02x)\n", 2618 (routine==1)?"sbicgo": 2619 (routine==2)?"sbicintr": 2620 (routine==3)?"sbicicmd": 2621 (routine==4)?"sbicnext":"unknown", 2622 debug_asr, debug_csr, asr, csr); 2623 2624 } 2625 2626 void 2627 sbictimeout(struct sbic_softc *dev) 2628 { 2629 int s, asr; 2630 2631 s = splbio(); 2632 if (dev->sc_dmatimo) { 2633 if (dev->sc_dmatimo > 1) { 2634 printf("%s: DMA timeout #%d\n", 2635 dev->sc_dev.dv_xname, dev->sc_dmatimo - 1); 2636 GET_SBIC_asr(dev->sc_sbic, asr); 2637 if( asr & SBIC_ASR_INT ) { 2638 /* We need to service a missed IRQ */ 2639 printf("Servicing a missed int:(%02x,%02x)->(%02x,?)\n", 2640 debug_asr, debug_csr, asr); 2641 sbicintr(dev); 2642 } 2643 sbicdumpstate(); 2644 } 2645 dev->sc_dmatimo++; 2646 } 2647 splx(s); 2648 callout_reset(&dev->sc_timo_ch, 30 * hz, 2649 (void *)sbictimeout, dev); 2650 } 2651 2652 void 2653 sbic_dump_acb(struct sbic_acb *acb) 2654 { 2655 u_char *b = (u_char *) &acb->cmd; 2656 int i; 2657 2658 printf("acb@%p ", acb); 2659 if (acb->xs == NULL) { 2660 printf("<unused>\n"); 2661 return; 2662 } 2663 printf("(%d:%d) flags %2x clen %2d cmd ", 2664 acb->xs->xs_periph->periph_target, 2665 acb->xs->xs_periph->periph_lun, acb->flags, acb->clen); 2666 for (i = acb->clen; i; --i) 2667 printf(" %02x", *b++); 2668 printf("\n"); 2669 printf(" xs: %8p data %8p:%04x ", acb->xs, acb->xs->data, 2670 acb->xs->datalen); 2671 printf("va %8p:%04x ", acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 2672 printf("pa %8p:%04x tcnt %lx\n", acb->sc_pa.dc_addr, acb->sc_pa.dc_count, 2673 acb->sc_tcnt); 2674 } 2675 2676 void 2677 sbic_dump(struct sbic_softc *dev) 2678 { 2679 sbic_regmap_t regs; 2680 u_char csr, asr; 2681 struct sbic_acb *acb; 2682 int s; 2683 int i; 2684 2685 s = splbio(); 2686 regs = dev->sc_sbic; 2687 #if CSR_TRACE_SIZE 2688 printf("csr trace: "); 2689 i = csr_traceptr; 2690 do { 2691 printf("%c%02x%02x%02x ", csr_trace[i].whr, 2692 csr_trace[i].csr, csr_trace[i].asr, csr_trace[i].xtn); 2693 switch(csr_trace[i].whr) { 2694 case 'g': 2695 printf("go "); break; 2696 case 's': 2697 printf("select "); break; 2698 case 'y': 2699 printf("select+ "); break; 2700 case 'i': 2701 printf("intr "); break; 2702 case 'f': 2703 printf("finish "); break; 2704 case '>': 2705 printf("out "); break; 2706 case '<': 2707 printf("in "); break; 2708 case 'm': 2709 printf("msgin "); break; 2710 case 'x': 2711 printf("msginx "); break; 2712 case 'X': 2713 printf("msginX "); break; 2714 case 'r': 2715 printf("reselect "); break; 2716 case 'I': 2717 printf("icmd "); break; 2718 case 'a': 2719 printf("abort "); break; 2720 default: 2721 printf("? "); 2722 } 2723 switch(csr_trace[i].csr) { 2724 case 0x11: 2725 printf("INITIATOR"); break; 2726 case 0x16: 2727 printf("S_XFERRED"); break; 2728 case 0x20: 2729 printf("MSGIN_ACK"); break; 2730 case 0x41: 2731 printf("DISC"); break; 2732 case 0x42: 2733 printf("SEL_TIMEO"); break; 2734 case 0x80: 2735 printf("RSLT_NI"); break; 2736 case 0x81: 2737 printf("RSLT_IFY"); break; 2738 case 0x85: 2739 printf("DISC_1"); break; 2740 case 0x18: case 0x19: case 0x1a: 2741 case 0x1b: case 0x1e: case 0x1f: 2742 case 0x28: case 0x29: case 0x2a: 2743 case 0x2b: case 0x2e: case 0x2f: 2744 case 0x48: case 0x49: case 0x4a: 2745 case 0x4b: case 0x4e: case 0x4f: 2746 case 0x88: case 0x89: case 0x8a: 2747 case 0x8b: case 0x8e: case 0x8f: 2748 switch(csr_trace[i].csr & 0xf0) { 2749 case 0x10: 2750 printf("DONE_"); break; 2751 case 0x20: 2752 printf("STOP_"); break; 2753 case 0x40: 2754 printf("ERR_"); break; 2755 case 0x80: 2756 printf("REQ_"); break; 2757 } 2758 switch(csr_trace[i].csr & 7) { 2759 case 0: 2760 printf("DATA_OUT"); break; 2761 case 1: 2762 printf("DATA_IN"); break; 2763 case 2: 2764 printf("CMD"); break; 2765 case 3: 2766 printf("STATUS"); break; 2767 case 6: 2768 printf("MSG_OUT"); break; 2769 case 7: 2770 printf("MSG_IN"); break; 2771 default: 2772 printf("invld phs"); 2773 } 2774 break; 2775 default: printf("****"); break; 2776 } 2777 if (csr_trace[i].asr & SBIC_ASR_INT) 2778 printf(" ASR_INT"); 2779 if (csr_trace[i].asr & SBIC_ASR_LCI) 2780 printf(" ASR_LCI"); 2781 if (csr_trace[i].asr & SBIC_ASR_BSY) 2782 printf(" ASR_BSY"); 2783 if (csr_trace[i].asr & SBIC_ASR_CIP) 2784 printf(" ASR_CIP"); 2785 printf("\n"); 2786 i = (i + 1) & (CSR_TRACE_SIZE - 1); 2787 } while (i != csr_traceptr); 2788 #endif 2789 GET_SBIC_asr(regs, asr); 2790 if ((asr & SBIC_ASR_INT) == 0) 2791 GET_SBIC_csr(regs, csr); 2792 else 2793 csr = 0; 2794 printf("%s@%p regs %p/%p asr %x csr %x\n", dev->sc_dev.dv_xname, 2795 dev, regs.sbic_asr_p, regs.sbic_value_p, asr, csr); 2796 if ((acb = dev->free_list.tqh_first)) { 2797 printf("Free list:\n"); 2798 while (acb) { 2799 sbic_dump_acb(acb); 2800 acb = acb->chain.tqe_next; 2801 } 2802 } 2803 if ((acb = dev->ready_list.tqh_first)) { 2804 printf("Ready list:\n"); 2805 while (acb) { 2806 sbic_dump_acb(acb); 2807 acb = acb->chain.tqe_next; 2808 } 2809 } 2810 if ((acb = dev->nexus_list.tqh_first)) { 2811 printf("Nexus list:\n"); 2812 while (acb) { 2813 sbic_dump_acb(acb); 2814 acb = acb->chain.tqe_next; 2815 } 2816 } 2817 if (dev->sc_nexus) { 2818 printf("nexus:\n"); 2819 sbic_dump_acb(dev->sc_nexus); 2820 } 2821 printf("sc_xs %p targ %d lun %d flags %x tcnt %lx dmacmd %x mask %lx\n", 2822 dev->sc_xs, dev->target, dev->lun, dev->sc_flags, dev->sc_tcnt, 2823 dev->sc_dmacmd, dev->sc_dmamask); 2824 for (i = 0; i < 8; ++i) { 2825 if (dev->sc_tinfo[i].cmds > 2) { 2826 printf("tgt %d: cmds %d disc %d lubusy %x\n", 2827 i, dev->sc_tinfo[i].cmds, 2828 dev->sc_tinfo[i].dconns, 2829 dev->sc_tinfo[i].lubusy); 2830 } 2831 } 2832 splx(s); 2833 } 2834 2835 #endif 2836
Indexes created Thu Oct 02 14:10:14 GMT 2025