sbic.c revision 1.66.2.2
1 /* $NetBSD: sbic.c,v 1.66.2.2 2010/10/22 07:21:00 uebayasi Exp $ */ 2 3 /* 4 * Copyright (c) 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Van Jacobson of Lawrence Berkeley Laboratory. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)scsi.c 7.5 (Berkeley) 5/4/91 35 */ 36 37 /* 38 * Copyright (c) 1994 Christian E. Hopps 39 * 40 * This code is derived from software contributed to Berkeley by 41 * Van Jacobson of Lawrence Berkeley Laboratory. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed by the University of 54 * California, Berkeley and its contributors. 55 * 4. Neither the name of the University nor the names of its contributors 56 * may be used to endorse or promote products derived from this software 57 * without specific prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 61 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 62 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 63 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 64 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 65 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 67 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 68 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 69 * SUCH DAMAGE. 70 * 71 * @(#)scsi.c 7.5 (Berkeley) 5/4/91 72 */ 73 74 /* 75 * AMIGA AMD 33C93 scsi adaptor driver 76 */ 77 78 #include "opt_ddb.h" 79 #ifdef __m68k__ 80 #include "opt_m68k_arch.h" 81 #endif 82 83 #include <sys/cdefs.h> 84 __KERNEL_RCSID(0, "$NetBSD: sbic.c,v 1.66.2.2 2010/10/22 07:21:00 uebayasi Exp $"); 85 86 #include <sys/param.h> 87 #include <sys/systm.h> 88 #include <sys/device.h> 89 #include <sys/kernel.h> /* For hz */ 90 #include <sys/disklabel.h> 91 #include <sys/buf.h> 92 #include <dev/scsipi/scsi_all.h> 93 #include <dev/scsipi/scsipi_all.h> 94 #include <dev/scsipi/scsiconf.h> 95 #include <uvm/uvm_extern.h> 96 #include <machine/cpu.h> 97 #include <amiga/amiga/device.h> 98 #include <amiga/amiga/custom.h> 99 #include <amiga/amiga/isr.h> 100 #include <amiga/dev/dmavar.h> 101 #include <amiga/dev/sbicreg.h> 102 #include <amiga/dev/sbicvar.h> 103 104 /* These are for bounce buffers */ 105 #include <amiga/amiga/cc.h> 106 #include <amiga/dev/zbusvar.h> 107 108 /* Since I can't find this in any other header files */ 109 #define SCSI_PHASE(reg) (reg&0x07) 110 111 /* 112 * SCSI delays 113 * In u-seconds, primarily for state changes on the SPC. 114 */ 115 #define SBIC_CMD_WAIT 50000 /* wait per step of 'immediate' cmds */ 116 #define SBIC_DATA_WAIT 50000 /* wait per data in/out step */ 117 #define SBIC_INIT_WAIT 50000 /* wait per step (both) during init */ 118 119 #define SBIC_WAIT(regs, until, timeo) sbicwait(regs, until, timeo, __LINE__) 120 121 int sbicicmd(struct sbic_softc *, int, int, void *, int, void *, int); 122 int sbicgo(struct sbic_softc *, struct scsipi_xfer *); 123 int sbicdmaok(struct sbic_softc *, struct scsipi_xfer *); 124 int sbicwait(sbic_regmap_t, char, int , int); 125 int sbiccheckdmap(void *, u_long, u_long); 126 int sbicselectbus(struct sbic_softc *, sbic_regmap_t, u_char, u_char, u_char); 127 int sbicxfstart(sbic_regmap_t, int, u_char, int); 128 int sbicxfout(sbic_regmap_t regs, int, void *, int); 129 int sbicfromscsiperiod(struct sbic_softc *, sbic_regmap_t, int); 130 int sbictoscsiperiod(struct sbic_softc *, sbic_regmap_t, int); 131 int sbicpoll(struct sbic_softc *); 132 int sbicnextstate(struct sbic_softc *, u_char, u_char); 133 int sbicmsgin(struct sbic_softc *); 134 int sbicxfin(sbic_regmap_t regs, int, void *); 135 int sbicabort(struct sbic_softc *, sbic_regmap_t, const char *); 136 void sbicxfdone(struct sbic_softc *, sbic_regmap_t, int); 137 void sbicerror(struct sbic_softc *, sbic_regmap_t, u_char); 138 void sbicstart(struct sbic_softc *); 139 void sbicreset(struct sbic_softc *); 140 void sbic_scsidone(struct sbic_acb *, int); 141 void sbic_sched(struct sbic_softc *); 142 void sbic_save_ptrs(struct sbic_softc *, sbic_regmap_t,int,int); 143 void sbic_load_ptrs(struct sbic_softc *, sbic_regmap_t,int,int); 144 #ifdef DEBUG 145 void sbicdumpstate(void); 146 void sbic_dump_acb(struct sbic_acb *); 147 #endif 148 149 /* 150 * Synch xfer parameters, and timing conversions 151 */ 152 int sbic_min_period = SBIC_SYN_MIN_PERIOD; /* in cycles = f(ICLK,FSn) */ 153 int sbic_max_offset = SBIC_SYN_MAX_OFFSET; /* pure number */ 154 155 int sbic_cmd_wait = SBIC_CMD_WAIT; 156 int sbic_data_wait = SBIC_DATA_WAIT; 157 int sbic_init_wait = SBIC_INIT_WAIT; 158 159 /* 160 * was broken before.. now if you want this you get it for all drives 161 * on sbic controllers. 162 */ 163 u_char sbic_inhibit_sync[8]; 164 int sbic_enable_reselect = 1; 165 int sbic_clock_override = 0; 166 int sbic_no_dma = 0; 167 int sbic_parallel_operations = 1; 168 169 #ifdef DEBUG 170 sbic_regmap_t debug_sbic_regs; 171 int sbicdma_ops = 0; /* total DMA operations */ 172 int sbicdma_bounces = 0; /* number operations using bounce buffer */ 173 int sbicdma_hits = 0; /* number of DMA chains that were contiguous */ 174 int sbicdma_misses = 0; /* number of DMA chains that were not contiguous */ 175 int sbicdma_saves = 0; 176 #define QPRINTF(a) if (sbic_debug > 1) printf a 177 int sbic_debug = 0; 178 int sync_debug = 0; 179 int sbic_dma_debug = 0; 180 int reselect_debug = 0; 181 int data_pointer_debug = 0; 182 u_char debug_asr, debug_csr, routine; 183 void sbictimeout(struct sbic_softc *dev); 184 185 #define CSR_TRACE_SIZE 32 186 #if CSR_TRACE_SIZE 187 #define CSR_TRACE(w,c,a,x) do { \ 188 int s_csr_trace = splbio(); \ 189 csr_trace[csr_traceptr].whr = (w); csr_trace[csr_traceptr].csr = (c); \ 190 csr_trace[csr_traceptr].asr = (a); csr_trace[csr_traceptr].xtn = (x); \ 191 dma_cachectl((void *)&csr_trace[csr_traceptr], sizeof(csr_trace[0])); \ 192 csr_traceptr = (csr_traceptr + 1) & (CSR_TRACE_SIZE - 1); \ 193 /* dma_cachectl((void *)&csr_traceptr, sizeof(csr_traceptr));*/ \ 194 splx(s_csr_trace); \ 195 } while (0) 196 int csr_traceptr; 197 int csr_tracesize = CSR_TRACE_SIZE; 198 struct { 199 u_char whr; 200 u_char csr; 201 u_char asr; 202 u_char xtn; 203 } csr_trace[CSR_TRACE_SIZE]; 204 #else 205 #define CSR_TRACE(w,c,a,x) 206 #endif 207 208 #define SBIC_TRACE_SIZE 0 209 #if SBIC_TRACE_SIZE 210 #define SBIC_TRACE(dev) do { \ 211 int s = splbio(); \ 212 sbic_trace[sbic_traceptr].sp = &s; \ 213 sbic_trace[sbic_traceptr].line = __LINE__; \ 214 sbic_trace[sbic_traceptr].sr = s; \ 215 sbic_trace[sbic_traceptr].csr = csr_traceptr; \ 216 dma_cachectl(&sbic_trace[sbic_traceptr], sizeof(sbic_trace[0])); \ 217 sbic_traceptr = (sbic_traceptr + 1) & (SBIC_TRACE_SIZE - 1); \ 218 dma_cachectl(&sbic_traceptr, sizeof(sbic_traceptr)); \ 219 if (dev) dma_cachectl(dev, sizeof(*dev)); \ 220 splx(s); \ 221 } while (0) 222 int sbic_traceptr; 223 int sbic_tracesize = SBIC_TRACE_SIZE; 224 struct { 225 void *sp; 226 u_short line; 227 u_short sr; 228 int csr; 229 } sbic_trace[SBIC_TRACE_SIZE]; 230 #else 231 #define SBIC_TRACE(dev) 232 #endif 233 234 #else /* DEBUG */ 235 #define QPRINTF(a) 236 #define CSR_TRACE(w,c,a,x) 237 #define SBIC_TRACE(dev) 238 #endif /* DEBUG */ 239 240 /* 241 * default minphys routine for sbic based controllers 242 */ 243 void 244 sbic_minphys(struct buf *bp) 245 { 246 247 /* 248 * No max transfer at this level. 249 */ 250 minphys(bp); 251 } 252 253 /* 254 * Save DMA pointers. Take into account partial transfer. Shut down DMA. 255 */ 256 void 257 sbic_save_ptrs(struct sbic_softc *dev, sbic_regmap_t regs, int target, int lun) 258 { 259 int count, asr, s; 260 struct sbic_acb* acb; 261 262 SBIC_TRACE(dev); 263 if( !dev->sc_cur ) return; 264 if( !(dev->sc_flags & SBICF_INDMA) ) return; /* DMA not active */ 265 266 s = splbio(); 267 268 acb = dev->sc_nexus; 269 count = -1; 270 do { 271 GET_SBIC_asr(regs, asr); 272 if( asr & SBIC_ASR_DBR ) { 273 printf("sbic_save_ptrs: asr %02x canceled!\n", asr); 274 splx(s); 275 SBIC_TRACE(dev); 276 return; 277 } 278 } while( asr & (SBIC_ASR_BSY|SBIC_ASR_CIP) ); 279 280 /* Save important state */ 281 /* must be done before dmastop */ 282 acb->sc_dmacmd = dev->sc_dmacmd; 283 SBIC_TC_GET(regs, count); 284 285 /* Shut down DMA ====CAREFUL==== */ 286 dev->sc_dmastop(dev); 287 dev->sc_flags &= ~SBICF_INDMA; 288 SBIC_TC_PUT(regs, 0); 289 290 #ifdef DEBUG 291 if(!count && sbic_debug) printf("%dcount0",target); 292 if(data_pointer_debug == -1) 293 printf("SBIC saving target %d data pointers from (%p,%x)%xASR:%02x", 294 target, dev->sc_cur->dc_addr, dev->sc_cur->dc_count, 295 acb->sc_dmacmd, asr); 296 #endif 297 298 /* Fixup partial xfers */ 299 acb->sc_kv.dc_addr += (dev->sc_tcnt - count); 300 acb->sc_kv.dc_count -= (dev->sc_tcnt - count); 301 acb->sc_pa.dc_addr += (dev->sc_tcnt - count); 302 acb->sc_pa.dc_count -= ((dev->sc_tcnt - count)>>1); 303 304 acb->sc_tcnt = dev->sc_tcnt = count; 305 #ifdef DEBUG 306 if(data_pointer_debug) 307 printf(" at (%p,%x):%x\n", 308 dev->sc_cur->dc_addr, dev->sc_cur->dc_count,count); 309 sbicdma_saves++; 310 #endif 311 splx(s); 312 SBIC_TRACE(dev); 313 } 314 315 316 /* 317 * DOES NOT RESTART DMA!!! 318 */ 319 void 320 sbic_load_ptrs(struct sbic_softc *dev, sbic_regmap_t regs, int target, int lun) 321 { 322 int s, count; 323 char* vaddr, * paddr; 324 struct sbic_acb *acb; 325 326 SBIC_TRACE(dev); 327 acb = dev->sc_nexus; 328 if( !acb->sc_kv.dc_count ) { 329 /* No data to xfer */ 330 SBIC_TRACE(dev); 331 return; 332 } 333 334 s = splbio(); 335 336 dev->sc_last = dev->sc_cur = &acb->sc_pa; 337 dev->sc_tcnt = acb->sc_tcnt; 338 dev->sc_dmacmd = acb->sc_dmacmd; 339 340 #ifdef DEBUG 341 sbicdma_ops++; 342 #endif 343 if( !dev->sc_tcnt ) { 344 /* sc_tcnt == 0 implies end of segment */ 345 346 /* do kvm to pa mappings */ 347 paddr = acb->sc_pa.dc_addr = 348 (char *) kvtop(acb->sc_kv.dc_addr); 349 350 vaddr = acb->sc_kv.dc_addr; 351 count = acb->sc_kv.dc_count; 352 for(count = (PAGE_SIZE - ((int)vaddr & PGOFSET)); 353 count < acb->sc_kv.dc_count 354 && (char*)kvtop(vaddr + count + 4) == paddr + count + 4; 355 count += PAGE_SIZE); 356 /* If it's all contiguous... */ 357 if(count > acb->sc_kv.dc_count ) { 358 count = acb->sc_kv.dc_count; 359 #ifdef DEBUG 360 sbicdma_hits++; 361 #endif 362 } else { 363 #ifdef DEBUG 364 sbicdma_misses++; 365 #endif 366 } 367 acb->sc_tcnt = count; 368 acb->sc_pa.dc_count = count >> 1; 369 370 #ifdef DEBUG 371 if(data_pointer_debug) 372 printf("DMA recalc:kv(%p,%x)pa(%p,%lx)\n", 373 acb->sc_kv.dc_addr, 374 acb->sc_kv.dc_count, 375 acb->sc_pa.dc_addr, 376 acb->sc_tcnt); 377 #endif 378 } 379 splx(s); 380 #ifdef DEBUG 381 if(data_pointer_debug) 382 printf("SBIC restoring target %d data pointers at (%p,%x)%x\n", 383 target, dev->sc_cur->dc_addr, dev->sc_cur->dc_count, 384 dev->sc_dmacmd); 385 #endif 386 SBIC_TRACE(dev); 387 } 388 389 /* 390 * used by specific sbic controller 391 * 392 * it appears that the higher level code does nothing with LUN's 393 * so I will too. I could plug it in, however so could they 394 * in scsi_scsipi_cmd(). 395 */ 396 void 397 sbic_scsipi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req, 398 void *arg) 399 { 400 struct scsipi_xfer *xs; 401 struct scsipi_periph *periph; 402 struct sbic_acb *acb; 403 struct sbic_softc *dev = (void *)chan->chan_adapter->adapt_dev; 404 int flags, s, stat; 405 406 switch (req) { 407 case ADAPTER_REQ_RUN_XFER: 408 xs = arg; 409 periph = xs->xs_periph; 410 411 SBIC_TRACE(dev); 412 flags = xs->xs_control; 413 414 if (flags & XS_CTL_DATA_UIO) 415 panic("sbic: scsi data uio requested"); 416 417 if (dev->sc_nexus && flags & XS_CTL_POLL) 418 panic("sbic_scsipi_request: busy"); 419 420 s = splbio(); 421 acb = dev->free_list.tqh_first; 422 if (acb) 423 TAILQ_REMOVE(&dev->free_list, acb, chain); 424 splx(s); 425 426 #ifdef DIAGNOSTIC 427 if (acb == NULL) { 428 scsipi_printaddr(periph); 429 printf("unable to allocate acb\n"); 430 panic("sbic_scsipi_request"); 431 } 432 #endif 433 acb->flags = ACB_ACTIVE; 434 if (flags & XS_CTL_DATA_IN) 435 acb->flags |= ACB_DATAIN; 436 acb->xs = xs; 437 memcpy(&acb->cmd, xs->cmd, xs->cmdlen); 438 acb->clen = xs->cmdlen; 439 acb->sc_kv.dc_addr = xs->data; 440 acb->sc_kv.dc_count = xs->datalen; 441 acb->pa_addr = xs->data ? (char *)kvtop(xs->data) : 0; /* XXXX check */ 442 443 if (flags & XS_CTL_POLL) { 444 s = splbio(); 445 /* 446 * This has major side effects - it locks up the machine 447 */ 448 449 dev->sc_flags |= SBICF_ICMD; 450 do { 451 while(dev->sc_nexus) 452 sbicpoll(dev); 453 dev->sc_nexus = acb; 454 dev->sc_stat[0] = -1; 455 dev->sc_xs = xs; 456 dev->target = periph->periph_target; 457 dev->lun = periph->periph_lun; 458 stat = sbicicmd(dev, dev->target, dev->lun, 459 &acb->cmd, acb->clen, 460 acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 461 } while (dev->sc_nexus != acb); 462 sbic_scsidone(acb, stat); 463 464 splx(s); 465 SBIC_TRACE(dev); 466 return; 467 } 468 469 s = splbio(); 470 TAILQ_INSERT_TAIL(&dev->ready_list, acb, chain); 471 472 if (dev->sc_nexus) { 473 splx(s); 474 SBIC_TRACE(dev); 475 return; 476 } 477 478 /* 479 * nothing is active, try to start it now. 480 */ 481 sbic_sched(dev); 482 splx(s); 483 484 SBIC_TRACE(dev); 485 /* TODO: add sbic_poll to do XS_CTL_POLL operations */ 486 #if 0 487 if (flags & XS_CTL_POLL) 488 return(COMPLETE); 489 #endif 490 return; 491 492 case ADAPTER_REQ_GROW_RESOURCES: 493 return; 494 495 case ADAPTER_REQ_SET_XFER_MODE: 496 return; 497 } 498 } 499 500 /* 501 * attempt to start the next available command 502 */ 503 void 504 sbic_sched(struct sbic_softc *dev) 505 { 506 struct scsipi_xfer *xs; 507 struct scsipi_periph *periph; 508 struct sbic_acb *acb; 509 int flags, /*phase,*/ stat, i; 510 511 SBIC_TRACE(dev); 512 if (dev->sc_nexus) 513 return; /* a command is current active */ 514 515 SBIC_TRACE(dev); 516 for (acb = dev->ready_list.tqh_first; acb; acb = acb->chain.tqe_next) { 517 periph = acb->xs->xs_periph; 518 i = periph->periph_target; 519 if (!(dev->sc_tinfo[i].lubusy & (1 << periph->periph_lun))) { 520 struct sbic_tinfo *ti = &dev->sc_tinfo[i]; 521 522 TAILQ_REMOVE(&dev->ready_list, acb, chain); 523 dev->sc_nexus = acb; 524 ti = &dev->sc_tinfo[periph->periph_target]; 525 ti->lubusy |= (1 << periph->periph_lun); 526 acb->sc_pa.dc_addr = acb->pa_addr; /* XXXX check */ 527 break; 528 } 529 } 530 531 SBIC_TRACE(dev); 532 if (acb == NULL) 533 return; /* did not find an available command */ 534 535 dev->sc_xs = xs = acb->xs; 536 periph = xs->xs_periph; 537 flags = xs->xs_control; 538 539 if (flags & XS_CTL_RESET) 540 sbicreset(dev); 541 542 #ifdef DEBUG 543 if( data_pointer_debug > 1 ) 544 printf("sbic_sched(%d,%d)\n", periph->periph_target, 545 periph->periph_lun); 546 #endif 547 dev->sc_stat[0] = -1; 548 dev->target = periph->periph_target; 549 dev->lun = periph->periph_lun; 550 if ( flags & XS_CTL_POLL || ( !sbic_parallel_operations 551 && (sbicdmaok(dev, xs) == 0))) 552 stat = sbicicmd(dev, periph->periph_target, 553 periph->periph_lun, &acb->cmd, 554 acb->clen, acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 555 else if (sbicgo(dev, xs) == 0 && xs->error != XS_SELTIMEOUT) { 556 SBIC_TRACE(dev); 557 return; 558 } else 559 stat = dev->sc_stat[0]; 560 561 sbic_scsidone(acb, stat); 562 SBIC_TRACE(dev); 563 } 564 565 void 566 sbic_scsidone(struct sbic_acb *acb, int stat) 567 { 568 struct scsipi_xfer *xs; 569 struct scsipi_periph *periph; 570 struct sbic_softc *dev; 571 int dosched = 0; 572 573 xs = acb->xs; 574 periph = xs->xs_periph; 575 dev = (void *)periph->periph_channel->chan_adapter->adapt_dev; 576 SBIC_TRACE(dev); 577 #ifdef DIAGNOSTIC 578 if (acb == NULL || xs == NULL) { 579 printf("sbic_scsidone -- (%d,%d) no scsi_xfer\n", 580 dev->target, dev->lun); 581 #ifdef DDB 582 Debugger(); 583 #endif 584 return; 585 } 586 #endif 587 588 xs->status = stat; 589 xs->resid = 0; /* XXXX */ 590 #ifdef DEBUG 591 if( data_pointer_debug > 1 ) 592 printf("scsidone: (%d,%d)->(%d,%d)%02x\n", 593 periph->periph_target, periph->periph_lun, 594 dev->target, dev->lun, stat); 595 if( periph->periph_target == 596 periph->periph_channel->chan_id) 597 panic("target == hostid"); 598 #endif 599 600 if (xs->error == XS_NOERROR) { 601 if (stat == SCSI_CHECK || stat == SCSI_BUSY) 602 xs->error = XS_BUSY; 603 } 604 605 /* 606 * Remove the ACB from whatever queue it's on. We have to do a bit of 607 * a hack to figure out which queue it's on. Note that it is *not* 608 * necessary to cdr down the ready queue, but we must cdr down the 609 * nexus queue and see if it's there, so we can mark the unit as no 610 * longer busy. This code is sickening, but it works. 611 */ 612 if (acb == dev->sc_nexus) { 613 dev->sc_nexus = NULL; 614 dev->sc_xs = NULL; 615 dev->sc_tinfo[periph->periph_target].lubusy &= 616 ~(1<<periph->periph_lun); 617 if (dev->ready_list.tqh_first) 618 dosched = 1; /* start next command */ 619 } else if (dev->ready_list.tqh_last == &acb->chain.tqe_next) { 620 TAILQ_REMOVE(&dev->ready_list, acb, chain); 621 } else { 622 register struct sbic_acb *acb2; 623 for (acb2 = dev->nexus_list.tqh_first; acb2; 624 acb2 = acb2->chain.tqe_next) { 625 if (acb2 == acb) { 626 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 627 dev->sc_tinfo[periph->periph_target].lubusy 628 &= ~(1<<periph->periph_lun); 629 break; 630 } 631 } 632 if (acb2) 633 ; 634 else if (acb->chain.tqe_next) { 635 TAILQ_REMOVE(&dev->ready_list, acb, chain); 636 } else { 637 printf("%s: can't find matching acb\n", 638 dev->sc_dev.dv_xname); 639 #ifdef DDB 640 Debugger(); 641 #endif 642 } 643 } 644 /* Put it on the free list. */ 645 acb->flags = ACB_FREE; 646 TAILQ_INSERT_HEAD(&dev->free_list, acb, chain); 647 648 dev->sc_tinfo[periph->periph_target].cmds++; 649 650 scsipi_done(xs); 651 652 if (dosched) 653 sbic_sched(dev); 654 SBIC_TRACE(dev); 655 } 656 657 int 658 sbicdmaok(struct sbic_softc *dev, struct scsipi_xfer *xs) 659 { 660 if (sbic_no_dma || !xs->datalen || xs->datalen & 0x1 || 661 (u_int)xs->data & 0x3) 662 return(0); 663 /* 664 * controller supports dma to any addresses? 665 */ 666 else if ((dev->sc_flags & SBICF_BADDMA) == 0) 667 return(1); 668 /* 669 * this address is ok for DMA? 670 */ 671 else if (sbiccheckdmap(xs->data, xs->datalen, dev->sc_dmamask) == 0) 672 return(1); 673 /* 674 * we have a bounce buffer? 675 */ 676 else if (dev->sc_tinfo[xs->xs_periph->periph_target].bounce) 677 return(1); 678 /* 679 * try to get one 680 */ 681 else if ((dev->sc_tinfo[xs->xs_periph->periph_target].bounce 682 = (char *)alloc_z2mem(MAXPHYS))) { 683 if (isztwomem(dev->sc_tinfo[xs->xs_periph->periph_target].bounce)) 684 printf("alloc ZII target %d bounce pa 0x%x\n", 685 xs->xs_periph->periph_target, 686 (unsigned)kvtop(dev->sc_tinfo[xs->xs_periph->periph_target].bounce)); 687 else if (dev->sc_tinfo[xs->xs_periph->periph_target].bounce) 688 printf("alloc CHIP target %d bounce pa %p\n", 689 xs->xs_periph->periph_target, 690 PREP_DMA_MEM(dev->sc_tinfo[xs->xs_periph->periph_target].bounce)); 691 return(1); 692 } 693 694 return(0); 695 } 696 697 698 int 699 sbicwait(sbic_regmap_t regs, char until, int timeo, int line) 700 { 701 u_char val; 702 int csr; 703 704 SBIC_TRACE((struct sbic_softc *)0); 705 if (timeo == 0) 706 timeo = 1000000; /* some large value.. */ 707 708 GET_SBIC_asr(regs,val); 709 while ((val & until) == 0) { 710 if (timeo-- == 0) { 711 GET_SBIC_csr(regs, csr); 712 printf("sbicwait TIMEO @%d with asr=x%x csr=x%x\n", 713 line, val, csr); 714 #if defined(DDB) && defined(DEBUG) 715 Debugger(); 716 #endif 717 return(val); /* Maybe I should abort */ 718 break; 719 } 720 DELAY(1); 721 GET_SBIC_asr(regs,val); 722 } 723 SBIC_TRACE((struct sbic_softc *)0); 724 return(val); 725 } 726 727 int 728 sbicabort(struct sbic_softc *dev, sbic_regmap_t regs, const char *where) 729 { 730 u_char csr, asr; 731 732 GET_SBIC_asr(regs, asr); 733 GET_SBIC_csr(regs, csr); 734 735 printf ("%s: abort %s: csr = 0x%02x, asr = 0x%02x\n", 736 dev->sc_dev.dv_xname, where, csr, asr); 737 738 739 #if 0 740 /* Clean up running command */ 741 if (dev->sc_nexus != NULL) { 742 dev->sc_nexus->xs->error = XS_DRIVER_STUFFUP; 743 sbic_scsidone(dev->sc_nexus, dev->sc_stat[0]); 744 } 745 while (acb = dev->nexus_list.tqh_first) { 746 acb->xs->error = XS_DRIVER_STUFFUP; 747 sbic_scsidone(acb, -1 /*acb->stat[0]*/); 748 } 749 #endif 750 751 /* Clean up chip itself */ 752 if (dev->sc_flags & SBICF_SELECTED) { 753 while( asr & SBIC_ASR_DBR ) { 754 /* sbic is jammed w/data. need to clear it */ 755 /* But we don't know what direction it needs to go */ 756 GET_SBIC_data(regs, asr); 757 printf("%s: abort %s: clearing data buffer 0x%02x\n", 758 dev->sc_dev.dv_xname, where, asr); 759 GET_SBIC_asr(regs, asr); 760 if( asr & SBIC_ASR_DBR ) /* Not the read direction, then */ 761 SET_SBIC_data(regs, asr); 762 GET_SBIC_asr(regs, asr); 763 } 764 WAIT_CIP(regs); 765 printf("%s: sbicabort - sending ABORT command\n", dev->sc_dev.dv_xname); 766 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 767 WAIT_CIP(regs); 768 769 GET_SBIC_asr(regs, asr); 770 if (asr & (SBIC_ASR_BSY|SBIC_ASR_LCI)) { 771 /* ok, get more drastic.. */ 772 773 printf("%s: sbicabort - asr %x, trying to reset\n", dev->sc_dev.dv_xname, asr); 774 sbicreset(dev); 775 dev->sc_flags &= ~SBICF_SELECTED; 776 return -1; 777 } 778 printf("%s: sbicabort - sending DISC command\n", dev->sc_dev.dv_xname); 779 SET_SBIC_cmd(regs, SBIC_CMD_DISC); 780 781 do { 782 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0); 783 GET_SBIC_csr (regs, csr); 784 CSR_TRACE('a',csr,asr,0); 785 } while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) 786 && (csr != SBIC_CSR_CMD_INVALID)); 787 788 /* lets just hope it worked.. */ 789 dev->sc_flags &= ~SBICF_SELECTED; 790 } 791 return -1; 792 } 793 794 795 /* 796 * Initialize driver-private structures 797 */ 798 799 void 800 sbicinit(struct sbic_softc *dev) 801 { 802 sbic_regmap_t regs; 803 u_int i; 804 struct sbic_acb *acb; 805 u_int inhibit_sync; 806 807 extern u_long scsi_nosync; 808 extern int shift_nosync; 809 810 regs = dev->sc_sbic; 811 812 if ((dev->sc_flags & SBICF_ALIVE) == 0) { 813 TAILQ_INIT(&dev->ready_list); 814 TAILQ_INIT(&dev->nexus_list); 815 TAILQ_INIT(&dev->free_list); 816 callout_init(&dev->sc_timo_ch, 0); 817 dev->sc_nexus = NULL; 818 dev->sc_xs = NULL; 819 acb = dev->sc_acb; 820 memset(acb, 0, sizeof(dev->sc_acb)); 821 for (i = 0; i < sizeof(dev->sc_acb) / sizeof(*acb); i++) { 822 TAILQ_INSERT_TAIL(&dev->free_list, acb, chain); 823 acb++; 824 } 825 memset(dev->sc_tinfo, 0, sizeof(dev->sc_tinfo)); 826 #ifdef DEBUG 827 /* make sure timeout is really not needed */ 828 callout_reset(&dev->sc_timo_ch, 30 * hz, 829 (void *)sbictimeout, dev); 830 #endif 831 832 } else panic("sbic: reinitializing driver!"); 833 834 dev->sc_flags |= SBICF_ALIVE; 835 dev->sc_flags &= ~SBICF_SELECTED; 836 837 /* initialize inhibit array */ 838 if (scsi_nosync) { 839 inhibit_sync = (scsi_nosync >> shift_nosync) & 0xff; 840 shift_nosync += 8; 841 #ifdef DEBUG 842 if (inhibit_sync) 843 printf("%s: Inhibiting synchronous transfer %02x\n", 844 dev->sc_dev.dv_xname, inhibit_sync); 845 #endif 846 for (i = 0; i < 8; ++i) 847 if (inhibit_sync & (1 << i)) 848 sbic_inhibit_sync[i] = 1; 849 } 850 851 sbicreset(dev); 852 } 853 854 void 855 sbicreset(struct sbic_softc *dev) 856 { 857 sbic_regmap_t regs; 858 u_int my_id, s; 859 u_char csr; 860 #if 0 861 u_int i; 862 struct sbic_acb *acb; 863 #endif 864 865 regs = dev->sc_sbic; 866 #if 0 867 if (dev->sc_flags & SBICF_ALIVE) { 868 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 869 WAIT_CIP(regs); 870 } 871 #else 872 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 873 WAIT_CIP(regs); 874 #endif 875 s = splbio(); 876 my_id = dev->sc_channel.chan_id & SBIC_ID_MASK; 877 878 /* Enable advanced mode */ 879 my_id |= SBIC_ID_EAF /*| SBIC_ID_EHP*/ ; 880 SET_SBIC_myid(regs, my_id); 881 882 /* 883 * Disable interrupts (in dmainit) then reset the chip 884 */ 885 SET_SBIC_cmd(regs, SBIC_CMD_RESET); 886 DELAY(25); 887 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 888 GET_SBIC_csr(regs, csr); /* clears interrupt also */ 889 890 if (dev->sc_clkfreq < 110) 891 my_id |= SBIC_ID_FS_8_10; 892 else if (dev->sc_clkfreq < 160) 893 my_id |= SBIC_ID_FS_12_15; 894 else if (dev->sc_clkfreq < 210) 895 my_id |= SBIC_ID_FS_16_20; 896 897 SET_SBIC_myid(regs, my_id); 898 899 /* 900 * Set up various chip parameters 901 */ 902 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI /* | SBIC_CTL_HSP */ 903 | SBIC_MACHINE_DMA_MODE); 904 /* 905 * don't allow (re)selection (SBIC_RID_ES) 906 * until we can handle target mode!! 907 */ 908 SET_SBIC_rselid(regs, SBIC_RID_ER); 909 SET_SBIC_syn(regs, 0); /* asynch for now */ 910 911 /* 912 * anything else was zeroed by reset 913 */ 914 splx(s); 915 916 #if 0 917 if ((dev->sc_flags & SBICF_ALIVE) == 0) { 918 TAILQ_INIT(&dev->ready_list); 919 TAILQ_INIT(&dev->nexus_list); 920 TAILQ_INIT(&dev->free_list); 921 dev->sc_nexus = NULL; 922 dev->sc_xs = NULL; 923 acb = dev->sc_acb; 924 memset(acb, 0, sizeof(dev->sc_acb)); 925 for (i = 0; i < sizeof(dev->sc_acb) / sizeof(*acb); i++) { 926 TAILQ_INSERT_TAIL(&dev->free_list, acb, chain); 927 acb++; 928 } 929 memset(dev->sc_tinfo, 0, sizeof(dev->sc_tinfo)); 930 } else { 931 if (dev->sc_nexus != NULL) { 932 dev->sc_nexus->xs->error = XS_DRIVER_STUFFUP; 933 sbic_scsidone(dev->sc_nexus, dev->sc_stat[0]); 934 } 935 while (acb = dev->nexus_list.tqh_first) { 936 acb->xs->error = XS_DRIVER_STUFFUP; 937 sbic_scsidone(acb, -1 /*acb->stat[0]*/); 938 } 939 } 940 941 dev->sc_flags |= SBICF_ALIVE; 942 #endif 943 dev->sc_flags &= ~SBICF_SELECTED; 944 } 945 946 void 947 sbicerror(struct sbic_softc *dev, sbic_regmap_t regs, u_char csr) 948 { 949 struct scsipi_xfer *xs; 950 951 xs = dev->sc_xs; 952 953 #ifdef DIAGNOSTIC 954 if (xs == NULL) 955 panic("sbicerror"); 956 #endif 957 if (xs->xs_control & XS_CTL_SILENT) 958 return; 959 960 printf("%s: ", dev->sc_dev.dv_xname); 961 printf("csr == 0x%02x\n", csr); /* XXX */ 962 } 963 964 /* 965 * select the bus, return when selected or error. 966 */ 967 int 968 sbicselectbus(struct sbic_softc *dev, sbic_regmap_t regs, u_char target, 969 u_char lun, u_char our_addr) 970 { 971 u_char asr, csr, id; 972 973 SBIC_TRACE(dev); 974 QPRINTF(("sbicselectbus %d\n", target)); 975 976 /* 977 * if we're already selected, return (XXXX panic maybe?) 978 */ 979 if (dev->sc_flags & SBICF_SELECTED) { 980 SBIC_TRACE(dev); 981 return(1); 982 } 983 984 /* 985 * issue select 986 */ 987 SBIC_TC_PUT(regs, 0); 988 SET_SBIC_selid(regs, target); 989 SET_SBIC_timeo(regs, SBIC_TIMEOUT(250,dev->sc_clkfreq)); 990 991 /* 992 * set sync or async 993 */ 994 if (dev->sc_sync[target].state == SYNC_DONE) 995 SET_SBIC_syn(regs, SBIC_SYN (dev->sc_sync[target].offset, 996 dev->sc_sync[target].period)); 997 else 998 SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period)); 999 1000 GET_SBIC_asr(regs, asr); 1001 if( asr & (SBIC_ASR_INT|SBIC_ASR_BSY) ) { 1002 /* This means we got ourselves reselected upon */ 1003 /* printf("sbicselectbus: INT/BSY asr %02x\n", asr);*/ 1004 #ifdef DDB 1005 /* Debugger();*/ 1006 #endif 1007 SBIC_TRACE(dev); 1008 return 1; 1009 } 1010 1011 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN); 1012 1013 /* 1014 * wait for select (merged from separate function may need 1015 * cleanup) 1016 */ 1017 WAIT_CIP(regs); 1018 do { 1019 asr = SBIC_WAIT(regs, SBIC_ASR_INT | SBIC_ASR_LCI, 0); 1020 if (asr & SBIC_ASR_LCI) { 1021 #ifdef DEBUG 1022 if (reselect_debug) 1023 printf("sbicselectbus: late LCI asr %02x\n", asr); 1024 #endif 1025 SBIC_TRACE(dev); 1026 return 1; 1027 } 1028 GET_SBIC_csr (regs, csr); 1029 CSR_TRACE('s',csr,asr,target); 1030 QPRINTF(("%02x ", csr)); 1031 if( csr == SBIC_CSR_RSLT_NI || csr == SBIC_CSR_RSLT_IFY) { 1032 #ifdef DEBUG 1033 if(reselect_debug) 1034 printf("sbicselectbus: reselected asr %02x\n", asr); 1035 #endif 1036 /* We need to handle this now so we don't lock up later */ 1037 sbicnextstate(dev, csr, asr); 1038 SBIC_TRACE(dev); 1039 return 1; 1040 } 1041 if( csr == SBIC_CSR_SLT || csr == SBIC_CSR_SLT_ATN) { 1042 panic("sbicselectbus: target issued select!"); 1043 return 1; 1044 } 1045 } while (csr != (SBIC_CSR_MIS_2|MESG_OUT_PHASE) 1046 && csr != (SBIC_CSR_MIS_2|CMD_PHASE) && csr != SBIC_CSR_SEL_TIMEO); 1047 1048 /* Enable (or not) reselection */ 1049 if(!sbic_enable_reselect && dev->nexus_list.tqh_first == NULL) 1050 SET_SBIC_rselid (regs, 0); 1051 else 1052 SET_SBIC_rselid (regs, SBIC_RID_ER); 1053 1054 if (csr == (SBIC_CSR_MIS_2|CMD_PHASE)) { 1055 dev->sc_flags |= SBICF_SELECTED; /* device ignored ATN */ 1056 GET_SBIC_selid(regs, id); 1057 dev->target = id; 1058 GET_SBIC_tlun(regs,dev->lun); 1059 if( dev->lun & SBIC_TLUN_VALID ) 1060 dev->lun &= SBIC_TLUN_MASK; 1061 else 1062 dev->lun = lun; 1063 } else if (csr == (SBIC_CSR_MIS_2|MESG_OUT_PHASE)) { 1064 /* 1065 * Send identify message 1066 * (SCSI-2 requires an identify msg (?)) 1067 */ 1068 GET_SBIC_selid(regs, id); 1069 dev->target = id; 1070 GET_SBIC_tlun(regs,dev->lun); 1071 if( dev->lun & SBIC_TLUN_VALID ) 1072 dev->lun &= SBIC_TLUN_MASK; 1073 else 1074 dev->lun = lun; 1075 /* 1076 * handle drives that don't want to be asked 1077 * whether to go sync at all. 1078 */ 1079 if (sbic_inhibit_sync[id] 1080 && dev->sc_sync[id].state == SYNC_START) { 1081 #ifdef DEBUG 1082 if (sync_debug) 1083 printf("Forcing target %d asynchronous.\n", id); 1084 #endif 1085 dev->sc_sync[id].offset = 0; 1086 dev->sc_sync[id].period = sbic_min_period; 1087 dev->sc_sync[id].state = SYNC_DONE; 1088 } 1089 1090 1091 if (dev->sc_sync[id].state != SYNC_START){ 1092 if( dev->sc_xs->xs_control & XS_CTL_POLL 1093 || (dev->sc_flags & SBICF_ICMD) 1094 || !sbic_enable_reselect ) 1095 SEND_BYTE (regs, MSG_IDENTIFY | lun); 1096 else 1097 SEND_BYTE (regs, MSG_IDENTIFY_DR | lun); 1098 } else { 1099 /* 1100 * try to initiate a sync transfer. 1101 * So compose the sync message we're going 1102 * to send to the target 1103 */ 1104 1105 #ifdef DEBUG 1106 if (sync_debug) 1107 printf("Sending sync request to target %d ... ", 1108 id); 1109 #endif 1110 /* 1111 * setup scsi message sync message request 1112 */ 1113 dev->sc_msg[0] = MSG_IDENTIFY | lun; 1114 dev->sc_msg[1] = MSG_EXT_MESSAGE; 1115 dev->sc_msg[2] = 3; 1116 dev->sc_msg[3] = MSG_SYNC_REQ; 1117 dev->sc_msg[4] = sbictoscsiperiod(dev, regs, 1118 sbic_min_period); 1119 dev->sc_msg[5] = sbic_max_offset; 1120 1121 if (sbicxfstart(regs, 6, MESG_OUT_PHASE, sbic_cmd_wait)) 1122 sbicxfout(regs, 6, dev->sc_msg, MESG_OUT_PHASE); 1123 1124 dev->sc_sync[id].state = SYNC_SENT; 1125 #ifdef DEBUG 1126 if (sync_debug) 1127 printf ("sent\n"); 1128 #endif 1129 } 1130 1131 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0); 1132 GET_SBIC_csr (regs, csr); 1133 CSR_TRACE('y',csr,asr,target); 1134 QPRINTF(("[%02x]", csr)); 1135 #ifdef DEBUG 1136 if (sync_debug && dev->sc_sync[id].state == SYNC_SENT) 1137 printf("csr-result of last msgout: 0x%x\n", csr); 1138 #endif 1139 1140 if (csr != SBIC_CSR_SEL_TIMEO) 1141 dev->sc_flags |= SBICF_SELECTED; 1142 } 1143 if (csr == SBIC_CSR_SEL_TIMEO) 1144 dev->sc_xs->error = XS_SELTIMEOUT; 1145 1146 QPRINTF(("\n")); 1147 1148 SBIC_TRACE(dev); 1149 return(csr == SBIC_CSR_SEL_TIMEO); 1150 } 1151 1152 int 1153 sbicxfstart(sbic_regmap_t regs, int len, u_char phase, int wait) 1154 { 1155 u_char id; 1156 1157 switch (phase) { 1158 case DATA_IN_PHASE: 1159 case MESG_IN_PHASE: 1160 GET_SBIC_selid (regs, id); 1161 id |= SBIC_SID_FROM_SCSI; 1162 SET_SBIC_selid (regs, id); 1163 SBIC_TC_PUT (regs, (unsigned)len); 1164 break; 1165 case DATA_OUT_PHASE: 1166 case MESG_OUT_PHASE: 1167 case CMD_PHASE: 1168 GET_SBIC_selid (regs, id); 1169 id &= ~SBIC_SID_FROM_SCSI; 1170 SET_SBIC_selid (regs, id); 1171 SBIC_TC_PUT (regs, (unsigned)len); 1172 break; 1173 default: 1174 SBIC_TC_PUT (regs, 0); 1175 } 1176 QPRINTF(("sbicxfstart %d, %d, %d\n", len, phase, wait)); 1177 1178 return(1); 1179 } 1180 1181 int 1182 sbicxfout(sbic_regmap_t regs, int len, void *bp, int phase) 1183 { 1184 u_char orig_csr, asr, *buf; 1185 int wait; 1186 1187 buf = bp; 1188 wait = sbic_data_wait; 1189 1190 QPRINTF(("sbicxfout {%d} %02x %02x %02x %02x %02x " 1191 "%02x %02x %02x %02x %02x\n", len, buf[0], buf[1], buf[2], 1192 buf[3], buf[4], buf[5], buf[6], buf[7], buf[8], buf[9])); 1193 1194 GET_SBIC_csr (regs, orig_csr); 1195 CSR_TRACE('>',orig_csr,0,0); 1196 1197 /* 1198 * sigh.. WD-PROTO strikes again.. sending the command in one go 1199 * causes the chip to lock up if talking to certain (misbehaving?) 1200 * targets. Anyway, this procedure should work for all targets, but 1201 * it's slightly slower due to the overhead 1202 */ 1203 WAIT_CIP (regs); 1204 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1205 for (;len > 0; len--) { 1206 GET_SBIC_asr (regs, asr); 1207 while ((asr & SBIC_ASR_DBR) == 0) { 1208 if ((asr & SBIC_ASR_INT) || --wait < 0) { 1209 #ifdef DEBUG 1210 if (sbic_debug) 1211 printf("sbicxfout fail: l%d i%x w%d\n", 1212 len, asr, wait); 1213 #endif 1214 return (len); 1215 } 1216 /* DELAY(1);*/ 1217 GET_SBIC_asr (regs, asr); 1218 } 1219 1220 SET_SBIC_data (regs, *buf); 1221 buf++; 1222 } 1223 SBIC_TC_GET(regs, len); 1224 QPRINTF(("sbicxfout done %d bytes\n", len)); 1225 /* 1226 * this leaves with one csr to be read 1227 */ 1228 return(0); 1229 } 1230 1231 /* returns # bytes left to read */ 1232 int 1233 sbicxfin(sbic_regmap_t regs, int len, void *bp) 1234 { 1235 int wait; 1236 u_char *obp, *buf; 1237 u_char orig_csr, csr, asr; 1238 1239 wait = sbic_data_wait; 1240 obp = bp; 1241 buf = bp; 1242 1243 GET_SBIC_csr (regs, orig_csr); 1244 CSR_TRACE('<',orig_csr,0,0); 1245 1246 QPRINTF(("sbicxfin %d, csr=%02x\n", len, orig_csr)); 1247 1248 WAIT_CIP (regs); 1249 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1250 for (;len > 0; len--) { 1251 GET_SBIC_asr (regs, asr); 1252 if((asr & SBIC_ASR_PE)) { 1253 #ifdef DEBUG 1254 printf("sbicxfin parity error: l%d i%x w%d\n", 1255 len, asr, wait); 1256 /* return ((unsigned long)buf - (unsigned long)bp); */ 1257 #ifdef DDB 1258 Debugger(); 1259 #endif 1260 #endif 1261 } 1262 while ((asr & SBIC_ASR_DBR) == 0) { 1263 if ((asr & SBIC_ASR_INT) || --wait < 0) { 1264 #ifdef DEBUG 1265 if (sbic_debug) { 1266 QPRINTF(("sbicxfin fail:{%d} %02x %02x %02x %02x %02x %02x " 1267 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1268 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1269 printf("sbicxfin fail: l%d i%x w%d\n", 1270 len, asr, wait); 1271 } 1272 #endif 1273 return len; 1274 } 1275 1276 if( ! asr & SBIC_ASR_BSY ) { 1277 GET_SBIC_csr(regs, csr); 1278 CSR_TRACE('<',csr,asr,len); 1279 QPRINTF(("[CSR%02xASR%02x]", csr, asr)); 1280 } 1281 1282 /* DELAY(1);*/ 1283 GET_SBIC_asr (regs, asr); 1284 } 1285 1286 GET_SBIC_data (regs, *buf); 1287 /* QPRINTF(("asr=%02x, csr=%02x, data=%02x\n", asr, csr, *buf));*/ 1288 buf++; 1289 } 1290 1291 QPRINTF(("sbicxfin {%d} %02x %02x %02x %02x %02x %02x " 1292 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1293 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1294 1295 /* this leaves with one csr to be read */ 1296 return len; 1297 } 1298 1299 /* 1300 * SCSI 'immediate' command: issue a command to some SCSI device 1301 * and get back an 'immediate' response (i.e., do programmed xfer 1302 * to get the response data). 'cbuf' is a buffer containing a scsi 1303 * command of length clen bytes. 'buf' is a buffer of length 'len' 1304 * bytes for data. The transfer direction is determined by the device 1305 * (i.e., by the scsi bus data xfer phase). If 'len' is zero, the 1306 * command must supply no data. 1307 */ 1308 int 1309 sbicicmd(struct sbic_softc *dev, int target, int lun, void *cbuf, int clen, 1310 void *buf, int len) 1311 { 1312 sbic_regmap_t regs; 1313 u_char phase, csr, asr; 1314 int wait, i; 1315 struct sbic_acb *acb; 1316 1317 #define CSR_LOG_BUF_SIZE 0 1318 #if CSR_LOG_BUF_SIZE 1319 int bufptr; 1320 int csrbuf[CSR_LOG_BUF_SIZE]; 1321 bufptr=0; 1322 #endif 1323 1324 SBIC_TRACE(dev); 1325 regs = dev->sc_sbic; 1326 acb = dev->sc_nexus; 1327 1328 /* Make sure pointers are OK */ 1329 dev->sc_last = dev->sc_cur = &acb->sc_pa; 1330 dev->sc_tcnt = acb->sc_tcnt = 0; 1331 acb->sc_pa.dc_count = 0; /* No DMA */ 1332 acb->sc_kv.dc_addr = buf; 1333 acb->sc_kv.dc_count = len; 1334 1335 #ifdef DEBUG 1336 routine = 3; 1337 debug_sbic_regs = regs; /* store this to allow debug calls */ 1338 if( data_pointer_debug > 1 ) 1339 printf("sbicicmd(%d,%d):%d\n", target, lun, 1340 acb->sc_kv.dc_count); 1341 #endif 1342 1343 /* 1344 * set the sbic into non-DMA mode 1345 */ 1346 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI /*| SBIC_CTL_HSP*/); 1347 1348 dev->sc_stat[0] = 0xff; 1349 dev->sc_msg[0] = 0xff; 1350 i = 1; /* pre-load */ 1351 1352 /* We're stealing the SCSI bus */ 1353 dev->sc_flags |= SBICF_ICMD; 1354 1355 do { 1356 /* 1357 * select the SCSI bus (it's an error if bus isn't free) 1358 */ 1359 if (!( dev->sc_flags & SBICF_SELECTED ) 1360 && sbicselectbus(dev, regs, target, lun, dev->sc_scsiaddr)) { 1361 /* printf("sbicicmd: trying to select busy bus!\n"); */ 1362 dev->sc_flags &= ~SBICF_ICMD; 1363 return(-1); 1364 } 1365 1366 /* 1367 * Wait for a phase change (or error) then let the device sequence 1368 * us through the various SCSI phases. 1369 */ 1370 1371 wait = sbic_cmd_wait; 1372 1373 GET_SBIC_asr (regs, asr); 1374 GET_SBIC_csr (regs, csr); 1375 CSR_TRACE('I',csr,asr,target); 1376 QPRINTF((">ASR:%02xCSR:%02x<", asr, csr)); 1377 1378 #if CSR_LOG_BUF_SIZE 1379 csrbuf[bufptr++] = csr; 1380 #endif 1381 1382 1383 switch (csr) { 1384 case SBIC_CSR_S_XFERRED: 1385 case SBIC_CSR_DISC: 1386 case SBIC_CSR_DISC_1: 1387 dev->sc_flags &= ~SBICF_SELECTED; 1388 GET_SBIC_cmd_phase (regs, phase); 1389 if (phase == 0x60) { 1390 GET_SBIC_tlun (regs, dev->sc_stat[0]); 1391 i = 0; /* done */ 1392 /* break; */ /* Bypass all the state gobldygook */ 1393 } else { 1394 #ifdef DEBUG 1395 if(reselect_debug>1) 1396 printf("sbicicmd: handling disconnect\n"); 1397 #endif 1398 i = SBIC_STATE_DISCONNECT; 1399 } 1400 break; 1401 1402 case SBIC_CSR_XFERRED|CMD_PHASE: 1403 case SBIC_CSR_MIS|CMD_PHASE: 1404 case SBIC_CSR_MIS_1|CMD_PHASE: 1405 case SBIC_CSR_MIS_2|CMD_PHASE: 1406 if (sbicxfstart(regs, clen, CMD_PHASE, sbic_cmd_wait)) 1407 if (sbicxfout(regs, clen, 1408 cbuf, CMD_PHASE)) 1409 i = sbicabort(dev, regs, "icmd sending cmd"); 1410 #if 0 1411 GET_SBIC_csr(regs, csr); /* Lets us reload tcount */ 1412 WAIT_CIP(regs); 1413 GET_SBIC_asr(regs, asr); 1414 CSR_TRACE('I',csr,asr,target); 1415 if( asr & (SBIC_ASR_BSY|SBIC_ASR_LCI|SBIC_ASR_CIP) ) 1416 printf("next: cmd sent asr %02x, csr %02x\n", 1417 asr, csr); 1418 #endif 1419 break; 1420 1421 #if 0 1422 case SBIC_CSR_XFERRED|DATA_OUT_PHASE: 1423 case SBIC_CSR_XFERRED|DATA_IN_PHASE: 1424 case SBIC_CSR_MIS|DATA_OUT_PHASE: 1425 case SBIC_CSR_MIS|DATA_IN_PHASE: 1426 case SBIC_CSR_MIS_1|DATA_OUT_PHASE: 1427 case SBIC_CSR_MIS_1|DATA_IN_PHASE: 1428 case SBIC_CSR_MIS_2|DATA_OUT_PHASE: 1429 case SBIC_CSR_MIS_2|DATA_IN_PHASE: 1430 if (acb->sc_kv.dc_count <= 0) 1431 i = sbicabort(dev, regs, "icmd out of data"); 1432 else { 1433 wait = sbic_data_wait; 1434 if (sbicxfstart(regs, 1435 acb->sc_kv.dc_count, 1436 SBIC_PHASE(csr), wait)) 1437 if (csr & 0x01) 1438 /* data in? */ 1439 i=sbicxfin(regs, 1440 acb->sc_kv.dc_count, 1441 acb->sc_kv.dc_addr); 1442 else 1443 i=sbicxfout(regs, 1444 acb->sc_kv.dc_count, 1445 acb->sc_kv.dc_addr, 1446 SBIC_PHASE(csr)); 1447 acb->sc_kv.dc_addr += 1448 (acb->sc_kv.dc_count - i); 1449 acb->sc_kv.dc_count = i; 1450 i = 1; 1451 } 1452 break; 1453 1454 #endif 1455 case SBIC_CSR_XFERRED|STATUS_PHASE: 1456 case SBIC_CSR_MIS|STATUS_PHASE: 1457 case SBIC_CSR_MIS_1|STATUS_PHASE: 1458 case SBIC_CSR_MIS_2|STATUS_PHASE: 1459 /* 1460 * the sbic does the status/cmd-complete reading ok, 1461 * so do this with its hi-level commands. 1462 */ 1463 #ifdef DEBUG 1464 if(sbic_debug) 1465 printf("SBICICMD status phase\n"); 1466 #endif 1467 SBIC_TC_PUT(regs, 0); 1468 SET_SBIC_cmd_phase(regs, 0x46); 1469 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1470 break; 1471 1472 #if THIS_IS_A_RESERVED_STATE 1473 case BUS_FREE_PHASE: /* This is not legal */ 1474 if( dev->sc_stat[0] != 0xff ) 1475 goto out; 1476 break; 1477 #endif 1478 1479 default: 1480 i = sbicnextstate(dev, csr, asr); 1481 } 1482 1483 /* 1484 * make sure the last command was taken, 1485 * ie. we're not hunting after an ignored command.. 1486 */ 1487 GET_SBIC_asr(regs, asr); 1488 1489 /* tapes may take a loooong time.. */ 1490 while (asr & SBIC_ASR_BSY){ 1491 if(asr & SBIC_ASR_DBR) { 1492 printf("sbicicmd: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", 1493 csr,asr); 1494 #ifdef DDB 1495 Debugger(); 1496 #endif 1497 /* SBIC is jammed */ 1498 /* DUNNO which direction */ 1499 /* Try old direction */ 1500 GET_SBIC_data(regs,i); 1501 GET_SBIC_asr(regs, asr); 1502 if( asr & SBIC_ASR_DBR) /* Wants us to write */ 1503 SET_SBIC_data(regs,i); 1504 } 1505 GET_SBIC_asr(regs, asr); 1506 } 1507 1508 /* 1509 * wait for last command to complete 1510 */ 1511 if (asr & SBIC_ASR_LCI) { 1512 printf("sbicicmd: last command ignored\n"); 1513 } 1514 else if( i == 1 ) /* Bsy */ 1515 SBIC_WAIT (regs, SBIC_ASR_INT, wait); 1516 1517 /* 1518 * do it again 1519 */ 1520 } while ( i > 0 && dev->sc_stat[0] == 0xff); 1521 1522 /* Sometimes we need to do an extra read of the CSR */ 1523 GET_SBIC_csr(regs, csr); 1524 CSR_TRACE('I',csr,asr,0xff); 1525 1526 #if CSR_LOG_BUF_SIZE 1527 if(reselect_debug>1) 1528 for(i=0; i<bufptr; i++) 1529 printf("CSR:%02x", csrbuf[i]); 1530 #endif 1531 1532 #ifdef DEBUG 1533 if(data_pointer_debug > 1) 1534 printf("sbicicmd done(%d,%d):%d =%d=\n", 1535 dev->target, lun, 1536 acb->sc_kv.dc_count, 1537 dev->sc_stat[0]); 1538 #endif 1539 1540 QPRINTF(("=STS:%02x=", dev->sc_stat[0])); 1541 dev->sc_flags &= ~SBICF_ICMD; 1542 1543 SBIC_TRACE(dev); 1544 return(dev->sc_stat[0]); 1545 } 1546 1547 /* 1548 * Finish SCSI xfer command: After the completion interrupt from 1549 * a read/write operation, sequence through the final phases in 1550 * programmed i/o. This routine is a lot like sbicicmd except we 1551 * skip (and don't allow) the select, cmd out and data in/out phases. 1552 */ 1553 void 1554 sbicxfdone(struct sbic_softc *dev, sbic_regmap_t regs, int target) 1555 { 1556 u_char phase, asr, csr; 1557 int s; 1558 1559 SBIC_TRACE(dev); 1560 QPRINTF(("{")); 1561 s = splbio(); 1562 1563 /* 1564 * have the sbic complete on its own 1565 */ 1566 SBIC_TC_PUT(regs, 0); 1567 SET_SBIC_cmd_phase(regs, 0x46); 1568 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1569 1570 do { 1571 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0); 1572 GET_SBIC_csr (regs, csr); 1573 CSR_TRACE('f',csr,asr,target); 1574 QPRINTF(("%02x:", csr)); 1575 } while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) 1576 && (csr != SBIC_CSR_S_XFERRED)); 1577 1578 dev->sc_flags &= ~SBICF_SELECTED; 1579 1580 GET_SBIC_cmd_phase (regs, phase); 1581 QPRINTF(("}%02x", phase)); 1582 if (phase == 0x60) 1583 GET_SBIC_tlun(regs, dev->sc_stat[0]); 1584 else 1585 sbicerror(dev, regs, csr); 1586 1587 QPRINTF(("=STS:%02x=\n", dev->sc_stat[0])); 1588 splx(s); 1589 SBIC_TRACE(dev); 1590 } 1591 1592 /* 1593 * No DMA chains 1594 */ 1595 1596 int 1597 sbicgo(struct sbic_softc *dev, struct scsipi_xfer *xs) 1598 { 1599 int i, dmaflags, count, usedma; 1600 u_char csr, asr, *addr; 1601 sbic_regmap_t regs; 1602 struct sbic_acb *acb; 1603 1604 SBIC_TRACE(dev); 1605 dev->target = xs->xs_periph->periph_target; 1606 dev->lun = xs->xs_periph->periph_lun; 1607 acb = dev->sc_nexus; 1608 regs = dev->sc_sbic; 1609 1610 usedma = sbicdmaok(dev, xs); 1611 #ifdef DEBUG 1612 routine = 1; 1613 debug_sbic_regs = regs; /* store this to allow debug calls */ 1614 if( data_pointer_debug > 1 ) 1615 printf("sbicgo(%d,%d)\n", dev->target, dev->lun); 1616 #endif 1617 1618 /* 1619 * set the sbic into DMA mode 1620 */ 1621 if( usedma ) 1622 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI | 1623 SBIC_MACHINE_DMA_MODE); 1624 else 1625 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1626 1627 1628 /* 1629 * select the SCSI bus (it's an error if bus isn't free) 1630 */ 1631 if (sbicselectbus(dev, regs, dev->target, dev->lun, 1632 dev->sc_scsiaddr)) { 1633 /* printf("sbicgo: Trying to select busy bus!\n"); */ 1634 SBIC_TRACE(dev); 1635 return(0); /* Not done: needs to be rescheduled */ 1636 } 1637 dev->sc_stat[0] = 0xff; 1638 1639 /* 1640 * Calculate DMA chains now 1641 */ 1642 1643 dmaflags = 0; 1644 if (acb->flags & ACB_DATAIN) 1645 dmaflags |= DMAGO_READ; 1646 1647 1648 /* 1649 * Deal w/bounce buffers. 1650 */ 1651 1652 addr = acb->sc_kv.dc_addr; 1653 count = acb->sc_kv.dc_count; 1654 if (count && (char *)kvtop(addr) != acb->sc_pa.dc_addr) { /* XXXX check */ 1655 printf("sbic: DMA buffer mapping changed %p->%x\n", 1656 acb->sc_pa.dc_addr, (unsigned)kvtop(addr)); 1657 #ifdef DDB 1658 Debugger(); 1659 #endif 1660 } 1661 1662 #ifdef DEBUG 1663 ++sbicdma_ops; /* count total DMA operations */ 1664 #endif 1665 if (count && usedma && dev->sc_flags & SBICF_BADDMA && 1666 sbiccheckdmap(addr, count, dev->sc_dmamask)) { 1667 /* 1668 * need to bounce the DMA. 1669 */ 1670 if (dmaflags & DMAGO_READ) { 1671 acb->flags |= ACB_BBUF; 1672 acb->sc_dmausrbuf = addr; 1673 acb->sc_dmausrlen = count; 1674 acb->sc_usrbufpa = (u_char *)kvtop(addr); 1675 if(!dev->sc_tinfo[dev->target].bounce) { 1676 printf("sbicgo: HELP! no bounce allocated for %d\n", 1677 dev->target); 1678 printf("xfer: (%p->%p,%lx)\n", acb->sc_dmausrbuf, 1679 acb->sc_usrbufpa, acb->sc_dmausrlen); 1680 dev->sc_tinfo[xs->xs_periph->periph_target].bounce 1681 = (char *)alloc_z2mem(MAXPHYS); 1682 if (isztwomem(dev->sc_tinfo[xs->xs_periph->periph_target].bounce)) 1683 printf("alloc ZII target %d bounce pa 0x%x\n", 1684 xs->xs_periph->periph_target, 1685 (unsigned)kvtop(dev->sc_tinfo[xs->xs_periph->periph_target].bounce)); 1686 else if (dev->sc_tinfo[xs->xs_periph->periph_target].bounce) 1687 printf("alloc CHIP target %d bounce pa %p\n", 1688 xs->xs_periph->periph_target, 1689 PREP_DMA_MEM(dev->sc_tinfo[xs->xs_periph->periph_target].bounce)); 1690 1691 printf("Allocating %d bounce at %x\n", 1692 dev->target, 1693 (unsigned)kvtop(dev->sc_tinfo[dev->target].bounce)); 1694 } 1695 } else { /* write: copy to DMA buffer */ 1696 #ifdef DEBUG 1697 if(data_pointer_debug) 1698 printf("sbicgo: copying %x bytes to target %d bounce %x\n", 1699 count, dev->target, 1700 (unsigned)kvtop(dev->sc_tinfo[dev->target].bounce)); 1701 #endif 1702 bcopy (addr, dev->sc_tinfo[dev->target].bounce, count); 1703 } 1704 addr = dev->sc_tinfo[dev->target].bounce;/* and use DMA buffer */ 1705 acb->sc_kv.dc_addr = addr; 1706 #ifdef DEBUG 1707 ++sbicdma_bounces; /* count number of bounced */ 1708 #endif 1709 } 1710 1711 /* 1712 * Allocate the DMA chain 1713 */ 1714 1715 /* Set start KVM addresses */ 1716 #if 0 1717 acb->sc_kv.dc_addr = addr; 1718 acb->sc_kv.dc_count = count; 1719 #endif 1720 1721 /* Mark end of segment */ 1722 acb->sc_tcnt = dev->sc_tcnt = 0; 1723 acb->sc_pa.dc_count = 0; 1724 1725 sbic_load_ptrs(dev, regs, dev->target, dev->lun); 1726 SBIC_TRACE(dev); 1727 /* Enable interrupts but don't do any DMA */ 1728 dev->sc_enintr(dev); 1729 if (usedma) { 1730 dev->sc_tcnt = dev->sc_dmago(dev, acb->sc_pa.dc_addr, 1731 acb->sc_pa.dc_count, 1732 dmaflags); 1733 #ifdef DEBUG 1734 dev->sc_dmatimo = dev->sc_tcnt ? 1 : 0; 1735 #endif 1736 } else 1737 dev->sc_dmacmd = 0; /* Don't use DMA */ 1738 dev->sc_flags |= SBICF_INDMA; 1739 /* SBIC_TC_PUT(regs, dev->sc_tcnt); */ /* XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX */ 1740 SBIC_TRACE(dev); 1741 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 1742 1743 /* 1744 * push the data cache ( I think this won't work (EH)) 1745 */ 1746 #if defined(M68040) || defined(M68060) 1747 if (mmutype == MMU_68040 && usedma && count) { 1748 dma_cachectl(addr, count); 1749 if (((u_int)addr & 0xF) || (((u_int)addr + count) & 0xF)) 1750 dev->sc_flags |= SBICF_DCFLUSH; 1751 } 1752 #endif 1753 #ifdef __powerpc__ 1754 dma_cachectl(addr, count); 1755 #endif 1756 1757 /* 1758 * enintr() also enables interrupts for the sbic 1759 */ 1760 #ifdef DEBUG 1761 if( data_pointer_debug > 1 ) 1762 printf("sbicgo dmago:%d(%p:%lx)\n", 1763 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 1764 #if 0 1765 /* 1766 * Hmm - this isn't right: asr and csr haven't been set yet. 1767 */ 1768 debug_asr = asr; 1769 debug_csr = csr; 1770 #endif 1771 #endif 1772 1773 /* 1774 * Lets cycle a while then let the interrupt handler take over 1775 */ 1776 1777 GET_SBIC_asr(regs, asr); 1778 do { 1779 GET_SBIC_csr(regs, csr); 1780 CSR_TRACE('g',csr,asr,dev->target); 1781 #ifdef DEBUG 1782 debug_csr = csr; 1783 routine = 1; 1784 #endif 1785 QPRINTF(("go[0x%x]", csr)); 1786 1787 i = sbicnextstate(dev, csr, asr); 1788 1789 WAIT_CIP(regs); 1790 GET_SBIC_asr(regs, asr); 1791 #ifdef DEBUG 1792 debug_asr = asr; 1793 #endif 1794 if(asr & SBIC_ASR_LCI) printf("sbicgo: LCI asr:%02x csr:%02x\n", 1795 asr,csr); 1796 } while( i == SBIC_STATE_RUNNING 1797 && asr & (SBIC_ASR_INT|SBIC_ASR_LCI) ); 1798 1799 CSR_TRACE('g',csr,asr,i<<4); 1800 SBIC_TRACE(dev); 1801 if (i == SBIC_STATE_DONE && dev->sc_stat[0] == 0xff) printf("sbicgo: done & stat = 0xff\n"); 1802 if (i == SBIC_STATE_DONE && dev->sc_stat[0] != 0xff) { 1803 /* if( i == SBIC_STATE_DONE && dev->sc_stat[0] ) { */ 1804 /* Did we really finish that fast? */ 1805 return 1; 1806 } 1807 return 0; 1808 } 1809 1810 1811 int 1812 sbicintr(struct sbic_softc *dev) 1813 { 1814 sbic_regmap_t regs; 1815 u_char asr, csr; 1816 int i; 1817 1818 regs = dev->sc_sbic; 1819 1820 /* 1821 * pending interrupt? 1822 */ 1823 GET_SBIC_asr (regs, asr); 1824 if ((asr & SBIC_ASR_INT) == 0) 1825 return(0); 1826 1827 SBIC_TRACE(dev); 1828 do { 1829 GET_SBIC_csr(regs, csr); 1830 CSR_TRACE('i',csr,asr,dev->target); 1831 #ifdef DEBUG 1832 debug_csr = csr; 1833 routine = 2; 1834 #endif 1835 QPRINTF(("intr[0x%x]", csr)); 1836 1837 i = sbicnextstate(dev, csr, asr); 1838 1839 WAIT_CIP(regs); 1840 GET_SBIC_asr(regs, asr); 1841 #ifdef DEBUG 1842 debug_asr = asr; 1843 #endif 1844 #if 0 1845 if(asr & SBIC_ASR_LCI) printf("sbicintr: LCI asr:%02x csr:%02x\n", 1846 asr,csr); 1847 #endif 1848 } while(i == SBIC_STATE_RUNNING && 1849 asr & (SBIC_ASR_INT|SBIC_ASR_LCI)); 1850 CSR_TRACE('i',csr,asr,i<<4); 1851 SBIC_TRACE(dev); 1852 return(1); 1853 } 1854 1855 /* 1856 * Run commands and wait for disconnect 1857 */ 1858 int 1859 sbicpoll(struct sbic_softc *dev) 1860 { 1861 sbic_regmap_t regs; 1862 u_char asr, csr; 1863 int i; 1864 1865 SBIC_TRACE(dev); 1866 regs = dev->sc_sbic; 1867 1868 do { 1869 GET_SBIC_asr (regs, asr); 1870 #ifdef DEBUG 1871 debug_asr = asr; 1872 #endif 1873 GET_SBIC_csr(regs, csr); 1874 CSR_TRACE('p',csr,asr,dev->target); 1875 #ifdef DEBUG 1876 debug_csr = csr; 1877 routine = 2; 1878 #endif 1879 QPRINTF(("poll[0x%x]", csr)); 1880 1881 i = sbicnextstate(dev, csr, asr); 1882 1883 WAIT_CIP(regs); 1884 GET_SBIC_asr(regs, asr); 1885 /* tapes may take a loooong time.. */ 1886 while (asr & SBIC_ASR_BSY){ 1887 if(asr & SBIC_ASR_DBR) { 1888 printf("sbipoll: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", 1889 csr,asr); 1890 #ifdef DDB 1891 Debugger(); 1892 #endif 1893 /* SBIC is jammed */ 1894 /* DUNNO which direction */ 1895 /* Try old direction */ 1896 GET_SBIC_data(regs,i); 1897 GET_SBIC_asr(regs, asr); 1898 if( asr & SBIC_ASR_DBR) /* Wants us to write */ 1899 SET_SBIC_data(regs,i); 1900 } 1901 GET_SBIC_asr(regs, asr); 1902 } 1903 1904 if(asr & SBIC_ASR_LCI) printf("sbicpoll: LCI asr:%02x csr:%02x\n", 1905 asr,csr); 1906 else if( i == 1 ) /* BSY */ 1907 SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait); 1908 } while(i == SBIC_STATE_RUNNING); 1909 CSR_TRACE('p',csr,asr,i<<4); 1910 SBIC_TRACE(dev); 1911 return(1); 1912 } 1913 1914 /* 1915 * Handle a single msgin 1916 */ 1917 1918 int 1919 sbicmsgin(struct sbic_softc *dev) 1920 { 1921 sbic_regmap_t regs; 1922 int recvlen; 1923 u_char asr, csr, *tmpaddr; 1924 1925 regs = dev->sc_sbic; 1926 1927 dev->sc_msg[0] = 0xff; 1928 dev->sc_msg[1] = 0xff; 1929 1930 GET_SBIC_asr(regs, asr); 1931 #ifdef DEBUG 1932 if(reselect_debug>1) 1933 printf("sbicmsgin asr=%02x\n", asr); 1934 #endif 1935 1936 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 1937 1938 GET_SBIC_selid (regs, csr); 1939 SET_SBIC_selid (regs, csr | SBIC_SID_FROM_SCSI); 1940 1941 SBIC_TC_PUT(regs, 0); 1942 tmpaddr = dev->sc_msg; 1943 recvlen = 1; 1944 do { 1945 while( recvlen-- ) { 1946 GET_SBIC_asr(regs, asr); 1947 GET_SBIC_csr(regs, csr); 1948 QPRINTF(("sbicmsgin ready to go (csr,asr)=(%02x,%02x)\n", 1949 csr, asr)); 1950 1951 RECV_BYTE(regs, *tmpaddr); 1952 CSR_TRACE('m',csr,asr,*tmpaddr); 1953 #if 1 1954 /* 1955 * get the command completion interrupt, or we 1956 * can't send a new command (LCI) 1957 */ 1958 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1959 GET_SBIC_csr(regs, csr); 1960 CSR_TRACE('X',csr,asr,dev->target); 1961 #else 1962 WAIT_CIP(regs); 1963 do { 1964 GET_SBIC_asr(regs, asr); 1965 csr = 0xff; 1966 GET_SBIC_csr(regs, csr); 1967 CSR_TRACE('X',csr,asr,dev->target); 1968 if( csr == 0xff ) 1969 printf("sbicmsgin waiting: csr %02x asr %02x\n", csr, asr); 1970 } while( csr == 0xff ); 1971 #endif 1972 #ifdef DEBUG 1973 if(reselect_debug>1) 1974 printf("sbicmsgin: got %02x csr %02x asr %02x\n", 1975 *tmpaddr, csr, asr); 1976 #endif 1977 #if do_parity_check 1978 if( asr & SBIC_ASR_PE ) { 1979 printf ("Parity error"); 1980 /* This code simply does not work. */ 1981 WAIT_CIP(regs); 1982 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 1983 WAIT_CIP(regs); 1984 GET_SBIC_asr(regs, asr); 1985 WAIT_CIP(regs); 1986 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 1987 WAIT_CIP(regs); 1988 if( !(asr & SBIC_ASR_LCI) ) 1989 /* Target wants to send garbled msg*/ 1990 continue; 1991 printf("--fixing\n"); 1992 /* loop until a msgout phase occurs on target */ 1993 while(csr & 0x07 != MESG_OUT_PHASE) { 1994 while( asr & SBIC_ASR_BSY && 1995 !(asr & SBIC_ASR_DBR|SBIC_ASR_INT) ) 1996 GET_SBIC_asr(regs, asr); 1997 if( asr & SBIC_ASR_DBR ) 1998 panic("msgin: jammed again!"); 1999 GET_SBIC_csr(regs, csr); 2000 CSR_TRACE('e',csr,asr,dev->target); 2001 if( csr & 0x07 != MESG_OUT_PHASE ) { 2002 sbicnextstate(dev, csr, asr); 2003 sbic_save_ptrs(dev, regs, 2004 dev->target, 2005 dev->lun); 2006 } 2007 } 2008 /* Should be msg out by now */ 2009 SEND_BYTE(regs, MSG_PARITY_ERROR); 2010 } 2011 else 2012 #endif 2013 tmpaddr++; 2014 2015 if(recvlen) { 2016 /* Clear ACK */ 2017 WAIT_CIP(regs); 2018 GET_SBIC_asr(regs, asr); 2019 GET_SBIC_csr(regs, csr); 2020 CSR_TRACE('X',csr,asr,dev->target); 2021 QPRINTF(("sbicmsgin pre byte CLR_ACK (csr,asr)=(%02x,%02x)\n", 2022 csr, asr)); 2023 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2024 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2025 } 2026 2027 }; 2028 2029 if(dev->sc_msg[0] == 0xff) { 2030 printf("sbicmsgin: sbic swallowed our message\n"); 2031 break; 2032 } 2033 #ifdef DEBUG 2034 if (sync_debug) 2035 printf("msgin done csr 0x%x asr 0x%x msg 0x%x\n", 2036 csr, asr, dev->sc_msg[0]); 2037 #endif 2038 /* 2039 * test whether this is a reply to our sync 2040 * request 2041 */ 2042 if (MSG_ISIDENTIFY(dev->sc_msg[0])) { 2043 QPRINTF(("IFFY")); 2044 #if 0 2045 /* There is an implied load-ptrs here */ 2046 sbic_load_ptrs(dev, regs, dev->target, dev->lun); 2047 #endif 2048 /* Got IFFY msg -- ack it */ 2049 } else if (dev->sc_msg[0] == MSG_REJECT 2050 && dev->sc_sync[dev->target].state == SYNC_SENT) { 2051 QPRINTF(("REJECT of SYN")); 2052 #ifdef DEBUG 2053 if (sync_debug) 2054 printf("target %d rejected sync, going async\n", 2055 dev->target); 2056 #endif 2057 dev->sc_sync[dev->target].period = sbic_min_period; 2058 dev->sc_sync[dev->target].offset = 0; 2059 dev->sc_sync[dev->target].state = SYNC_DONE; 2060 SET_SBIC_syn(regs, 2061 SBIC_SYN(dev->sc_sync[dev->target].offset, 2062 dev->sc_sync[dev->target].period)); 2063 } else if ((dev->sc_msg[0] == MSG_REJECT)) { 2064 QPRINTF(("REJECT")); 2065 /* 2066 * we'll never REJECt a REJECT message.. 2067 */ 2068 } else if ((dev->sc_msg[0] == MSG_SAVE_DATA_PTR)) { 2069 QPRINTF(("MSG_SAVE_DATA_PTR")); 2070 /* 2071 * don't reject this either. 2072 */ 2073 } else if ((dev->sc_msg[0] == MSG_DISCONNECT)) { 2074 QPRINTF(("DISCONNECT")); 2075 #ifdef DEBUG 2076 if( reselect_debug>1 && dev->sc_msg[0] == MSG_DISCONNECT ) 2077 printf("sbicmsgin: got disconnect msg %s\n", 2078 (dev->sc_flags & SBICF_ICMD)?"rejecting":""); 2079 #endif 2080 if( dev->sc_flags & SBICF_ICMD ) { 2081 /* We're in immediate mode. Prevent disconnects. */ 2082 /* prepare to reject the message, NACK */ 2083 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2084 WAIT_CIP(regs); 2085 } 2086 } else if (dev->sc_msg[0] == MSG_CMD_COMPLETE ) { 2087 QPRINTF(("CMD_COMPLETE")); 2088 /* !! KLUDGE ALERT !! quite a few drives don't seem to 2089 * really like the current way of sending the 2090 * sync-handshake together with the ident-message, and 2091 * they react by sending command-complete and 2092 * disconnecting right after returning the valid sync 2093 * handshake. So, all I can do is reselect the drive, 2094 * and hope it won't disconnect again. I don't think 2095 * this is valid behavior, but I can't help fixing a 2096 * problem that apparently exists. 2097 * 2098 * Note: we should not get here on `normal' command 2099 * completion, as that condition is handled by the 2100 * high-level sel&xfer resume command used to walk 2101 * thru status/cc-phase. 2102 */ 2103 2104 #ifdef DEBUG 2105 if (sync_debug) 2106 printf ("GOT MSG %d! target %d acting weird.." 2107 " waiting for disconnect...\n", 2108 dev->sc_msg[0], dev->target); 2109 #endif 2110 /* Check to see if sbic is handling this */ 2111 GET_SBIC_asr(regs, asr); 2112 if(asr & SBIC_ASR_BSY) 2113 return SBIC_STATE_RUNNING; 2114 2115 /* Let's try this: Assume it works and set status to 00 */ 2116 dev->sc_stat[0] = 0; 2117 } else if (dev->sc_msg[0] == MSG_EXT_MESSAGE 2118 && tmpaddr == &dev->sc_msg[1]) { 2119 QPRINTF(("ExtMSG\n")); 2120 /* Read in whole extended message */ 2121 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2122 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2123 GET_SBIC_asr(regs, asr); 2124 GET_SBIC_csr(regs, csr); 2125 QPRINTF(("CLR ACK asr %02x, csr %02x\n", asr, csr)); 2126 RECV_BYTE(regs, *tmpaddr); 2127 CSR_TRACE('x',csr,asr,*tmpaddr); 2128 /* Wait for command completion IRQ */ 2129 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2130 recvlen = *tmpaddr++; 2131 QPRINTF(("Recving ext msg, asr %02x csr %02x len %02x\n", 2132 asr, csr, recvlen)); 2133 } else if (dev->sc_msg[0] == MSG_EXT_MESSAGE && dev->sc_msg[1] == 3 2134 && dev->sc_msg[2] == MSG_SYNC_REQ) { 2135 QPRINTF(("SYN")); 2136 dev->sc_sync[dev->target].period = 2137 sbicfromscsiperiod(dev, 2138 regs, dev->sc_msg[3]); 2139 dev->sc_sync[dev->target].offset = dev->sc_msg[4]; 2140 dev->sc_sync[dev->target].state = SYNC_DONE; 2141 SET_SBIC_syn(regs, 2142 SBIC_SYN(dev->sc_sync[dev->target].offset, 2143 dev->sc_sync[dev->target].period)); 2144 printf("%s: target %d now synchronous," 2145 " period=%dns, offset=%d.\n", 2146 dev->sc_dev.dv_xname, dev->target, 2147 dev->sc_msg[3] * 4, dev->sc_msg[4]); 2148 } else { 2149 #ifdef DEBUG 2150 if (sbic_debug || sync_debug) 2151 printf ("sbicmsgin: Rejecting message 0x%02x\n", 2152 dev->sc_msg[0]); 2153 #endif 2154 /* prepare to reject the message, NACK */ 2155 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2156 WAIT_CIP(regs); 2157 } 2158 /* Clear ACK */ 2159 WAIT_CIP(regs); 2160 GET_SBIC_asr(regs, asr); 2161 GET_SBIC_csr(regs, csr); 2162 CSR_TRACE('X',csr,asr,dev->target); 2163 QPRINTF(("sbicmsgin pre CLR_ACK (csr,asr)=(%02x,%02x)%d\n", 2164 csr, asr, recvlen)); 2165 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2166 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2167 } 2168 #if 0 2169 while((csr == SBIC_CSR_MSGIN_W_ACK) 2170 || (SBIC_PHASE(csr) == MESG_IN_PHASE)); 2171 #else 2172 while (recvlen>0); 2173 #endif 2174 2175 QPRINTF(("sbicmsgin finished: csr %02x, asr %02x\n",csr, asr)); 2176 2177 /* Should still have one CSR to read */ 2178 return SBIC_STATE_RUNNING; 2179 } 2180 2181 2182 /* 2183 * sbicnextstate() 2184 * return: 2185 * 0 == done 2186 * 1 == working 2187 * 2 == disconnected 2188 * -1 == error 2189 */ 2190 int 2191 sbicnextstate(struct sbic_softc *dev, u_char csr, u_char asr) 2192 { 2193 sbic_regmap_t regs; 2194 struct sbic_acb *acb; 2195 int i, newtarget, newlun, wait; 2196 #if 0 2197 unsigned tcnt; 2198 #endif 2199 2200 i = 0; 2201 SBIC_TRACE(dev); 2202 regs = dev->sc_sbic; 2203 acb = dev->sc_nexus; 2204 2205 QPRINTF(("next[%02x,%02x]",asr,csr)); 2206 2207 switch (csr) { 2208 case SBIC_CSR_XFERRED|CMD_PHASE: 2209 case SBIC_CSR_MIS|CMD_PHASE: 2210 case SBIC_CSR_MIS_1|CMD_PHASE: 2211 case SBIC_CSR_MIS_2|CMD_PHASE: 2212 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 2213 if (sbicxfstart(regs, acb->clen, CMD_PHASE, sbic_cmd_wait)) 2214 if (sbicxfout(regs, acb->clen, 2215 &acb->cmd, CMD_PHASE)) 2216 goto abort; 2217 break; 2218 2219 case SBIC_CSR_XFERRED|STATUS_PHASE: 2220 case SBIC_CSR_MIS|STATUS_PHASE: 2221 case SBIC_CSR_MIS_1|STATUS_PHASE: 2222 case SBIC_CSR_MIS_2|STATUS_PHASE: 2223 /* 2224 * this should be the normal i/o completion case. 2225 * get the status & cmd complete msg then let the 2226 * device driver look at what happened. 2227 */ 2228 sbicxfdone(dev,regs,dev->target); 2229 /* 2230 * check for overlapping cache line, flush if so 2231 */ 2232 #if defined(M68040) || defined(M68060) 2233 if (dev->sc_flags & SBICF_DCFLUSH) { 2234 #if 0 2235 printf("sbic: 68040/68060 DMA cache flush needs" 2236 "fixing? %x:%x\n", 2237 dev->sc_xs->data, dev->sc_xs->datalen); 2238 #endif 2239 } 2240 #endif 2241 #ifdef DEBUG 2242 if( data_pointer_debug > 1 ) 2243 printf("next dmastop: %d(%p:%lx)\n", 2244 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 2245 dev->sc_dmatimo = 0; 2246 #endif 2247 dev->sc_dmastop(dev); /* was dmafree */ 2248 if (acb->flags & ACB_BBUF) { 2249 if ((u_char *)kvtop(acb->sc_dmausrbuf) != acb->sc_usrbufpa) 2250 printf("%s: WARNING - buffer mapping changed %p->%x\n", 2251 dev->sc_dev.dv_xname, acb->sc_usrbufpa, 2252 (unsigned)kvtop(acb->sc_dmausrbuf)); 2253 #ifdef DEBUG 2254 if(data_pointer_debug) 2255 printf("sbicgo:copying %lx bytes from target %d bounce %x\n", 2256 acb->sc_dmausrlen, 2257 dev->target, 2258 (unsigned)kvtop(dev->sc_tinfo[dev->target].bounce)); 2259 #endif 2260 bcopy(dev->sc_tinfo[dev->target].bounce, 2261 acb->sc_dmausrbuf, 2262 acb->sc_dmausrlen); 2263 } 2264 dev->sc_flags &= ~(SBICF_INDMA | SBICF_DCFLUSH); 2265 sbic_scsidone(acb, dev->sc_stat[0]); 2266 SBIC_TRACE(dev); 2267 return SBIC_STATE_DONE; 2268 2269 case SBIC_CSR_XFERRED|DATA_OUT_PHASE: 2270 case SBIC_CSR_XFERRED|DATA_IN_PHASE: 2271 case SBIC_CSR_MIS|DATA_OUT_PHASE: 2272 case SBIC_CSR_MIS|DATA_IN_PHASE: 2273 case SBIC_CSR_MIS_1|DATA_OUT_PHASE: 2274 case SBIC_CSR_MIS_1|DATA_IN_PHASE: 2275 case SBIC_CSR_MIS_2|DATA_OUT_PHASE: 2276 case SBIC_CSR_MIS_2|DATA_IN_PHASE: 2277 if( dev->sc_xs->xs_control & XS_CTL_POLL || dev->sc_flags & SBICF_ICMD 2278 || acb->sc_dmacmd == 0 ) { 2279 /* Do PIO */ 2280 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2281 if (acb->sc_kv.dc_count <= 0) { 2282 printf("sbicnextstate:xfer count %d asr%x csr%x\n", 2283 acb->sc_kv.dc_count, asr, csr); 2284 goto abort; 2285 } 2286 wait = sbic_data_wait; 2287 if( sbicxfstart(regs, 2288 acb->sc_kv.dc_count, 2289 SBIC_PHASE(csr), wait)) { 2290 if( SBIC_PHASE(csr) == DATA_IN_PHASE ) 2291 /* data in? */ 2292 i=sbicxfin(regs, 2293 acb->sc_kv.dc_count, 2294 acb->sc_kv.dc_addr); 2295 else 2296 i=sbicxfout(regs, 2297 acb->sc_kv.dc_count, 2298 acb->sc_kv.dc_addr, 2299 SBIC_PHASE(csr)); 2300 } 2301 acb->sc_kv.dc_addr += 2302 (acb->sc_kv.dc_count - i); 2303 acb->sc_kv.dc_count = i; 2304 } else { 2305 if (acb->sc_kv.dc_count <= 0) { 2306 printf("sbicnextstate:xfer count %d asr%x csr%x\n", 2307 acb->sc_kv.dc_count, asr, csr); 2308 goto abort; 2309 } 2310 /* 2311 * do scatter-gather DMA 2312 * hacking the controller chip, ouch.. 2313 */ 2314 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI | 2315 SBIC_MACHINE_DMA_MODE); 2316 /* 2317 * set next DMA addr and dec count 2318 */ 2319 #if 0 2320 SBIC_TC_GET(regs, tcnt); 2321 dev->sc_cur->dc_count -= ((dev->sc_tcnt - tcnt) >> 1); 2322 dev->sc_cur->dc_addr += (dev->sc_tcnt - tcnt); 2323 dev->sc_tcnt = acb->sc_tcnt = tcnt; 2324 #else 2325 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 2326 sbic_load_ptrs(dev, regs, dev->target, dev->lun); 2327 #endif 2328 #ifdef DEBUG 2329 if( data_pointer_debug > 1 ) 2330 printf("next dmanext: %d(%p:%lx)\n", 2331 dev->target,dev->sc_cur->dc_addr, 2332 dev->sc_tcnt); 2333 dev->sc_dmatimo = 1; 2334 #endif 2335 dev->sc_tcnt = dev->sc_dmanext(dev); 2336 SBIC_TC_PUT(regs, (unsigned)dev->sc_tcnt); 2337 SET_SBIC_cmd(regs, SBIC_CMD_XFER_INFO); 2338 dev->sc_flags |= SBICF_INDMA; 2339 } 2340 break; 2341 2342 case SBIC_CSR_XFERRED|MESG_IN_PHASE: 2343 case SBIC_CSR_MIS|MESG_IN_PHASE: 2344 case SBIC_CSR_MIS_1|MESG_IN_PHASE: 2345 case SBIC_CSR_MIS_2|MESG_IN_PHASE: 2346 SBIC_TRACE(dev); 2347 return sbicmsgin(dev); 2348 2349 case SBIC_CSR_MSGIN_W_ACK: 2350 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); /* Dunno what I'm ACKing */ 2351 printf("Acking unknown msgin CSR:%02x",csr); 2352 break; 2353 2354 case SBIC_CSR_XFERRED|MESG_OUT_PHASE: 2355 case SBIC_CSR_MIS|MESG_OUT_PHASE: 2356 case SBIC_CSR_MIS_1|MESG_OUT_PHASE: 2357 case SBIC_CSR_MIS_2|MESG_OUT_PHASE: 2358 #ifdef DEBUG 2359 if (sync_debug) 2360 printf ("sending REJECT msg to last msg.\n"); 2361 #endif 2362 2363 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 2364 /* 2365 * should only get here on reject, 2366 * since it's always US that 2367 * initiate a sync transfer 2368 */ 2369 SEND_BYTE(regs, MSG_REJECT); 2370 WAIT_CIP(regs); 2371 if( asr & (SBIC_ASR_BSY|SBIC_ASR_LCI|SBIC_ASR_CIP) ) 2372 printf("next: REJECT sent asr %02x\n", asr); 2373 SBIC_TRACE(dev); 2374 return SBIC_STATE_RUNNING; 2375 2376 case SBIC_CSR_DISC: 2377 case SBIC_CSR_DISC_1: 2378 dev->sc_flags &= ~(SBICF_INDMA|SBICF_SELECTED); 2379 2380 /* Try to schedule another target */ 2381 #ifdef DEBUG 2382 if(reselect_debug>1) 2383 printf("sbicnext target %d disconnected\n", dev->target); 2384 #endif 2385 TAILQ_INSERT_HEAD(&dev->nexus_list, acb, chain); 2386 ++dev->sc_tinfo[dev->target].dconns; 2387 dev->sc_nexus = NULL; 2388 dev->sc_xs = NULL; 2389 2390 if( acb->xs->xs_control & XS_CTL_POLL 2391 || (dev->sc_flags & SBICF_ICMD) 2392 || !sbic_parallel_operations ) { 2393 SBIC_TRACE(dev); 2394 return SBIC_STATE_DISCONNECT; 2395 } 2396 sbic_sched(dev); 2397 SBIC_TRACE(dev); 2398 return SBIC_STATE_DISCONNECT; 2399 2400 case SBIC_CSR_RSLT_NI: 2401 case SBIC_CSR_RSLT_IFY: 2402 GET_SBIC_rselid(regs, newtarget); 2403 /* check SBIC_RID_SIV? */ 2404 newtarget &= SBIC_RID_MASK; 2405 if (csr == SBIC_CSR_RSLT_IFY) { 2406 /* Read IFY msg to avoid lockup */ 2407 GET_SBIC_data(regs, newlun); 2408 WAIT_CIP(regs); 2409 newlun &= SBIC_TLUN_MASK; 2410 CSR_TRACE('r',csr,asr,newtarget); 2411 } else { 2412 /* Need to get IFY message */ 2413 for (newlun = 256; newlun; --newlun) { 2414 GET_SBIC_asr(regs, asr); 2415 if (asr & SBIC_ASR_INT) 2416 break; 2417 delay(1); 2418 } 2419 newlun = 0; /* XXXX */ 2420 if ((asr & SBIC_ASR_INT) == 0) { 2421 #ifdef DEBUG 2422 if (reselect_debug) 2423 printf("RSLT_NI - no IFFY message? asr %x\n", asr); 2424 #endif 2425 } else { 2426 GET_SBIC_csr(regs,csr); 2427 CSR_TRACE('n',csr,asr,newtarget); 2428 if (csr == (SBIC_CSR_MIS | MESG_IN_PHASE) || 2429 csr == (SBIC_CSR_MIS_1 | MESG_IN_PHASE) || 2430 csr == (SBIC_CSR_MIS_2 | MESG_IN_PHASE)) { 2431 sbicmsgin(dev); 2432 newlun = dev->sc_msg[0] & 7; 2433 } else { 2434 printf("RSLT_NI - not MESG_IN_PHASE %x\n", 2435 csr); 2436 } 2437 } 2438 } 2439 #ifdef DEBUG 2440 if(reselect_debug>1 || (reselect_debug && csr==SBIC_CSR_RSLT_NI)) 2441 printf("sbicnext: reselect %s from targ %d lun %d\n", 2442 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", 2443 newtarget, newlun); 2444 #endif 2445 if (dev->sc_nexus) { 2446 #ifdef DEBUG 2447 if (reselect_debug > 1) 2448 printf("%s: reselect %s with active command\n", 2449 dev->sc_dev.dv_xname, 2450 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY"); 2451 #ifdef DDB 2452 /* Debugger();*/ 2453 #endif 2454 #endif 2455 TAILQ_INSERT_HEAD(&dev->ready_list, dev->sc_nexus, chain); 2456 dev->sc_tinfo[dev->target].lubusy &= ~(1 << dev->lun); 2457 dev->sc_nexus = NULL; 2458 dev->sc_xs = NULL; 2459 } 2460 /* Reload sync values for this target */ 2461 if (dev->sc_sync[newtarget].state == SYNC_DONE) 2462 SET_SBIC_syn(regs, SBIC_SYN (dev->sc_sync[newtarget].offset, 2463 dev->sc_sync[newtarget].period)); 2464 else 2465 SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period)); 2466 for (acb = dev->nexus_list.tqh_first; acb; 2467 acb = acb->chain.tqe_next) { 2468 if (acb->xs->xs_periph->periph_target != newtarget || 2469 acb->xs->xs_periph->periph_lun != newlun) 2470 continue; 2471 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 2472 dev->sc_nexus = acb; 2473 dev->sc_xs = acb->xs; 2474 dev->sc_flags |= SBICF_SELECTED; 2475 dev->target = newtarget; 2476 dev->lun = newlun; 2477 break; 2478 } 2479 if (acb == NULL) { 2480 printf("%s: reselect %s targ %d not in nexus_list %p\n", 2481 dev->sc_dev.dv_xname, 2482 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", newtarget, 2483 &dev->nexus_list.tqh_first); 2484 panic("bad reselect in sbic"); 2485 } 2486 if (csr == SBIC_CSR_RSLT_IFY) 2487 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2488 break; 2489 2490 default: 2491 abort: 2492 /* 2493 * Something unexpected happened -- deal with it. 2494 */ 2495 printf("sbicnextstate: aborting csr %02x asr %02x\n", csr, asr); 2496 #ifdef DDB 2497 Debugger(); 2498 #endif 2499 #ifdef DEBUG 2500 if( data_pointer_debug > 1 ) 2501 printf("next dmastop: %d(%p:%lx)\n", 2502 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 2503 dev->sc_dmatimo = 0; 2504 #endif 2505 dev->sc_dmastop(dev); 2506 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2507 sbicerror(dev, regs, csr); 2508 sbicabort(dev, regs, "next"); 2509 if (dev->sc_flags & SBICF_INDMA) { 2510 /* 2511 * check for overlapping cache line, flush if so 2512 */ 2513 #if defined(M68040) || defined(M68060) 2514 if (dev->sc_flags & SBICF_DCFLUSH) { 2515 #if 0 2516 printf("sbic: 68040/060 DMA cache flush needs" 2517 "fixing? %x:%x\n", 2518 dev->sc_xs->data, dev->sc_xs->datalen); 2519 #endif 2520 } 2521 #endif 2522 dev->sc_flags &= 2523 ~(SBICF_INDMA | SBICF_DCFLUSH); 2524 #ifdef DEBUG 2525 if( data_pointer_debug > 1 ) 2526 printf("next dmastop: %d(%p:%lx)\n", 2527 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 2528 dev->sc_dmatimo = 0; 2529 #endif 2530 dev->sc_dmastop(dev); 2531 sbic_scsidone(acb, -1); 2532 } 2533 SBIC_TRACE(dev); 2534 return SBIC_STATE_ERROR; 2535 } 2536 2537 SBIC_TRACE(dev); 2538 return(SBIC_STATE_RUNNING); 2539 } 2540 2541 2542 /* 2543 * Check if DMA can not be used with specified buffer 2544 */ 2545 2546 int 2547 sbiccheckdmap(void *bp, u_long len, u_long mask) 2548 { 2549 u_char *buffer; 2550 u_long phy_buf; 2551 u_long phy_len; 2552 2553 buffer = bp; 2554 2555 if (len == 0) 2556 return(0); 2557 2558 while (len) { 2559 phy_buf = kvtop(buffer); 2560 if (len < (phy_len = PAGE_SIZE - ((int) buffer & PGOFSET))) 2561 phy_len = len; 2562 if (phy_buf & mask) 2563 return(1); 2564 buffer += phy_len; 2565 len -= phy_len; 2566 } 2567 return(0); 2568 } 2569 2570 int 2571 sbictoscsiperiod(struct sbic_softc *dev, sbic_regmap_t regs, int a) 2572 { 2573 unsigned int fs; 2574 2575 /* 2576 * cycle = DIV / (2*CLK) 2577 * DIV = FS+2 2578 * best we can do is 200ns at 20 MHz, 2 cycles 2579 */ 2580 2581 GET_SBIC_myid(regs,fs); 2582 fs = (fs >>6) + 2; /* DIV */ 2583 fs = (fs * 10000) / (dev->sc_clkfreq<<1); /* Cycle, in ns */ 2584 if (a < 2) a = 8; /* map to Cycles */ 2585 return ((fs*a)>>2); /* in 4 ns units */ 2586 } 2587 2588 int 2589 sbicfromscsiperiod(struct sbic_softc *dev, sbic_regmap_t regs, int p) 2590 { 2591 register unsigned int fs, ret; 2592 2593 /* Just the inverse of the above */ 2594 2595 GET_SBIC_myid(regs,fs); 2596 fs = (fs >>6) + 2; /* DIV */ 2597 fs = (fs * 10000) / (dev->sc_clkfreq<<1); /* Cycle, in ns */ 2598 2599 ret = p << 2; /* in ns units */ 2600 ret = ret / fs; /* in Cycles */ 2601 if (ret < sbic_min_period) 2602 return(sbic_min_period); 2603 2604 /* verify rounding */ 2605 if (sbictoscsiperiod(dev, regs, ret) < p) 2606 ret++; 2607 return (ret >= 8) ? 0 : ret; 2608 } 2609 2610 #ifdef DEBUG 2611 2612 void 2613 sbicdumpstate(void) 2614 { 2615 u_char csr, asr; 2616 2617 GET_SBIC_asr(debug_sbic_regs,asr); 2618 GET_SBIC_csr(debug_sbic_regs,csr); 2619 printf("%s: asr:csr(%02x:%02x)->(%02x:%02x)\n", 2620 (routine==1)?"sbicgo": 2621 (routine==2)?"sbicintr": 2622 (routine==3)?"sbicicmd": 2623 (routine==4)?"sbicnext":"unknown", 2624 debug_asr, debug_csr, asr, csr); 2625 2626 } 2627 2628 void 2629 sbictimeout(struct sbic_softc *dev) 2630 { 2631 int s, asr; 2632 2633 s = splbio(); 2634 if (dev->sc_dmatimo) { 2635 if (dev->sc_dmatimo > 1) { 2636 printf("%s: DMA timeout #%d\n", 2637 dev->sc_dev.dv_xname, dev->sc_dmatimo - 1); 2638 GET_SBIC_asr(dev->sc_sbic, asr); 2639 if( asr & SBIC_ASR_INT ) { 2640 /* We need to service a missed IRQ */ 2641 printf("Servicing a missed int:(%02x,%02x)->(%02x,?)\n", 2642 debug_asr, debug_csr, asr); 2643 sbicintr(dev); 2644 } 2645 sbicdumpstate(); 2646 } 2647 dev->sc_dmatimo++; 2648 } 2649 splx(s); 2650 callout_reset(&dev->sc_timo_ch, 30 * hz, 2651 (void *)sbictimeout, dev); 2652 } 2653 2654 void 2655 sbic_dump_acb(struct sbic_acb *acb) 2656 { 2657 u_char *b = (u_char *) &acb->cmd; 2658 int i; 2659 2660 printf("acb@%p ", acb); 2661 if (acb->xs == NULL) { 2662 printf("<unused>\n"); 2663 return; 2664 } 2665 printf("(%d:%d) flags %2x clen %2d cmd ", 2666 acb->xs->xs_periph->periph_target, 2667 acb->xs->xs_periph->periph_lun, acb->flags, acb->clen); 2668 for (i = acb->clen; i; --i) 2669 printf(" %02x", *b++); 2670 printf("\n"); 2671 printf(" xs: %8p data %8p:%04x ", acb->xs, acb->xs->data, 2672 acb->xs->datalen); 2673 printf("va %8p:%04x ", acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 2674 printf("pa %8p:%04x tcnt %lx\n", acb->sc_pa.dc_addr, acb->sc_pa.dc_count, 2675 acb->sc_tcnt); 2676 } 2677 2678 void 2679 sbic_dump(struct sbic_softc *dev) 2680 { 2681 sbic_regmap_t regs; 2682 u_char csr, asr; 2683 struct sbic_acb *acb; 2684 int s; 2685 int i; 2686 2687 s = splbio(); 2688 regs = dev->sc_sbic; 2689 #if CSR_TRACE_SIZE 2690 printf("csr trace: "); 2691 i = csr_traceptr; 2692 do { 2693 printf("%c%02x%02x%02x ", csr_trace[i].whr, 2694 csr_trace[i].csr, csr_trace[i].asr, csr_trace[i].xtn); 2695 switch(csr_trace[i].whr) { 2696 case 'g': 2697 printf("go "); break; 2698 case 's': 2699 printf("select "); break; 2700 case 'y': 2701 printf("select+ "); break; 2702 case 'i': 2703 printf("intr "); break; 2704 case 'f': 2705 printf("finish "); break; 2706 case '>': 2707 printf("out "); break; 2708 case '<': 2709 printf("in "); break; 2710 case 'm': 2711 printf("msgin "); break; 2712 case 'x': 2713 printf("msginx "); break; 2714 case 'X': 2715 printf("msginX "); break; 2716 case 'r': 2717 printf("reselect "); break; 2718 case 'I': 2719 printf("icmd "); break; 2720 case 'a': 2721 printf("abort "); break; 2722 default: 2723 printf("? "); 2724 } 2725 switch(csr_trace[i].csr) { 2726 case 0x11: 2727 printf("INITIATOR"); break; 2728 case 0x16: 2729 printf("S_XFERRED"); break; 2730 case 0x20: 2731 printf("MSGIN_ACK"); break; 2732 case 0x41: 2733 printf("DISC"); break; 2734 case 0x42: 2735 printf("SEL_TIMEO"); break; 2736 case 0x80: 2737 printf("RSLT_NI"); break; 2738 case 0x81: 2739 printf("RSLT_IFY"); break; 2740 case 0x85: 2741 printf("DISC_1"); break; 2742 case 0x18: case 0x19: case 0x1a: 2743 case 0x1b: case 0x1e: case 0x1f: 2744 case 0x28: case 0x29: case 0x2a: 2745 case 0x2b: case 0x2e: case 0x2f: 2746 case 0x48: case 0x49: case 0x4a: 2747 case 0x4b: case 0x4e: case 0x4f: 2748 case 0x88: case 0x89: case 0x8a: 2749 case 0x8b: case 0x8e: case 0x8f: 2750 switch(csr_trace[i].csr & 0xf0) { 2751 case 0x10: 2752 printf("DONE_"); break; 2753 case 0x20: 2754 printf("STOP_"); break; 2755 case 0x40: 2756 printf("ERR_"); break; 2757 case 0x80: 2758 printf("REQ_"); break; 2759 } 2760 switch(csr_trace[i].csr & 7) { 2761 case 0: 2762 printf("DATA_OUT"); break; 2763 case 1: 2764 printf("DATA_IN"); break; 2765 case 2: 2766 printf("CMD"); break; 2767 case 3: 2768 printf("STATUS"); break; 2769 case 6: 2770 printf("MSG_OUT"); break; 2771 case 7: 2772 printf("MSG_IN"); break; 2773 default: 2774 printf("invld phs"); 2775 } 2776 break; 2777 default: printf("****"); break; 2778 } 2779 if (csr_trace[i].asr & SBIC_ASR_INT) 2780 printf(" ASR_INT"); 2781 if (csr_trace[i].asr & SBIC_ASR_LCI) 2782 printf(" ASR_LCI"); 2783 if (csr_trace[i].asr & SBIC_ASR_BSY) 2784 printf(" ASR_BSY"); 2785 if (csr_trace[i].asr & SBIC_ASR_CIP) 2786 printf(" ASR_CIP"); 2787 printf("\n"); 2788 i = (i + 1) & (CSR_TRACE_SIZE - 1); 2789 } while (i != csr_traceptr); 2790 #endif 2791 GET_SBIC_asr(regs, asr); 2792 if ((asr & SBIC_ASR_INT) == 0) 2793 GET_SBIC_csr(regs, csr); 2794 else 2795 csr = 0; 2796 printf("%s@%p regs %p/%p asr %x csr %x\n", dev->sc_dev.dv_xname, 2797 dev, regs.sbic_asr_p, regs.sbic_value_p, asr, csr); 2798 if ((acb = dev->free_list.tqh_first)) { 2799 printf("Free list:\n"); 2800 while (acb) { 2801 sbic_dump_acb(acb); 2802 acb = acb->chain.tqe_next; 2803 } 2804 } 2805 if ((acb = dev->ready_list.tqh_first)) { 2806 printf("Ready list:\n"); 2807 while (acb) { 2808 sbic_dump_acb(acb); 2809 acb = acb->chain.tqe_next; 2810 } 2811 } 2812 if ((acb = dev->nexus_list.tqh_first)) { 2813 printf("Nexus list:\n"); 2814 while (acb) { 2815 sbic_dump_acb(acb); 2816 acb = acb->chain.tqe_next; 2817 } 2818 } 2819 if (dev->sc_nexus) { 2820 printf("nexus:\n"); 2821 sbic_dump_acb(dev->sc_nexus); 2822 } 2823 printf("sc_xs %p targ %d lun %d flags %x tcnt %lx dmacmd %x mask %lx\n", 2824 dev->sc_xs, dev->target, dev->lun, dev->sc_flags, dev->sc_tcnt, 2825 dev->sc_dmacmd, dev->sc_dmamask); 2826 for (i = 0; i < 8; ++i) { 2827 if (dev->sc_tinfo[i].cmds > 2) { 2828 printf("tgt %d: cmds %d disc %d lubusy %x\n", 2829 i, dev->sc_tinfo[i].cmds, 2830 dev->sc_tinfo[i].dconns, 2831 dev->sc_tinfo[i].lubusy); 2832 } 2833 } 2834 splx(s); 2835 } 2836 2837 #endif 2838
Indexes created Thu Oct 02 14:10:14 GMT 2025