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sbicvar.h revision 1.1
      1 /*
      2  * Copyright (c) 1990 The Regents of the University of California.
      3  * All rights reserved.
      4  *
      5  * This code is derived from software contributed to Berkeley by
      6  * Van Jacobson of Lawrence Berkeley Laboratory.
      7  *
      8  * Redistribution and use in source and binary forms, with or without
      9  * modification, are permitted provided that the following conditions
     10  * are met:
     11  * 1. Redistributions of source code must retain the above copyright
     12  *    notice, this list of conditions and the following disclaimer.
     13  * 2. Redistributions in binary form must reproduce the above copyright
     14  *    notice, this list of conditions and the following disclaimer in the
     15  *    documentation and/or other materials provided with the distribution.
     16  * 3. All advertising materials mentioning features or use of this software
     17  *    must display the following acknowledgement:
     18  *	This product includes software developed by the University of
     19  *	California, Berkeley and its contributors.
     20  * 4. Neither the name of the University nor the names of its contributors
     21  *    may be used to endorse or promote products derived from this software
     22  *    without specific prior written permission.
     23  *
     24  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
     25  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     26  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     27  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
     28  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     29  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     30  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     31  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     32  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     33  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     34  * SUCH DAMAGE.
     35  *
     36  *	@(#)scsivar.h	7.1 (Berkeley) 5/8/90
     37  *	$Id: sbicvar.h,v 1.1 1994/05/08 05:53:39 chopps Exp $
     38  */
     39 #ifndef _SBICVAR_H_
     40 #define _SBICVAR_H_
     41 
     42 /*
     43  * The largest single request will be MAXPHYS bytes which will require
     44  * at most MAXPHYS/NBPG+1 chain elements to describe, i.e. if none of
     45  * the buffer pages are physically contiguous (MAXPHYS/NBPG) and the
     46  * buffer is not page aligned (+1).
     47  */
     48 #define	DMAMAXIO	(MAXPHYS/NBPG+1)
     49 
     50 struct	dma_chain {
     51 	int	dc_count;
     52 	char	*dc_addr;
     53 };
     54 
     55 struct	sbic_pending {
     56 	TAILQ_ENTRY(sbic_pending) link;
     57 	struct scsi_xfer *xs;
     58 };
     59 
     60 struct	sbic_softc {
     61 	struct	device sc_dev;
     62 	struct	target_sync {
     63 		u_char	state;
     64 		u_char	period;
     65 		u_char	offset;
     66 	} sc_sync[8];
     67 	struct	scsi_link sc_link;	/* proto for sub devices */
     68 	sbic_regmap_p	sc_sbicp;	/* the SBIC */
     69 	volatile void 	*sc_cregs;	/* driver specific regs */
     70 	TAILQ_HEAD(,sbic_pending) sc_xslist;	/* LIFO */
     71 	struct	sbic_pending sc_xsstore[8][8];	/* one for every unit */
     72 	struct	scsi_xfer *sc_xs;	/* transfer from high level code */
     73 	u_char	sc_flags;
     74 	u_char	sc_scsiaddr;
     75 	u_char	sc_stat[2];
     76 	u_char	sc_msg[7];
     77 	u_long	sc_clkfreq;
     78 	u_long	sc_tcnt;		/* number of bytes transfered */
     79 	u_char *sc_dmabuffer;
     80 	u_char *sc_dmausrbuf;
     81 	u_long  sc_dmausrlen;
     82 	u_short sc_dmacmd;		/* used by dma drivers */
     83 	u_short	sc_dmatimo;		/* dma timeout */
     84 	u_long	sc_dmamask;		/* dma valid mem mask */
     85 	struct	dma_chain sc_chain[DMAMAXIO];
     86 	struct	dma_chain *sc_cur;
     87 	struct	dma_chain *sc_last;
     88 	int  (*sc_dmago)	__P((struct sbic_softc *, char *, int, int));
     89 	int  (*sc_dmanext)	__P((struct sbic_softc *));
     90 	void (*sc_dmafree)	__P((struct sbic_softc *));
     91 	void (*sc_dmastop)	__P((struct sbic_softc *));
     92 	u_short	gtsc_bankmask;		/* GVP specific bank selected */
     93 };
     94 
     95 /* sc_flags */
     96 #define	SBICF_ALIVE	0x01	/* controller initialized */
     97 #define SBICF_SELECTED	0x04	/* bus is in selected state. */
     98 #define SBICF_BADDMA	0x10	/* controller can only DMA to ztwobus space */
     99 #define SBICF_BBUF	0x20	/* DMA input needs to be copied from bounce */
    100 #define	SBICF_INTR	0x40	/* SBICF interrupt expected */
    101 #define	SBICF_INDMA	0x80	/* not used yet, DMA I/O in progress */
    102 
    103 /* sync states */
    104 #define SYNC_START	0	/* no sync handshake started */
    105 #define SYNC_SENT	1	/* we sent sync request, no answer yet */
    106 #define SYNC_DONE	2	/* target accepted our (or inferior) settings,
    107 				   or it rejected the request and we stay async */
    108 #ifdef DEBUG
    109 #define	DDB_FOLLOW	0x04
    110 #define DDB_IO		0x08
    111 #endif
    112 extern int sbic_inhibit_sync;
    113 extern int sbic_no_dma;
    114 extern int sbic_clock_override;
    115 
    116 #define	PHASE		0x07		/* mask for psns/pctl phase */
    117 #define	DATA_OUT_PHASE	0x00
    118 #define	DATA_IN_PHASE	0x01
    119 #define	CMD_PHASE	0x02
    120 #define	STATUS_PHASE	0x03
    121 #define	BUS_FREE_PHASE	0x04
    122 #define	ARB_SEL_PHASE	0x05	/* Fuji chip combines arbitration with sel. */
    123 #define	MESG_OUT_PHASE	0x06
    124 #define	MESG_IN_PHASE	0x07
    125 
    126 #define	MSG_CMD_COMPLETE	0x00
    127 #define MSG_EXT_MESSAGE		0x01
    128 #define	MSG_SAVE_DATA_PTR	0x02
    129 #define	MSG_RESTORE_PTR		0x03
    130 #define	MSG_DISCONNECT		0x04
    131 #define	MSG_INIT_DETECT_ERROR	0x05
    132 #define	MSG_ABORT		0x06
    133 #define	MSG_REJECT		0x07
    134 #define	MSG_NOOP		0x08
    135 #define	MSG_PARITY_ERROR	0x09
    136 #define	MSG_BUS_DEVICE_RESET	0x0C
    137 #define	MSG_IDENTIFY		0x80
    138 #define	MSG_IDENTIFY_DR		0xc0	/* (disconnect/reconnect allowed) */
    139 #define	MSG_SYNC_REQ 		0x01
    140 
    141 
    142 #define	STS_CHECKCOND	0x02	/* Check Condition (ie., read sense) */
    143 #define	STS_CONDMET	0x04	/* Condition Met (ie., search worked) */
    144 #define	STS_BUSY	0x08
    145 #define	STS_INTERMED	0x10	/* Intermediate status sent */
    146 #define	STS_EXT		0x80	/* Extended status valid */
    147 
    148 /*
    149  * XXXX
    150  */
    151 struct scsi_fmt_cdb {
    152 	int len;		/* cdb length (in bytes) */
    153 	u_char cdb[28];		/* cdb to use on next read/write */
    154 };
    155 
    156 struct buf;
    157 struct scsi_xfer;
    158 
    159 void sbic_minphys __P((struct buf *bp));
    160 u_int sbic_adinfo __P((void));
    161 int sbic_scsicmd __P((struct scsi_xfer *));
    162 
    163 #endif /* _SBICVAR_H_ */
    164