sci.c revision 1.25.8.2 1 1.25.8.2 nathanw /* $NetBSD: sci.c,v 1.25.8.2 2002/02/28 04:06:59 nathanw Exp $ */
2 1.25.8.2 nathanw
3 1.25.8.2 nathanw /*
4 1.25.8.2 nathanw * Copyright (c) 1994 Michael L. Hitch
5 1.25.8.2 nathanw * Copyright (c) 1990 The Regents of the University of California.
6 1.25.8.2 nathanw * All rights reserved.
7 1.25.8.2 nathanw *
8 1.25.8.2 nathanw * This code is derived from software contributed to Berkeley by
9 1.25.8.2 nathanw * Van Jacobson of Lawrence Berkeley Laboratory.
10 1.25.8.2 nathanw *
11 1.25.8.2 nathanw * Redistribution and use in source and binary forms, with or without
12 1.25.8.2 nathanw * modification, are permitted provided that the following conditions
13 1.25.8.2 nathanw * are met:
14 1.25.8.2 nathanw * 1. Redistributions of source code must retain the above copyright
15 1.25.8.2 nathanw * notice, this list of conditions and the following disclaimer.
16 1.25.8.2 nathanw * 2. Redistributions in binary form must reproduce the above copyright
17 1.25.8.2 nathanw * notice, this list of conditions and the following disclaimer in the
18 1.25.8.2 nathanw * documentation and/or other materials provided with the distribution.
19 1.25.8.2 nathanw * 3. All advertising materials mentioning features or use of this software
20 1.25.8.2 nathanw * must display the following acknowledgement:
21 1.25.8.2 nathanw * This product includes software developed by the University of
22 1.25.8.2 nathanw * California, Berkeley and its contributors.
23 1.25.8.2 nathanw * 4. Neither the name of the University nor the names of its contributors
24 1.25.8.2 nathanw * may be used to endorse or promote products derived from this software
25 1.25.8.2 nathanw * without specific prior written permission.
26 1.25.8.2 nathanw *
27 1.25.8.2 nathanw * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
28 1.25.8.2 nathanw * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29 1.25.8.2 nathanw * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
30 1.25.8.2 nathanw * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
31 1.25.8.2 nathanw * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 1.25.8.2 nathanw * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 1.25.8.2 nathanw * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 1.25.8.2 nathanw * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
35 1.25.8.2 nathanw * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
36 1.25.8.2 nathanw * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 1.25.8.2 nathanw * SUCH DAMAGE.
38 1.25.8.2 nathanw *
39 1.25.8.2 nathanw * @(#)scsi.c 7.5 (Berkeley) 5/4/91
40 1.25.8.2 nathanw */
41 1.25.8.2 nathanw
42 1.25.8.2 nathanw /*
43 1.25.8.2 nathanw * AMIGA NCR 5380 scsi adaptor driver
44 1.25.8.2 nathanw */
45 1.25.8.2 nathanw
46 1.25.8.2 nathanw #include <sys/cdefs.h>
47 1.25.8.2 nathanw __KERNEL_RCSID(0, "$NetBSD: sci.c,v 1.25.8.2 2002/02/28 04:06:59 nathanw Exp $");
48 1.25.8.2 nathanw
49 1.25.8.2 nathanw #include <sys/param.h>
50 1.25.8.2 nathanw #include <sys/systm.h>
51 1.25.8.2 nathanw #include <sys/device.h>
52 1.25.8.2 nathanw #include <sys/disklabel.h>
53 1.25.8.2 nathanw #include <sys/dkstat.h>
54 1.25.8.2 nathanw #include <sys/buf.h>
55 1.25.8.2 nathanw #include <dev/scsipi/scsi_all.h>
56 1.25.8.2 nathanw #include <dev/scsipi/scsipi_all.h>
57 1.25.8.2 nathanw #include <dev/scsipi/scsiconf.h>
58 1.25.8.2 nathanw #include <uvm/uvm_extern.h>
59 1.25.8.2 nathanw #include <machine/pmap.h>
60 1.25.8.2 nathanw #include <machine/cpu.h>
61 1.25.8.2 nathanw #include <amiga/amiga/device.h>
62 1.25.8.2 nathanw #include <amiga/amiga/custom.h>
63 1.25.8.2 nathanw #include <amiga/amiga/isr.h>
64 1.25.8.2 nathanw #include <amiga/dev/scireg.h>
65 1.25.8.2 nathanw #include <amiga/dev/scivar.h>
66 1.25.8.2 nathanw
67 1.25.8.2 nathanw /*
68 1.25.8.2 nathanw * SCSI delays
69 1.25.8.2 nathanw * In u-seconds, primarily for state changes on the SPC.
70 1.25.8.2 nathanw */
71 1.25.8.2 nathanw #define SCI_CMD_WAIT 50000 /* wait per step of 'immediate' cmds */
72 1.25.8.2 nathanw #define SCI_DATA_WAIT 50000 /* wait per data in/out step */
73 1.25.8.2 nathanw #define SCI_INIT_WAIT 50000 /* wait per step (both) during init */
74 1.25.8.2 nathanw
75 1.25.8.2 nathanw int sciicmd(struct sci_softc *, int, void *, int, void *, int,u_char);
76 1.25.8.2 nathanw int scigo(struct sci_softc *, struct scsipi_xfer *);
77 1.25.8.2 nathanw int sciselectbus(struct sci_softc *, u_char, u_char);
78 1.25.8.2 nathanw void sciabort(struct sci_softc *, char *);
79 1.25.8.2 nathanw void scierror(struct sci_softc *, u_char);
80 1.25.8.2 nathanw void scisetdelay(int);
81 1.25.8.2 nathanw void sci_scsidone(struct sci_softc *, int);
82 1.25.8.2 nathanw void sci_donextcmd(struct sci_softc *);
83 1.25.8.2 nathanw int sci_ixfer_out(struct sci_softc *, int, register u_char *, int);
84 1.25.8.2 nathanw void sci_ixfer_in(struct sci_softc *, int, register u_char *, int);
85 1.25.8.2 nathanw
86 1.25.8.2 nathanw int sci_cmd_wait = SCI_CMD_WAIT;
87 1.25.8.2 nathanw int sci_data_wait = SCI_DATA_WAIT;
88 1.25.8.2 nathanw int sci_init_wait = SCI_INIT_WAIT;
89 1.25.8.2 nathanw
90 1.25.8.2 nathanw int sci_no_dma = 0;
91 1.25.8.2 nathanw
92 1.25.8.2 nathanw #ifdef DEBUG
93 1.25.8.2 nathanw #define QPRINTF(a) if (sci_debug > 1) printf a
94 1.25.8.2 nathanw int sci_debug = 0;
95 1.25.8.2 nathanw #else
96 1.25.8.2 nathanw #define QPRINTF(a)
97 1.25.8.2 nathanw #endif
98 1.25.8.2 nathanw
99 1.25.8.2 nathanw /*
100 1.25.8.2 nathanw * default minphys routine for sci based controllers
101 1.25.8.2 nathanw */
102 1.25.8.2 nathanw void
103 1.25.8.2 nathanw sci_minphys(struct buf *bp)
104 1.25.8.2 nathanw {
105 1.25.8.2 nathanw
106 1.25.8.2 nathanw /*
107 1.25.8.2 nathanw * No max transfer at this level.
108 1.25.8.2 nathanw */
109 1.25.8.2 nathanw minphys(bp);
110 1.25.8.2 nathanw }
111 1.25.8.2 nathanw
112 1.25.8.2 nathanw /*
113 1.25.8.2 nathanw * used by specific sci controller
114 1.25.8.2 nathanw *
115 1.25.8.2 nathanw * it appears that the higher level code does nothing with LUN's
116 1.25.8.2 nathanw * so I will too. I could plug it in, however so could they
117 1.25.8.2 nathanw * in scsi_scsipi_cmd().
118 1.25.8.2 nathanw */
119 1.25.8.2 nathanw void
120 1.25.8.2 nathanw sci_scsipi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req,
121 1.25.8.2 nathanw void *arg)
122 1.25.8.2 nathanw {
123 1.25.8.2 nathanw struct scsipi_xfer *xs;
124 1.25.8.2 nathanw struct scsipi_periph *periph;
125 1.25.8.2 nathanw struct sci_softc *dev = (void *)chan->chan_adapter->adapt_dev;
126 1.25.8.2 nathanw int flags, s;
127 1.25.8.2 nathanw
128 1.25.8.2 nathanw switch (req) {
129 1.25.8.2 nathanw case ADAPTER_REQ_RUN_XFER:
130 1.25.8.2 nathanw xs = arg;
131 1.25.8.2 nathanw periph = xs->xs_periph;
132 1.25.8.2 nathanw flags = xs->xs_control;
133 1.25.8.2 nathanw
134 1.25.8.2 nathanw if (flags & XS_CTL_DATA_UIO)
135 1.25.8.2 nathanw panic("sci: scsi data uio requested");
136 1.25.8.2 nathanw
137 1.25.8.2 nathanw if (dev->sc_xs && flags & XS_CTL_POLL)
138 1.25.8.2 nathanw panic("sci_scsicmd: busy");
139 1.25.8.2 nathanw
140 1.25.8.2 nathanw #ifdef DIAGNOSTIC
141 1.25.8.2 nathanw /*
142 1.25.8.2 nathanw * This should never happen as we track the resources
143 1.25.8.2 nathanw * in the mid-layer.
144 1.25.8.2 nathanw */
145 1.25.8.2 nathanw if (dev->sc_xs) {
146 1.25.8.2 nathanw scsipi_printaddr(periph);
147 1.25.8.2 nathanw printf("unable to allocate scb\n");
148 1.25.8.2 nathanw panic("sea_scsipi_request");
149 1.25.8.2 nathanw }
150 1.25.8.2 nathanw #endif
151 1.25.8.2 nathanw
152 1.25.8.2 nathanw dev->sc_xs = xs;
153 1.25.8.2 nathanw splx(s);
154 1.25.8.2 nathanw
155 1.25.8.2 nathanw /*
156 1.25.8.2 nathanw * nothing is pending do it now.
157 1.25.8.2 nathanw */
158 1.25.8.2 nathanw sci_donextcmd(dev);
159 1.25.8.2 nathanw
160 1.25.8.2 nathanw return;
161 1.25.8.2 nathanw
162 1.25.8.2 nathanw case ADAPTER_REQ_GROW_RESOURCES:
163 1.25.8.2 nathanw return;
164 1.25.8.2 nathanw
165 1.25.8.2 nathanw case ADAPTER_REQ_SET_XFER_MODE:
166 1.25.8.2 nathanw return;
167 1.25.8.2 nathanw }
168 1.25.8.2 nathanw }
169 1.25.8.2 nathanw
170 1.25.8.2 nathanw /*
171 1.25.8.2 nathanw * entered with dev->sc_xs pointing to the next xfer to perform
172 1.25.8.2 nathanw */
173 1.25.8.2 nathanw void
174 1.25.8.2 nathanw sci_donextcmd(struct sci_softc *dev)
175 1.25.8.2 nathanw {
176 1.25.8.2 nathanw struct scsipi_xfer *xs;
177 1.25.8.2 nathanw struct scsipi_periph *periph;
178 1.25.8.2 nathanw int flags, phase, stat;
179 1.25.8.2 nathanw
180 1.25.8.2 nathanw xs = dev->sc_xs;
181 1.25.8.2 nathanw periph = xs->xs_periph;
182 1.25.8.2 nathanw flags = xs->xs_control;
183 1.25.8.2 nathanw
184 1.25.8.2 nathanw if (flags & XS_CTL_DATA_IN)
185 1.25.8.2 nathanw phase = DATA_IN_PHASE;
186 1.25.8.2 nathanw else if (flags & XS_CTL_DATA_OUT)
187 1.25.8.2 nathanw phase = DATA_OUT_PHASE;
188 1.25.8.2 nathanw else
189 1.25.8.2 nathanw phase = STATUS_PHASE;
190 1.25.8.2 nathanw
191 1.25.8.2 nathanw if (flags & XS_CTL_RESET)
192 1.25.8.2 nathanw scireset(dev);
193 1.25.8.2 nathanw
194 1.25.8.2 nathanw dev->sc_stat[0] = -1;
195 1.25.8.2 nathanw xs->cmd->bytes[0] |= periph->periph_lun << 5;
196 1.25.8.2 nathanw if (phase == STATUS_PHASE || flags & XS_CTL_POLL)
197 1.25.8.2 nathanw stat = sciicmd(dev, periph->periph_target, xs->cmd, xs->cmdlen,
198 1.25.8.2 nathanw xs->data, xs->datalen, phase);
199 1.25.8.2 nathanw else if (scigo(dev, xs) == 0)
200 1.25.8.2 nathanw return;
201 1.25.8.2 nathanw else
202 1.25.8.2 nathanw stat = dev->sc_stat[0];
203 1.25.8.2 nathanw
204 1.25.8.2 nathanw sci_scsidone(dev, stat);
205 1.25.8.2 nathanw }
206 1.25.8.2 nathanw
207 1.25.8.2 nathanw void
208 1.25.8.2 nathanw sci_scsidone(struct sci_softc *dev, int stat)
209 1.25.8.2 nathanw {
210 1.25.8.2 nathanw struct scsipi_xfer *xs;
211 1.25.8.2 nathanw
212 1.25.8.2 nathanw xs = dev->sc_xs;
213 1.25.8.2 nathanw #ifdef DIAGNOSTIC
214 1.25.8.2 nathanw if (xs == NULL)
215 1.25.8.2 nathanw panic("sci_scsidone");
216 1.25.8.2 nathanw #endif
217 1.25.8.2 nathanw xs->status = stat;
218 1.25.8.2 nathanw if (stat == 0)
219 1.25.8.2 nathanw xs->resid = 0;
220 1.25.8.2 nathanw else {
221 1.25.8.2 nathanw switch(stat) {
222 1.25.8.2 nathanw case SCSI_CHECK:
223 1.25.8.2 nathanw xs->resid = 0;
224 1.25.8.2 nathanw /* FALLTHOUGH */
225 1.25.8.2 nathanw case SCSI_BUSY:
226 1.25.8.2 nathanw xs->error = XS_BUSY;
227 1.25.8.2 nathanw break;
228 1.25.8.2 nathanw default:
229 1.25.8.2 nathanw xs->error = XS_DRIVER_STUFFUP;
230 1.25.8.2 nathanw QPRINTF(("sci_scsicmd() bad %x\n", stat));
231 1.25.8.2 nathanw break;
232 1.25.8.2 nathanw }
233 1.25.8.2 nathanw }
234 1.25.8.2 nathanw
235 1.25.8.2 nathanw scsipi_done(xs);
236 1.25.8.2 nathanw
237 1.25.8.2 nathanw }
238 1.25.8.2 nathanw
239 1.25.8.2 nathanw void
240 1.25.8.2 nathanw sciabort(struct sci_softc *dev, char *where)
241 1.25.8.2 nathanw {
242 1.25.8.2 nathanw printf ("%s: abort %s: csr = 0x%02x, bus = 0x%02x\n",
243 1.25.8.2 nathanw dev->sc_dev.dv_xname, where, *dev->sci_csr, *dev->sci_bus_csr);
244 1.25.8.2 nathanw
245 1.25.8.2 nathanw if (dev->sc_flags & SCI_SELECTED) {
246 1.25.8.2 nathanw
247 1.25.8.2 nathanw /* lets just hope it worked.. */
248 1.25.8.2 nathanw dev->sc_flags &= ~SCI_SELECTED;
249 1.25.8.2 nathanw /* XXX */
250 1.25.8.2 nathanw scireset (dev);
251 1.25.8.2 nathanw }
252 1.25.8.2 nathanw }
253 1.25.8.2 nathanw
254 1.25.8.2 nathanw /*
255 1.25.8.2 nathanw * XXX Set/reset long delays.
256 1.25.8.2 nathanw *
257 1.25.8.2 nathanw * if delay == 0, reset default delays
258 1.25.8.2 nathanw * if delay < 0, set both delays to default long initialization values
259 1.25.8.2 nathanw * if delay > 0, set both delays to this value
260 1.25.8.2 nathanw *
261 1.25.8.2 nathanw * Used when a devices is expected to respond slowly (e.g. during
262 1.25.8.2 nathanw * initialization).
263 1.25.8.2 nathanw */
264 1.25.8.2 nathanw void
265 1.25.8.2 nathanw scisetdelay(int del)
266 1.25.8.2 nathanw {
267 1.25.8.2 nathanw static int saved_cmd_wait, saved_data_wait;
268 1.25.8.2 nathanw
269 1.25.8.2 nathanw if (del) {
270 1.25.8.2 nathanw saved_cmd_wait = sci_cmd_wait;
271 1.25.8.2 nathanw saved_data_wait = sci_data_wait;
272 1.25.8.2 nathanw if (del > 0)
273 1.25.8.2 nathanw sci_cmd_wait = sci_data_wait = del;
274 1.25.8.2 nathanw else
275 1.25.8.2 nathanw sci_cmd_wait = sci_data_wait = sci_init_wait;
276 1.25.8.2 nathanw } else {
277 1.25.8.2 nathanw sci_cmd_wait = saved_cmd_wait;
278 1.25.8.2 nathanw sci_data_wait = saved_data_wait;
279 1.25.8.2 nathanw }
280 1.25.8.2 nathanw }
281 1.25.8.2 nathanw
282 1.25.8.2 nathanw void
283 1.25.8.2 nathanw scireset(struct sci_softc *dev)
284 1.25.8.2 nathanw {
285 1.25.8.2 nathanw u_int s;
286 1.25.8.2 nathanw u_char my_id;
287 1.25.8.2 nathanw
288 1.25.8.2 nathanw dev->sc_flags &= ~SCI_SELECTED;
289 1.25.8.2 nathanw if (dev->sc_flags & SCI_ALIVE)
290 1.25.8.2 nathanw sciabort(dev, "reset");
291 1.25.8.2 nathanw
292 1.25.8.2 nathanw printf("%s: ", dev->sc_dev.dv_xname);
293 1.25.8.2 nathanw
294 1.25.8.2 nathanw s = splbio();
295 1.25.8.2 nathanw /* preserve our ID for now */
296 1.25.8.2 nathanw my_id = 7;
297 1.25.8.2 nathanw
298 1.25.8.2 nathanw /*
299 1.25.8.2 nathanw * Reset the chip
300 1.25.8.2 nathanw */
301 1.25.8.2 nathanw *dev->sci_icmd = SCI_ICMD_TEST;
302 1.25.8.2 nathanw *dev->sci_icmd = SCI_ICMD_TEST | SCI_ICMD_RST;
303 1.25.8.2 nathanw delay (25);
304 1.25.8.2 nathanw *dev->sci_icmd = 0;
305 1.25.8.2 nathanw
306 1.25.8.2 nathanw /*
307 1.25.8.2 nathanw * Set up various chip parameters
308 1.25.8.2 nathanw */
309 1.25.8.2 nathanw *dev->sci_icmd = 0;
310 1.25.8.2 nathanw *dev->sci_tcmd = 0;
311 1.25.8.2 nathanw *dev->sci_sel_enb = 0;
312 1.25.8.2 nathanw
313 1.25.8.2 nathanw /* anything else was zeroed by reset */
314 1.25.8.2 nathanw
315 1.25.8.2 nathanw splx (s);
316 1.25.8.2 nathanw
317 1.25.8.2 nathanw printf("sci id %d\n", my_id);
318 1.25.8.2 nathanw dev->sc_flags |= SCI_ALIVE;
319 1.25.8.2 nathanw }
320 1.25.8.2 nathanw
321 1.25.8.2 nathanw void
322 1.25.8.2 nathanw scierror(struct sci_softc *dev, u_char csr)
323 1.25.8.2 nathanw {
324 1.25.8.2 nathanw struct scsipi_xfer *xs;
325 1.25.8.2 nathanw
326 1.25.8.2 nathanw xs = dev->sc_xs;
327 1.25.8.2 nathanw
328 1.25.8.2 nathanw #ifdef DIAGNOSTIC
329 1.25.8.2 nathanw if (xs == NULL)
330 1.25.8.2 nathanw panic("scierror");
331 1.25.8.2 nathanw #endif
332 1.25.8.2 nathanw if (xs->xs_control & XS_CTL_SILENT)
333 1.25.8.2 nathanw return;
334 1.25.8.2 nathanw
335 1.25.8.2 nathanw printf("%s: ", dev->sc_dev.dv_xname);
336 1.25.8.2 nathanw printf("csr == 0x%02i\n", csr); /* XXX */
337 1.25.8.2 nathanw }
338 1.25.8.2 nathanw
339 1.25.8.2 nathanw /*
340 1.25.8.2 nathanw * select the bus, return when selected or error.
341 1.25.8.2 nathanw */
342 1.25.8.2 nathanw int
343 1.25.8.2 nathanw sciselectbus(struct sci_softc *dev, u_char target, u_char our_addr)
344 1.25.8.2 nathanw {
345 1.25.8.2 nathanw register int timeo = 2500;
346 1.25.8.2 nathanw
347 1.25.8.2 nathanw QPRINTF (("sciselectbus %d\n", target));
348 1.25.8.2 nathanw
349 1.25.8.2 nathanw /* if we're already selected, return */
350 1.25.8.2 nathanw if (dev->sc_flags & SCI_SELECTED) /* XXXX */
351 1.25.8.2 nathanw return 1;
352 1.25.8.2 nathanw
353 1.25.8.2 nathanw if ((*dev->sci_bus_csr & (SCI_BUS_BSY|SCI_BUS_SEL)) &&
354 1.25.8.2 nathanw (*dev->sci_bus_csr & (SCI_BUS_BSY|SCI_BUS_SEL)) &&
355 1.25.8.2 nathanw (*dev->sci_bus_csr & (SCI_BUS_BSY|SCI_BUS_SEL)))
356 1.25.8.2 nathanw return 1;
357 1.25.8.2 nathanw
358 1.25.8.2 nathanw *dev->sci_tcmd = 0;
359 1.25.8.2 nathanw *dev->sci_odata = 0x80 + (1 << target);
360 1.25.8.2 nathanw *dev->sci_icmd = SCI_ICMD_DATA|SCI_ICMD_SEL;
361 1.25.8.2 nathanw while ((*dev->sci_bus_csr & SCI_BUS_BSY) == 0) {
362 1.25.8.2 nathanw if (--timeo > 0) {
363 1.25.8.2 nathanw delay(100);
364 1.25.8.2 nathanw } else {
365 1.25.8.2 nathanw break;
366 1.25.8.2 nathanw }
367 1.25.8.2 nathanw }
368 1.25.8.2 nathanw if (timeo) {
369 1.25.8.2 nathanw *dev->sci_icmd = 0;
370 1.25.8.2 nathanw dev->sc_flags |= SCI_SELECTED;
371 1.25.8.2 nathanw return (0);
372 1.25.8.2 nathanw }
373 1.25.8.2 nathanw *dev->sci_icmd = 0;
374 1.25.8.2 nathanw return (1);
375 1.25.8.2 nathanw }
376 1.25.8.2 nathanw
377 1.25.8.2 nathanw int
378 1.25.8.2 nathanw sci_ixfer_out(register struct sci_softc *dev, int len, register u_char *buf,
379 1.25.8.2 nathanw int phase)
380 1.25.8.2 nathanw {
381 1.25.8.2 nathanw register int wait = sci_data_wait;
382 1.25.8.2 nathanw u_char csr;
383 1.25.8.2 nathanw
384 1.25.8.2 nathanw QPRINTF(("sci_ixfer_out {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
385 1.25.8.2 nathanw len, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5],
386 1.25.8.2 nathanw buf[6], buf[7], buf[8], buf[9]));
387 1.25.8.2 nathanw
388 1.25.8.2 nathanw *dev->sci_tcmd = phase;
389 1.25.8.2 nathanw *dev->sci_icmd = SCI_ICMD_DATA;
390 1.25.8.2 nathanw for (;len > 0; len--) {
391 1.25.8.2 nathanw csr = *dev->sci_bus_csr;
392 1.25.8.2 nathanw while (!(csr & SCI_BUS_REQ)) {
393 1.25.8.2 nathanw if ((csr & SCI_BUS_BSY) == 0 || --wait < 0) {
394 1.25.8.2 nathanw #ifdef DEBUG
395 1.25.8.2 nathanw if (sci_debug)
396 1.25.8.2 nathanw printf("sci_ixfer_out fail: l%d i%x w%d\n",
397 1.25.8.2 nathanw len, csr, wait);
398 1.25.8.2 nathanw #endif
399 1.25.8.2 nathanw return (len);
400 1.25.8.2 nathanw }
401 1.25.8.2 nathanw delay(1);
402 1.25.8.2 nathanw csr = *dev->sci_bus_csr;
403 1.25.8.2 nathanw }
404 1.25.8.2 nathanw
405 1.25.8.2 nathanw if (!(*dev->sci_csr & SCI_CSR_PHASE_MATCH))
406 1.25.8.2 nathanw break;
407 1.25.8.2 nathanw *dev->sci_odata = *buf;
408 1.25.8.2 nathanw *dev->sci_icmd = SCI_ICMD_DATA|SCI_ICMD_ACK;
409 1.25.8.2 nathanw buf++;
410 1.25.8.2 nathanw while (*dev->sci_bus_csr & SCI_BUS_REQ);
411 1.25.8.2 nathanw *dev->sci_icmd = SCI_ICMD_DATA;
412 1.25.8.2 nathanw }
413 1.25.8.2 nathanw
414 1.25.8.2 nathanw QPRINTF(("sci_ixfer_out done\n"));
415 1.25.8.2 nathanw return (0);
416 1.25.8.2 nathanw }
417 1.25.8.2 nathanw
418 1.25.8.2 nathanw void
419 1.25.8.2 nathanw sci_ixfer_in(struct sci_softc *dev, int len, register u_char *buf, int phase)
420 1.25.8.2 nathanw {
421 1.25.8.2 nathanw int wait = sci_data_wait;
422 1.25.8.2 nathanw u_char csr;
423 1.25.8.2 nathanw volatile register u_char *sci_bus_csr = dev->sci_bus_csr;
424 1.25.8.2 nathanw volatile register u_char *sci_data = dev->sci_data;
425 1.25.8.2 nathanw volatile register u_char *sci_icmd = dev->sci_icmd;
426 1.25.8.2 nathanw #ifdef DEBUG
427 1.25.8.2 nathanw u_char *obp = buf;
428 1.25.8.2 nathanw #endif
429 1.25.8.2 nathanw
430 1.25.8.2 nathanw csr = *sci_bus_csr;
431 1.25.8.2 nathanw
432 1.25.8.2 nathanw QPRINTF(("sci_ixfer_in %d, csr=%02x\n", len, csr));
433 1.25.8.2 nathanw
434 1.25.8.2 nathanw *dev->sci_tcmd = phase;
435 1.25.8.2 nathanw *sci_icmd = 0;
436 1.25.8.2 nathanw for (;len > 0; len--) {
437 1.25.8.2 nathanw csr = *sci_bus_csr;
438 1.25.8.2 nathanw while (!(csr & SCI_BUS_REQ)) {
439 1.25.8.2 nathanw if (!(csr & SCI_BUS_BSY) || --wait < 0) {
440 1.25.8.2 nathanw #ifdef DEBUG
441 1.25.8.2 nathanw if (sci_debug)
442 1.25.8.2 nathanw printf("sci_ixfer_in fail: l%d i%x w%d\n",
443 1.25.8.2 nathanw len, csr, wait);
444 1.25.8.2 nathanw #endif
445 1.25.8.2 nathanw return;
446 1.25.8.2 nathanw }
447 1.25.8.2 nathanw
448 1.25.8.2 nathanw delay(1);
449 1.25.8.2 nathanw csr = *sci_bus_csr;
450 1.25.8.2 nathanw }
451 1.25.8.2 nathanw
452 1.25.8.2 nathanw if (!(*dev->sci_csr & SCI_CSR_PHASE_MATCH))
453 1.25.8.2 nathanw break;
454 1.25.8.2 nathanw *buf = *sci_data;
455 1.25.8.2 nathanw *sci_icmd = SCI_ICMD_ACK;
456 1.25.8.2 nathanw buf++;
457 1.25.8.2 nathanw while (*sci_bus_csr & SCI_BUS_REQ);
458 1.25.8.2 nathanw *sci_icmd = 0;
459 1.25.8.2 nathanw }
460 1.25.8.2 nathanw
461 1.25.8.2 nathanw QPRINTF(("sci_ixfer_in {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
462 1.25.8.2 nathanw len, obp[0], obp[1], obp[2], obp[3], obp[4], obp[5],
463 1.25.8.2 nathanw obp[6], obp[7], obp[8], obp[9]));
464 1.25.8.2 nathanw }
465 1.25.8.2 nathanw
466 1.25.8.2 nathanw /*
467 1.25.8.2 nathanw * SCSI 'immediate' command: issue a command to some SCSI device
468 1.25.8.2 nathanw * and get back an 'immediate' response (i.e., do programmed xfer
469 1.25.8.2 nathanw * to get the response data). 'cbuf' is a buffer containing a scsi
470 1.25.8.2 nathanw * command of length clen bytes. 'buf' is a buffer of length 'len'
471 1.25.8.2 nathanw * bytes for data. The transfer direction is determined by the device
472 1.25.8.2 nathanw * (i.e., by the scsi bus data xfer phase). If 'len' is zero, the
473 1.25.8.2 nathanw * command must supply no data. 'xferphase' is the bus phase the
474 1.25.8.2 nathanw * caller expects to happen after the command is issued. It should
475 1.25.8.2 nathanw * be one of DATA_IN_PHASE, DATA_OUT_PHASE or STATUS_PHASE.
476 1.25.8.2 nathanw */
477 1.25.8.2 nathanw int
478 1.25.8.2 nathanw sciicmd(struct sci_softc *dev, int target, void *cbuf, int clen, void *buf,
479 1.25.8.2 nathanw int len, u_char xferphase)
480 1.25.8.2 nathanw {
481 1.25.8.2 nathanw u_char phase;
482 1.25.8.2 nathanw register int wait;
483 1.25.8.2 nathanw
484 1.25.8.2 nathanw /* select the SCSI bus (it's an error if bus isn't free) */
485 1.25.8.2 nathanw if (sciselectbus (dev, target, dev->sc_scsi_addr))
486 1.25.8.2 nathanw return -1;
487 1.25.8.2 nathanw /*
488 1.25.8.2 nathanw * Wait for a phase change (or error) then let the device
489 1.25.8.2 nathanw * sequence us through the various SCSI phases.
490 1.25.8.2 nathanw */
491 1.25.8.2 nathanw dev->sc_stat[0] = 0xff;
492 1.25.8.2 nathanw dev->sc_msg[0] = 0xff;
493 1.25.8.2 nathanw phase = CMD_PHASE;
494 1.25.8.2 nathanw while (1) {
495 1.25.8.2 nathanw wait = sci_cmd_wait;
496 1.25.8.2 nathanw
497 1.25.8.2 nathanw while ((*dev->sci_bus_csr & (SCI_BUS_REQ|SCI_BUS_BSY)) == SCI_BUS_BSY);
498 1.25.8.2 nathanw
499 1.25.8.2 nathanw QPRINTF((">CSR:%02x<", *dev->sci_bus_csr));
500 1.25.8.2 nathanw if ((*dev->sci_bus_csr & SCI_BUS_REQ) == 0) {
501 1.25.8.2 nathanw return -1;
502 1.25.8.2 nathanw }
503 1.25.8.2 nathanw phase = SCI_PHASE(*dev->sci_bus_csr);
504 1.25.8.2 nathanw
505 1.25.8.2 nathanw switch (phase) {
506 1.25.8.2 nathanw case CMD_PHASE:
507 1.25.8.2 nathanw if (sci_ixfer_out (dev, clen, cbuf, phase))
508 1.25.8.2 nathanw goto abort;
509 1.25.8.2 nathanw phase = xferphase;
510 1.25.8.2 nathanw break;
511 1.25.8.2 nathanw
512 1.25.8.2 nathanw case DATA_IN_PHASE:
513 1.25.8.2 nathanw if (len <= 0)
514 1.25.8.2 nathanw goto abort;
515 1.25.8.2 nathanw wait = sci_data_wait;
516 1.25.8.2 nathanw sci_ixfer_in (dev, len, buf, phase);
517 1.25.8.2 nathanw phase = STATUS_PHASE;
518 1.25.8.2 nathanw break;
519 1.25.8.2 nathanw
520 1.25.8.2 nathanw case DATA_OUT_PHASE:
521 1.25.8.2 nathanw if (len <= 0)
522 1.25.8.2 nathanw goto abort;
523 1.25.8.2 nathanw wait = sci_data_wait;
524 1.25.8.2 nathanw if (sci_ixfer_out (dev, len, buf, phase))
525 1.25.8.2 nathanw goto abort;
526 1.25.8.2 nathanw phase = STATUS_PHASE;
527 1.25.8.2 nathanw break;
528 1.25.8.2 nathanw
529 1.25.8.2 nathanw case MESG_IN_PHASE:
530 1.25.8.2 nathanw dev->sc_msg[0] = 0xff;
531 1.25.8.2 nathanw sci_ixfer_in (dev, 1, dev->sc_msg,phase);
532 1.25.8.2 nathanw dev->sc_flags &= ~SCI_SELECTED;
533 1.25.8.2 nathanw while (*dev->sci_bus_csr & SCI_BUS_BSY);
534 1.25.8.2 nathanw goto out;
535 1.25.8.2 nathanw break;
536 1.25.8.2 nathanw
537 1.25.8.2 nathanw case MESG_OUT_PHASE:
538 1.25.8.2 nathanw phase = STATUS_PHASE;
539 1.25.8.2 nathanw break;
540 1.25.8.2 nathanw
541 1.25.8.2 nathanw case STATUS_PHASE:
542 1.25.8.2 nathanw sci_ixfer_in (dev, 1, dev->sc_stat, phase);
543 1.25.8.2 nathanw phase = MESG_IN_PHASE;
544 1.25.8.2 nathanw break;
545 1.25.8.2 nathanw
546 1.25.8.2 nathanw case BUS_FREE_PHASE:
547 1.25.8.2 nathanw goto out;
548 1.25.8.2 nathanw
549 1.25.8.2 nathanw default:
550 1.25.8.2 nathanw printf("sci: unexpected phase %d in icmd from %d\n",
551 1.25.8.2 nathanw phase, target);
552 1.25.8.2 nathanw goto abort;
553 1.25.8.2 nathanw }
554 1.25.8.2 nathanw #if 0
555 1.25.8.2 nathanw if (wait <= 0)
556 1.25.8.2 nathanw goto abort;
557 1.25.8.2 nathanw #endif
558 1.25.8.2 nathanw }
559 1.25.8.2 nathanw
560 1.25.8.2 nathanw abort:
561 1.25.8.2 nathanw sciabort(dev, "icmd");
562 1.25.8.2 nathanw out:
563 1.25.8.2 nathanw QPRINTF(("=STS:%02x=", dev->sc_stat[0]));
564 1.25.8.2 nathanw return (dev->sc_stat[0]);
565 1.25.8.2 nathanw }
566 1.25.8.2 nathanw
567 1.25.8.2 nathanw int
568 1.25.8.2 nathanw scigo(struct sci_softc *dev, struct scsipi_xfer *xs)
569 1.25.8.2 nathanw {
570 1.25.8.2 nathanw int count, target;
571 1.25.8.2 nathanw u_char phase, *addr;
572 1.25.8.2 nathanw
573 1.25.8.2 nathanw target = xs->xs_periph->periph_target;
574 1.25.8.2 nathanw count = xs->datalen;
575 1.25.8.2 nathanw addr = xs->data;
576 1.25.8.2 nathanw
577 1.25.8.2 nathanw if (sci_no_dma) {
578 1.25.8.2 nathanw sciicmd (dev, target, (u_char *) xs->cmd, xs->cmdlen,
579 1.25.8.2 nathanw addr, count,
580 1.25.8.2 nathanw xs->xs_control & XS_CTL_DATA_IN ? DATA_IN_PHASE : DATA_OUT_PHASE);
581 1.25.8.2 nathanw
582 1.25.8.2 nathanw return (1);
583 1.25.8.2 nathanw }
584 1.25.8.2 nathanw
585 1.25.8.2 nathanw /* select the SCSI bus (it's an error if bus isn't free) */
586 1.25.8.2 nathanw if (sciselectbus (dev, target, dev->sc_scsi_addr))
587 1.25.8.2 nathanw return -1;
588 1.25.8.2 nathanw /*
589 1.25.8.2 nathanw * Wait for a phase change (or error) then let the device
590 1.25.8.2 nathanw * sequence us through the various SCSI phases.
591 1.25.8.2 nathanw */
592 1.25.8.2 nathanw dev->sc_stat[0] = 0xff;
593 1.25.8.2 nathanw dev->sc_msg[0] = 0xff;
594 1.25.8.2 nathanw phase = CMD_PHASE;
595 1.25.8.2 nathanw while (1) {
596 1.25.8.2 nathanw while ((*dev->sci_bus_csr & (SCI_BUS_REQ|SCI_BUS_BSY)) ==
597 1.25.8.2 nathanw SCI_BUS_BSY);
598 1.25.8.2 nathanw
599 1.25.8.2 nathanw QPRINTF((">CSR:%02x<", *dev->sci_bus_csr));
600 1.25.8.2 nathanw if ((*dev->sci_bus_csr & SCI_BUS_REQ) == 0) {
601 1.25.8.2 nathanw goto abort;
602 1.25.8.2 nathanw }
603 1.25.8.2 nathanw phase = SCI_PHASE(*dev->sci_bus_csr);
604 1.25.8.2 nathanw
605 1.25.8.2 nathanw switch (phase) {
606 1.25.8.2 nathanw case CMD_PHASE:
607 1.25.8.2 nathanw if (sci_ixfer_out (dev, xs->cmdlen, (u_char *) xs->cmd, phase))
608 1.25.8.2 nathanw goto abort;
609 1.25.8.2 nathanw phase = xs->xs_control & XS_CTL_DATA_IN ? DATA_IN_PHASE : DATA_OUT_PHASE;
610 1.25.8.2 nathanw break;
611 1.25.8.2 nathanw
612 1.25.8.2 nathanw case DATA_IN_PHASE:
613 1.25.8.2 nathanw if (count <= 0)
614 1.25.8.2 nathanw goto abort;
615 1.25.8.2 nathanw /* XXX use psuedo DMA if available */
616 1.25.8.2 nathanw if (count >= 128 && dev->dma_xfer_in)
617 1.25.8.2 nathanw (*dev->dma_xfer_in)(dev, count, addr, phase);
618 1.25.8.2 nathanw else
619 1.25.8.2 nathanw sci_ixfer_in (dev, count, addr, phase);
620 1.25.8.2 nathanw phase = STATUS_PHASE;
621 1.25.8.2 nathanw break;
622 1.25.8.2 nathanw
623 1.25.8.2 nathanw case DATA_OUT_PHASE:
624 1.25.8.2 nathanw if (count <= 0)
625 1.25.8.2 nathanw goto abort;
626 1.25.8.2 nathanw /* XXX use psuedo DMA if available */
627 1.25.8.2 nathanw if (count >= 128 && dev->dma_xfer_out)
628 1.25.8.2 nathanw (*dev->dma_xfer_out)(dev, count, addr, phase);
629 1.25.8.2 nathanw else
630 1.25.8.2 nathanw if (sci_ixfer_out (dev, count, addr, phase))
631 1.25.8.2 nathanw goto abort;
632 1.25.8.2 nathanw phase = STATUS_PHASE;
633 1.25.8.2 nathanw break;
634 1.25.8.2 nathanw
635 1.25.8.2 nathanw case MESG_IN_PHASE:
636 1.25.8.2 nathanw dev->sc_msg[0] = 0xff;
637 1.25.8.2 nathanw sci_ixfer_in (dev, 1, dev->sc_msg,phase);
638 1.25.8.2 nathanw dev->sc_flags &= ~SCI_SELECTED;
639 1.25.8.2 nathanw while (*dev->sci_bus_csr & SCI_BUS_BSY);
640 1.25.8.2 nathanw goto out;
641 1.25.8.2 nathanw break;
642 1.25.8.2 nathanw
643 1.25.8.2 nathanw case MESG_OUT_PHASE:
644 1.25.8.2 nathanw phase = STATUS_PHASE;
645 1.25.8.2 nathanw break;
646 1.25.8.2 nathanw
647 1.25.8.2 nathanw case STATUS_PHASE:
648 1.25.8.2 nathanw sci_ixfer_in (dev, 1, dev->sc_stat, phase);
649 1.25.8.2 nathanw phase = MESG_IN_PHASE;
650 1.25.8.2 nathanw break;
651 1.25.8.2 nathanw
652 1.25.8.2 nathanw case BUS_FREE_PHASE:
653 1.25.8.2 nathanw goto out;
654 1.25.8.2 nathanw
655 1.25.8.2 nathanw default:
656 1.25.8.2 nathanw printf("sci: unexpected phase %d in icmd from %d\n",
657 1.25.8.2 nathanw phase, target);
658 1.25.8.2 nathanw goto abort;
659 1.25.8.2 nathanw }
660 1.25.8.2 nathanw }
661 1.25.8.2 nathanw
662 1.25.8.2 nathanw abort:
663 1.25.8.2 nathanw sciabort(dev, "go");
664 1.25.8.2 nathanw out:
665 1.25.8.2 nathanw QPRINTF(("=STS:%02x=", dev->sc_stat[0]));
666 1.25.8.2 nathanw return (1);
667 1.25.8.2 nathanw }
668