sci.c revision 1.1
1 /* 2 * Copyright (c) 1990 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * Van Jacobson of Lawrence Berkeley Laboratory. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * @(#)sci.c 7.5 (Berkeley) 5/4/91 37 * $Id: sci.c,v 1.1 1994/02/28 06:06:23 chopps Exp $ 38 * 39 */ 40 41 /* 42 * AMIGA NCR 5380 scsi adaptor driver 43 */ 44 45 #include "mlhscsi.h" 46 #include "csa12gscsi.h" 47 #include "suprascsi.h" 48 #include "ivsscsi.h" 49 #if (NMLHSCSI + NCSA12GSCSI + NSUPRASCSI + NIVSSCSI) > 0 50 #define NSCI NMLHSCSI 51 #if NSCI < NCSA12GSCSI 52 #undef NSCI 53 #define NSCI NCSA12GSCSI 54 #endif 55 #if NSCI < NSUPRASCSI 56 #undef NSCI 57 #define NSCI NSUPRASCI 58 #endif 59 #if NSCI < NIVSSCSI 60 #undef NSCI 61 #define NSCI NIVSSCI 62 #endif 63 64 #ifndef lint 65 static char rcsid[] = "$Header: /tank/opengrok/rsync2/NetBSD/src/sys/arch/amiga/dev/sci.c,v 1.1 1994/02/28 06:06:23 chopps Exp $"; 66 #endif 67 68 /* need to know if any tapes have been configured */ 69 #include "st.h" 70 71 #include <sys/param.h> 72 #include <sys/systm.h> 73 #include <sys/buf.h> 74 #include <vm/vm.h> 75 #include <vm/vm_kern.h> 76 #include <vm/vm_page.h> 77 #include <vm/vm_statistics.h> 78 #include <machine/pmap.h> 79 80 #include <amiga/dev/device.h> 81 82 #include <amiga/dev/scsidefs.h> 83 #include <amiga/dev/scivar.h> 84 #include <amiga/dev/scireg.h> 85 86 #include <amiga/amiga/custom.h> 87 88 #include <machine/cpu.h> 89 90 extern u_int kvtop(); 91 92 static int sci_wait __P((char until, int timeo, int line)); 93 static void scsiabort __P((register struct sci_softc *dev, char *where)); 94 static void scsierror __P((register struct sci_softc *dev, u_char csr)); 95 static int issue_select __P((register struct sci_softc *dev, u_char target, 96 u_char our_addr)); 97 static int ixfer_out __P((register struct sci_softc *dev, int len, 98 register u_char *buf, int phase)); 99 static void ixfer_in __P((register struct sci_softc *dev, int len, 100 register u_char *buf, int phase)); 101 static int scsiicmd __P((struct sci_softc *dev, int target, u_char *cbuf, 102 int clen, u_char *buf, int len, u_char xferphase)); 103 104 105 /* 106 * SCSI delays 107 * In u-seconds, primarily for state changes on the SPC. 108 */ 109 #define SCSI_CMD_WAIT 50000 /* wait per step of 'immediate' cmds */ 110 #define SCSI_DATA_WAIT 50000 /* wait per data in/out step */ 111 #define SCSI_INIT_WAIT 50000 /* wait per step (both) during init */ 112 113 extern void _insque(); 114 extern void _remque(); 115 116 void scistart __P((int unit)); 117 int scigo __P((int ctlr, int slave, int unit, struct buf *bp, 118 struct scsi_fmt_cdb *cdb, int pad)); 119 int sciintr __P((void)); 120 void scidone __P((int unit)); 121 int sciustart __P((int unit)); 122 int scireq __P((register struct devqueue *dq)); 123 void scifree __P((register struct devqueue *dq)); 124 void scireset __P((int unit)); 125 void sci_delay __P((int delay)); 126 int sci_test_unit_rdy __P((int ctlr, int slave, int unit)); 127 int sci_start_stop_unit __P((int ctlr, int slave, int unit, int start)); 128 int sci_request_sense __P((int ctlr, int slave, int unit, u_char *buf, 129 unsigned int len)); 130 int sci_immed_command __P((int ctlr, int slave, int unit, 131 struct scsi_fmt_cdb *cdb, u_char *buf, unsigned int len, int rd)); 132 int sci_immed_command_nd __P((int ctlr, int slave, int unit, 133 struct scsi_fmt_cdb *cdb)); 134 int sci_tt_read __P((int ctlr, int slave, int unit, u_char *buf, 135 u_int len, daddr_t blk, int bshift)); 136 int sci_tt_write __P((int ctlr, int slave, int unit, u_char *buf, 137 u_int len, daddr_t blk, int bshift)); 138 #if NST > 0 139 int sci_tt_oddio __P((int ctlr, int slave, int unit, u_char *buf, u_int len, int b_flags, int freedma)); 140 #endif 141 142 143 #if NMLHSCSI > 0 144 int mlhscsiinit (); 145 146 struct driver mlhscsidriver = { 147 (int (*)(void *)) mlhscsiinit, "Mlhscsi", (int (*)(int)) scistart, 148 (int (*)(int,...)) scigo, (int (*)(int,int)) sciintr, 149 (int (*)())scidone, sciustart, scireq, scifree, scireset, 150 sci_delay, sci_test_unit_rdy, sci_start_stop_unit, 151 sci_request_sense, sci_immed_command, sci_immed_command_nd, 152 sci_tt_read, sci_tt_write, 153 #if NST > 0 154 sci_tt_oddio 155 #else 156 NULL 157 #endif 158 }; 159 #endif 160 161 #if NCSA12GSCSI > 0 162 int csa12gscsiinit (); 163 164 struct driver csa12gscsidriver = { 165 (int (*)(void *)) csa12gscsiinit, "Csa12gscsi", (int (*)(int)) scistart, 166 (int (*)(int,...)) scigo, (int (*)(int,int)) sciintr, 167 (int (*)())scidone, sciustart, scireq, scifree, scireset, 168 sci_delay, sci_test_unit_rdy, sci_start_stop_unit, 169 sci_request_sense, sci_immed_command, sci_immed_command_nd, 170 sci_tt_read, sci_tt_write, 171 #if NST > 0 172 sci_tt_oddio 173 #else 174 NULL 175 #endif 176 }; 177 #endif 178 179 #if NSUPRASCSI > 0 180 int suprascsiinit (); 181 182 struct driver suprascsidriver = { 183 (int (*)(void *)) suprascsiinit, "Suprascsi", (int (*)(int)) scistart, 184 (int (*)(int,...)) scigo, (int (*)(int,int)) sciintr, 185 (int (*)())scidone, sciustart, scireq, scifree, scireset, 186 sci_delay, sci_test_unit_rdy, sci_start_stop_unit, 187 sci_request_sense, sci_immed_command, sci_immed_command_nd, 188 sci_tt_read, sci_tt_write, 189 #if NST > 0 190 sci_tt_oddio 191 #else 192 NULL 193 #endif 194 }; 195 #endif 196 197 #if NIVSSCSI > 0 198 int ivsscsiinit (); 199 200 struct driver ivsscsidriver = { 201 (int (*)(void *)) ivsscsiinit, "IVSscsi", (int (*)(int)) scistart, 202 (int (*)(int,...)) scigo, (int (*)(int,int)) sciintr, 203 (int (*)())scidone, sciustart, scireq, scifree, scireset, 204 sci_delay, sci_test_unit_rdy, sci_start_stop_unit, 205 sci_request_sense, sci_immed_command, sci_immed_command_nd, 206 sci_tt_read, sci_tt_write, 207 #if NST > 0 208 sci_tt_oddio 209 #else 210 NULL 211 #endif 212 }; 213 #endif 214 215 struct sci_softc sci_softc[NSCI]; 216 217 int sci_cmd_wait = SCSI_CMD_WAIT; 218 int sci_data_wait = SCSI_DATA_WAIT; 219 int sci_init_wait = SCSI_INIT_WAIT; 220 221 int sci_no_dma = 0; 222 223 #ifdef DEBUG 224 int sci_debug = 0; 225 #define WAITHIST 226 #define QUASEL 227 228 static long dmahits[NSCI]; 229 static long dmamisses[NSCI]; 230 #endif 231 232 #ifdef QUASEL 233 #define QPRINTF(a) if (sci_debug > 1) printf a 234 #else 235 #define QPRINTF 236 #endif 237 238 #ifdef WAITHIST 239 #define MAXWAIT 1022 240 u_int ixstart_wait[MAXWAIT+2]; 241 u_int ixin_wait[MAXWAIT+2]; 242 u_int ixout_wait[MAXWAIT+2]; 243 u_int mxin_wait[MAXWAIT+2]; 244 u_int mxin2_wait[MAXWAIT+2]; 245 u_int cxin_wait[MAXWAIT+2]; 246 u_int fxfr_wait[MAXWAIT+2]; 247 u_int sgo_wait[MAXWAIT+2]; 248 #define HIST(h,w) (++h[((w)>MAXWAIT? MAXWAIT : ((w) < 0 ? -1 : (w))) + 1]); 249 #else 250 #define HIST(h,w) 251 #endif 252 253 #define b_cylin b_resid 254 255 static sci_wait (until, timeo, line) 256 char until; 257 int timeo; 258 int line; 259 { 260 register unsigned char val; 261 262 if (! timeo) 263 timeo = 1000000; /* some large value.. */ 264 265 return val; 266 } 267 268 static void 269 scsiabort(dev, where) 270 register struct sci_softc *dev; 271 char *where; 272 { 273 274 printf ("sci%d: abort %s: csr = 0x%02x, bus = 0x%02x\n", 275 dev->sc_ac->amiga_unit, 276 where, *dev->sci_csr, *dev->sci_bus_csr); 277 278 if (dev->sc_flags & SCI_SELECTED) { 279 280 /* XXX */ 281 scireset (dev->sc_ac->amiga_unit); 282 /* lets just hope it worked.. */ 283 dev->sc_flags &= ~SCI_SELECTED; 284 } 285 } 286 287 /* 288 * XXX Set/reset long delays. 289 * 290 * if delay == 0, reset default delays 291 * if delay < 0, set both delays to default long initialization values 292 * if delay > 0, set both delays to this value 293 * 294 * Used when a devices is expected to respond slowly (e.g. during 295 * initialization). 296 */ 297 void 298 sci_delay(delay) 299 int delay; 300 { 301 static int saved_cmd_wait, saved_data_wait; 302 303 if (delay) { 304 saved_cmd_wait = sci_cmd_wait; 305 saved_data_wait = sci_data_wait; 306 if (delay > 0) 307 sci_cmd_wait = sci_data_wait = delay; 308 else 309 sci_cmd_wait = sci_data_wait = sci_init_wait; 310 } else { 311 sci_cmd_wait = saved_cmd_wait; 312 sci_data_wait = saved_data_wait; 313 } 314 } 315 316 static int initialized[NSCI]; 317 318 #if NMLHSCSI > 0 319 int 320 mlhscsiinit(ac) 321 register struct amiga_ctlr *ac; 322 { 323 register struct sci_softc *dev = &sci_softc[ac->amiga_unit]; 324 325 if (! ac->amiga_addr) 326 return 0; 327 328 if (initialized[ac->amiga_unit]) 329 return 0; 330 331 if (ac->amiga_unit > NSCI) 332 return 0; 333 334 initialized[ac->amiga_unit] = 1; 335 336 /* advance ac->amiga_addr to point to the real sci-registers */ 337 ac->amiga_addr = (caddr_t) ((int)ac->amiga_addr); 338 dev->sci_data = (caddr_t) ac->amiga_addr + 1; 339 dev->sci_odata = (caddr_t) ac->amiga_addr + 1; 340 dev->sci_icmd = (caddr_t) ac->amiga_addr + 3; 341 dev->sci_mode = (caddr_t) ac->amiga_addr + 5; 342 dev->sci_tcmd = (caddr_t) ac->amiga_addr + 7; 343 dev->sci_bus_csr = (caddr_t) ac->amiga_addr + 9; 344 dev->sci_sel_enb = (caddr_t) ac->amiga_addr + 9; 345 dev->sci_csr = (caddr_t) ac->amiga_addr + 11; 346 dev->sci_dma_send = (caddr_t) ac->amiga_addr + 11; 347 dev->sci_idata = (caddr_t) ac->amiga_addr + 13; 348 dev->sci_trecv = (caddr_t) ac->amiga_addr + 13; 349 dev->sci_iack = (caddr_t) ac->amiga_addr + 15; 350 dev->sci_irecv = (caddr_t) ac->amiga_addr + 15; 351 mlhdmainit (dev); 352 353 /* hardwired IPL */ 354 ac->amiga_ipl = 0; /* doesn't use interrupts */ 355 dev->sc_ac = ac; 356 dev->sc_sq.dq_forw = dev->sc_sq.dq_back = &dev->sc_sq; 357 scireset (ac->amiga_unit); 358 359 return(1); 360 } 361 #endif 362 363 #if NCSA12GSCSI > 0 364 int 365 csa12gscsiinit(ac) 366 register struct amiga_ctlr *ac; 367 { 368 register struct sci_softc *dev = &sci_softc[ac->amiga_unit]; 369 370 if (! ac->amiga_addr) 371 return 0; 372 373 if (initialized[ac->amiga_unit]) 374 return 0; 375 376 if (ac->amiga_unit > NSCI) 377 return 0; 378 379 initialized[ac->amiga_unit] = 1; 380 381 /* advance ac->amiga_addr to point to the real sci-registers */ 382 ac->amiga_addr = (caddr_t) ((int)ac->amiga_addr + 0x2000); 383 dev->sci_data = (caddr_t) ac->amiga_addr; 384 dev->sci_odata = (caddr_t) ac->amiga_addr; 385 dev->sci_icmd = (caddr_t) ac->amiga_addr + 0x10; 386 dev->sci_mode = (caddr_t) ac->amiga_addr + 0x20; 387 dev->sci_tcmd = (caddr_t) ac->amiga_addr + 0x30; 388 dev->sci_bus_csr = (caddr_t) ac->amiga_addr + 0x40; 389 dev->sci_sel_enb = (caddr_t) ac->amiga_addr + 0x40; 390 dev->sci_csr = (caddr_t) ac->amiga_addr + 0x50; 391 dev->sci_dma_send = (caddr_t) ac->amiga_addr + 0x50; 392 dev->sci_idata = (caddr_t) ac->amiga_addr + 0x60; 393 dev->sci_trecv = (caddr_t) ac->amiga_addr + 0x60; 394 dev->sci_iack = (caddr_t) ac->amiga_addr + 0x70; 395 dev->sci_irecv = (caddr_t) ac->amiga_addr + 0x70; 396 csa12gdmainit (dev); 397 398 /* hardwired IPL */ 399 ac->amiga_ipl = 2; 400 dev->sc_ac = ac; 401 dev->sc_sq.dq_forw = dev->sc_sq.dq_back = &dev->sc_sq; 402 scireset (ac->amiga_unit); 403 404 /* make sure IPL2 interrupts are delivered to the cpu when the sci 405 generates some. Note that this does not yet enable sci-interrupts, 406 this is handled in dma.c, which selectively enables interrupts only 407 while DMA requests are pending. 408 409 Note that enabling PORTS interrupts also enables keyboard interrupts 410 as soon as the corresponding int-enable bit in CIA-A is set. */ 411 412 custom.intreq = INTF_PORTS; 413 custom.intena = INTF_SETCLR | INTF_PORTS; 414 return(1); 415 } 416 #endif 417 418 #if NSUPRASCSI > 0 419 int 420 suprascsiinit(ac) 421 register struct amiga_ctlr *ac; 422 { 423 register struct sci_softc *dev = &sci_softc[ac->amiga_unit]; 424 425 if (! ac->amiga_addr) 426 return 0; 427 428 if (initialized[ac->amiga_unit]) 429 return 0; 430 431 if (ac->amiga_unit > NSCI) 432 return 0; 433 434 initialized[ac->amiga_unit] = 1; 435 436 /* advance ac->amiga_addr to point to the real sci-registers */ 437 /* XXX Supra Word Sync version 2 only for now !!! */ 438 dev->sci_data = (caddr_t) ac->amiga_addr; 439 dev->sci_odata = (caddr_t) ac->amiga_addr; 440 dev->sci_icmd = (caddr_t) ac->amiga_addr + 2; 441 dev->sci_mode = (caddr_t) ac->amiga_addr + 4; 442 dev->sci_tcmd = (caddr_t) ac->amiga_addr + 6; 443 dev->sci_bus_csr = (caddr_t) ac->amiga_addr + 8; 444 dev->sci_sel_enb = (caddr_t) ac->amiga_addr + 8; 445 dev->sci_csr = (caddr_t) ac->amiga_addr + 10; 446 dev->sci_dma_send = (caddr_t) ac->amiga_addr + 10; 447 dev->sci_idata = (caddr_t) ac->amiga_addr + 12; 448 dev->sci_trecv = (caddr_t) ac->amiga_addr + 12; 449 dev->sci_iack = (caddr_t) ac->amiga_addr + 14; 450 dev->sci_irecv = (caddr_t) ac->amiga_addr + 14; 451 supradmainit (dev); 452 453 /* hardwired IPL */ 454 ac->amiga_ipl = 2; 455 dev->sc_ac = ac; 456 dev->sc_sq.dq_forw = dev->sc_sq.dq_back = &dev->sc_sq; 457 scireset (ac->amiga_unit); 458 459 /* make sure IPL2 interrupts are delivered to the cpu when the sci 460 generates some. Note that this does not yet enable sci-interrupts, 461 this is handled in dma.c, which selectively enables interrupts only 462 while DMA requests are pending. 463 464 Note that enabling PORTS interrupts also enables keyboard interrupts 465 as soon as the corresponding int-enable bit in CIA-A is set. */ 466 467 custom.intreq = INTF_PORTS; 468 custom.intena = INTF_SETCLR | INTF_PORTS; 469 return(1); 470 } 471 #endif 472 473 #if NIVSSCSI > 0 474 int 475 ivsscsiinit(ac) 476 register struct amiga_ctlr *ac; 477 { 478 register struct sci_softc *dev = &sci_softc[ac->amiga_unit]; 479 480 if (! ac->amiga_addr) 481 return 0; 482 483 if (initialized[ac->amiga_unit]) 484 return 0; 485 486 if (ac->amiga_unit > NSCI) 487 return 0; 488 489 initialized[ac->amiga_unit] = 1; 490 491 /* advance ac->amiga_addr to point to the real sci-registers */ 492 ac->amiga_addr = (caddr_t) ((int)ac->amiga_addr + 0x40); 493 dev->sci_data = (caddr_t) ac->amiga_addr; 494 dev->sci_odata = (caddr_t) ac->amiga_addr; 495 dev->sci_icmd = (caddr_t) ac->amiga_addr + 2; 496 dev->sci_mode = (caddr_t) ac->amiga_addr + 4; 497 dev->sci_tcmd = (caddr_t) ac->amiga_addr + 6; 498 dev->sci_bus_csr = (caddr_t) ac->amiga_addr + 8; 499 dev->sci_sel_enb = (caddr_t) ac->amiga_addr + 8; 500 dev->sci_csr = (caddr_t) ac->amiga_addr + 10; 501 dev->sci_dma_send = (caddr_t) ac->amiga_addr + 10; 502 dev->sci_idata = (caddr_t) ac->amiga_addr + 12; 503 dev->sci_trecv = (caddr_t) ac->amiga_addr + 12; 504 dev->sci_iack = (caddr_t) ac->amiga_addr + 14; 505 dev->sci_irecv = (caddr_t) ac->amiga_addr + 14; 506 ivsdmainit (dev); 507 508 /* hardwired IPL */ 509 ac->amiga_ipl = 2; 510 dev->sc_ac = ac; 511 dev->sc_sq.dq_forw = dev->sc_sq.dq_back = &dev->sc_sq; 512 scireset (ac->amiga_unit); 513 514 /* make sure IPL2 interrupts are delivered to the cpu when the sci 515 generates some. Note that this does not yet enable sci-interrupts, 516 this is handled in dma.c, which selectively enables interrupts only 517 while DMA requests are pending. 518 519 Note that enabling PORTS interrupts also enables keyboard interrupts 520 as soon as the corresponding int-enable bit in CIA-A is set. */ 521 522 custom.intreq = INTF_PORTS; 523 custom.intena = INTF_SETCLR | INTF_PORTS; 524 return(1); 525 } 526 #endif 527 528 void 529 scireset(unit) 530 register int unit; 531 { 532 register struct sci_softc *dev = &sci_softc[unit]; 533 u_int i, s; 534 u_char my_id, csr; 535 536 if (dev->sc_flags & SCI_ALIVE) 537 scsiabort(dev, "reset"); 538 539 printf("sci%d: ", unit); 540 541 s = splbio(); 542 /* preserve our ID for now */ 543 my_id = 7; 544 545 /* 546 * Disable interrupts (in dmainit) then reset the chip 547 */ 548 *dev->sci_icmd = SCI_ICMD_TEST; 549 *dev->sci_icmd = SCI_ICMD_TEST | SCI_ICMD_RST; 550 DELAY (25); 551 *dev->sci_icmd = 0; 552 553 /* 554 * Set up various chip parameters 555 */ 556 *dev->sci_icmd = 0; 557 *dev->sci_tcmd = 0; 558 *dev->sci_sel_enb = 0; 559 560 /* anything else was zeroed by reset */ 561 562 splx (s); 563 564 printf("sci id %d\n", my_id); 565 dev->sc_flags |= SCI_ALIVE; 566 dev->sc_flags &= ~SCI_SELECTED; 567 } 568 569 static void 570 scsierror(dev, csr) 571 register struct sci_softc *dev; 572 u_char csr; 573 { 574 int unit = dev->sc_ac->amiga_unit; 575 char *sep = ""; 576 577 printf("sci%d: ", unit); 578 printf("\n"); 579 } 580 581 static int 582 issue_select(dev, target, our_addr) 583 register struct sci_softc *dev; 584 u_char target, our_addr; 585 { 586 register int timeo = 2500; 587 588 QPRINTF (("issue_select %d\n", target)); 589 590 /* if we're already selected, return */ 591 if (dev->sc_flags & SCI_SELECTED) /* XXXX */ 592 return 1; 593 594 if ((*dev->sci_bus_csr & (SCI_BUS_BSY|SCI_BUS_SEL)) && 595 (*dev->sci_bus_csr & (SCI_BUS_BSY|SCI_BUS_SEL)) && 596 (*dev->sci_bus_csr & (SCI_BUS_BSY|SCI_BUS_SEL))) 597 return 1; 598 599 *dev->sci_tcmd = 0; 600 *dev->sci_odata = 0x80 + (1 << target); 601 *dev->sci_icmd = SCI_ICMD_DATA|SCI_ICMD_SEL; 602 while ((*dev->sci_bus_csr & SCI_BUS_BSY) == 0) { 603 if (--timeo > 0) { 604 DELAY(100); 605 } else { 606 break; 607 } 608 } 609 if (timeo) { 610 *dev->sci_icmd = 0; 611 dev->sc_flags |= SCI_SELECTED; 612 return (0); 613 } 614 *dev->sci_icmd = 0; 615 return (1); 616 } 617 618 static int 619 ixfer_out(dev, len, buf, phase) 620 register struct sci_softc *dev; 621 int len; 622 register u_char *buf; 623 int phase; 624 { 625 register int wait = sci_data_wait; 626 u_char csr; 627 628 QPRINTF(("ixfer_out {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", 629 len, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], 630 buf[6], buf[7], buf[8], buf[9])); 631 632 *dev->sci_tcmd = phase; 633 *dev->sci_icmd = SCI_ICMD_DATA; 634 for (;len > 0; len--) { 635 csr = *dev->sci_bus_csr; 636 while (!(csr & SCI_BUS_REQ)) { 637 if ((csr & SCI_BUS_BSY) == 0 || --wait < 0) { 638 #ifdef DEBUG 639 if (sci_debug) 640 printf("ixfer_out fail: l%d i%x w%d\n", 641 len, csr, wait); 642 #endif 643 HIST(ixout_wait, wait) 644 return (len); 645 } 646 DELAY(1); 647 csr = *dev->sci_bus_csr; 648 } 649 650 if (!(*dev->sci_csr & SCI_CSR_PHASE_MATCH)) 651 break; 652 *dev->sci_odata = *buf; 653 *dev->sci_icmd = SCI_ICMD_DATA|SCI_ICMD_ACK; 654 buf++; 655 while (*dev->sci_bus_csr & SCI_BUS_REQ); 656 *dev->sci_icmd = SCI_ICMD_DATA; 657 } 658 659 QPRINTF(("ixfer_out done\n")); 660 /* this leaves with one csr to be read */ 661 HIST(ixout_wait, wait) 662 return (0); 663 } 664 665 static void 666 ixfer_in(dev, len, buf, phase) 667 struct sci_softc *dev; 668 int len; 669 register u_char *buf; 670 int phase; 671 { 672 int wait = sci_data_wait; 673 u_char *obp = buf; 674 u_char csr; 675 volatile register u_char *sci_bus_csr = dev->sci_bus_csr; 676 volatile register u_char *sci_data = dev->sci_data; 677 volatile register u_char *sci_icmd = dev->sci_icmd; 678 679 csr = *sci_bus_csr; 680 681 QPRINTF(("ixfer_in %d, csr=%02x\n", len, csr)); 682 683 *dev->sci_tcmd = phase; 684 *sci_icmd = 0; 685 for (;len > 0; len--) { 686 csr = *sci_bus_csr; 687 while (!(csr & SCI_BUS_REQ)) { 688 if (!(csr & SCI_BUS_BSY) || --wait < 0) { 689 #ifdef DEBUG 690 if (sci_debug) 691 printf("ixfer_in fail: l%d i%x w%d\n", 692 len, csr, wait); 693 #endif 694 HIST(ixin_wait, wait) 695 return; 696 } 697 698 DELAY(1); 699 csr = *sci_bus_csr; 700 } 701 702 if (!(*dev->sci_csr & SCI_CSR_PHASE_MATCH)) 703 break; 704 *buf = *sci_data; 705 *sci_icmd = SCI_ICMD_ACK; 706 buf++; 707 while (*sci_bus_csr & SCI_BUS_REQ); 708 *sci_icmd = 0; 709 } 710 711 QPRINTF(("ixfer_in {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", 712 len, obp[0], obp[1], obp[2], obp[3], obp[4], obp[5], 713 obp[6], obp[7], obp[8], obp[9])); 714 715 /* this leaves with one csr to be read */ 716 HIST(ixin_wait, wait) 717 } 718 719 /* 720 * SCSI 'immediate' command: issue a command to some SCSI device 721 * and get back an 'immediate' response (i.e., do programmed xfer 722 * to get the response data). 'cbuf' is a buffer containing a scsi 723 * command of length clen bytes. 'buf' is a buffer of length 'len' 724 * bytes for data. The transfer direction is determined by the device 725 * (i.e., by the scsi bus data xfer phase). If 'len' is zero, the 726 * command must supply no data. 'xferphase' is the bus phase the 727 * caller expects to happen after the command is issued. It should 728 * be one of DATA_IN_PHASE, DATA_OUT_PHASE or STATUS_PHASE. 729 */ 730 static int 731 scsiicmd(dev, target, cbuf, clen, buf, len, xferphase) 732 struct sci_softc *dev; 733 int target; 734 u_char *cbuf; 735 int clen; 736 u_char *buf; 737 int len; 738 u_char xferphase; 739 { 740 u_char phase, csr, asr; 741 register int wait; 742 743 /* select the SCSI bus (it's an error if bus isn't free) */ 744 if (issue_select (dev, target, dev->sc_scsi_addr)) 745 return -1; 746 /* 747 * Wait for a phase change (or error) then let the device 748 * sequence us through the various SCSI phases. 749 */ 750 dev->sc_stat[0] = 0xff; 751 dev->sc_msg[0] = 0xff; 752 phase = CMD_PHASE; 753 while (1) { 754 wait = sci_cmd_wait; 755 756 while ((*dev->sci_bus_csr & (SCI_BUS_REQ|SCI_BUS_BSY)) == SCI_BUS_BSY); 757 758 QPRINTF((">CSR:%02x<", *dev->sci_bus_csr)); 759 if ((*dev->sci_bus_csr & SCI_BUS_REQ) == 0) { 760 return -1; 761 } 762 phase = SCI_PHASE(*dev->sci_bus_csr); 763 764 switch (phase) { 765 case CMD_PHASE: 766 if (ixfer_out (dev, clen, cbuf, phase)) 767 goto abort; 768 phase = xferphase; 769 break; 770 771 case DATA_IN_PHASE: 772 if (len <= 0) 773 goto abort; 774 wait = sci_data_wait; 775 ixfer_in (dev, len, buf, phase); 776 phase = STATUS_PHASE; 777 break; 778 779 case DATA_OUT_PHASE: 780 if (len <= 0) 781 goto abort; 782 wait = sci_data_wait; 783 if (ixfer_out (dev, len, buf, phase)) 784 goto abort; 785 phase = STATUS_PHASE; 786 break; 787 788 case MESG_IN_PHASE: 789 dev->sc_msg[0] = 0xff; 790 ixfer_in (dev, 1, dev->sc_msg,phase); 791 dev->sc_flags &= ~SCI_SELECTED; 792 while (*dev->sci_bus_csr & SCI_BUS_BSY); 793 goto out; 794 break; 795 796 case MESG_OUT_PHASE: 797 phase = STATUS_PHASE; 798 break; 799 800 case STATUS_PHASE: 801 ixfer_in (dev, 1, dev->sc_stat, phase); 802 phase = MESG_IN_PHASE; 803 break; 804 805 case BUS_FREE_PHASE: 806 goto out; 807 808 default: 809 printf("sci: unexpected phase %d in icmd from %d\n", 810 phase, target); 811 goto abort; 812 } 813 #if 0 814 if (wait <= 0) 815 goto abort; 816 #endif 817 } 818 819 abort: 820 scsiabort(dev, "icmd"); 821 out: 822 QPRINTF(("=STS:%02x=", dev->sc_stat[0])); 823 return (dev->sc_stat[0]); 824 } 825 826 int 827 sci_test_unit_rdy(ctlr, slave, unit) 828 int ctlr, slave, unit; 829 { 830 register struct sci_softc *dev = &sci_softc[ctlr]; 831 static struct scsi_cdb6 cdb = { CMD_TEST_UNIT_READY }; 832 833 cdb.lun = unit; 834 return (scsiicmd(dev, slave, (u_char *)&cdb, sizeof(cdb), (u_char *)0, 0, 835 STATUS_PHASE)); 836 } 837 838 int 839 sci_start_stop_unit (ctlr, slave, unit, start) 840 int ctlr, slave, unit; 841 { 842 register struct sci_softc *dev = &sci_softc[ctlr]; 843 static struct scsi_cdb6 cdb = { CMD_LOADUNLOAD }; 844 845 cdb.lun = unit; 846 /* we don't set the immediate bit, so we wait for the 847 command to succeed. 848 We also don't touch the LoEj bit, which is primarily meant 849 for floppies. */ 850 cdb.len = start & 0x01; 851 return (scsiicmd(dev, slave, (u_char *)&cdb, sizeof(cdb), (u_char *)0, 0, 852 STATUS_PHASE)); 853 } 854 855 856 int 857 sci_request_sense(ctlr, slave, unit, buf, len) 858 int ctlr, slave, unit; 859 u_char *buf; 860 unsigned len; 861 { 862 register struct sci_softc *dev = &sci_softc[ctlr]; 863 static struct scsi_cdb6 cdb = { CMD_REQUEST_SENSE }; 864 865 cdb.lun = unit; 866 cdb.len = len; 867 return (scsiicmd(dev, slave, (u_char *)&cdb, sizeof(cdb), buf, len, DATA_IN_PHASE)); 868 } 869 870 int 871 sci_immed_command_nd(ctlr, slave, unit, cdb) 872 int ctlr, slave, unit; 873 struct scsi_fmt_cdb *cdb; 874 { 875 register struct sci_softc *dev = &sci_softc[ctlr]; 876 877 cdb->cdb[1] |= (unit << 5); 878 return(scsiicmd(dev, slave, (u_char *) cdb->cdb, cdb->len, 879 0, 0, STATUS_PHASE)); 880 } 881 882 int 883 sci_immed_command(ctlr, slave, unit, cdb, buf, len, rd) 884 int ctlr, slave, unit; 885 struct scsi_fmt_cdb *cdb; 886 u_char *buf; 887 unsigned len; 888 { 889 register struct sci_softc *dev = &sci_softc[ctlr]; 890 891 cdb->cdb[1] |= (unit << 5); 892 return (scsiicmd(dev, slave, (u_char *) cdb->cdb, cdb->len, buf, len, 893 rd != 0? DATA_IN_PHASE : DATA_OUT_PHASE)); 894 } 895 896 /* 897 * The following routines are test-and-transfer i/o versions of read/write 898 * for things like reading disk labels and writing core dumps. The 899 * routine scigo should be used for normal data transfers, NOT these 900 * routines. 901 */ 902 int 903 sci_tt_read(ctlr, slave, unit, buf, len, blk, bshift) 904 int ctlr, slave, unit; 905 u_char *buf; 906 u_int len; 907 daddr_t blk; 908 int bshift; 909 { 910 register struct sci_softc *dev = &sci_softc[ctlr]; 911 struct scsi_cdb10 cdb; 912 int stat; 913 int old_wait = sci_data_wait; 914 915 sci_data_wait = 300000; 916 bzero(&cdb, sizeof(cdb)); 917 cdb.cmd = CMD_READ_EXT; 918 cdb.lun = unit; 919 blk >>= bshift; 920 cdb.lbah = blk >> 24; 921 cdb.lbahm = blk >> 16; 922 cdb.lbalm = blk >> 8; 923 cdb.lbal = blk; 924 cdb.lenh = len >> (8 + DEV_BSHIFT + bshift); 925 cdb.lenl = len >> (DEV_BSHIFT + bshift); 926 stat = scsiicmd(dev, slave, (u_char *) &cdb, sizeof(cdb), buf, len, DATA_IN_PHASE); 927 sci_data_wait = old_wait; 928 return (stat); 929 } 930 931 int 932 sci_tt_write(ctlr, slave, unit, buf, len, blk, bshift) 933 int ctlr, slave, unit; 934 u_char *buf; 935 u_int len; 936 daddr_t blk; 937 int bshift; 938 { 939 register struct sci_softc *dev = &sci_softc[ctlr]; 940 struct scsi_cdb10 cdb; 941 int stat; 942 int old_wait = sci_data_wait; 943 944 sci_data_wait = 300000; 945 946 bzero(&cdb, sizeof(cdb)); 947 cdb.cmd = CMD_WRITE_EXT; 948 cdb.lun = unit; 949 blk >>= bshift; 950 cdb.lbah = blk >> 24; 951 cdb.lbahm = blk >> 16; 952 cdb.lbalm = blk >> 8; 953 cdb.lbal = blk; 954 cdb.lenh = len >> (8 + DEV_BSHIFT + bshift); 955 cdb.lenl = len >> (DEV_BSHIFT + bshift); 956 stat = scsiicmd(dev, slave, (u_char *) &cdb, sizeof(cdb), buf, len, DATA_OUT_PHASE); 957 sci_data_wait = old_wait; 958 return (stat); 959 } 960 961 int 962 scireq(dq) 963 register struct devqueue *dq; 964 { 965 register struct devqueue *hq; 966 967 hq = &sci_softc[dq->dq_ctlr].sc_sq; 968 insque(dq, hq->dq_back); 969 if (dq->dq_back == hq) 970 return(1); 971 return(0); 972 } 973 974 int 975 sciustart (int unit) 976 { 977 register struct sci_softc *dev = &sci_softc[unit]; 978 979 /* If we got here, this controller is not busy 980 so we are ready to accept a command 981 */ 982 return(1); 983 } 984 985 void 986 scistart (int unit) 987 { 988 register struct devqueue *dq; 989 990 dq = sci_softc[unit].sc_sq.dq_forw; 991 (dq->dq_driver->d_go)(dq->dq_unit); 992 } 993 994 int 995 scigo(ctlr, slave, unit, bp, cdb, pad) 996 int ctlr, slave, unit; 997 struct buf *bp; 998 struct scsi_fmt_cdb *cdb; 999 int pad; 1000 { 1001 register struct sci_softc *dev = &sci_softc[ctlr]; 1002 u_char phase, csr, asr, cmd; 1003 char *addr; 1004 int count; 1005 register struct devqueue *dq; 1006 1007 cdb->cdb[1] |= unit << 5; 1008 1009 addr = bp->b_un.b_addr; 1010 count = bp->b_bcount; 1011 1012 if (sci_no_dma) { 1013 1014 scsiicmd (dev, slave, (u_char *) cdb->cdb, cdb->len, 1015 addr, count, 1016 bp->b_flags & B_READ ? DATA_IN_PHASE : DATA_OUT_PHASE); 1017 1018 dq = dev->sc_sq.dq_forw; 1019 dev->sc_flags &=~ (SCI_IO); 1020 (dq->dq_driver->d_intr)(dq->dq_unit, dev->sc_stat[0]); 1021 return dev->sc_stat[0]; 1022 } 1023 1024 /* select the SCSI bus (it's an error if bus isn't free) */ 1025 if (issue_select (dev, slave, dev->sc_scsi_addr)) 1026 return -1; 1027 /* 1028 * Wait for a phase change (or error) then let the device 1029 * sequence us through the various SCSI phases. 1030 */ 1031 dev->sc_stat[0] = 0xff; 1032 dev->sc_msg[0] = 0xff; 1033 phase = CMD_PHASE; 1034 while (1) { 1035 while ((*dev->sci_bus_csr & (SCI_BUS_REQ|SCI_BUS_BSY)) == 1036 SCI_BUS_BSY); 1037 1038 QPRINTF((">CSR:%02x<", *dev->sci_bus_csr)); 1039 if ((*dev->sci_bus_csr & SCI_BUS_REQ) == 0) { 1040 goto abort; 1041 } 1042 phase = SCI_PHASE(*dev->sci_bus_csr); 1043 1044 switch (phase) { 1045 case CMD_PHASE: 1046 if (ixfer_out (dev, cdb->len, cdb->cdb, phase)) 1047 goto abort; 1048 phase = bp->b_flags & B_READ ? DATA_IN_PHASE : DATA_OUT_PHASE; 1049 break; 1050 1051 case DATA_IN_PHASE: 1052 if (count <= 0) 1053 goto abort; 1054 /* XXX use psuedo DMA if available */ 1055 if (count >= 128 && dev->dma_xfer_in) 1056 (*dev->dma_xfer_in)(dev, count, addr, phase); 1057 else 1058 ixfer_in (dev, count, addr, phase); 1059 phase = STATUS_PHASE; 1060 break; 1061 1062 case DATA_OUT_PHASE: 1063 if (count <= 0) 1064 goto abort; 1065 /* XXX use psuedo DMA if available */ 1066 if (count >= 128 && dev->dma_xfer_out) 1067 (*dev->dma_xfer_out)(dev, count, addr, phase); 1068 else 1069 if (ixfer_out (dev, count, addr, phase)) 1070 goto abort; 1071 phase = STATUS_PHASE; 1072 break; 1073 1074 case MESG_IN_PHASE: 1075 dev->sc_msg[0] = 0xff; 1076 ixfer_in (dev, 1, dev->sc_msg,phase); 1077 dev->sc_flags &= ~SCI_SELECTED; 1078 while (*dev->sci_bus_csr & SCI_BUS_BSY); 1079 goto out; 1080 break; 1081 1082 case MESG_OUT_PHASE: 1083 phase = STATUS_PHASE; 1084 break; 1085 1086 case STATUS_PHASE: 1087 ixfer_in (dev, 1, dev->sc_stat, phase); 1088 phase = MESG_IN_PHASE; 1089 break; 1090 1091 case BUS_FREE_PHASE: 1092 goto out; 1093 1094 default: 1095 printf("sci: unexpected phase %d in icmd from %d\n", 1096 phase, slave); 1097 goto abort; 1098 } 1099 } 1100 1101 abort: 1102 scsiabort(dev, "go"); 1103 out: 1104 QPRINTF(("=STS:%02x=", dev->sc_stat[0])); 1105 dq = dev->sc_sq.dq_forw; 1106 dev->sc_flags &=~ (SCI_IO); 1107 (dq->dq_driver->d_intr)(dq->dq_unit, dev->sc_stat[0]); 1108 return dev->sc_stat[0]; 1109 } 1110 1111 void 1112 scidone (int unit) 1113 { 1114 1115 #ifdef DEBUG 1116 if (sci_debug) 1117 printf("sci%d: done called!\n", unit); 1118 #endif 1119 } 1120 1121 int 1122 sciintr () 1123 { 1124 register struct sci_softc *dev = sci_softc; 1125 int unit; 1126 int dummy; 1127 int found = 0; 1128 1129 for (unit = 0; unit < NSCI; ++unit, ++dev) { 1130 if (dev->sc_ac->amiga_ipl == 0) 1131 continue; 1132 /* XXX check if expecting interrupt? */ 1133 if (dev->dma_intr) 1134 found += (*dev->dma_intr)(dev); 1135 else if ((*dev->sci_csr & SCI_CSR_INT)) { 1136 *dev->sci_mode = 0; 1137 dummy = *dev->sci_iack; 1138 ++found; 1139 } 1140 } 1141 return found; 1142 } 1143 1144 void 1145 scifree(dq) 1146 register struct devqueue *dq; 1147 { 1148 register struct devqueue *hq; 1149 1150 hq = &sci_softc[dq->dq_ctlr].sc_sq; 1151 remque(dq); 1152 if ((dq = hq->dq_forw) != hq) 1153 (dq->dq_driver->d_start)(dq->dq_unit); 1154 } 1155 1156 /* 1157 * (XXX) The following routine is needed for the SCSI tape driver 1158 * to read odd-size records. 1159 */ 1160 1161 #if NST > 0 1162 int 1163 sci_tt_oddio(ctlr, slave, unit, buf, len, b_flags, freedma) 1164 int ctlr, slave, unit, b_flags; 1165 u_char *buf; 1166 u_int len; 1167 { 1168 register struct sci_softc *dev = &sci_softc[ctlr]; 1169 struct scsi_cdb6 cdb; 1170 u_char iphase; 1171 int stat; 1172 1173 /* 1174 * First free any DMA channel that was allocated. 1175 * We can't use DMA to do this transfer. 1176 */ 1177 /* 1178 * Initialize command block 1179 */ 1180 bzero(&cdb, sizeof(cdb)); 1181 cdb.lun = unit; 1182 cdb.lbam = (len >> 16) & 0xff; 1183 cdb.lbal = (len >> 8) & 0xff; 1184 cdb.len = len & 0xff; 1185 if (buf == 0) { 1186 cdb.cmd = CMD_SPACE; 1187 cdb.lun |= 0x00; 1188 len = 0; 1189 iphase = MESG_IN_PHASE; 1190 } else if (b_flags & B_READ) { 1191 cdb.cmd = CMD_READ; 1192 iphase = DATA_IN_PHASE; 1193 } else { 1194 cdb.cmd = CMD_WRITE; 1195 iphase = DATA_OUT_PHASE; 1196 } 1197 /* 1198 * Perform command (with very long delays) 1199 */ 1200 sci_delay(30000000); 1201 stat = scsiicmd(dev, slave, (u_char *) &cdb, sizeof(cdb), buf, len, iphase); 1202 sci_delay(0); 1203 return (stat); 1204 } 1205 #endif 1206 #endif 1207
Indexes created Tue Sep 23 02:09:52 GMT 2025