scireg.h revision 1.2
1 /* 2 * Copyright (c) 1990 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * Van Jacobson of Lawrence Berkeley Laboratory. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * @(#)scireg.h 7.3 (Berkeley) 2/5/91 37 * $Id: scireg.h,v 1.2 1994/05/29 04:50:23 chopps Exp $ 38 */ 39 40 /* 41 * NCR 5380 SCSI interface hardware description. 42 * 43 */ 44 45 #if 0 /* for reference */ 46 typedef struct { 47 unsigned char pad0[1]; 48 volatile unsigned char sci_data; /* r: Current data */ 49 #define sci_odata sci_data /* w: Out data */ 50 51 unsigned char pad1[1]; 52 volatile unsigned char sci_icmd; /* rw: Initiator command */ 53 54 unsigned char pad2[1]; 55 volatile unsigned char sci_mode; /* rw: Mode */ 56 57 unsigned char pad3[1]; 58 volatile unsigned char sci_tcmd; /* rw: Target command */ 59 60 unsigned char pad4[1]; 61 volatile unsigned char sci_bus_csr; /* r: Bus Status */ 62 #define sci_sel_enb sci_bus_csr /* w: Select enable */ 63 64 unsigned char pad5[1]; 65 volatile unsigned char sci_csr; /* r: Status */ 66 #define sci_dma_send sci_csr /* w: Start dma send data */ 67 68 unsigned char pad6[1]; 69 volatile unsigned char sci_idata; /* r: Input data */ 70 #define sci_trecv sci_idata /* w: Start dma receive, target */ 71 72 unsigned char pad7[1]; 73 volatile unsigned char sci_iack; /* r: Interrupt Acknowledge */ 74 #define sci_irecv sci_iack /* w: Start dma receive, initiator */ 75 } sci_regmap_t; 76 #endif 77 78 /* 79 * Initiator command register 80 */ 81 82 #define SCI_ICMD_DATA 0x01 /* rw: Assert data bus */ 83 #define SCI_ICMD_ATN 0x02 /* rw: Assert ATN signal */ 84 #define SCI_ICMD_SEL 0x04 /* rw: Assert SEL signal */ 85 #define SCI_ICMD_BSY 0x08 /* rw: Assert BSY signal */ 86 #define SCI_ICMD_ACK 0x10 /* rw: Assert ACK signal */ 87 #define SCI_ICMD_LST 0x20 /* r: Lost arbitration */ 88 #define SCI_ICMD_DIFF SCI_ICMD_LST /* w: Differential cable */ 89 #define SCI_ICMD_AIP 0x40 /* r: Arbitration in progress */ 90 #define SCI_ICMD_TEST SCI_ICMD_AIP /* w: Test mode */ 91 #define SCI_ICMD_RST 0x80 /* rw: Assert RST signal */ 92 93 94 /* 95 * Mode register 96 */ 97 98 #define SCI_MODE_ARB 0x01 /* rw: Start arbitration */ 99 #define SCI_MODE_DMA 0x02 /* rw: Enable DMA xfers */ 100 #define SCI_MODE_MONBSY 0x04 /* rw: Monitor BSY signal */ 101 #define SCI_MODE_DMA_IE 0x08 /* rw: Enable DMA complete interrupt */ 102 #define SCI_MODE_PERR_IE 0x10 /* rw: Interrupt on parity errors */ 103 #define SCI_MODE_PAR_CHK 0x20 /* rw: Check parity */ 104 #define SCI_MODE_TARGET 0x40 /* rw: Target mode (Initiator if 0) */ 105 #define SCI_MODE_BLOCKDMA 0x80 /* rw: Block-mode DMA handshake (MBZ) */ 106 107 108 /* 109 * Target command register 110 */ 111 112 #define SCI_TCMD_IO 0x01 /* rw: Assert I/O signal */ 113 #define SCI_TCMD_CD 0x02 /* rw: Assert C/D signal */ 114 #define SCI_TCMD_MSG 0x04 /* rw: Assert MSG signal */ 115 #define SCI_TCMD_PHASE_MASK 0x07 /* r: Mask for current bus phase */ 116 #define SCI_TCMD_REQ 0x08 /* rw: Assert REQ signal */ 117 #define SCI_TCMD_LAST_SENT 0x80 /* ro: Last byte was xferred 118 * (not on 5380/1) */ 119 120 #define SCI_PHASE(x) ((x>>2) & 7) 121 122 /* 123 * Current (SCSI) Bus status 124 */ 125 126 #define SCI_BUS_DBP 0x01 /* r: Data Bus parity */ 127 #define SCI_BUS_SEL 0x02 /* r: SEL signal */ 128 #define SCI_BUS_IO 0x04 /* r: I/O signal */ 129 #define SCI_BUS_CD 0x08 /* r: C/D signal */ 130 #define SCI_BUS_MSG 0x10 /* r: MSG signal */ 131 #define SCI_BUS_REQ 0x20 /* r: REQ signal */ 132 #define SCI_BUS_BSY 0x40 /* r: BSY signal */ 133 #define SCI_BUS_RST 0x80 /* r: RST signal */ 134 135 #define SCI_CUR_PHASE(x) SCSI_PHASE((x)>>2) 136 137 /* 138 * Bus and Status register 139 */ 140 141 #define SCI_CSR_ACK 0x01 /* r: ACK signal */ 142 #define SCI_CSR_ATN 0x02 /* r: ATN signal */ 143 #define SCI_CSR_DISC 0x04 /* r: Disconnected (BSY==0) */ 144 #define SCI_CSR_PHASE_MATCH 0x08 /* r: Bus and SCI_TCMD match */ 145 #define SCI_CSR_INT 0x10 /* r: Interrupt request */ 146 #define SCI_CSR_PERR 0x20 /* r: Parity error */ 147 #define SCI_CSR_DREQ 0x40 /* r: DMA request */ 148 #define SCI_CSR_DONE 0x80 /* r: DMA count is zero */ 149 150
Indexes created Fri Sep 26 08:10:20 GMT 2025