scireg.h revision 1.4
1 /* $NetBSD: scireg.h,v 1.4 2003/05/03 18:10:44 wiz Exp $ */ 2 3 /* 4 * Copyright (c) 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Van Jacobson of Lawrence Berkeley Laboratory. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * @(#)scireg.h 7.3 (Berkeley) 2/5/91 39 */ 40 41 /* 42 * NCR 5380 SCSI interface hardware description. 43 * 44 */ 45 46 #if 0 /* for reference */ 47 typedef struct { 48 unsigned char pad0[1]; 49 volatile unsigned char sci_data; /* r: Current data */ 50 #define sci_odata sci_data /* w: Out data */ 51 52 unsigned char pad1[1]; 53 volatile unsigned char sci_icmd; /* rw: Initiator command */ 54 55 unsigned char pad2[1]; 56 volatile unsigned char sci_mode; /* rw: Mode */ 57 58 unsigned char pad3[1]; 59 volatile unsigned char sci_tcmd; /* rw: Target command */ 60 61 unsigned char pad4[1]; 62 volatile unsigned char sci_bus_csr; /* r: Bus Status */ 63 #define sci_sel_enb sci_bus_csr /* w: Select enable */ 64 65 unsigned char pad5[1]; 66 volatile unsigned char sci_csr; /* r: Status */ 67 #define sci_dma_send sci_csr /* w: Start DMA send data */ 68 69 unsigned char pad6[1]; 70 volatile unsigned char sci_idata; /* r: Input data */ 71 #define sci_trecv sci_idata /* w: Start DMA receive, target */ 72 73 unsigned char pad7[1]; 74 volatile unsigned char sci_iack; /* r: Interrupt Acknowledge */ 75 #define sci_irecv sci_iack /* w: Start DMA receive, initiator */ 76 } sci_regmap_t; 77 #endif 78 79 /* 80 * Initiator command register 81 */ 82 83 #define SCI_ICMD_DATA 0x01 /* rw: Assert data bus */ 84 #define SCI_ICMD_ATN 0x02 /* rw: Assert ATN signal */ 85 #define SCI_ICMD_SEL 0x04 /* rw: Assert SEL signal */ 86 #define SCI_ICMD_BSY 0x08 /* rw: Assert BSY signal */ 87 #define SCI_ICMD_ACK 0x10 /* rw: Assert ACK signal */ 88 #define SCI_ICMD_LST 0x20 /* r: Lost arbitration */ 89 #define SCI_ICMD_DIFF SCI_ICMD_LST /* w: Differential cable */ 90 #define SCI_ICMD_AIP 0x40 /* r: Arbitration in progress */ 91 #define SCI_ICMD_TEST SCI_ICMD_AIP /* w: Test mode */ 92 #define SCI_ICMD_RST 0x80 /* rw: Assert RST signal */ 93 94 95 /* 96 * Mode register 97 */ 98 99 #define SCI_MODE_ARB 0x01 /* rw: Start arbitration */ 100 #define SCI_MODE_DMA 0x02 /* rw: Enable DMA xfers */ 101 #define SCI_MODE_MONBSY 0x04 /* rw: Monitor BSY signal */ 102 #define SCI_MODE_DMA_IE 0x08 /* rw: Enable DMA complete interrupt */ 103 #define SCI_MODE_PERR_IE 0x10 /* rw: Interrupt on parity errors */ 104 #define SCI_MODE_PAR_CHK 0x20 /* rw: Check parity */ 105 #define SCI_MODE_TARGET 0x40 /* rw: Target mode (Initiator if 0) */ 106 #define SCI_MODE_BLOCKDMA 0x80 /* rw: Block-mode DMA handshake (MBZ) */ 107 108 109 /* 110 * Target command register 111 */ 112 113 #define SCI_TCMD_IO 0x01 /* rw: Assert I/O signal */ 114 #define SCI_TCMD_CD 0x02 /* rw: Assert C/D signal */ 115 #define SCI_TCMD_MSG 0x04 /* rw: Assert MSG signal */ 116 #define SCI_TCMD_PHASE_MASK 0x07 /* r: Mask for current bus phase */ 117 #define SCI_TCMD_REQ 0x08 /* rw: Assert REQ signal */ 118 #define SCI_TCMD_LAST_SENT 0x80 /* ro: Last byte was xferred 119 * (not on 5380/1) */ 120 121 #define SCI_PHASE(x) ((x>>2) & 7) 122 123 /* 124 * Current (SCSI) Bus status 125 */ 126 127 #define SCI_BUS_DBP 0x01 /* r: Data Bus parity */ 128 #define SCI_BUS_SEL 0x02 /* r: SEL signal */ 129 #define SCI_BUS_IO 0x04 /* r: I/O signal */ 130 #define SCI_BUS_CD 0x08 /* r: C/D signal */ 131 #define SCI_BUS_MSG 0x10 /* r: MSG signal */ 132 #define SCI_BUS_REQ 0x20 /* r: REQ signal */ 133 #define SCI_BUS_BSY 0x40 /* r: BSY signal */ 134 #define SCI_BUS_RST 0x80 /* r: RST signal */ 135 136 #define SCI_CUR_PHASE(x) SCSI_PHASE((x)>>2) 137 138 /* 139 * Bus and Status register 140 */ 141 142 #define SCI_CSR_ACK 0x01 /* r: ACK signal */ 143 #define SCI_CSR_ATN 0x02 /* r: ATN signal */ 144 #define SCI_CSR_DISC 0x04 /* r: Disconnected (BSY==0) */ 145 #define SCI_CSR_PHASE_MATCH 0x08 /* r: Bus and SCI_TCMD match */ 146 #define SCI_CSR_INT 0x10 /* r: Interrupt request */ 147 #define SCI_CSR_PERR 0x20 /* r: Parity error */ 148 #define SCI_CSR_DREQ 0x40 /* r: DMA request */ 149 #define SCI_CSR_DONE 0x80 /* r: DMA count is zero */ 150 151
Indexes created Sun Sep 28 16:09:52 GMT 2025